Defect detection method

Abstract

A defect detection method comprises the following steps: providing a static random access memory which comprises a plurality of memory cells arranged in an array; obtaining a plurality of invalid storage units, wherein one invalid storage unit corresponds to one address; obtaining a plurality of failure modes according to the addresses corresponding to the failure storage units; a failure mode proportion database is provided, the failure mode proportion database comprises a plurality of failure mode proportions and a plurality of failure structures, and the failure mode proportions and the failure structures are in one-to-one correspondence; obtaining a measurement failure mode proportion according to the plurality of failure modes; and obtaining a failure structure corresponding to the measurement failure mode proportion according to the failure mode proportion database. According to the defect detection method, the defect analysis period can be shortened, and the production efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a defect detection method. Background Art

[0002] The circuit structure of static random access memory (SRAM) consists of a memory array and peripheral circuits, where the memory array consists of repeated memory cells (bitcells) arranged in rows and columns. The manufacturing process of static random access memory is an issue that requires continuous attention. Usually, the problems in the process are fed back by testing the yield and performance changes of static random access memory (SRAM), and then the process is improved according to the feedback problems to improve the production yield.

[0003] Therefore, a fast and efficient failure analysis method is needed to quickly locate problems in the process, improve the process, and increase the yield. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a defect detection method so as to quickly locate the problem in the process, improve the process and increase the yield.

[0005] To solve the above technical problems, the technical solution of the present invention provides a defect detection method, including: providing a static random access memory, the static random access memory including a plurality of storage units arranged in an array; obtaining a plurality of failed storage units, one failed storage unit corresponding to an address; obtaining a plurality of failure modes according to the addresses corresponding to the plurality of failed storage units; providing a failure mode ratio database, the failure mode ratio database including a plurality of failure mode ratios and a plurality of failure structures, the plurality of failure mode ratios corresponding one to one with the plurality of failure structures; obtaining a measured failure mode ratio according to the plurality of failure modes; obtaining a failure structure corresponding to the measured failure mode ratio according to the failure mode ratio database.

[0006] Optionally, the failure mode ratio database further includes: a number of process types corresponding to a number of failure structures, and a number of the failure structures correspond to a number of process types in a one-to-one manner; and a number of process types have corresponding working machines.

[0007] Optionally, the method further includes: obtaining a process type corresponding to the failure structure according to the failure structure corresponding to the failure mode ratio; and obtaining a work machine corresponding to the process type according to the process type corresponding to the failure structure.

[0008] Optionally, the failure modes include: a single failure mode, a double failure mode in the row direction, a double failure mode in the column direction, and a quadruple failure mode in a grid pattern.

[0009] Optionally, the failure mode ratio includes: a first proportional relationship, a second proportional relationship, a third proportional relationship, a fourth proportional relationship and a fifth proportional relationship; the first proportional relationship is, single failure mode: double failure mode in the row direction: double failure mode in the column direction = 4:3:1; the second proportional relationship is, single failure mode: double failure mode in the row direction: double failure mode in the column direction: quadruple failure mode in the field grid = 4:2:2:1; the third proportional relationship is, double failure mode in the row direction: double failure mode in the column direction: quadruple failure mode in the field grid = 4:2:1; the fourth proportional relationship is, double failure mode in the column direction: quadruple failure mode in the field grid = 2:1.

[0010] Optionally, the storage unit includes: a substrate; a bottom layer structure located on the substrate, a first layer structure located on the bottom layer structure, a second layer structure located on the first layer structure, a third layer structure located on the second layer structure, a fourth layer structure located on the third layer structure, and a fifth layer structure located on the fourth layer structure; the several failure structures include failure of the first layer structure, failure of the second layer structure, failure of the third layer structure, failure of the fourth layer structure, and failure of the fifth layer structure.

[0011] Optionally, the first proportional relationship corresponds to the failure of the first layer structure; the second proportional relationship corresponds to the failure of the second layer structure; the third proportional relationship corresponds to the failure of the third layer structure; the fourth proportional relationship corresponds to the failure of the fourth layer structure or the fifth layer structure.

[0012] Optionally, the underlying structure includes: a first fin, a second fin, a third fin and a fourth fin arranged in sequence along a first direction on the substrate, the first fin, the second fin, the third fin and the fourth fin being parallel to the second direction, the first direction and the second direction being parallel to the substrate surface and the first direction and the second direction being perpendicular to each other; a first gate spanning the first fin and the second fin, a second gate spanning the fourth fin, the first gate and the second gate being parallel to the first direction and the extension directions of the first gate and the second gate being on the same straight line; a third gate spanning the third fin and the fourth fin, a fourth gate spanning the first fin, the third gate and the fourth gate being parallel to the first direction and the extension directions of the third gate and the fourth gate being on the same straight line; a first source-drain doped region, a second source-drain doped region and a third source-drain doped region located in the first fin, the first source-drain doped region and the second source-drain doped region, the first source-drain doped region and the second source-drain doped region being parallel to the first direction and the extension directions of the third gate and the fourth gate being on the same straight line. A first source-drain doping region and a second source-drain doping region are respectively located in the first fins on both sides of the first gate, and the second source-drain doping region and the third source-drain doping region are respectively located in the first fins on both sides of the fourth gate; a fourth source-drain doping region and a fifth source-drain doping region are located in the second fin, and the fourth source-drain doping region and the fifth source-drain doping region are respectively located in the second fins on both sides of the second gate; a sixth source-drain doping region and a seventh source-drain doping region are located in the third fin, and the sixth source-drain doping region and the seventh source-drain doping region are respectively located in the third fins on both sides of the third gate; an eighth source-drain doping region, a ninth source-drain doping region and a tenth source-drain doping region are located in the fourth fin, and the eighth source-drain doping region and the ninth source-drain doping region are respectively located in the fourth fins on both sides of the second gate, and the ninth source-drain doping region and the tenth source-drain doping region are respectively located in the fourth fins on both sides of the third gate.

[0013] Optionally, the first layer structure includes a plurality of discrete first plugs, and the plurality of first plugs are respectively located on: the first source and drain doping region; the second source and drain doping region; the third source and drain doping region; the fourth source and drain doping region; the seventh source and drain doping region; the eighth source and drain doping region; the ninth source and drain doping region; the tenth source and drain doping region; the fifth source and drain doping region, and the third gate on the second fin; the sixth source and drain doping region and the first gate on the third fin; the fourth gate on the first fin; and the second gate on the fourth fin; the second layer structure includes a plurality of first metal layers parallel to the first direction, and the plurality of first metal layers are respectively located on the first plug and electrically connected to the first plug, and the plurality of first metal layers are respectively located on: the first source and drain doping region; the third source and drain doping region; the fourth source and drain doping region; ... third source and drain doping region; the fourth source and drain doping region; the third source and drain doping region; the third source and drain doping region; the fourth source and drain doping region; the third source and drain doping region; the third source and drain doping region; the third source and drain doping region; the third source and drain doping region; the third source and drain doping region; the third source and drain doping region; the third source and drain doping region; the third source and drain do On the seventh source and drain doping region; on the eighth source and drain doping region; on the tenth source and drain doping region; on the fourth gate on the first fin; on the second gate on the fourth fin; on the second source and drain doping region; on the fifth source and drain doping region and the third gate on the second fin; on the sixth source and drain doping region, on the ninth source and drain doping region and on the first gate on the third fin; the third layer structure includes a plurality of discrete second plugs, and the plurality of second plugs are respectively located on the first metal layer and electrically connected to the first metal layer, and the plurality of second plugs are respectively located on: the first source and drain doping region; on the third source and drain doping region; on the fourth source and drain doping region; on the seventh source and drain doping region; on the eighth source and drain doping region; on the tenth source and drain doping region; on the second gate on the fourth fin; on the fourth gate on the first fin.

[0014] Optionally, the fourth layer structure includes several second metal layers parallel to the second direction, and the several second metal layers are respectively located: on the first source and drain doped region; on the fourth gate on the first fin; on the second gate on the fourth fin; on the third source and drain doped region; on the fourth source and drain doped region and on the seventh source and drain doped region; on the eighth source and drain doped region; on the tenth source and drain doped region; the fifth layer structure includes several discrete third plugs, several of the third plugs are respectively located on the second metal layer and electrically connected to the second metal layer, and several of the third plugs are respectively located on the first source and drain doped region, on the tenth source and drain doped region, on the second gate on the fourth fin, and on the fourth gate on the first fin.

[0015] Optionally, obtaining a measured failure mode ratio according to a number of failure modes includes: obtaining the number of various failure modes in the static random access memory; and obtaining a measured failure mode ratio according to the number of various failure modes.

[0016] Optionally, obtaining a failure structure corresponding to the measured failure mode ratio according to the failure mode ratio database includes: obtaining a failure mode ratio that is the same as the measured failure mode ratio in the failure mode ratio database; and obtaining a failure structure corresponding to the failure mode ratio, wherein the failure structure corresponds to the measured failure mode ratio.

[0017] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0018] The defect detection method of the present invention obtains the measured failure mode ratio according to a plurality of failure modes, and then obtains the failure structure corresponding to the measured failure mode ratio according to the failure mode ratio database. The process can quickly locate the failure structure, and can quickly locate the process defects according to the failure structure, thereby shortening the defect analysis cycle and improving production efficiency.

[0019] Furthermore, some of the failure structures correspond one-to-one to some process types, and some process types have corresponding working machines, so that the working machine causing the defect can be quickly located according to the measured failure mode ratio, and the problem can be quickly solved, thereby shortening the defect analysis cycle and improving production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic flow chart of a defect detection method in an embodiment of the present invention;

[0021] Figures 2 to 7 is a schematic diagram of the structure of a static random access memory in an embodiment of the present invention;

[0022] Figures 8 to 11 Schematic diagram of failure mode in an embodiment of the present invention. DETAILED DESCRIPTION

[0023] As described in the background art, a fast and efficient failure analysis method is needed to quickly locate problems in the process, improve the process, and increase the yield.

[0024] Specifically, the static random access memory includes a plurality of storage units arranged in an array. The existing failure analysis method for the static random access memory (SRAM) includes: using a test machine to test a plurality of storage units of the static random access memory to obtain the test results of the static random access memory, the test results including failed storage units and addresses of failed storage units, the addresses of the failed storage units being the positions of rows and columns where the failed storage units are located; using analysis software to analyze a plurality of failed storage units and addresses of failed storage units to obtain failure modes of the plurality of failed storage units, the failure modes including: a single failure mode, a double failure mode in the row direction, a double failure mode in the column direction, and a quadruple failure mode in a grid.

[0025] The usual yield analysis path is to sort the histogram according to different failure modes, then find out the bit failure mode that has the greatest impact on the yield and focus on it, and then perform FA slice analysis based on the coordinates of the failed storage unit given by the tester to locate the process problem. The process not only generates additional costs, but also has a long cycle, which is not conducive to quickly locating problems and improving manufacturing processes.

[0026] In order to solve the above problems, the technical solution of the present invention provides a defect detection method, which obtains the measured failure mode ratio according to a number of failure modes, and then obtains the failure structure corresponding to the measured failure mode ratio according to the failure mode ratio database. The process can quickly locate the failure structure, and can quickly locate the process defects according to the failure structure, thereby shortening the defect analysis cycle and improving production efficiency.

[0027] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0028] Figure 1 It is a flow chart of the defect detection method in an embodiment of the present invention.

[0029] Please refer to Figure 1 , the process of the defect detection method includes:

[0030] Step S10: providing a static random access memory, wherein the static random access memory comprises a plurality of storage units arranged in an array;

[0031] Step S20: obtaining a number of failed storage units, where one failed storage unit corresponds to one address;

[0032] Step S30: obtaining a plurality of failure modes according to the addresses corresponding to the plurality of failed storage units;

[0033] Step S40: providing a failure mode ratio database, wherein the failure mode ratio database includes a plurality of failure mode ratios and a plurality of failure structures, and the plurality of failure mode ratios correspond to the plurality of failure structures in a one-to-one manner;

[0034] Step S50: obtaining a measured failure mode ratio according to a plurality of failure modes;

[0035] Step S60: acquiring the failure structure corresponding to the measured failure mode ratio according to the failure mode ratio database.

[0036] The defect detection method obtains the measured failure mode ratio according to a number of failure modes, and then obtains the failure structure corresponding to the measured failure mode ratio according to the failure mode ratio database. The process can quickly locate the failure structure, and can quickly locate the process defects according to the failure structure, thereby shortening the defect analysis cycle and improving production efficiency.

[0037] Next, combine Figures 2 to 11 The defect detection method is analyzed and explained. Figures 2 to 7 is a schematic diagram of the structure of a static random access memory in an embodiment of the present invention; Figures 8 to 11 Schematic diagram of failure mode in an embodiment of the present invention.

[0038] Please combine Figures 2 to 7 Continue to refer Figure 1 , executing step S10: providing a static random access memory, wherein the static random access memory includes a plurality of storage units arranged in an array.

[0039] The storage unit includes: a substrate (not shown); a bottom layer structure located on the substrate, a first layer structure located on the bottom layer structure, a second layer structure located on the first layer structure, a third layer structure located on the second layer structure, a fourth layer structure located on the third layer structure, and a fifth layer structure located on the fourth layer structure.

[0040] Figure 2 The schematic diagram of the underlying structure of a static random access memory is shown in FIG. 1 , where a plurality of memory bit cells are arranged in an array along a first direction X and a second direction Y. The first direction X is a column direction, and the second direction Y is a row direction. Figure 2 Two storage units bitcells arranged along the second direction Y are schematically shown.

[0041] Please refer to Figure 2The bottom layer structure includes: a first fin 101, a second fin 102, a third fin 103 and a fourth fin 104 arranged in sequence along a first direction X on a substrate, the first fin 101, the second fin 102, the third fin 103 and the fourth fin 104 are parallel to a second direction Y, the first direction X and the second direction Y are parallel to a substrate surface and the first direction X and the second direction Y are perpendicular to each other; a first gate 201 spanning the first fin 101 and the second fin 102, a second gate 202 spanning the fourth fin 104, the first gate 20 The first gate 201 and the second gate 202 are parallel to the first direction X, and the extension directions of the first gate 201 and the second gate 202 are located on the same straight line; the third gate 203 spanning the third fin 103 and the fourth fin 104, the fourth gate 204 spanning the first fin 101, the third gate 203 and the fourth gate 204 are parallel to the first direction X, and the extension directions of the third gate 203 and the fourth gate 204 are located on the same straight line; the first source-drain doped region (not shown), the second source-drain doped region (not shown) and the third source-drain doped region (not shown) located in the first fin 101 doped regions (not shown), the first source-drain doped region and the second source-drain doped region are respectively located in the first fin 101 on both sides of the first gate 201, the second source-drain doped region and the third source-drain doped region are respectively located in the first fin 101 on both sides of the fourth gate 204; a fourth source-drain doped region (not shown) and a fifth source-drain doped region (not shown) located in the second fin 102, the fourth source-drain doped region and the fifth source-drain doped region are respectively located in the second fin 102 on both sides of the second gate 202; a sixth source-drain doped region (not shown) located in the third fin 103 The sixth source-drain doping region and the seventh source-drain doping region are respectively located in the third fin 103 on both sides of the third gate 203; an eighth source-drain doping region (not shown), a ninth source-drain doping region (not shown) and a tenth source-drain doping region (not shown) are located in the fourth fin 104, the eighth source-drain doping region and the ninth source-drain doping region are respectively located in the fourth fin 104 on both sides of the second gate 202, and the ninth source-drain doping region and the tenth source-drain doping region are respectively located in the fourth fin 104 on both sides of the third gate 203.

[0042] Figure 2 In the two adjacent bitcells shown in FIG. 1 , the third source-drain doping region is shared by the two bitcells, the seventh source-drain doping region is shared by the two bitcells, and the tenth source-drain doping region is shared by the two bitcells.

[0043] In this embodiment, the conductivity types of the fourth source-drain doping region and the fifth source-drain doping region include P-type; the conductivity types of the sixth source-drain doping region and the seventh source-drain doping region include P-type; the conductivity types of the first source-drain doping region, the second source-drain doping region, the third source-drain doping region, the eighth source-drain doping region, the ninth source-drain doping region and the tenth source-drain doping region include N-type.

[0044] In this embodiment, the fourth source-drain doping region and the first source-drain doping region are located on the same side of the first gate 201 ; the seventh source-drain doping region and the tenth source-drain doping region are located on the same side of the third gate 203 .

[0045] Please refer to Figure 3 , Figure 3 A schematic diagram of the first-level structure of the static random access memory structure. Figure 3 For Figure 2 Based on the schematic diagram, the first layer structure includes a plurality of discrete first plugs 105, and the plurality of first plugs 105 are respectively located: on the first source and drain doping region; on the second source and drain doping region; on the third source and drain doping region; on the fourth source and drain doping region; on the seventh source and drain doping region; on the eighth source and drain doping region; on the ninth source and drain doping region; on the tenth source and drain doping region; on the fifth source and drain doping region and on the third gate 203 on the second fin 102; on the sixth source and drain doping region and on the first gate 201 on the third fin 103; on the fourth gate 204 on the first fin 101; on the second gate 202 on the fourth fin 104.

[0046] Please refer to Figure 4 , Figure 4 A schematic diagram of the second layer structure of the static random access memory structure. Figure 4 For Figure 3 Based on the schematic diagram, the second layer structure includes a plurality of first metal layers 106, and the plurality of first metal layers 106 are respectively located on the first plug 105 and electrically connected to the first plug 105, and the plurality of first metal layers 106 are respectively located: on the first source and drain doping region; on the third source and drain doping region; on the fourth source and drain doping region; on the seventh source and drain doping region; on the eighth source and drain doping region; on the tenth source and drain doping region; on the fourth gate 204 on the first fin 101; on the second gate 202 on the fourth fin 104; on the second source and drain doping region; on the fifth source and drain doping region and on the third gate 203 on the second fin 102; on the sixth source and drain doping region, on the ninth source and drain doping region and on the first gate 201 on the third fin 103.

[0047] The first metal layer 106 located on the first source and drain doping region, on the third source and drain doping region, on the fourth source and drain doping region, on the seventh source and drain doping region, on the eighth source and drain doping region, and on the tenth source and drain doping region is parallel to the first direction X; the first metal layer 106 located on the fourth gate 204 on the first fin 101 and on the second gate 202 on the fourth fin 104 is parallel to the second direction Y; the first metal layer 106 located on the second source and drain doping region, on the fifth source and drain doping region, and on the third gate 203 on the second fin 102 is "L"-shaped; the first metal layer 106 located on the first gate 201 located on the sixth source and drain doping region, on the ninth source and drain doping region, and on the third fin 103 is "L"-shaped.

[0048] The first metal layer 106 located on the second source-drain doping region, the fifth source-drain doping region and the third gate 203 on the second fin 102 is electrically connected to the second source-drain doping region, the fifth source-drain doping region and the third gate 203 on the second fin 102; the first metal layer 106 located on the first gate 201 on the sixth source-drain doping region, the ninth source-drain doping region and the third fin 103 is electrically connected to the sixth source-drain doping region, the ninth source-drain doping region and the first gate 201 on the third fin 103.

[0049] Please refer to Figure 5 , Figure 5 A schematic diagram of the third layer structure of the static random access memory. Figure 5 For Figure 4 Based on the schematic diagram, the third layer structure includes a plurality of discrete second plugs 107, and the plurality of second plugs 107 are respectively located on the first metal layer 106 and electrically connected to the first metal layer 106, and the plurality of second plugs 107 are respectively located: on the first source-drain doping region; on the third source-drain doping region; on the fourth source-drain doping region; on the seventh source-drain doping region; on the eighth source-drain doping region; on the tenth source-drain doping region; on the second gate 202 on the fourth fin 104; and on the fourth gate 204 on the first fin 101.

[0050] Please refer to Figure 6 , Figure 6 A schematic diagram of the fourth layer structure of the static random access memory structure. Figure 6 For Figure 5Based on the schematic diagram, the fourth layer structure includes a plurality of second metal layers 108 parallel to the second direction Y, and the plurality of second metal layers 108 are respectively located on the second plug 107 and electrically connected to the second plug 107, and the plurality of second metal layers 108 are respectively located: on the first source-drain doped region; on the fourth gate 204 on the first fin 101; on the second gate 202 on the fourth fin 104; on the third source-drain doped region; on the fourth source-drain doped region and the seventh source-drain doped region; on the eighth source-drain doped region; and on the tenth source-drain doped region.

[0051] In this embodiment, the second metal layer 108 located on the third source-drain doping region serves as a first bit line BL1, which is electrically connected to a row (second direction Y) of memory cells bitcell; the second metal layer 108 located on the eighth source-drain doping region serves as a second bit line BL2, which is electrically connected to a row (second direction Y) of memory cells bitcell; the second metal layer 108 located on the fourth source-drain doping region and the seventh source-drain doping region serves as a power line VDD, which is electrically connected to a row (second direction Y) of memory cells bitcell.

[0052] The first bit line BL1 , the second bit line BL2 , and the power line VDD are parallel to the second direction Y.

[0053] In this embodiment, the second metal layer 108 located on the first source-drain doped region is used to be electrically connected to the first ground line VSS1; the second metal layer 108 located on the tenth source-drain doped region is used to be electrically connected to the second ground line VSS2; the second metal layer 108 located on the fourth gate 204 on the first fin 101 is used to be subsequently electrically connected to the first word line WL1; the second metal layer 108 located on the second gate 202 on the fourth fin 104 is used to be subsequently electrically connected to the second word line WL2.

[0054] Please refer to Figure 7 , Figure 7 A schematic diagram of the fifth layer structure of the static random access memory. Figure 7 For Figure 6 According to the schematic diagram on the basis, the fifth layer structure includes a plurality of discrete third plugs 109, and the plurality of third plugs 109 are respectively located on the second metal layer 108 and electrically connected to the second metal layer 108, and the plurality of third plugs 109 are respectively located on the first source-drain doped region, on the tenth source-drain doped region, on the second gate 202 on the fourth fin 104, and on the fourth gate 204 on the first fin 101.

[0055] In this embodiment, the third plug 109 located on the first source-drain doped region is used to be electrically connected to the first ground line VSS1, and the first ground line VSS1 is electrically connected to a column (first direction X) of memory cells bitcell; the third plug 109 located on the tenth source-drain doped region is used to be electrically connected to the second ground line VSS2, and the second ground line VSS2 is electrically connected to a column (first direction X) of memory cells bitcell; the third plug 109 located on the fourth gate 204 on the first fin 101 is used to be electrically connected to the first word line WL1, and the first word line WL1 is electrically connected to a column (first direction X) of memory cells bitcell; the third plug 109 located on the second gate 202 on the fourth fin 104 is used to be electrically connected to the second word line WL2, and the second word line WL2 is electrically connected to a column (first direction X) of memory cells bitcell.

[0056] The first ground line VSS1 , the second ground line VSS2 , the first word line WL1 , and the second word line WL2 are parallel to the first direction X.

[0057] Please continue to refer to Figure 1 , execute step S20: obtain a number of failed storage units, one failed storage unit corresponds to one address.

[0058] One failed storage cell corresponds to one address, that is, one failed storage cell corresponds to information of one row and column in the storage array.

[0059] Please combine Figures 8 to 11 Continue to refer Figure 1 , executing step S30: obtaining a plurality of failure modes according to the addresses corresponding to the plurality of failed storage units.

[0060] Some of the failure modes include: a single failure mode SB (Single bitcell), a double failure mode DBR (Double bitcell row) in the row direction, a double failure mode DBR (Double bitcell column) in the column direction, and a quadruple failure mode QB (Quad bit cell).

[0061] Please refer to Figure 8 , Figure 8 It is a schematic diagram of a single failure mode, that is, the storage units adjacent to the failed storage unit are all functioning normally.

[0062] Please refer to Fig. 9 , Fig. 9 Schematic diagram of a double failure mode in the row direction, that is, there are two consecutive failed memory cells in the second direction Y.

[0063] Please refer to Fig.10 , Fig.10 FIG. 1 is a schematic diagram of a column-by-column failure mode in the row direction, that is, there are two consecutive failed memory cells in the first direction X. FIG.

[0064] Please refer to Fig.11 , Fig.11 Schematic diagram of a quadruple failure mode in a grid pattern, i.e., four failed storage cells are continuously distributed in a grid pattern.

[0065] Please continue to refer to Figure 1 , executing step S40: providing a failure mode ratio database, wherein the failure mode ratio database includes a plurality of failure mode ratios and a plurality of failure structures, and the plurality of failure mode ratios correspond to the plurality of failure structures in a one-to-one manner.

[0066] The several failure structures include first layer structure failure, second layer structure failure, third layer structure failure, fourth layer structure failure, and fifth layer structure failure.

[0067] The first layer structure fails, that is, a number of the first plugs 105 are disconnected, have positional deviation and other defects, and a number of the first plugs 105 have no normal electrical connection with the source and drain doping regions of the underlying structure.

[0068] The second layer structure fails, that is, some of the first metal layers 106 are broken, have defects such as position shift, and some of the first metal layers 106 have no normal electrical connection with the first plugs 105 of the first layer structure.

[0069] The third layer structure fails, that is, a number of the second plugs 107 are disconnected, have positional deviation and other defects, and a number of the second plugs 107 have no normal electrical connection with the first metal layer 106 of the second layer structure.

[0070] The fourth layer structure fails, that is, some of the second metal layers 108 are broken, have positional deviation and other defects, and some of the second metal layers 108 have no normal electrical connection with the second plugs 107 of the third layer structure.

[0071] The fifth layer structure fails, that is, a number of the third plugs 109 are disconnected, have positional deviation and other defects, and a number of the third plugs 109 have no normal electrical connection with the second metal layer 108 of the fourth layer structure.

[0072] In this embodiment, the failure mode ratios include: a first ratio relationship, a second ratio relationship, a third ratio relationship, a fourth ratio relationship and a fifth ratio relationship.

[0073] The first ratio relationship is: single failure mode: double failure mode in the row direction: double failure mode in the column direction = 4:3:1. The first ratio relationship corresponds to the failure of the first layer structure.

[0074] Please continue to refer to Figure 3 , several of the first plugs 105 are respectively located: on the first source-drain doping region; on the second source-drain doping region; on the third source-drain doping region; on the fourth source-drain doping region; on the seventh source-drain doping region; on the eighth source-drain doping region; on the ninth source-drain doping region; on the tenth source-drain doping region; on the fifth source-drain doping region and on the third gate 203 on the second fin 102; on the sixth source-drain doping region and on the first gate 201 on the third fin 103; on the fourth gate 204 on the first fin 101; on the second gate 202 on the fourth fin 104, and the number of the first plugs 105 in one storage unit is 12.

[0075] The first direction X is the column direction, and the second direction Y is the row direction. When the first plug 105 located on the second source-drain doping region, the fifth source-drain doping region, the third gate 203 on the second fin 102, the sixth source-drain doping region and the first gate 201 on the third fin 103, or the ninth source-drain doping region fails, a single storage unit failure (SB) will be caused, that is, the number of first plugs 105 that will cause the failure of a single storage unit is 4; when the first source-drain doping region, the third source-drain doping region, the fourth source-drain doping region, the seventh source-drain doping region, the eighth source-drain doping region, When the first plug 105 on the tenth source-drain doping region fails, two adjacent storage cells in the row direction (second direction Y) will fail (DBR), that is, the number of first plugs 105 that will cause the failure of two adjacent storage cells in the row direction is 6; when the first plug 105 located on the fourth gate 204 on the first fin 101 and the second gate 202 on the fourth fin 104 fails, two adjacent storage cells in the column direction (first direction X) will fail (DBC), that is, the number of first plugs 105 that will cause the failure of two adjacent storage cells in the column direction is 2.

[0076] Therefore, when the first layer structure fails, a first proportional relationship is obtained, single failure mode (SB): double failure mode in the row direction (DBR): double failure mode in the column direction (DBC) = 4:6*1 / 2:2*1 / 2 = 4:3:1.

[0077] The second proportional relationship is: single failure mode: double failure mode in the row direction: double failure mode in the column direction: quadruple failure mode in a grid pattern = 4:2:2:1. The second proportional relationship corresponds to the failure of the second layer structure.

[0078] Please continue to refer to Figure 4, the second layer structure includes a plurality of first metal layers 106, and the plurality of first metal layers 106 are respectively located on the first plugs 105 and are electrically connected to the first plugs 105. The plurality of first metal layers 106 are respectively located on: the first source / drain doping region; on the third source / drain doping region; on the fourth source / drain doping region; on the seventh source / drain doping region; on the eighth source / drain doping region; on the tenth source / drain doping region; on the fourth gate 204 on the first fin 101; on the second gate 202 on the fourth fin 104; on the second source / drain doping region; on the fifth source / drain doping region and on the third gate 203 on the second fin 102; on the sixth source / drain doping region, on the ninth source / drain doping region and on the first gate 201 on the third fin 103.

[0079] The first direction X is the column direction, and the second direction Y is the row direction. When the first metal layer 106 on the third gate 203 on the fifth source / drain doping region and on the second fin 102, or when the first metal layer 106 on the first gate 201 on the sixth source / drain doping region, on the ninth source / drain doping region and on the third fin 103 fails, it will cause a single memory cell to fail (SB), that is, the number of first metal layers 106 that will cause a single memory cell to fail is 2; when the first metal layer 106 on the third source / drain doping region, on the fourth source / drain doping region, on the seventh source / drain doping region, or on the eighth source / drain doping region fails, it will cause two adjacent memory cells in the row direction (the second direction Y) to fail (DBR), that is, the number of first metal layers 106 that will cause two adjacent memory cells in the row direction to fail is 4; when the first metal layer 106 on the first source / drain doping region or on the tenth source / drain doping region fails, it will cause two adjacent memory cells in the column direction (the first direction X) and two adjacent memory cells in the row direction (the second direction Y) to fail, that is, it will cause 4 memory cells distributed in a "field" shape to fail (QB), that is, the number of first metal layers 106 that will cause 4 memory cells distributed in a "field" shape to fail (QB) is 2; when the first metal layer 106 on the second gate 202 on the fourth fin 104, or on the fourth gate 204 on the first fin 101 fails, it will cause two adjacent memory cells in the column direction (the first direction X) to fail (DBC), that is, the number of first metal layers 106 that will cause two adjacent memory cells in the column direction to fail is 2.

[0080] Therefore, when the second layer structure fails, a second proportional relationship will be obtained. The second proportional relationship is that the single failure mode: the double failure mode in the row direction: the double failure mode in the column direction: the four-fold failure mode of the "field" grid = 2:4*1 / 2:2*1 / 2:2*1 / 4 = 4:2:2:1.

[0081] The third proportional relationship is that the double failure mode in the row direction: the double failure mode in the column direction: the cross-shaped quadruple failure mode = 4:2:1. The third proportional relationship corresponds to the failure of the third-layer structure.

[0082] Please continue to refer to Figure 5 , the third-layer structure includes a plurality of discrete second plugs 107, and a plurality of the second plugs 107 are respectively located on the first metal layer 106 and are electrically connected to the first metal layer 106. A plurality of the second plugs 107 are respectively located on: the first source / drain doping region; on the third source / drain doping region; on the fourth source / drain doping region; on the seventh source / drain doping region; on the eighth source / drain doping region; on the tenth source / drain doping region; on the second gate 202 on the fourth fin 104; on the fourth gate 204 on the first fin 101.

[0083] The first direction X is the column direction, and the second direction Y is the row direction. When the second plug 107 located on the third source / drain doping region, on the fourth source / drain doping region, on the seventh source / drain doping region, or on the eighth source / drain doping region fails, it will cause two adjacent memory cells in the row direction (the second direction Y) to fail (DBR), that is, the number of second plugs 107 that will cause two adjacent memory cells in the row direction to fail is 4; when the second plug 107 located on the second gate 202 on the fourth fin 104 or on the fourth gate 204 on the first fin 101 fails, it will cause two adjacent memory cells in the column direction (the first direction X) to fail (DBC), that is, the number of second plugs 107 that will cause two adjacent memory cells in the column direction to fail is 2; when the second plug 107 located on the first source / drain doping region or on the tenth source / drain doping region fails, it will cause two adjacent memory cells in the column direction (the first direction X) and two adjacent memory cells in the row direction (the second direction Y) to fail, that is, it will cause 4 memory cells distributed in a "cross" shape to fail (QB), that is, the number of second plugs 107 that will cause 4 memory cells distributed in a "cross" shape to fail (QB) is 2.

[0084] Therefore, when the third-layer structure fails, the third proportional relationship can be obtained. The third proportional relationship is that the double failure mode in the row direction: the double failure mode in the column direction: the cross-shaped quadruple failure mode = 4*1 / 2: 2*1 / 2: 2*1 / 4 = 4:2:1.

[0085] The fourth proportional relationship is that the double failure mode in the column direction: the cross-shaped quadruple failure mode = 2:1. The fourth proportional relationship corresponds to the failure of the fourth-layer structure or the fifth-layer structure.

[0086] Please continue to refer to Figure 6, the fourth layer structure includes a plurality of second metal layers 108 parallel to the second direction Y. A plurality of the second metal layers 108 are respectively located on the second plugs 107 and electrically connected to the second plugs 107. The plurality of the second metal layers 108 are respectively located on: the first source / drain doping region; the fourth gate 204 on the first fin 101; the second gate 202 on the fourth fin 104; the third source / drain doping region; the fourth source / drain doping region and the seventh source / drain doping region; the eighth source / drain doping region; the tenth source / drain doping region. The first direction X is the column direction, and the second direction Y is the row direction. When the second metal layer 108 on the second gate 202 on the fourth fin 104 or the fourth gate 204 on the first fin 101 fails, it will cause two adjacent memory cells in the column direction (the first direction X) to fail (DBC), that is, the number of second metal layers 108 that will cause two adjacent memory cells in the column direction to fail is 2; when the second metal layer 108 on the first source / drain doping region or the tenth source / drain doping region fails, it will cause two adjacent memory cells in the column direction (the first direction X) and two adjacent memory cells in the row direction (the second direction Y) to fail, that is, it will cause 4 memory cells distributed in a "field" shape to fail (QB), that is, the number of second metal layers 108 that will cause 4 memory cells distributed in a "field" shape to fail (QB) is 2.

[0087] Therefore, when the fourth layer structure fails, a fourth proportional relationship can be obtained. The fourth proportional relationship is that in the column direction, the double failure mode: the "field" quadruple failure mode = 2 * 1 / 2: 2 * 1 / 4 = 2:1.

[0088] Please continue to refer to Figure 7 , the fifth layer structure includes a plurality of discrete third plugs 109. A plurality of the third plugs 109 are respectively located on the second metal layers 108 and electrically connected to the second metal layers 108. The plurality of the third plugs 109 are respectively located on the first source / drain doping region, the tenth source / drain doping region, the second gate 202 on the fourth fin 104, and the fourth gate 204 on the first fin 101.

[0089] The first direction X is the column direction, and the second direction Y is the row direction. When the third plug 109 on the second gate 202 located on the fourth fin 104 or on the fourth gate 204 located on the first fin 101 fails, it will cause two adjacent memory cells in the column direction (the first direction X) to fail (DBC), that is, the number of third plugs 109 that will cause two adjacent memory cells in the column direction to fail is 2; when the third plug 109 on the first source / drain doping region or on the tenth source / drain doping region fails, it will cause two adjacent memory cells in the column direction (the first direction X) and two adjacent memory cells in the row direction (the second direction Y) to fail, that is, it will cause 4 memory cells distributed in a "field" shape to fail (QB), that is, the number of third plugs 109 that will cause 4 memory cells distributed in a "field" shape to fail (QB) is 2.

[0090] Therefore, when the fifth layer structure fails, a fourth proportional relationship can be obtained. The fourth proportional relationship is that the double failure mode in the column direction: the four-fold failure mode of the "field" grid = 2 * 1 / 2: 2 * 1 / 4 = 2:1.

[0091] In this embodiment, the failure mode ratio database further includes: several process types corresponding to several failure structures, and the several failure structures correspond to the several process types one by one; the several process types have corresponding working machines.

[0092] The process types include: deposition process, etching process, etc.; the deposition process corresponds to a deposition machine, and the etching process corresponds to an etching machine.

[0093] The several failure structures correspond to the several process types one by one, and the several process types have corresponding working machines, so that the working machine that generates defects can be quickly located according to the measured failure mode ratio, the problem can be quickly solved, and thus the cycle of defect analysis can be shortened and the production efficiency can be improved.

[0094] Please continue to refer to Figure 1 , and execute step S50: Obtain the measured failure mode ratio according to several failure modes.

[0095] Obtaining the measured failure mode ratio according to several failure modes includes: obtaining the number of various failure modes in the static random access memory; obtaining the measured failure mode ratio according to the number of various failure modes.

[0096] The various failure modes include a single failure mode SB (Single bitcell), a double failure mode DBR (Double bitcell row) in the row direction, a double failure mode DBR (Double bitcell column) in the column direction, and a four-fold failure mode QB (Quad bit cell) of the "field" grid.

[0097] The number of various failure modes in the static random access memory is obtained, that is, the number of single failure modes SB, the number of double failure modes DBR in the row direction, the number of double failure modes DBR in the column direction, and the number of quadruple failure modes QB in the Tianzi grid.

[0098] The measured failure mode ratio is the ratio of the number of single failure modes SB, the number of double failure modes DBR in the row direction, the number of double failure modes DBR in the column direction, and the number of quadruple failure modes QB in the grid.

[0099] Please continue to refer to Figure 1 , executing step S60: acquiring the failure structure corresponding to the measured failure mode ratio according to the failure mode ratio database.

[0100] Obtaining a failure structure corresponding to the measured failure mode ratio according to the failure mode ratio database includes: obtaining a failure mode ratio that is the same as the measured failure mode ratio in the failure mode ratio database; obtaining a failure structure corresponding to the failure mode ratio, wherein the failure structure corresponds to the measured failure mode ratio.

[0101] The failure mode ratio includes: a first proportional relationship, a second proportional relationship, a third proportional relationship, a fourth proportional relationship and a fifth proportional relationship. The failure mode ratio that is the same as the measured failure mode ratio is obtained in the failure mode ratio database, that is, the measured failure mode ratio is matched with the first proportional relationship, the second proportional relationship, the third proportional relationship, the fourth proportional relationship and the fifth proportional relationship. If the measured failure mode can match the first proportional relationship, the second proportional relationship, the third proportional relationship, the fourth proportional relationship and the fifth proportional relationship, then the failure mode ratio that is the same as the measured failure mode ratio is obtained.

[0102] Obtaining a failure structure corresponding to the failure mode ratio, that is, obtaining a corresponding failure structure according to the failure mode ratio, wherein the failure structure includes a first layer structure failure, a second layer structure failure, a third layer structure failure, a fourth layer structure failure, and a fifth layer structure failure.

[0103] In this embodiment, the defect detection method further includes: obtaining a process type corresponding to the failure structure according to the failure structure corresponding to the failure mode ratio; and obtaining a working machine corresponding to the process type according to the process type corresponding to the failure structure.

[0104] Therefore, the reaction machine can be directly located according to the measured failure mode ratio, and the problem can be dealt with in time, thus improving the efficiency of defect detection and analysis.

[0105] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A defect detection method, characterized in that: include: A static random access memory is provided, wherein the static random access memory comprises a plurality of storage units arranged in an array; Obtain a number of failed storage units, where one failed storage unit corresponds to one address; Acquire a plurality of failure modes according to addresses corresponding to the plurality of failed storage units; Providing a failure mode ratio database, the failure mode ratio database comprising a plurality of failure mode ratios and a plurality of failure structures, wherein the plurality of failure mode ratios correspond to the plurality of failure structures in a one-to-one manner; Obtaining a measured failure mode ratio according to a number of failure modes; The failure structure corresponding to the measured failure mode ratio is obtained according to the failure mode ratio database.

2. The defect detection method according to claim 1, characterized in that: The failure mode ratio database also includes: a number of process types corresponding to a number of failure structures, the number of failure structures and the number of process types correspond one to one; and the number of process types have corresponding working machines.

3. The defect detection method according to claim 2, characterized in that: Also includes: According to the failure structure corresponding to the failure mode ratio, obtaining the process type corresponding to the failure structure; According to the process type corresponding to the failure structure, a working machine corresponding to the process type is obtained.

4. The defect detection method according to claim 1, characterized in that: The failure modes include: a single failure mode, a double failure mode in the row direction, a double failure mode in the column direction, and a quadruple failure mode in a grid.

5. The defect detection method according to claim 4, characterized in that: The failure mode ratio includes: a first proportional relationship, a second proportional relationship, a third proportional relationship, a fourth proportional relationship and a fifth proportional relationship; the first proportional relationship is, single failure mode: double failure mode in the row direction: double failure mode in the column direction = 4:3:1; the second proportional relationship is, single failure mode: double failure mode in the row direction: double failure mode in the column direction: quadruple failure mode in a grid pattern = 4:2:2:1; the third proportional relationship is, double failure mode in the row direction: double failure mode in the column direction: quadruple failure mode in a grid pattern = 4:2:1; the fourth proportional relationship is, double failure mode in the column direction: quadruple failure mode in a grid pattern = 2:

1.

6. The defect detection method according to claim 5, characterized in that: The storage unit includes: a substrate; a bottom layer structure located on the substrate, a first layer structure located on the bottom layer structure, a second layer structure located on the first layer structure, a third layer structure located on the second layer structure, a fourth layer structure located on the third layer structure, and a fifth layer structure located on the fourth layer structure; the several failure structures include failure of the first layer structure, failure of the second layer structure, failure of the third layer structure, failure of the fourth layer structure, and failure of the fifth layer structure.

7. The defect detection method according to claim 6, characterized in that: The first proportional relationship corresponds to a failure of the first layer structure; the second proportional relationship corresponds to a failure of the second layer structure; The third proportional relationship corresponds to the failure of the third layer structure; The fourth proportional relationship corresponds to the fourth layer structural failure or the fifth layer structural failure.

8. The defect detection method according to claim 6, characterized in that: The bottom layer structure includes: a first fin, a second fin, a third fin and a fourth fin arranged in sequence along a first direction on a substrate, wherein the first fin, the second fin, the third fin and the fourth fin are parallel to the second direction, the first direction and the second direction are parallel to the substrate surface and the first direction and the second direction are perpendicular to each other; a first gate across the first fin and the second fin, a second gate across the fourth fin, the first gate and the second gate are parallel to the first direction and the extension directions of the first gate and the second gate are located on the same straight line; a third gate across the third fin and the fourth fin, a fourth gate across the first fin, the third gate and the fourth gate are parallel to the first direction and the extension directions of the third gate and the fourth gate are located on the same straight line; a first source-drain doped region, a second source-drain doped region and a third source-drain doped region located in the first fin, the first source The drain doping region and the second source-drain doping region are respectively located in the first fins on both sides of the first gate, and the second source-drain doping region and the third source-drain doping region are respectively located in the first fins on both sides of the fourth gate; the fourth source-drain doping region and the fifth source-drain doping region are located in the second fin, and the fourth source-drain doping region and the fifth source-drain doping region are respectively located in the second fins on both sides of the second gate; the sixth source-drain doping region and the seventh source-drain doping region are located in the third fin, and the sixth source-drain doping region and the seventh source-drain doping region are respectively located in the third fins on both sides of the third gate; the eighth source-drain doping region, the ninth source-drain doping region and the tenth source-drain doping region are located in the fourth fin, and the eighth source-drain doping region and the ninth source-drain doping region are respectively located in the fourth fins on both sides of the second gate, and the ninth source-drain doping region and the tenth source-drain doping region are respectively located in the fourth fins on both sides of the third gate.

9. The defect detection method according to claim 8, characterized in that: The first layer structure includes a plurality of discrete first plugs, and the plurality of first plugs are respectively located on: the first source-drain doping region; the second source-drain doping region; the third source-drain doping region; and the fourth source-drain doping region; on the seventh source-drain doping region; on the eighth source-drain doping region; on the ninth source-drain doping region; on the tenth source-drain doping region; on the fifth source-drain doped region and on the third gate on the second fin; on the sixth source-drain doped region and on the first gate on the third fin; on the fourth gate on the first fin; on the second gate on the fourth fin; the second layer structure includes a plurality of first metal layers parallel to the first direction, the plurality of first metal layers are respectively located on the first plug and electrically connected to the first plug, and the plurality of first metal layers are respectively located on: the first source-drain doped region; on the third source-drain doped region; on the fourth source-drain doped region; on the seventh source-drain doped region; Located on the eighth source-drain doping region; Located on the tenth source-drain doped region; located on the fourth gate on the first fin; located on the second gate on the fourth fin; located on the second source-drain doped region; located on the fifth source-drain doped region and the third gate on the second fin; located on the sixth source-drain doped region, the ninth source-drain doped region and the first gate on the third fin; the third layer structure includes a plurality of discrete second plugs, the plurality of the second plugs are respectively located on the first metal layer and electrically connected to the first metal layer, and the plurality of the second plugs are respectively located on: the first source-drain doped region; located on the third source-drain doped region; located on the fourth source-drain doped region; located on the seventh source-drain doped region; Located on the eighth source-drain doping region; Located on the tenth source-drain doped region; located on the second gate on the fourth fin; located on the fourth gate on the first fin.

10. The defect detection method according to claim 9, characterized in that: The fourth layer structure includes several second metal layers parallel to the second direction, and the several second metal layers are respectively located: on the first source and drain doped region; on the fourth gate on the first fin; on the second gate on the fourth fin; on the third source and drain doped region; on the fourth source and drain doped region and on the seventh source and drain doped region; on the eighth source and drain doped region; on the tenth source and drain doped region; the fifth layer structure includes several discrete third plugs, several of the third plugs are respectively located on the second metal layer and electrically connected to the second metal layer, and several of the third plugs are respectively located on the first source and drain doped region, on the tenth source and drain doped region, on the second gate on the fourth fin, and on the fourth gate on the first fin.

11. The defect detection method according to claim 1, characterized in that: Obtaining a measured failure mode ratio according to a number of failure modes includes: obtaining the number of various failure modes in the static random access memory; and obtaining a measured failure mode ratio according to the number of various failure modes.

12. The defect detection method according to claim 1, characterized in that: Obtaining a failure structure corresponding to the measured failure mode ratio according to the failure mode ratio database includes: obtaining a failure mode ratio that is the same as the measured failure mode ratio in the failure mode ratio database; obtaining a failure structure corresponding to the failure mode ratio, wherein the failure structure corresponds to the measured failure mode ratio.

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