Nonvolatile memory and electric leakage detection and repair method and system thereof

Abstract

The invention provides a nonvolatile memory and an electric leakage detection and repair method and system thereof, the nonvolatile memory is provided with an erasure address storage area, the electric leakage detection method comprises the following steps: after an erasure instruction is received, obtaining a physical block address corresponding to the erasure instruction, and writing the physical block address into the erasure address storage area; and during power-on reset, acquiring a physical block address in the erasure address storage area, and executing an electric leakage detection operation on a physical block corresponding to the physical block address. According to the nonvolatile memory disclosed by the invention, the erasure address is firstly recorded during erasure, whether an electric leakage phenomenon caused by over-erasure exists or not is detected aiming at the recorded erasure address during power-on, if the electric leakage phenomenon exists, repair is immediately carried out, scanning aiming at over-erasure after power-on can only be carried out aiming at the last stored erasure unit address, and the scanning efficiency is improved. The scanning time can be greatly shortened, the efficiency can be improved, meanwhile, the nonvolatile memory can still work reliably after being powered on in the case of sudden power failure, and the reliability of a chip is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a non-volatile memory and a leakage detection and repair method and system thereof. Background Art

[0002] Non-volatile memory is widely used in various electronic systems, communication equipment, industrial control and automotive electronics. Almost all devices that need to store large amounts of code or data require non-volatile memory, especially non-volatile memory that has the ability to save code and data after power failure.

[0003] For various systems, the storage and operation of the code cannot go wrong, and the non-volatile memory that stores the code cannot go wrong. Once the non-volatile memory goes wrong, the system may be affected or even cause the entire system to crash. In addition, some systems, such as industrial and automotive electronics applications, have very high reliability requirements. At this time, it is particularly necessary to handle the impact of power on and off. Specifically, even if the system loses power during erasing and the system does not protect the non-volatile memory well, it is still hoped that the non-volatile memory can work normally after powering on again.

[0004] The storage cells of the Nor Flash (a type of non-volatile memory) type non-volatile memory chip may be over-erased during the erase operation. The chip's built-in erase process will repair the over-erasure problem. If the non-volatile memory is over-erased during erasure, it will be repaired immediately. However, if there is a sudden power outage during erasure, or if there is a power outage before repair, some storage cells will be over-erased and the power will be lost before it can be repaired. The over-erased storage cells will have leakage. After power-on, the leakage of the over-erased storage cells will affect the reading results of normal storage cells, causing other normal storage cells to be unable to be accessed normally.

[0005] Existing leakage detection usually scans the entire chip memory cells after power-on to find the leaking memory cells. This method consumes a lot of time and leads to low efficiency. For large-capacity chips, it takes longer to scan the entire chip. Another leakage detection method is to randomly select some areas for scanning and detection. This method may not scan the over-erased area. Although subsequent operations may continue to expand the scanning range, the scanning results at the initial power-on are not complete, which brings risks to chip applications. Summary of the invention

[0006] The technical problem to be solved by the present disclosure is to overcome the defects of low efficiency of leakage detection and repair of non-volatile memory chips in the prior art and inability to ensure chip reliability, and to provide a non-volatile memory and a leakage detection and repair method and system thereof.

[0007] The present invention solves the above technical problems through the following technical solutions:

[0008] According to a first aspect of the present disclosure, a leakage detection method for a non-volatile memory is provided, wherein an erase address storage area is provided in the non-volatile memory, and the leakage detection method comprises:

[0009] After receiving the erase instruction, obtaining the physical block address corresponding to the erase instruction, and writing the physical block address into the erase address storage area;

[0010] During a power-on reset, the physical block address in the erase address storage area is obtained, and a leakage detection operation is performed on the physical block corresponding to the physical block address.

[0011] Preferably, the step of obtaining the physical block address in the erase address storage area and performing a leakage detection operation on the physical block corresponding to the physical block address includes:

[0012] Acquire a target physical block address in the erase address storage area; the target physical block address indicates that the corresponding physical block has not been subjected to leakage detection after the previous erasure;

[0013] A leakage detection operation is performed on the physical block corresponding to the target physical block address.

[0014] Preferably, the step of writing the physical block address into the erase address storage area comprises:

[0015] In response to the existence of a vacant storage sub-region in the erase address storage region, the physical block address is written into the vacant storage sub-region.

[0016] Preferably, in response to the existence of a vacant storage sub-area in the erase address storage area, the step of writing the physical block address into the vacant storage sub-area comprises:

[0017] Scanning the sub-regions in the erase address storage region in sequence in a preset scanning manner, and in response to no data being stored in the sub-regions, determining the sub-regions to be the free storage sub-regions;

[0018] The physical block address is written into the free storage sub-area.

[0019] Preferably, the step of sequentially scanning the sub-regions in the erase address storage region in a preset scanning manner, and in response to no data being stored in the sub-region, determining that the sub-region is the free storage sub-region comprises:

[0020] Starting from the sub-region corresponding to the lowest address in the erase address storage region, scanning to the sub-region corresponding to the highest address in sequence, and taking out the stored data in each sub-region in sequence;

[0021] In response to no data being stored in the sub-region, determining the sub-region to be the free storage sub-region;

[0022] In response to data being stored in the sub-area corresponding to the highest-order address, it is determined that the erase address storage area is full, an erase operation is performed on the erase address storage area to clear the stored data in the erase address storage area, and the step of starting from the sub-area corresponding to the lowest-order address in the erase address storage area, scanning in sequence toward the sub-area corresponding to the highest-order address, and taking out the stored data in each of the sub-areas in sequence is returned to execute.

[0023] Preferably, the erase address storage area includes a target storage area and at least one spare storage area;

[0024] The step of sequentially scanning the sub-regions in the erase address storage region in a preset scanning manner, and determining that the sub-region is the free storage sub-region in response to no data being stored in the sub-region comprises:

[0025] Starting from the sub-region corresponding to the lowest address in the target storage region, scanning in sequence to the sub-region corresponding to the highest address, and sequentially taking out the stored data in the sub-region;

[0026] In response to no data being stored in the sub-region, determining the sub-region to be the free storage sub-region;

[0027] In response to data being stored in the sub-area corresponding to the highest-order address, the current target storage area is marked as a storage area to be erased, and any one of the spare storage areas is used as the new target storage area, and the step of returning to execute the step of starting from the sub-area corresponding to the lowest-order address in the target storage area, scanning in sequence to the sub-area corresponding to the highest-order address, and taking out the stored data in the sub-area in sequence.

[0028] Preferably, the leakage detection method further includes:

[0029] When the non-volatile memory is in an idle state, an erasing operation is performed on the storage area to be erased to clear the stored data in the storage area to be erased, and after the erasing operation is completed, the storage area to be erased is marked as the spare storage area.

[0030] Preferably, the number of storage bits of the sub-area is greater than or equal to the number of bits of the physical block address.

[0031] Preferably, the step of obtaining the target physical block address in the erase address storage area includes:

[0032] Starting from the sub-region corresponding to the lowest address in the erase address storage region, sequentially scanning the sub-region corresponding to the highest address, in response to the first sub-region not storing data, taking out the stored data in the previous sub-region of the sub-region as the target physical block address;

[0033] or,

[0034] Starting from the sub-region corresponding to the highest address in the erase address storage region, scanning the sub-regions corresponding to the lowest address in sequence, and in response to the first sub-region storing data, taking out the stored data in the sub-region as the target physical block address;

[0035] or,

[0036] The erase address storage area is scanned segment by segment using a binary method, and the stored data in the sub-areas are taken out in sequence to obtain the target physical block address.

[0037] Preferably, when the number of storage bits of the sub-area in the erase address storage area is equal to the number of bits of the physical block address, the step of performing the leakage detection operation on the physical block corresponding to the target physical block address includes:

[0038] A leakage detection operation is performed on the physical block corresponding to the target physical block address and the physical block whose physical block address is all "1".

[0039] Preferably, when the number of storage bits of the sub-region is greater than the number of bits of the physical block address, the sub-region includes the physical block address storage bits and identification bits;

[0040] The step of writing the physical block address into the free storage sub-area comprises:

[0041] The physical block address is written into the physical block address storage bit in the spare storage sub-area, and identification data is written into the identification bit in the spare storage sub-area.

[0042] Preferably, when the number of storage bits of the sub-region is greater than the number of bits of the physical block address, the step of writing the physical block address into the free storage sub-region comprises:

[0043] Mapping the physical block address using a preset algorithm to obtain a mapping address of the storage bit number;

[0044] The mapping address is written into the storage space in the free storage sub-area.

[0045] Preferably, the preset algorithm includes a linear feedback shift register algorithm.

[0046] Preferably, when the number of storage bits of the sub-region is greater than the number of bits of the physical block address, the sub-region includes the physical block address storage bit, the first identification bit and the second identification bit;

[0047] The step of writing the physical block address into the free storage sub-area comprises:

[0048] Writing the physical block address into the physical block address storage bit in the spare storage sub-area, and writing a valid flag into the first flag bit in the spare storage sub-area;

[0049] When the erase instruction is completed and there is no leakage, an invalid flag is written into the second flag bit in the free storage sub-area.

[0050] Preferably, the step of obtaining the target physical block address in the erase address storage area includes:

[0051] The target physical block address in the erase address storage area is obtained according to the first identification bit and the second identification bit in each of the sub-areas.

[0052] Preferably, during the power-on reset, the leakage detection method further includes:

[0053] Acquiring the amount of stored data in the erase address storage area;

[0054] In response to the amount of stored data meeting a preset threshold, an erasing operation is performed on the erase address storage area to clear the stored data in the erase address storage area.

[0055] According to a second aspect of the present disclosure, a method for repairing leakage of a non-volatile memory is provided, the method comprising:

[0056] Using the leakage detection method described in the first aspect of the present disclosure to perform leakage detection on the physical blocks in the non-volatile memory;

[0057] In response to a power leakage condition existing in the physical block, a power leakage repair operation is performed on the physical block.

[0058] According to a third aspect of the present disclosure, a leakage detection system for a non-volatile memory is provided, wherein an erase address storage area is provided in the non-volatile memory, and the leakage detection system comprises a recording module and a detection module;

[0059] The recording module is used for obtaining the physical block address corresponding to the erase instruction after receiving the erase instruction, and writing the physical block address into the erase address storage area;

[0060] The detection module is used to obtain the physical block address in the erase address storage area during power-on reset, and perform a leakage detection operation on the physical block corresponding to the physical block address.

[0061] According to a fourth aspect of the present disclosure, a leakage repair system for a non-volatile memory is provided, the leakage repair system comprising the leakage detection system and the repair module according to the third aspect of the present disclosure;

[0062] The leakage detection system is used to perform leakage detection on the physical blocks in the non-volatile memory;

[0063] The repair module is used for performing a leakage repair operation on the physical block in response to a leakage condition existing in the physical block.

[0064] According to a fifth aspect of the present disclosure, a non-volatile memory is provided, wherein the non-volatile memory includes the leakage detection system described in the third aspect of the present disclosure, or the leakage repair system described in the fourth aspect of the present disclosure.

[0065] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0066] The positive improvement effect of the present disclosure is that the non-volatile memory first records the erase address when erasing, and when powered on, detects whether there is leakage caused by over-erasure based on the recorded erase address. If there is leakage, it is repaired immediately. After power-on, the scan for over-erasure can only be performed on the last stored erase unit address, which can greatly shorten the scanning time and improve efficiency. At the same time, it can ensure that the non-volatile memory can still work reliably after power-on in the face of sudden power failure, and the code and data already stored in the chip will not be affected, thereby improving the reliability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 is a flow chart of the leakage detection method of the non-volatile memory in Example 1;

[0068] Figure 2 It is a Vt (threshold voltage) distribution diagram of a storage cell in a non-volatile memory;

[0069] Figure 3 This is a first flow chart of step S2 in the leakage detection method of embodiment 1;

[0070] Figure 4 This is a second flow chart of step S2 in the leakage detection method of embodiment 1;

[0071] Figure 5 is a flow chart of the non-volatile memory in the erasing operation phase in Example 1;

[0072] Figure 6 This is a flow chart of the non-volatile memory in the power-on reset stage in Example 1;

[0073] Figure 7 is a flow chart of the leakage repair method of the non-volatile memory in Example 2;

[0074] Figure 8 This is a module schematic diagram of the leakage detection system of the non-volatile memory in Example 3;

[0075] Fig. 9 This is a module diagram of the leakage repair system of the non-volatile memory in Example 4. DETAILED DESCRIPTION

[0076] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0077] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

[0078] In the embodiments of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0079] Example 1

[0080] In a specific embodiment of the present disclosure, a leakage detection method for a non-volatile memory is provided. An erase address storage area is provided in the non-volatile memory, such as Figure 1 As shown, the leakage detection method includes:

[0081] S1. After receiving the erase instruction, obtain the physical block address corresponding to the erase instruction, and write the physical block address into the erase address storage area;

[0082] S2. Upon power-on reset, a physical block address in the erase address storage area is obtained, and a leakage detection operation is performed on a physical block corresponding to the physical block address.

[0083] Specifically, Figure 2 As shown in the figure, f1 and f2 are the normal Vt distribution diagrams of the storage cell (cell), where the horizontal axis represents the voltage value of the storage cell, the vertical axis represents the number of storage cells at this voltage value, and the right side of the read voltage is 0 cell, and the left side is 1 cell. The erase operation changes the storage cell in the f2 state (high Vt distribution) to the f1 state (low Vt distribution), but the storage cell that is in the same physical block area as the storage cell performing the erase operation and is originally in the low Vt state will be affected, resulting in a lower Vt, and the distribution form of f3 will appear. Among them, the storage cell on the far left of f3 (left side of the coordinate zero point) will cause leakage during the read operation due to the low Vt, which will affect the read results of other storage cells, that is, over-erasure occurs.

[0084] Considering that the leakage effect of over-erasure only affects the same physical block, an erase address storage area is set in Nor Flash. After receiving the erase instruction, the physical block address of the storage unit corresponding to the erase instruction is obtained through step S1, and the physical block address is written into the erase address storage area; when the power is on and reset, the physical block address in the erase address storage area is obtained through step S2 to perform leakage detection on the physical block corresponding to the physical block address, which ensures leakage detection of all areas where over-erasure may occur, and does not require full chip scanning, thereby improving detection efficiency while ensuring chip reliability. It should be noted that this embodiment is explained by taking Nor Flash as an example, but it should not be limited to being applicable only to Nor Flash.

[0085] This specific implementation only performs an erase scan on the physical block where the storage unit that has performed the erase operation is located, which can greatly shorten the scan time and improve the leakage detection efficiency. At the same time, it can ensure that the non-volatile memory can still work reliably after power-on in the face of a sudden power outage, and the code and data already stored in the chip will not be affected, thereby improving the reliability of the chip.

[0086] In a specific embodiment, Figure 3 As shown, step S2 includes:

[0087] S21, obtaining a target physical block address in the erase address storage area; the target physical block address indicates that the corresponding physical block has not been subjected to leakage detection after the previous erase;

[0088] S22. Perform a leakage detection operation on the physical block corresponding to the target physical block address.

[0089] Specifically, since the non-volatile memory chip has a built-in over-erasure repair system for the erasing process, if there is over-erasure during erasing, repair will be performed immediately. If there is no sudden power outage during the entire erasing process (including erasing and repair), the physical block where the storage unit performing the erasing operation is located will not have leakage. Regardless of whether the entire erasing process has been completed, as long as the erase instruction is received, the physical block address corresponding to the erase instruction will be written into the erase address storage area. Therefore, the physical block address corresponding to the physical block that will not have leakage will also be written into the erase address storage area.

[0090] In order to further improve the leakage detection efficiency, it is not necessary to perform leakage detection on the physical blocks corresponding to each physical block address stored in the erase address storage area. Instead, leakage detection is only performed on the physical blocks corresponding to the target physical block addresses that have not been leakage detected after the previous erase, thereby greatly shortening the scanning time and further improving the leakage detection efficiency. At the same time, it can also ensure that the non-volatile memory can still work reliably after power-on in the face of sudden power failure, and the code and data already stored in the chip will not be affected, thereby improving the reliability of the chip.

[0091] In a specific implementation, step S1 includes:

[0092] S11. In response to the existence of a free storage sub-region in the erase address storage region, write a physical block address into the free storage sub-region.

[0093] Specifically, after obtaining the physical block address corresponding to the erase instruction, a free storage sub-region that has not stored data can be searched in the erase address storage region, and then the obtained physical block address can be written into the free storage sub-region for storage.

[0094] In a specific implementation, step S11 includes:

[0095] S111, sequentially scanning sub-regions in the erase address storage region using a preset scanning method, and in response to no data being stored in the sub-region, determining that the sub-region is a free storage sub-region;

[0096] S112. Write the physical block address into the free storage sub-area.

[0097] Specifically, a preset scanning method can be used, for example, scanning from the lowest address of the erase address storage area to the highest address in sequence, obtaining the storage data of each sub-area in the erase address storage area, and determining whether the corresponding sub-area is a vacant storage sub-area by judging whether data is stored.

[0098] In a specific implementation, step S111 specifically includes:

[0099] S11111, starting from the sub-region corresponding to the lowest address in the erase address storage region, scan the sub-region corresponding to the highest address in sequence, and take out the stored data in each sub-region in sequence;

[0100] S11112. In response to no data being stored in the sub-region, determining that the sub-region is a free storage sub-region;

[0101] S11113. In response to data being stored in the sub-area corresponding to the highest address, it is determined that the erase address storage area is full, an erase operation is performed on the erase address storage area to clear the stored data in the erase address storage area, and the process returns to step S11111.

[0102] Specifically, starting from the sub-region corresponding to the lowest address in the erase address storage area, the stored data in each sub-region is taken out in turn for judgment. If no data is stored, it can be determined that the corresponding sub-region is a free storage sub-region, and the obtained physical block address can be written into the sub-region. For example, the physical block address is a four-bit address, and the erase address storage area is composed of 64 four-bit sub-regions. Then the erase address storage area is a 4*64=256-bit storage space, which can record 64 physical block addresses corresponding to the erase instructions. After obtaining the physical block address corresponding to the erase instruction, the erase address storage area is scanned from address 0, and a sub-region (i.e., four-bit data) is taken out each time for judgment. When the four-bit data is all "1", it means that the content of the sub-region corresponding to the four bits is empty, and the physical block address can be written into the sub-region. Of course, the erase address storage area can also be a 4*512=2048-bit storage space, or any other structure, which is not limited in this specific implementation.

[0103] When data is also stored in the sub-area corresponding to the highest address, it means that the erase address storage area is full. You need to first perform an erase operation on the erase address storage area to clear all erase address contents written in the erase address storage area, and then write the acquired physical block address into the erase address storage area. Still taking the physical block address as a four-bit address and the erase address storage area as a 256-bit storage space as an example, start scanning from address 0. When the four-bit data of the last sub-area (i.e., address 252-255) taken out is not all "1", it means that the erase address storage area is full. Then erase all erase address contents written in the erase address storage area, and then write the acquired physical block address into the first sub-area (i.e., address 0-3).

[0104] Since the programming operation of the non-volatile memory chip can only write "1" to "0", if "0" needs to be changed to "1", a time-consuming erase operation is required. Therefore, when the storage space of the erase address storage area is large enough, most of the time only programming operations are required, and the efficiency of recording erase addresses can be greatly improved.

[0105] In a specific embodiment, Figure 4 As shown, step S2 also includes:

[0106] S23, obtaining the amount of stored data in the erase address storage area;

[0107] S24. In response to the amount of stored data meeting a preset threshold, performing an erase operation on the erase address storage area to clear the stored data in the erase address storage area.

[0108] Specifically, after completing the scan of the erase address storage area in the power-on reset process, if it is detected that the erase address storage area is full, or the physical block address content stored in the erase address storage area has reached a certain proportion, for example, 80% (the specific proportion can be set according to actual needs), then the erase address storage area is directly erased to clear the physical block address stored in the erase address storage area, thereby reducing the possibility of the erase address storage area being full during erasing, saving the time occupied by performing erasure in the working state of the non-volatile memory, and improving the efficiency of recording the erase address.

[0109] In another specific embodiment, the erase address storage area includes a target storage area and at least one spare storage area;

[0110] Step S111 includes:

[0111] S11121, starting from the sub-region corresponding to the lowest address in the target storage region, scan the sub-region corresponding to the highest address in sequence, and take out the stored data in the sub-region in sequence;

[0112] S11122. In response to no data being stored in the sub-region, determining that the sub-region is a free storage sub-region;

[0113] S11123. In response to data being stored in the sub-area corresponding to the highest address, the current target storage area is marked as a storage area to be erased, and any spare storage area is used as a new target storage area, and the process returns to step S11121.

[0114] In a specific implementation, the leakage detection method further includes: when the non-volatile memory is in an idle state, performing an erasing operation on the storage area to be erased to clear the stored data in the storage area to be erased, and marking the storage area to be erased as a spare storage area after the erasing operation is completed.

[0115] Specifically, in order to further improve the efficiency of recording erase addresses, the erase address storage area can be divided into two or more storage areas. When one storage area is full, the obtained physical block address is written to another empty storage area. For the specific method of determining the available storage sub-areas, please refer to the relevant instructions of the aforementioned steps S11111-S11113. This specific implementation will not be repeated here.

[0116] When the non-volatile memory is in an idle state, an erase operation is performed on the full storage area to clear the erase address content written in the full storage area, and the storage area is used as an empty storage area. When other storage areas are full, the storage area is written again, and this cycle is repeated, thereby reducing the possibility of encountering a full erase address storage area during erasing, and saving the time occupied by performing erasure in the working state of the non-volatile memory.

[0117] This specific implementation method sets up multiple storage spaces for erase addresses, writes the erase addresses to another storage space when one storage space is full, and uses the idle state of the non-volatile memory to perform the erase operation, thereby saving the time occupied by performing the erase operation in the working state of the non-volatile memory and further improving the efficiency of recording the erase address.

[0118] In a specific implementation, step S21 includes:

[0119] Starting from the sub-region corresponding to the lowest address in the erase address storage region, scanning the sub-region corresponding to the highest address in sequence, and in response to the first sub-region not storing data, taking out the storage data in the previous sub-region of the sub-region as the target physical block address;

[0120] or,

[0121] Starting from the sub-region corresponding to the highest address in the erase address storage region, scanning the sub-regions corresponding to the lowest address in sequence, and in response to the first sub-region storing data, taking out the stored data in the sub-region as the target physical block address;

[0122] or,

[0123] The erase address storage area is scanned segment by segment using a binary method, and the storage data in the sub-areas are taken out in sequence to obtain the target physical block address.

[0124] Specifically, since the physical block address obtained each time an erase instruction is received is usually written into the erase address storage area in sequence, and the non-volatile memory chip will immediately perform repairs if there is an erase phenomenon during erasure, the physical block corresponding to the storage unit that performs the erase operation before power failure may be the main one that may experience leakage, that is, the physical block corresponding to the physical block address last written into the erase address storage area.

[0125] Based on this, we can start from the sub-area corresponding to the lowest address in the erase address storage area, scan in sequence to the sub-area corresponding to the highest address, and obtain the physical block corresponding to the last physical block address that is not all "1" for leakage detection; we can also start from the sub-area corresponding to the highest address in the erase address storage area, scan in sequence to the sub-area corresponding to the lowest address, and obtain the physical block corresponding to the first physical block address that is not all "1" for leakage detection; we can also use algorithms such as binary search to perform segmented scanning, obtain the physical block corresponding to the physical block address last written in the erase address storage area for leakage detection, so as to quickly find the last written physical block address, and further improve the efficiency of leakage detection.

[0126] In a specific implementation, the number of storage bits of the sub-region is greater than or equal to the number of bits of the physical block address.

[0127] Specifically, when storing the physical block address, the number of storage bits corresponding to each sub-region in the erase address storage region can be set to be the same as the number of bits of the physical block address, or the number of storage bits corresponding to each sub-region can be set to be greater than the number of bits of the physical block address. For example, if the physical block address is a four-bit address, each sub-region can be set to a four-bit address storage space for storing a four-bit physical block address, or it can be set to a five-bit address storage space, with four bits storing the physical block address and one bit as an identification bit, or it can be set to a six-bit address storage space, with four bits storing the physical block address and two bits as identification bits. Of course, each sub-region can also be set to an address space with more bits, and only a few bits are selected to store the physical block address, and the other bits are used as flag bits or reserved for standby use, which is not limited in this specific implementation.

[0128] In a specific implementation, when the number of storage bits of the sub-area in the erase address storage area is equal to the number of bits of the physical block address, step S22 includes:

[0129] The leakage detection operation is performed on the physical block corresponding to the target physical block address and the physical block whose physical block address is all "1".

[0130] Specifically, when the number of storage bits of a sub-region is equal to the number of bits of a physical block address, for example, for 8 physical blocks, the physical block address is a three-bit address, and each sub-region is also a three-bit address storage space, wherein the physical block address of the three-bit address can identify eight physical block addresses, and the last physical block address is "111". Since the default value of an empty sub-region is "1", when the physical block address last written into the erase address storage area is "111", the erase address storage area is scanned after power-on, and the address is considered to be an empty sub-region, and the previously written physical block address is considered to be the last written physical block address, which results in the inability to perform leakage detection on the "111" physical block where leakage may occur, bringing risks to chip applications.

[0131] Therefore, in order to avoid the above situation, after each power-on, in addition to performing leakage detection on the physical block corresponding to the scanned target physical block address, leakage detection is also performed on the "111" physical block to ensure the reliability of the chip.

[0132] In a specific implementation, when the number of storage bits of the sub-region is greater than the number of bits of the physical block address, the sub-region includes a physical block address storage bit and an identification bit;

[0133] Step S112 includes: writing the physical block address into the physical block address storage bit in the free storage sub-area, and writing the identification data into the identification bit in the free storage sub-area.

[0134] Specifically, the number of storage bits in the sub-area can be set to be greater than the number of bits of the physical block address. For example, an identification bit is added based on the number of bits of the physical block address. Each time the physical block address is written into a vacant storage sub-area, "0" is written into the identification bit to indicate that the physical block address is stored in the sub-area. In this way, the situation where the full "1" address cannot be identified will not occur. Therefore, leakage detection can be performed only on the physical block corresponding to the physical block address in the last write-erase address storage area scanned, so as to further improve the efficiency of leakage detection.

[0135] In another specific implementation, when the number of storage bits of the sub-region is greater than the number of bits of the physical block address, step S112 includes:

[0136] The physical block address is mapped using a preset algorithm to obtain a mapping address of the storage bit number;

[0137] Write the mapping address to the storage space in the free storage sub-region.

[0138] Specifically, when the number of storage bits of the sub-area can be set to be greater than the number of bits of the physical block address, the identification bit may not be fixed, but the physical block address may be mapped to a mapping address that is not all "1" by mapping. For example, a linear feedback shift register (LFSR) algorithm may be used to map the three-bit physical block address to a four-bit mapping address and write it into the four-bit storage space in the sub-area, thereby avoiding the recording of the all-"1" address.

[0139] In a specific implementation, when the number of storage bits of the sub-region is greater than the number of bits of the physical block address, the sub-region includes a physical block address storage bit, a first identification bit, and a second identification bit;

[0140] Step S112 includes:

[0141] Writing the physical block address into the physical block address storage bit in the free storage sub-area, and writing the valid flag into the first flag bit in the free storage sub-area;

[0142] When the erase instruction is completed and there is no leakage, an invalid flag is written into the second flag bit of the free storage sub-area;

[0143] Step S21 includes: acquiring a target physical block address in the erase address storage area according to a first identification bit and a second identification bit in each sub-area.

[0144] Specifically, the number of storage bits in the sub-area can be set to be greater than the number of bits in the physical block address. For example, a first identification bit and a second identification bit are added based on the number of bits in the physical block address, and the first identification bit is used as a valid address bit, and the second identification bit is used as an invalid identification bit. When an erase operation instruction is received, the physical block of the storage unit that performs the erase operation is obtained and written into the vacant storage sub-area, and "0" is written in the first identification bit, indicating that the physical block address is valid; when the erase operation is completed, if there is no power failure, the over-erase repair of the erase process built into the non-volatile memory chip will perform leakage detection and repair on the physical block, therefore, the second identification bit is written to "0", indicating that the physical block address is invalid, and there is no need to perform leakage detection on the address again when power is on; and if there is a power failure during the erase operation, or before the repair, the second identification bit will not be written to "0". Therefore, when power is turned on, the target physical block address on which the leakage detection operation needs to be performed can be determined based on the first identification bit and the second identification bit in each sub-area. Only the physical block corresponding to the physical block address stored in the sub-area where the first identification bit is "0" and the second identification bit is "1" needs to perform the leakage detection operation when power is turned on, thereby further improving the efficiency of leakage detection.

[0145] In a specific example, if Figure 5As shown, when an erase instruction is received, the physical block address PB corresponding to the erase instruction is obtained, and the current address unit CAU of the erase address storage area is set to 0 to start scanning from the lowest bit of the erase address storage area, wherein the number of bits of each address unit AU can be the same as the number of bits of the physical block address, or can be greater than the number of bits of the physical block address. For example, if AU is a four-bit storage space, AU0 corresponds to the 0th-3rd bit storage space, AU1 corresponds to the 4th-7th bit storage space, and so on; if CAU is not greater than the last address unit LAU, the physical block address stored in CAU is obtained, and it is determined whether the physical block address in CAU is all "1". If so, it is determined that the storage space corresponding to CAU is empty, and the physical block address PB is written into the storage space corresponding to CAU, otherwise, the next address unit is used as CAU, and the judgment is continued; if CAU is greater than LAU, the erase operation is first performed on the erase address storage area, and CAU is set to 0, and the physical block address stored in CAU is re-obtained for judgment.

[0146] Another example Figure 6 As shown, at power-on reset, CAU is set equal to LAU to start scanning from the highest bit of the erase address storage area, obtain the physical block address stored in CAU, and determine whether the physical block address in CAU is all "1". If so, it means that the storage space corresponding to CAU is empty, and the previous address unit is used as CAU to re-obtain the physical block address stored in CAU for judgment. If CAU is less than 0, it means that no physical block address is stored in the erase address storage area; if the physical block address in CAU is not all "1", a leakage detection operation is performed on the physical block corresponding to the physical block address in CAU; in order to avoid missing all "1" physical blocks, leakage detection of all "1" physical blocks is performed regardless of whether there is a situation where the physical block address in CAU is not all "1".

[0147] By combining the erase process with the power-on process, the impact of over-erasure leakage caused by sudden power failure can be effectively resolved. At the same time, scanning and repairing during the power-on process can eliminate the impact of sudden power failure on the erase process. The recording of the erase address helps to efficiently scan the power-on process, which has less impact on the power-on time.

[0148] In this embodiment, the non-volatile memory first records the erase address when erasing. When power is turned on, the recorded erase address is detected to see if there is leakage caused by over-erasure. If there is leakage, it is repaired immediately. After power-on, the scan for over-erasure can only be performed on the last stored erase unit address, which can greatly shorten the scan time and improve efficiency. At the same time, it can ensure that the non-volatile memory can still work reliably after power-on in the face of sudden power failure, and the code and data stored in the chip will not be affected, thereby improving the reliability of the chip.

[0149] Example 2

[0150] In a specific embodiment of the present disclosure, a leakage repair method for a non-volatile memory is provided. The leakage repair method is implemented based on the leakage detection method described in any of the above embodiments, such as Figure 7 As shown, the leakage repair method includes:

[0151] S3, using a leakage detection method to perform leakage detection on the physical blocks in the non-volatile memory;

[0152] S4. In response to a power leakage condition existing in the physical block, a power leakage repair operation is performed on the physical block.

[0153] Specifically, when it is detected that a physical block in the non-volatile memory has a leakage condition, that is, an over-erasure phenomenon exists, a leakage repair operation is immediately performed on the physical block to ensure the reliability of the non-volatile memory.

[0154] In this embodiment, the non-volatile memory first records the erase address when erasing. When power is turned on, the recorded erase address is detected to see if there is leakage caused by over-erasure. If there is leakage, it is repaired immediately. After power-on, the scan for over-erasure can only be performed on the last stored erase unit address, which can greatly shorten the scan time and improve efficiency. At the same time, it can ensure that the non-volatile memory can still work reliably after power-on in the face of sudden power failure, and the code and data stored in the chip will not be affected, thereby improving the reliability of the chip.

[0155] Example 3

[0156] In a specific embodiment of the present disclosure, a non-volatile memory leakage detection system 100 is provided. Figure 8 As shown, the non-volatile memory is provided with an erase address storage area, and the leakage detection system 100 includes a recording module 101 and a detection module 102;

[0157] The recording module 101 is used to obtain the physical block address corresponding to the erase instruction after receiving the erase instruction, and write the physical block address into the erase address storage area;

[0158] The detection module 102 is used to obtain the physical block address in the erase address storage area during power-on reset, and perform a leakage detection operation on the physical block corresponding to the physical block address.

[0159] As for the system embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The system embodiment described above is only illustrative, wherein the units described as separate components may or may not be physically separated, and the components as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the disclosed solution.

[0160] In this embodiment, the non-volatile memory first records the erase address when erasing. When power is turned on, the recorded erase address is detected to see if there is leakage caused by over-erasure. If there is leakage, it is repaired immediately. After power-on, the scan for over-erasure can only be performed on the last stored erase unit address, which can greatly shorten the scan time and improve efficiency. At the same time, it can ensure that the non-volatile memory can still work reliably after power-on in the face of sudden power failure, and the code and data stored in the chip will not be affected, thereby improving the reliability of the chip.

[0161] Example 4

[0162] In a specific embodiment of the present disclosure, a non-volatile memory leakage repair system is provided, such as Fig. 9 As shown, the leakage repair system includes the leakage detection system 100 and the repair module 200 described in any of the above embodiments;

[0163] The leakage detection system 100 is used to perform leakage detection on physical blocks in a non-volatile memory;

[0164] The repair module 200 is used for performing a leakage repair operation on the physical block in response to a leakage situation in the physical block.

[0165] As for the system embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The system embodiment described above is only illustrative, wherein the units described as separate components may or may not be physically separated, and the components as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the disclosed solution.

[0166] In this embodiment, the non-volatile memory first records the erase address when erasing. When power is turned on, the recorded erase address is detected to see if there is leakage caused by over-erasure. If there is leakage, it is repaired immediately. After power-on, the scan for over-erasure can only be performed on the last stored erase unit address, which can greatly shorten the scan time and improve efficiency. At the same time, it can ensure that the non-volatile memory can still work reliably after power-on in the face of sudden power failure, and the code and data stored in the chip will not be affected, thereby improving the reliability of the chip.

[0167] Example 5

[0168] According to a fifth aspect of the present disclosure, a non-volatile memory is provided, which includes the leakage detection system described in any one of the above embodiments, or the leakage repair system described in any one of the above embodiments.

[0169] Specifically, the non-volatile memory may include various types such as Nor Flash, magnetic memory, phase change memory, ferroelectric memory, and resistive memory.

[0170] In this embodiment, the non-volatile memory first records the erase address when erasing. When power is turned on, the recorded erase address is detected to see if there is leakage caused by over-erasure. If there is leakage, it is repaired immediately. After power-on, the scan for over-erasure can only be performed on the last stored erase unit address, which can greatly shorten the scan time and improve efficiency. At the same time, it can ensure that the non-volatile memory can still work reliably after power-on in the face of sudden power failure, and the code and data stored in the chip will not be affected, thereby improving the reliability of the chip.

[0171] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A method for detecting leakage of a non-volatile memory, characterized in that: The non-volatile memory is provided with an erase address storage area, and the leakage detection method comprises: After receiving the erase instruction, obtaining the physical block address corresponding to the erase instruction, and writing the physical block address into the erase address storage area; During a power-on reset, the physical block address in the erase address storage area is obtained, and a leakage detection operation is performed on the physical block corresponding to the physical block address.

2. The leakage detection method according to claim 1, characterized in that: The step of obtaining the physical block address in the erase address storage area and performing a leakage detection operation on the physical block corresponding to the physical block address includes: Acquire a target physical block address in the erase address storage area; the target physical block address indicates that the corresponding physical block has not been subjected to leakage detection after the previous erasure; A leakage detection operation is performed on the physical block corresponding to the target physical block address.

3. The leakage detection method according to claim 2, characterized in that: The step of writing the physical block address into the erase address storage area comprises: In response to the existence of a vacant storage sub-region in the erase address storage region, the physical block address is written into the vacant storage sub-region.

4. The leakage detection method according to claim 3, characterized in that: In response to the existence of a free storage sub-area in the erase address storage area, the step of writing the physical block address into the free storage sub-area comprises: Scanning the sub-regions in the erase address storage region in sequence in a preset scanning manner, and in response to no data being stored in the sub-regions, determining the sub-regions to be the free storage sub-regions; The physical block address is written into the free storage sub-area.

5. The leakage detection method according to claim 4, characterized in that: The step of sequentially scanning the sub-regions in the erase address storage region in a preset scanning manner, and determining that the sub-region is the free storage sub-region in response to no data being stored in the sub-region comprises: Starting from the sub-region corresponding to the lowest address in the erase address storage region, scanning to the sub-region corresponding to the highest address in sequence, and taking out the stored data in each sub-region in sequence; In response to no data being stored in the sub-region, determining the sub-region to be the free storage sub-region; In response to data being stored in the sub-area corresponding to the highest-order address, it is determined that the erase address storage area is full, an erase operation is performed on the erase address storage area to clear the stored data in the erase address storage area, and the step of starting from the sub-area corresponding to the lowest-order address in the erase address storage area, scanning in sequence toward the sub-area corresponding to the highest-order address, and taking out the stored data in each of the sub-areas in sequence is returned to execute.

6. The leakage detection method according to claim 4, characterized in that: The erase address storage area includes a target storage area and at least one spare storage area; The step of sequentially scanning the sub-regions in the erase address storage region in a preset scanning manner, and determining that the sub-region is the free storage sub-region in response to no data being stored in the sub-region comprises: Starting from the sub-region corresponding to the lowest address in the target storage region, scanning in sequence to the sub-region corresponding to the highest address, and sequentially taking out the stored data in the sub-region; In response to no data being stored in the sub-region, determining the sub-region to be the free storage sub-region; In response to data being stored in the sub-area corresponding to the highest-order address, the current target storage area is marked as a storage area to be erased, and any one of the spare storage areas is used as the new target storage area, and the step of returning to execute the step of starting from the sub-area corresponding to the lowest-order address in the target storage area, scanning toward the sub-area corresponding to the highest-order address in sequence, and taking out the stored data in the sub-area in sequence.

7. The leakage detection method according to claim 6, characterized in that: The leakage detection method further comprises: When the non-volatile memory is in an idle state, an erasing operation is performed on the storage area to be erased to clear the stored data in the storage area to be erased, and after the erasing operation is completed, the storage area to be erased is marked as the spare storage area.

8. The leakage detection method according to claim 4, characterized in that: The number of storage bits of the sub-area is greater than or equal to the number of bits of the physical block address.

9. The leakage detection method according to claim 8, characterized in that: The step of obtaining the target physical block address in the erase address storage area comprises: Starting from the sub-region corresponding to the lowest address in the erase address storage region, sequentially scanning the sub-region corresponding to the highest address, in response to the first sub-region not storing data, taking out the stored data in the previous sub-region of the sub-region as the target physical block address; or, Starting from the sub-region corresponding to the highest address in the erase address storage region, scanning the sub-regions corresponding to the lowest address in sequence, and in response to the first sub-region storing data, taking out the stored data in the sub-region as the target physical block address; or, The erase address storage area is scanned segment by segment using a binary method, and the stored data in the sub-areas are taken out in sequence to obtain the target physical block address.

10. The leakage detection method according to claim 9, characterized in that: When the number of storage bits of the sub-area in the erase address storage area is equal to the number of bits of the physical block address, the step of performing a leakage detection operation on the physical block corresponding to the target physical block address includes: A leakage detection operation is performed on the physical block corresponding to the target physical block address and the physical block whose physical block address is all "1".

11. The leakage detection method according to claim 8 or 9, characterized in that: When the number of storage bits of the sub-region is greater than the number of bits of the physical block address, the sub-region includes the physical block address storage bits and identification bits; The step of writing the physical block address into the free storage sub-area comprises: The physical block address is written into the physical block address storage bit in the spare storage sub-area, and identification data is written into the identification bit in the spare storage sub-area.

12. The leakage detection method according to claim 8, characterized in that: When the number of storage bits of the sub-area is greater than the number of bits of the physical block address, the step of writing the physical block address into the free storage sub-area includes: Mapping the physical block address using a preset algorithm to obtain a mapping address of the storage bit number; The mapping address is written into the storage space in the free storage sub-area.

13. The leakage detection method according to claim 12, characterized in that: The preset algorithm includes a linear feedback shift register algorithm.

14. The leakage detection method according to claim 8, characterized in that: When the number of storage bits of the sub-region is greater than the number of bits of the physical block address, the sub-region includes the physical block address storage bit, the first identification bit and the second identification bit; The step of writing the physical block address into the free storage sub-area comprises: Writing the physical block address into the physical block address storage bit in the spare storage sub-area, and writing a valid flag into the first flag bit in the spare storage sub-area; When the erase instruction is completed and there is no leakage, an invalid flag is written into the second flag bit in the free storage sub-area.

15. The leakage detection method according to claim 14, characterized in that: The step of obtaining the target physical block address in the erase address storage area comprises: The target physical block address in the erase address storage area is obtained according to the first identification bit and the second identification bit in each of the sub-areas.

16. The leakage detection method according to any one of claims 1 to 5, characterized in that: During the power-on reset, the leakage detection method further includes: Acquiring the amount of stored data in the erase address storage area; In response to the amount of stored data meeting a preset threshold, an erasing operation is performed on the erase address storage area to clear the stored data in the erase address storage area.

17. A method for repairing leakage of a non-volatile memory, characterized in that: The leakage repair method comprises: Perform leakage detection on the physical blocks in the non-volatile memory using the leakage detection method described in any one of claims 1 to 16; In response to a power leakage condition existing in the physical block, a power leakage repair operation is performed on the physical block.

18. A leakage detection system for a non-volatile memory, characterized in that: The non-volatile memory is provided with an erase address storage area, and the leakage detection system includes a recording module and a detection module; The recording module is used for obtaining the physical block address corresponding to the erase instruction after receiving the erase instruction, and writing the physical block address into the erase address storage area; The detection module is used to obtain the physical block address in the erase address storage area during power-on reset, and perform a leakage detection operation on the physical block corresponding to the physical block address.

19. A non-volatile memory leakage repair system, characterized in that: The leakage repair system comprises the leakage detection system and repair module as claimed in claim 18; The leakage detection system is used to perform leakage detection on the physical blocks in the non-volatile memory; The repair module is used for performing a leakage repair operation on the physical block in response to a leakage condition existing in the physical block.

20. A non-volatile memory, characterized in that: The non-volatile memory includes the leakage detection system as claimed in claim 18, or the leakage repair system as claimed in claim 19.

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