Epitaxial wafer and preparation method thereof

Abstract

The invention provides an epitaxial wafer and a preparation method thereof, and the preparation method comprises the steps: introducing first hydrogen and hydrogen chloride gas into an epitaxial reaction chamber, and etching the inner wall of the epitaxial reaction chamber and the surface of a pedestal, the first hydrogen having a first flow Q1L / min; after the introduction of the hydrogen chloride gas is ended, cooling for the first time, keeping the flow of the first hydrogen at a first flow Q1L / min, introducing gaseous trichlorosilane into the epitaxial reaction cavity, and depositing an intrinsic silicon layer on the surface of the base; after the introduction of the gaseous trichlorosilane is finished, adjusting the flow of the first hydrogen to be second flow Q2L / min, and cooling for the second time; placing the substrate in an epitaxial reaction cavity, heating, and growing an epitaxial layer on the surface of the substrate; wherein Q1 is less than Q2. According to the preparation method, the overall process time is shortened, meanwhile, the front particles and the silicon stacking condition of the wafer reach the ideal state, and the quality of the epitaxial wafer is guaranteed while the preparation efficiency is improved.

Description

Technical Field

[0001] The present application belongs to the technical field of silicon-on-insulator, and specifically relates to an epitaxial wafer and a method for preparing the same. Background Art

[0002] In the field of semiconductor device manufacturing, a layer of single crystal silicon is usually formed on a silicon substrate as an epitaxial layer. The epitaxial layer can be subsequently doped with ions to form an implanted base region, an emitter region, and the like. In the process of heavily doped substrate epitaxy, in order to solve the problem of self-doping effect in epitaxial processing, it is usually necessary to take a series of steps to improve the quality and stability of the material before the process of the epitaxial film. One of the common operations is to grow a layer of intrinsic silicon film that meets the film thickness requirements on the surface of the base after the base is cooled to the crystal growth temperature. By controlling the temperature to stabilize, the diffusion of impurities between the substrate and the epitaxial layer is eliminated or reduced to improve the quality and uniformity of the doped layer and ensure the consistency of the structure and performance of the epitaxial film. However, the process of controlling the temperature will lead to a decrease in the efficiency of the wafer processing process.

[0003] Therefore, in the prior art, there is a need for a process that can reduce the processing steps and improve the impact of wafer processing efficiency while ensuring the quality and stability of the epitaxial layer. Summary of the invention

[0004] The present invention provides an epitaxial wafer and a preparation method thereof, aiming to solve the problems of long time consumption and low efficiency of epitaxial wafer preparation process in the existing semiconductor device manufacturing process.

[0005] On the one hand, an embodiment of the present application provides a method for preparing an epitaxial wafer, comprising the following steps:

[0006] Providing an epitaxial reaction chamber, the epitaxial reaction chamber including a susceptor, introducing a first hydrogen gas and a hydrogen chloride gas into the epitaxial reaction chamber, etching an inner wall of the epitaxial reaction chamber and a surface of the susceptor, wherein the first hydrogen gas has a first flow rate of Q1 L / min;

[0007] End the introduction of the hydrogen chloride gas, perform the first temperature reduction, maintain the flow rate of the first hydrogen gas at a first flow rate of Q1 L / min, and simultaneously introduce gaseous trichlorosilane into the epitaxial reaction chamber to deposit an intrinsic silicon layer on the surface of the base;

[0008] The introduction of the gaseous trichlorosilane is terminated, the flow rate of the first hydrogen is adjusted to a second flow rate of Q2 L / min, and the temperature is lowered for the second time;

[0009] Providing a substrate, placing the substrate in an epitaxial reaction chamber, heating the substrate, and growing an epitaxial layer on the surface of the substrate;

[0010] Among them, Q1<Q2.

[0011] In some embodiments, the first flow rate Q1 L / min and the second flow rate Q2 L / min satisfy:

[0012] Q1:Q2=1:2~2.25.

[0013] In some embodiments, in the step of introducing the first hydrogen gas and the hydrogen chloride gas into the epitaxial reaction chamber, the hydrogen chloride gas has a third flow rate Q3 L / min;

[0014] In the step of introducing gaseous trichlorosilane into the epitaxial reaction chamber, the gaseous trichlorosilane has a fourth flow rate Q4 L / min;

[0015] Satisfies: Q3:Q1=1:1~1:2.

[0016] In some embodiments, Q4:Q1=1:2-2:3.

[0017] In some embodiments, the first flow rate Q1 L / min, the second flow rate Q2 L / min, the third flow rate Q3 L / min, and the fourth flow rate Q4 L / min further satisfy at least one of the following characteristics:

[0018] a) 20L / min≤Q1≤40L / min;

[0019] b) 40L / min≤Q2≤45L / min;

[0020] c) 10L / min≤Q3≤20L / min;

[0021] d)10L / min≤Q4≤15L / min.

[0022] In some embodiments, the temperature for etching the inner wall of the epitaxial reaction chamber and the surface of the susceptor is 1170-1190°C.

[0023] In some embodiments, the end point temperature of the first cooling is 1130-1150°C.

[0024] In some embodiments, the end point temperature of the second cooling is 800-850°C.

[0025] In some embodiments, the etching time is t1 s, the first cooling time is t2 s, and the second cooling time is t3 s, satisfying:

[0026] t1:t2=2:1~5:1.

[0027] In some embodiments, the etching time satisfies: 15s≤t1≤60s.

[0028] In some embodiments, the first cooling time satisfies: 8s≤t2≤12s.

[0029] In some embodiments, the first temperature reduction has a first rate v1°C / s;

[0030] The second cooling has a second rate v2°C / s;

[0031] Satisfies: v1≤v2.

[0032] In some embodiments, the first rate satisfies: 5°C / s≤v1≤10°C / s.

[0033] In some embodiments, the second rate satisfies: 5°C / s≤v2≤10°C / s.

[0034] In some embodiments, before the step of introducing the first hydrogen gas and the hydrogen chloride gas into the epitaxial reaction chamber to etch the surface of the substrate, the step further includes:

[0035] A second hydrogen gas is introduced into the epitaxial reaction chamber, and the temperature of the epitaxial reaction chamber is increased at the same time, wherein the second hydrogen gas has a fifth flow rate Q5 L / min, satisfying: Q5≤Q1.

[0036] In some embodiments, the fifth flow rate Q5 L / min satisfies: 20 L / min≤Q5≤40 L / min.

[0037] In some embodiments, the temperature increase has a third rate v3°C / s, satisfying: 5°C / s≤v3≤10°C / s.

[0038] On the other hand, an embodiment of the present application further provides an epitaxial wafer, which is prepared using the method for preparing an epitaxial wafer in any of the above embodiments.

[0039] In some embodiments, the epitaxial wafer includes a substrate layer and an epitaxial layer disposed on one side of the substrate layer; a thickness ratio of the intrinsic silicon layer to the epitaxial layer is 1:10 to 1:20.

[0040] In some embodiments, the intrinsic silicon layer has a thickness of 1 to 1.5 μm.

[0041] In some embodiments, the epitaxial layer has a thickness of 20 to 30 μm.

[0042] The present application provides a method for preparing an epitaxial wafer, comprising the following steps: providing an epitaxial reaction chamber, wherein the epitaxial reaction chamber comprises a susceptor, introducing a first hydrogen gas and a hydrogen chloride gas into the epitaxial reaction chamber, and etching the inner wall of the epitaxial reaction chamber and the surface of the susceptor, wherein the first hydrogen gas has a first flow rate of Q1 L / min; stopping the introduction of the hydrogen chloride gas, performing a first cooling, maintaining the flow rate of the first hydrogen gas at the first flow rate of Q1 L / min, and simultaneously introducing gaseous trichlorosilane into the epitaxial reaction chamber to deposit an intrinsic silicon layer on the surface of the susceptor; stopping the introduction of the gaseous trichlorosilane, adjusting the flow rate of the first hydrogen gas to a second flow rate of Q2 L / min, and performing a second cooling; providing a substrate, placing the substrate in the epitaxial reaction chamber, heating the substrate, and growing an epitaxial layer on the surface of the substrate; performing a third cooling to complete the preparation of the epitaxial wafer; wherein Q1<Q2. By combining the step of depositing the intrinsic silicon layer with the step of the first cooling, the step of first adjusting the temperature and then depositing the intrinsic silicon layer in the original process is replaced, thereby shortening the overall process time and improving the preparation efficiency; at the same time, by reducing the flow rate of the first hydrogen gas in the step of depositing the intrinsic silicon layer, the concentration of trichlorosilane in the epitaxial reaction chamber is increased, so that the front particles and silicon stacking conditions of the chip reach an ideal state, thereby improving the preparation efficiency while ensuring the quality of the epitaxial wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0044] Figure 1 A diagram showing the change in reaction temperature in a method for preparing an epitaxial wafer provided in an embodiment of the present application;

[0045] Figure 2 A first hydrogen flow rate variation diagram in a method for preparing an epitaxial wafer provided in an embodiment of the present application;

[0046] Figure 3 A diagram showing changes in trichlorosilane flow rate in a method for preparing an epitaxial wafer provided in an embodiment of the present application;

[0047] Figure 4 A partial representation diagram of the front side of an epitaxial wafer provided in Comparative Example 1 of the present application;

[0048] Figure 5 A partial characterization diagram of the back side of an epitaxial wafer provided for comparative example 2 of the present application. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0050] In the description of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features.

[0051] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application.

[0052] The first embodiment of the present application provides a method for preparing an epitaxial wafer, comprising the following steps:

[0053] An epitaxial reaction chamber is provided, wherein the epitaxial reaction chamber includes a susceptor, and a first hydrogen gas and a hydrogen chloride gas are introduced into the epitaxial reaction chamber to etch the inner wall of the epitaxial reaction chamber and the surface of the susceptor, wherein the first hydrogen gas has a first flow rate of Q1 L / min;

[0054] The introduction of hydrogen chloride gas is terminated, and the temperature is lowered for the first time, the flow rate of the first hydrogen gas is maintained at the first flow rate Q1 L / min, and gaseous trichlorosilane is introduced into the epitaxial reaction chamber at the same time to deposit an intrinsic silicon layer on the surface of the base;

[0055] The introduction of gaseous trichlorosilane is terminated, the flow rate of the first hydrogen is adjusted to the second flow rate Q2 L / min, and the temperature is lowered for the second time;

[0056] Providing a substrate, placing the substrate in an epitaxial reaction chamber, heating the substrate, and growing an epitaxial layer on the surface of the substrate;

[0057] Among them, Q1<Q2.

[0058] In the preparation process of epitaxial wafers, the present application combines the step of depositing an intrinsic silicon layer before growing the epitaxial wafer with the step of cooling down for the first time, thereby replacing the step of first adjusting the temperature and then depositing the intrinsic silicon layer in the original process, thereby shortening the overall process time and improving the preparation efficiency; at the same time, by reducing the flow rate of the first hydrogen gas in the step of depositing the intrinsic silicon layer, the concentration of trichlorosilane in the epitaxial reaction chamber is increased, thereby further increasing the reaction rate and improving the preparation efficiency.

[0059] In some embodiments, the first flow rate Q1 L / min and the second flow rate Q2 L / min satisfy:

[0060] Q1:Q2=1:2~2.25.

[0061] It is understandable that the value of Q1:Q2 can be any value of 1:2, 1:2.1, 1:2.2, 1:2.3, 1:2.4, 1:2.5 or a range between any two values. By introducing hydrogen during the etching stage and the stage of depositing the intrinsic silicon layer, on the one hand, the hydrogen can react with the impurities in the epitaxial reaction chamber to make the surface of the intrinsic silicon layer cleaner, and on the other hand, it can also prevent the silicon wafer from oxidizing, thereby improving the quality of the intrinsic silicon layer; when the introduction of trichlorosilane stops, the temperature in the epitaxial chamber is controlled to drop. At this time, the continuous introduction of hydrogen can continue to clean the surface of the intrinsic silicon layer, and at the same time, it can clear the unreacted gases and compounds remaining on the surface of the intrinsic silicon layer. When the ratio of the first flow rate Q1 L / min to the second flow rate Q2 meets the above range of values, the efficiency of the intrinsic silicon layer preparation can be improved while ensuring the quality of the surface of the intrinsic silicon layer.

[0062] In some embodiments, in the step of introducing the first hydrogen gas and the hydrogen chloride gas into the epitaxial reaction chamber, the hydrogen chloride gas has a third flow rate Q3 L / min;

[0063] In the step of introducing gaseous trichlorosilane into the epitaxial reaction chamber, the gaseous trichlorosilane has a fourth flow rate of Q4 L / min;

[0064] Satisfies: Q3:Q1=1:1~1:2.

[0065] It is understandable that the value of Q3:Q1 can be any value of 1:1, 1:1.2, 1:1.4, 1:1.6, 1:1.8, 1:2 or a range between any two values. Hydrogen chloride is used to etch the inner wall of the epitaxial reaction chamber and the surface of the base. When the flow rate of hydrogen chloride is too high, it may cause over-etching and erosion of other materials, while too low a flow rate of hydrogen chloride may cause a decline in the quality and efficiency of etching. When the third flow rate Q3 of the hydrogen chloride gas and the first flow rate Q1 meet the above value range, it can ensure that the etching step has both ideal efficiency and quality.

[0066] In some embodiments, Q4:Q1=1:2-2:3.

[0067] It is understandable that the value of Q4:Q1 can be any value of 1:2, 1:2.2, 1:2.4, 1:2.6, 1:2.8, 1:3 or a range between any two values. Trichlorosilane is used to deposit an intrinsic silicon layer (also known as silicon coating). When the flow rate of trichlorosilane is low, it may lead to poor deposition of the intrinsic silicon layer, resulting in silicon stacking on the back of the wafer; when the flow rate of trichlorosilane is high, it may increase the thickness of the intrinsic silicon layer, resulting in particle bright spots on the front of the wafer. When the fourth flow rate Q4 of trichlorosilane and the first flow rate Q1 meet the above range of values, the formed intrinsic silicon layer can have an ideal thickness and surface quality.

[0068] In some embodiments, the first flow rate Q1 L / min, the second flow rate Q2 L / min, the third flow rate Q3 L / min, and the fourth flow rate Q4 L / min further satisfy at least one of the following characteristics:

[0069] a) 20L / min≤Q1≤40L / min;

[0070] b) 40L / min≤Q2≤45L / min;

[0071] c) 10L / min≤Q3≤20L / min;

[0072] d)10L / min≤Q4≤15L / min.

[0073] It can be understood that the value (L / min) of the first flow rate Q1 can be any value among 20, 25, 30, 35, 40 or a range between any two values; the value (L / min) of the second flow rate Q2 can be any value among 40, 41, 42, 43, 44, 45 or a range between any two values; the value (L / min) of the third flow rate Q3 can be any value among 10, 12, 14, 16, 18, 20 or a range between any two values; the value (L / min) of the fourth flow rate Q4 can be any value among 10, 11, 12, 13, 14, 15 or a range between any two values. When the first flow rate Q1, the second flow rate Q2, the third flow rate Q3, and the fourth flow rate Q4 meet the above value ranges, the process efficiency and quality in the etching and silicon packaging steps can be further ensured.

[0074] In some embodiments, the temperature for etching the inner wall of the epitaxial reaction chamber and the surface of the susceptor is 1170-1190°C.

[0075] It can be understood that the value (unit: °C) of the temperature for etching the inner wall of the epitaxial reaction chamber and the surface of the susceptor can be any value among 1170, 1175, 1180, 1185, 1190 or a range between any two values. When the temperature for etching the inner wall of the epitaxial reaction chamber and the surface of the susceptor meets the above value range, the etching of the inner wall of the epitaxial reaction chamber and the surface of the susceptor can have an ideal etching rate and a high etching selectivity.

[0076] In some embodiments, the end point temperature of the first cooling is 1130-1150°C.

[0077] It is understandable that the value of the end temperature of the first cooling (unit: °C) can be any value among 1130, 1135, 1140, 1145, 1150 or a range between any two values. When the temperature for etching the inner wall of the epitaxial reaction chamber and the surface of the susceptor (i.e., the starting point of the first cooling) and the end temperature of the first cooling meet the above value range, the step of depositing the characterizing silicon layer can be kept in a suitable temperature range throughout the process, thereby minimizing the impact of cooling on the quality of the silicon package, and ensuring the quality of the wafer while improving the overall efficiency of the epitaxial process.

[0078] In some embodiments, the end point temperature of the second cooling is 800-850°C.

[0079] It is understandable that the value (unit: °C) of the end temperature of the second cooling can be any value among 800, 810, 820, 830, 840, 850 or a range between any two values. When the end temperature of the second cooling meets the above value range, the epitaxial wafer can be grown in a more suitable temperature environment in the subsequent steps.

[0080] In some embodiments, the etching time is t1 s, the first cooling time is t2 s, and the second cooling time is t3 s, satisfying:

[0081] t1:t2=2:1~5:1.

[0082] It is understandable that the value of t1:t2 can be any value among 2:1, 3:1, 4:1, 5:1 or a range between any two values. If the etching time is insufficient, it will affect the particles on the front side of the wafer. If the silicon coating time is insufficient, silicon slag will be easily generated on the back side of the wafer. Both phenomena affect the yield of this process and subsequent processes.

[0083] In some embodiments, the etching time satisfies: 15s≤t1≤60s.

[0084] In some embodiments, the first cooling time satisfies: 8s≤t2≤12s.

[0085] It can be understood that the etching time (unit: s) can be any value among 15, 20, 25, 30, 35, 40, 45, 50, 55, 60 or a range between any two values; the first cooling time (unit: s) can be any value among 8, 9, 10, 11, 12 or a range between any two values.

[0086] In some embodiments, the first temperature reduction has a first rate v1°C / s;

[0087] The second cooling has a second rate v2°C / s;

[0088] Satisfies: v1≤v2.

[0089] Since the characterization silicon layer is deposited in the reaction chamber during the first cooling process, controlling the first cooling rate to be slightly lower than the second cooling rate can better balance the silicon packaging quality and the total efficiency of the two cooling stages.

[0090] In some embodiments, the first rate satisfies: 5°C / s≤v1≤10°C / s.

[0091] In some embodiments, the second rate satisfies: 5°C / s≤v2≤10°C / s.

[0092] It can be understood that the value of the first rate (unit: °C / s) can be any value among 5, 6, 7, 8, 9, 10 or a range between any two values; the value of the second rate (unit: °C / s) can be any value among 5, 6, 7, 8, 9, 10 or a range between any two values. When the first rate and the second rate meet the above value ranges, the balance between the quality of the silicon package and the total efficiency of the two cooling stages can be further ensured.

[0093] In some embodiments, before the step of introducing the first hydrogen gas and the hydrogen chloride gas into the epitaxial reaction chamber to etch the surface of the substrate, the step further includes:

[0094] A second hydrogen gas is introduced into the epitaxial reaction chamber, and the temperature of the epitaxial reaction chamber is increased at the same time. The second hydrogen gas has a fifth flow rate Q5 L / min, satisfying: Q5≤Q1.

[0095] In some embodiments, the fifth flow rate Q5 L / min satisfies: 20 L / min≤Q5≤40 L / min.

[0096] It can be understood that the value of the fifth flow rate Q5 (unit: L / min) can be any value among 20, 25, 30, 35, 40 or a range between any two values.

[0097] In some embodiments, the temperature rise has a third rate v3°C / s, satisfying: 5°C / s≤v3≤10°C / s.

[0098] It can be understood that the value of the third rate v3 (unit: °C / s) can be any value among 5, 6, 7, 8, 9, 10 or a range between any two values.

[0099] The second embodiment of the present application further provides an epitaxial wafer, which is prepared by the method for preparing the epitaxial wafer in any of the above embodiments.

[0100] In some embodiments, the epitaxial wafer includes a substrate layer and an epitaxial layer disposed on one side of the substrate layer; the thickness ratio of the intrinsic silicon layer to the epitaxial layer is 1:10 to 1:20.

[0101] It is understandable that the thickness ratio of the intrinsic silicon layer to the epitaxial layer can be any value of 1:10, 1:12, 1:14, 1:16, 1:18, 1:20 or a range between any two values. When the thickness ratio of the intrinsic silicon layer to the epitaxial layer meets the above range, the epitaxial wafer formed has better performance.

[0102] In some embodiments, the thickness of the intrinsic silicon layer is 1-1.5 μm.

[0103] It can be understood that the thickness of the intrinsic silicon layer (unit: μm) can be any value among 1, 1.1, 1.2, 1.3, 1.4, 1.5 or a range between any two values.

[0104] In some embodiments, the thickness of the epitaxial layer is 20-30 μm.

[0105] It can be understood that the thickness of the epitaxial layer (unit: μm) can be any value among 20, 22, 24, 26, 28, 30 or a range between any two values.

[0106] The following is a description of the epitaxial wafer provided in this application in conjunction with specific embodiments:

[0107] Example 1

[0108] Example 1 provides an epitaxial wafer and a method for preparing the same, see Figure 1 to Figure 3 , the preparation method comprises the following steps:

[0109] Providing an epitaxial reaction chamber, the epitaxial reaction chamber comprising a susceptor, introducing a second hydrogen gas into the epitaxial reaction chamber, and preheating the epitaxial reaction chamber, wherein the second hydrogen gas has a fifth flow rate of 20 L / min;

[0110] Introducing a first hydrogen gas and a hydrogen chloride gas into the epitaxial reaction chamber to etch the inner wall of the epitaxial reaction chamber and the surface of the susceptor, wherein the first hydrogen gas has a first flow rate of 20 L / min;

[0111] The introduction of hydrogen chloride gas is terminated, and the temperature is lowered for the first time, the flow rate of the first hydrogen gas is maintained at the first flow rate of 20 L / min, and gaseous trichlorosilane is introduced into the epitaxial reaction chamber at the same time to deposit an intrinsic silicon layer on the surface of the base;

[0112] The introduction of gaseous trichlorosilane is terminated, the flow rate of the first hydrogen is adjusted to the second flow rate of 40 L / min, and the temperature is lowered for the second time;

[0113] A substrate is provided, and the substrate is placed in an epitaxial reaction chamber, and the temperature is increased to grow an epitaxial layer on the surface of the substrate to obtain an epitaxial wafer.

[0114] Embodiment 2-3

[0115] The preparation method of the epitaxial wafer in Examples 2 to 3 is consistent with that in Example 1, and the only difference is the adjustment of the process parameters.

[0116] Comparative Examples 1-2

[0117] The preparation methods of the epitaxial wafers in Comparative Examples 1-2 are consistent with those in Example 1, with the only difference being the adjustment of the process parameters.

[0118] The relevant process parameters in Examples 1 to 3 and Comparative Examples 1 to 2 are shown in Table 1.

[0119] Table 1

[0120]

[0121]

[0122] The epitaxial wafers provided in the examples and comparative examples of the present application were tested, and the front and back surfaces of the obtained epitaxial wafers were observed under a strong light in a dark room. Under the various conditions used in this example, the front particles and silicon stacking conditions of the epitaxial wafers can meet the use requirements. See the front characterization diagram of the epitaxial wafer obtained in comparative example 1 under a strong light in a dark room. Figure 4 It can be seen that due to the low trichlorosilane flow rate (Q4), the silicon packing condition is poor, resulting in silicon stacking on the back of the wafer, which does not meet the process requirements. Figure 5 It can be seen that due to the excessively high trichlorosilane flow rate (Q4), the thickness of the silicon package increases, resulting in bright particles on the front side of the wafer, which does not meet the requirements.

[0123] The above is a detailed introduction to an epitaxial wafer and a preparation method thereof provided in the embodiments of the present application. Specific examples are used in the present application to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for preparing an epitaxial wafer, characterized in that: The steps include: Providing an epitaxial reaction chamber, the epitaxial reaction chamber including a susceptor, introducing a first hydrogen gas and a hydrogen chloride gas into the epitaxial reaction chamber, etching an inner wall of the epitaxial reaction chamber and a surface of the susceptor, wherein the first hydrogen gas has a first flow rate of Q1 L / min; End the introduction of the hydrogen chloride gas, perform the first temperature reduction, maintain the flow rate of the first hydrogen gas at a first flow rate of Q1 L / min, and simultaneously introduce gaseous trichlorosilane into the epitaxial reaction chamber to deposit an intrinsic silicon layer on the surface of the base; The introduction of the gaseous trichlorosilane is terminated, the flow rate of the first hydrogen is adjusted to a second flow rate of Q2 L / min, and the temperature is lowered for the second time; Providing a substrate, placing the substrate in an epitaxial reaction chamber, heating the substrate, and growing an epitaxial layer on the surface of the substrate; Performing a third cooling step to complete the preparation of the epitaxial wafer; Among them, Q1<Q2.

2. The method for preparing an epitaxial wafer according to claim 1, characterized in that: The first flow rate Q1 L / min and the second flow rate Q2 L / min satisfy: Q1:Q2=1:2~2.

25.

3. The method for preparing an epitaxial wafer according to claim 1, characterized in that: In the step of introducing the first hydrogen gas and the hydrogen chloride gas into the epitaxial reaction chamber, the hydrogen chloride gas has a third flow rate Q3 L / min; In the step of introducing gaseous trichlorosilane into the epitaxial reaction chamber, the gaseous trichlorosilane has a fourth flow rate Q4 L / min; Satisfy: Q3:Q1=1:1~1:2; and / or, Q4:Q1=1:2~2:

3.

4. The method for preparing an epitaxial wafer according to claim 3, characterized in that: The first flow rate Q1 L / min, the second flow rate Q2 L / min, the third flow rate Q3 L / min, and the fourth flow rate Q4 L / min further satisfy at least one of the following characteristics: a) 20L / min≤Q1≤40L / min; b) 40L / min≤Q2≤45L / min; c) 10L / min≤Q3≤20L / min; d)10L / min≤Q4≤15L / min.

5. The method for preparing an epitaxial wafer according to claim 1, characterized in that: The temperature for etching the inner wall of the epitaxial reaction chamber and the surface of the susceptor is 1170-1190° C.; and / or, The end point temperature of the first cooling is 1130-1150° C.; and / or, The end point temperature of the second cooling is 800-850°C.

6. The method for preparing an epitaxial wafer according to claim 1, characterized in that: The etching time is t1 s, and the first cooling time is t2 s, satisfying: t1:t2=2:1~5:

1.

7. The method for preparing an epitaxial wafer according to claim 6, characterized in that: The etching time satisfies: 15s≤t1≤60s; and / or, The first cooling time satisfies: 8s≤t2≤12s.

8. The method for preparing an epitaxial wafer according to claim 1, characterized in that: The first temperature reduction has a first rate v1°C / s; The second cooling has a second rate v2°C / s; Satisfies: v1≤v2.

9. The method for preparing an epitaxial wafer according to claim 8, characterized in that: The first rate satisfies: 5°C / s≤v1≤10°C / s; and / or, The second rate satisfies: 5°C / s≤v2≤10°C / s.

10. The method for preparing an epitaxial wafer according to claim 1, characterized in that: Before the step of introducing the first hydrogen gas and the hydrogen chloride gas into the epitaxial reaction chamber to etch the surface of the substrate, the method further comprises: A second hydrogen gas is introduced into the epitaxial reaction chamber, and the epitaxial reaction chamber is preheated at the same time, wherein the second hydrogen gas has a fifth flow rate Q5 L / min, satisfying: Q5≤Q1.

11. The method for preparing an epitaxial wafer according to claim 10, characterized in that: The fifth flow rate Q5 L / min satisfies: 20 L / min≤Q5≤40 L / min; and / or, The temperature rise has a third rate v3°C / s, satisfying: 5°C / s≤v3≤10°C / s.

12. An epitaxial wafer, characterized in that: The epitaxial wafer is prepared by the method for preparing the epitaxial wafer according to any one of claims 1 to 13.

13. An epitaxial wafer according to claim 12, characterized in that: The epitaxial wafer comprises a substrate layer and an epitaxial layer arranged on one side of the substrate layer; the thickness ratio of the intrinsic silicon layer to the epitaxial layer is 1:10 to 1:

20.

14. An epitaxial wafer according to claim 13, characterized in that: The thickness of the intrinsic silicon layer is 1 to 1.5 μm; and / or, The thickness of the epitaxial layer is 20-30 μm.

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