COF type semiconductor packaging device and manufacturing method thereof

Abstract

The invention provides a COF type semiconductor packaging device and a manufacturing method thereof. The COF type semiconductor packaging device comprises an insulating substrate which comprises a first surface and a second surface which are oppositely arranged; the first wiring layer is arranged on the first surface of the insulating substrate; the semiconductor chip is arranged on the insulating substrate, and the semiconductor chip is electrically connected with wires formed according to a preset pattern in the first wiring layer through the convex electrodes; a first solder resist layer covering a portion of the first wiring layer other than the semiconductor chip; and the second wiring layer is arranged on the second surface of the insulating substrate, the orthographic projection of the semiconductor chip falls into the orthographic projection of the second wiring layer, and the semiconductor chip establishes a heat transmission channel with the outside through the second wiring layer. On the basis, the second wiring layer serving as a heat dissipation component is directly formed on the insulating substrate, so that the heat conductivity between the semiconductor chip and the second wiring layer is relatively high, and the heat dissipation efficiency of the whole device can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a COF (Chip On Film) type semiconductor packaging device and a manufacturing method thereof. Background Art

[0002] Electronic devices such as displays are usually equipped with driver ICs and implemented in the form of semiconductor packaging devices (also referred to as "semiconductor devices"). These semiconductor packaging devices are packaged through technologies such as but not limited to COF, TCP (Tape Carrier Package), COG (Chip On Glass), etc. Among them, semiconductor packaging devices using COF technology, also known as COF-type semiconductor packaging devices, are more suitable for a variety of application scenarios due to their flexibility.

[0003] As the performance of electronic devices becomes stronger and stronger, for example, the display of displays becomes higher and higher definition, the driving load of COF-type semiconductor packaging devices will increase accordingly, which will undoubtedly generate excessive heat, which will easily lead to performance degradation and reduced reliability. In order to solve this problem, one of the current methods is to install a heat dissipation component (such as a heat sink) on the lower surface of the insulating substrate (i.e., the side facing away from the semiconductor chip). Usually, the heat sink is first bonded to the lower surface of the insulating substrate through an adhesive layer, and then a packaging layer (such as a PI film) is covered with the heat sink through another adhesive layer. The heat generated by the semiconductor chip is transmitted to the heat sink through an adhesive layer, and then transmitted to another adhesive layer through the heat sink, and then transmitted to the outside world through the packaging layer, thereby completing the heat dissipation of the entire semiconductor packaging device. However, the existing adhesives are generally made of materials with low thermal conductivity, resulting in a low thermal conductivity between the adhesive layer and the heat sink, and the heat dissipation efficiency of the entire semiconductor packaging device is low, which may not be enough to solve the problem of excessive heat. Summary of the invention

[0004] In view of this, the present application provides a COF type semiconductor packaging device and a manufacturing method thereof, which can improve the low heat dissipation efficiency and the resulting problem that it may not be sufficient to solve the problem of excessive heat.

[0005] The present application provides a COF type semiconductor packaging device, comprising: An insulating substrate comprising a first surface and a second surface arranged opposite to each other; A first wiring layer is provided on the first surface of the insulating substrate; A semiconductor chip is disposed on the insulating substrate, and the semiconductor chip is electrically connected to wirings formed in a preset pattern in the first wiring layer through protruding electrodes; a first solder resist layer covering a portion of the first wiring layer excluding the semiconductor chip; The second wiring layer is arranged on the second surface of the insulating substrate, and the orthographic projection of the semiconductor chip falls within the orthographic projection of the second wiring layer. The semiconductor chip establishes a heat transfer channel with the outside world via the second wiring layer.

[0006] Optionally, the COF type semiconductor packaging device further includes: The second solder resist layer is disposed on the second surface of the insulating substrate and covers the second wiring layer.

[0007] Optionally, a concave-convex structure is provided on a side surface of the second wiring layer facing the second solder resist layer.

[0008] Optionally, the COF type semiconductor packaging device further includes: The second solder resist layer is arranged on the second surface of the insulating substrate, and the second solder resist layer is provided with an avoidance area, the orthographic projection of the avoidance area falls within the orthographic projection of the second wiring layer, and the second wiring layer is connected to the outside through the exposed part of the avoidance area.

[0009] Optionally, the insulating substrate is provided with a first through hole, and a portion of wirings of the first wiring layer is electrically connected to the second wiring layer through the first through hole.

[0010] Optionally, a portion of the wirings in the first wiring layer and the second wiring layer serve together as power pins or ground pins of the semiconductor package device.

[0011] Optionally, the orthographic projection of the first through hole falls within the orthographic projection of the semiconductor chip.

[0012] Optionally, the insulating substrate is also provided with a second through hole, the orthographic projection of the second through hole falls outside the orthographic projection of the semiconductor chip, part of the wiring of the first wiring layer also extends outside the semiconductor chip, and part of the wiring of the first wiring layer is also electrically connected to the second wiring layer through the second through hole.

[0013] Optionally, the second wiring layer has a mesh structure or a stripe structure.

[0014] The present application provides a method for manufacturing a COF type semiconductor packaging device, which is used to manufacture the semiconductor packaging device as described in any one of the above items, and the method comprises: Providing an insulating substrate, comprising a first surface and a second surface disposed opposite to each other; forming a first wiring layer on a first surface of the insulating substrate; forming a semiconductor chip on the insulating substrate, wherein the semiconductor chip is electrically connected to wirings formed in a preset pattern in the first wiring layer through protruding electrodes; forming a first solder resist layer on the first wiring layer, the first solder resist layer covering a portion of the first wiring layer excluding the semiconductor chip; A second wiring layer is formed on the second surface of the insulating substrate, and the orthographic projection of the semiconductor chip falls within the orthographic projection of the second wiring layer, so that the semiconductor chip establishes a heat transfer channel with the outside through the second wiring layer.

[0015] As described above, the present application directly forms a second wiring layer on (the second surface of) an insulating substrate. The second wiring layer, which serves as a heat dissipation component, is in direct contact with the insulating substrate. The heat generated by the semiconductor chip can be directly transferred to the heat dissipation component via the insulating substrate. The heat transfer channel is short, so that the thermal conductivity between the semiconductor chip and the second wiring layer is high, which can improve the heat dissipation efficiency of the entire device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a cross-sectional schematic diagram of a semiconductor packaging device according to the first embodiment of the present application; Figure 2 is a top view of the structure of the first second wiring layer provided in an embodiment of the present application; Figure 3 is a top view of the structure of a second second wiring layer provided in an embodiment of the present application; Figure 4 is a top view of the structure of the third second wiring layer provided in an embodiment of the present application; Figure 5 is a cross-sectional schematic diagram of a first semiconductor package device according to a second embodiment of the present application; Figure 6 is a cross-sectional schematic diagram of a second semiconductor package device according to a second embodiment of the present application; Figure 7 is a cross-sectional schematic diagram of a third semiconductor package device of the second embodiment of the present application; Figure 8 is a cross-sectional schematic diagram of a semiconductor packaging device according to a third embodiment of the present application; Fig. 9 A schematic cross-sectional view of a first semiconductor package device according to a fourth embodiment of the present application; Fig.10 A schematic cross-sectional view of a second semiconductor package device according to a fourth embodiment of the present application; Fig.11 A schematic cross-sectional view of a third semiconductor package device according to a fourth embodiment of the present application; Fig.12is a top view of the relative positions of a second wiring layer electrically connected to a semiconductor chip through a first through hole and a second through hole provided by an embodiment of the present application; Fig.13 It is a flow chart of a method for manufacturing a semiconductor packaging device provided in an embodiment of the present application.

[0017] Insulating substrate 1, first surface 11, second surface 12, first through hole 13, second through hole 14 The first wiring layer 2, a portion of which is a wiring 20 Semiconductor chip 3, bump electrode 30, resin 31 First solder resist layer 4 Second wiring layer 5, connection line 51 Second solder resist layer 6, free space 60 DETAILED DESCRIPTION In order to solve the above-mentioned technical problems existing in the prior art, in the COF-type semiconductor packaging device and its manufacturing method of the present application, a second wiring layer is directly formed on the insulating substrate. The second wiring layer is used as a heat dissipation component (or it can also be called a "heat sink"). The heat generated by the semiconductor chip can be directly transmitted to the heat dissipation component through the insulating substrate. The heat transfer between the semiconductor chip and the heat dissipation component passes through fewer structural layers and the heat transfer channel is shorter, thereby improving the heat dissipation efficiency.

[0018] The specific form of parameters such as shape, quantity, size (such as thickness) of any one of the insulating substrate, the first wiring layer, the semiconductor chip, the first solder resist layer and the second wiring layer can be determined according to the adaptability required by the actual scenario, and this application does not limit it.

[0019] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be clearly described below in conjunction with specific embodiments and corresponding drawings. Obviously, the embodiments described below are only part of the embodiments of the present application, not all of the embodiments. In the absence of conflict, the following embodiments and their technical features can be combined with each other and also belong to the technical solutions of the present application.

[0020] In the description of the embodiments of the present application, terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", and "counterclockwise" indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the technical solutions of the corresponding embodiments, rather than indicating or implying that a device or element must have a specific orientation, be constructed and operated in a specific orientation, and should not be understood as a limitation on the present application.

[0021] First embodiment See also Figure 1 As shown, the COF-type semiconductor packaging device of this embodiment (may be referred to as "semiconductor packaging device", "semiconductor device" or "device" in some places in this document) includes an insulating substrate 1, a first wiring layer 2, a semiconductor chip 3, a first solder resist layer 4 and a second wiring layer 5.

[0022] The insulating substrate 1 includes two surfaces arranged opposite to each other along its thickness direction, which are respectively referred to as a first surface 11 and a second surface 12 . Figure 1 It shows a schematic cross-sectional view of the local structure of a semiconductor device along its thickness direction. Figure 1 In the shown placement orientation, the first surface 11 can be regarded as the lower surface of the insulating substrate 1 , and the second surface 12 can be regarded as the upper surface of the insulating substrate 1 .

[0023] The insulating substrate 1 may be in the form of a sheet or layered structure with uniform thickness, and the first surface 11 and the second surface 12 may be planes. In practical scenarios, the insulating substrate 1 may be a flexible insulating substrate, such as a PI film (Polyimide Film).

[0024] The first wiring layer 2 is disposed on the first surface 11 of the insulating substrate 1. The first wiring layer 2 includes one or more wirings formed according to a preset pattern. The connection relationship between these wirings and the function of each wiring can be determined according to the adaptability of the actual scene, and the present application does not limit it. For example, the wiring in the first wiring layer 2 is made based on a conductive material such as copper and through an etching process.

[0025] The semiconductor chip 3 is disposed on the insulating substrate 1, and the semiconductor chip 3 is electrically connected to the corresponding wiring in the first wiring layer 2 through the protruding electrode 30. The protruding electrode 30 may be a gold protrusion.

[0026] The first solder resist layer 4 covers the portion of the first wiring layer 2 except the semiconductor chip 3. In one example, after the semiconductor chip 3 is electrically connected to the corresponding wiring in the first wiring layer 2, as shown in FIG. Figure 1 As shown, the side surfaces of the semiconductor chip 3, the overlapping portions between the semiconductor chip 3 and the first wiring layer 2, and the overlapping portions between the semiconductor chip 3 and the insulating substrate 1 are encapsulated by resin 31, wherein the first solder resist layer 4 surrounds the resin 31 and covers the other portions of the first wiring layer 2.

[0027] The second wiring layer 5 is arranged on the second surface 12 of the insulating substrate 1, and along the line of sight perpendicular to the first surface 11 and the second surface 12, the orthographic projection of the semiconductor chip 3 falls within the orthographic projection of the second wiring layer 5. The semiconductor chip 3 establishes a heat transfer channel with the outside world through the second wiring layer 5, that is, the second wiring layer 5 is a structural layer with a heat conducting function, which can be called a "heat dissipation component" or a "heat sink".

[0028] Here, the present application directly forms a heat dissipation component on the insulating substrate 1 (the second surface 12). Since the heat dissipation component is in direct contact with the insulating substrate 1, the heat generated by the semiconductor chip 3 can be directly transmitted to the heat dissipation component through the insulating substrate 1, and then directly transmitted to the outside air by the heat dissipation component (i.e., the second wiring layer 5), thereby completing the heat dissipation of the entire device. The heat transfer channel between the semiconductor chip 3 and the heat dissipation component is short, so that the thermal conductivity between the semiconductor chip 3 and the heat dissipation component is high, which can improve the heat dissipation efficiency of the entire device and meet the heat dissipation requirements in scenarios where excessive heat is generated.

[0029] In one example, one or more of the material, preparation process, and thickness of the second wiring layer 5 and the first wiring layer 2 may be the same. Of course, in other examples, in view of the different functions of the second wiring layer 5 and the first wiring layer 2, that is, the core function of the second wiring layer 5 is heat conduction, and the core function of the first wiring layer 2 is electricity conduction, the second wiring layer 5 may be made of a material different from the first wiring layer 2, for example, the resistance value of the first wiring layer 2 may be greater than the resistance value of the second wiring layer 5, and the material of the second wiring layer 5 includes but is not limited to aluminum; the thickness of the second wiring layer 5 may be greater than the thickness of the first wiring layer 2.

[0030] In one example, any surface of the second wiring layer 5 is an integrated plane. The so-called integrated plane can be understood as: a complete plane without cracks or air avoidance areas, or in other words, the cracks and air avoidance areas of the plane are small enough not to affect the entire contact with the second surface 12 of the insulating substrate 1. The entire contact means that the orthographic projection area enclosed by the outermost edge of the second wiring layer 5 is equal to the overlapping area between the second wiring layer 5 and the second surface 12 of the insulating substrate 1.

[0031] In other examples, such as Figure 2 As shown, the second wiring layer 5 may be in a mesh structure, or as shown in FIG. Figure 3 and Figure 4 As shown, the second wiring layer 5 may be in a stripe structure. In this way, the elastic stress of the entire second wiring layer 5 can be weakened to meet the needs of flexible bending scenarios and save space. Figures 2 to 4 In FIG. 1 , the area indicated by the dotted line is the orthographic projection area of ​​the semiconductor chip 3 .

[0032] exist Figure 3 and Figure 4 In the example shown, all stripes of the second wiring layer 5 can be connected to each other. Optionally, the second wiring layer 5 is provided with a connecting line 51, through which the wiring of the second wiring layer 5 located within the orthographic projection range of the semiconductor chip 3 is connected, so that the second wiring layer 5 has a larger wiring area within the orthographic projection range of the semiconductor chip 3, thereby meeting the flexible bending requirements while increasing the thermal conductivity of the area facing the semiconductor chip 3.

[0033] Second embodiment For structural elements with the same name, the present application uses the same reference numerals to identify them in various embodiments. Based on the description of the first embodiment above, the difference is that, Figure 5 As shown, in addition to the insulating substrate 1, the first wiring layer 2, the semiconductor chip 3, the first solder resist layer 4 and the second wiring layer 5, the semiconductor packaging device of the second embodiment also includes a second solder resist layer 6, which is arranged on the second surface of the insulating substrate 1 and covers the second wiring layer 5.

[0034] The second solder resist layer 6 is a whole-surface structural layer, and the second wiring layer 5 is completely covered between the second solder resist layer 6 and the insulating substrate 1, and the functions achieved include but are not limited to: preventing soldering, that is, the second solder resist layer 6 covers the wiring of the second wiring layer 5, which can prevent solder from adhering to the wiring of the second wiring layer 5 that does not need soldering; insulation protection, that is, it plays an insulating role to protect the wiring of the second wiring layer 5 from damage; limiting the welding area to prevent bridging and short circuit phenomena during welding, avoid manual rework, and improve labor productivity; reducing thermal shock, that is, the thermal shock to the second wiring layer 5 in subsequent possible welding scenarios can be reduced, and delamination between the second wiring layer 5 and the insulating substrate 1 can be prevented.

[0035] In one example, a concavo-convex structure may be provided on the side of the second wiring layer 5 facing the second solder resist layer 6. The concavo-convex structure may increase the surface area of ​​the second wiring layer 5 on the side, thereby increasing the heat transfer area of ​​the second wiring layer 5, which is beneficial to improving the thermal conductivity and heat dissipation effect, and may also increase the bonding area between the second wiring layer 5 and the second solder resist layer 6, thereby improving the connection stability between the second wiring layer 5 and the second solder resist layer 6.

[0036] The concave-convex structure may be a pattern with a predetermined arrangement order or a random pattern, which is not limited in the present application. Figure 6 and Figure 7 The concave-convex structure shown is for exemplary purposes only.

[0037] The second solder resist layer 6 and the first solder resist layer 4 can be made of the same material and the same manufacturing process, for example, both can be formed by processes including screen printing ink, exposure and development, etc. The concave-convex structure can be made by exposure and development, etc.

[0038] Third embodiment Based on the description of the second embodiment, the difference is that Figure 8 As shown, the semiconductor package device of the third embodiment also includes a second solder resist layer 6 disposed on the second surface 12 of the insulating substrate 1 , but the second solder resist layer 6 is not a full-surface structure, but is provided with a void area 60 .

[0039] Along the line of sight perpendicular to the first surface 11 and the second surface 12, the orthographic projection of the avoidance area 60 falls within the orthographic projection of the second wiring layer 5, for example, the second solder resist layer 6 surrounds and covers the edge portion of the second wiring layer 5, so that the other majority of the second wiring layer 5 is not covered by the second solder resist layer 6, and the second wiring layer 5 is connected to the outside through the exposed portion of the avoidance area 60. Here, the second wiring layer 5 is directly in contact with the outside air and establishes heat exchange, which can improve the heat dissipation effect.

[0040] In actual scenarios, the second solder resist layer 6 having the air-avoiding area 60 can be directly formed by an etching process, or a second solder resist layer 6 having the air-avoiding area 60 can be first formed. Figures 5 to 7 The entire second solder resist layer 6 is shown, and then an empty space 60 is formed by etching process, so that the second solder resist layer 6 has Figure 8 The structure shown.

[0041] Fourth embodiment Based on the description of any of the above embodiments, the difference is that in the semiconductor package device of the fourth embodiment, the second wiring layer 5 is electrically connected to the first wiring layer 2. Figure 5 The fourth embodiment is described using the semiconductor package device shown as a basic structure.

[0042] like Fig. 9 As shown, the insulating substrate 1 is provided with a first through hole 13 , and a portion of the wiring 20 of the first wiring layer 2 is electrically connected to the second wiring layer 5 through the first through hole 13 .

[0043] In actual scenarios, the present application can open a first through hole 13 at a preset position of the insulating substrate 1 through an etching process. When preparing the second wiring layer 5, the preparation material of the second wiring layer 5 flows into the first through hole 13, thereby electrically connecting with a portion of the wiring 20 of the first wiring layer 2.

[0044] The heat generated by the semiconductor chip 3 can also be transferred to the second wiring layer 5 through the first wiring layer 2 and the first through hole 13, and then transmitted to the outside through the second wiring layer 5. Since the first wiring layer 2 and the second wiring layer 5 are both made of conductive materials, the thermal conductivity of the conductive material is higher than that of the insulating substrate 1, and thus a higher heat dissipation effect can be achieved than through the insulating substrate 1. It should be understood that the number of the first through holes 13 can be determined according to the adaptability of actual needs, and the more the number, the better the heat dissipation effect.

[0045] In one example, after a portion of the wiring 20 of the first wiring layer 2 is electrically connected to the second wiring layer 5, they can jointly serve as a power pin or a ground pin of a semiconductor packaging device. The specific needs depend on the function of a portion of the wiring 20 of the first wiring layer 2. For example, if a portion of the wiring 20 of the first wiring layer 2 is electrically connected to the power pin of the semiconductor packaging device, then the second wiring layer 5 serves as a power pin, thereby reducing the impedance of the power pin of the entire device.

[0046] Along the line of sight perpendicular to the first surface 11 and the second surface 12 , the orthographic projection of the first through hole 13 can fall within the orthographic projection of the semiconductor chip 3 , that is, a portion of the wiring 20 of the first wiring layer 2 and the first through hole 13 are located in the area where the semiconductor chip 3 is located.

[0047] The structural design of the first through hole 13 can also be applied to the semiconductor packaging device of any of the above embodiments. Fig.10 As shown, the semiconductor package device of the third embodiment described above may be provided with a first through hole 13; for another example, refer to Fig.11 As shown, the semiconductor package device of the first embodiment may also be provided with a first through hole 13 .

[0048] Combination Fig. 9 and Fig.12 As shown, the insulating substrate 1 may also be provided with second through holes 14. It should be understood that the number of the second through holes 14 may also be determined according to actual needs.

[0049] Along the line of sight perpendicular to the first surface 11 and the second surface 12, the orthographic projection of the second through hole 14 falls outside the orthographic projection of the semiconductor chip 3, a portion of the wiring 20 of the first wiring layer 2 also extends outside the semiconductor chip 3, and a portion of the wiring 20 of the first wiring layer 2 is also electrically connected to the second wiring layer 5 through the second through hole 14.

[0050] Here, a portion of the wiring 20 of the first wiring layer 2 is electrically connected to the second wiring layer 5 through the first through hole 13 and the second through hole 14, which is equivalent to increasing the electrical connection channel between the two layers of wiring, which can further improve the heat dissipation effect and further reduce the impedance.

[0051] The present application also provides a method for manufacturing a semiconductor packaging device. Fig.13 As shown, the method includes the following steps S1 to S5.

[0052] S1: providing an insulating substrate, comprising a first surface and a second surface arranged opposite to each other; S2: forming a first wiring layer on the first surface of the insulating substrate; S3: Arranging a semiconductor chip on the insulating substrate, the semiconductor chip being electrically connected to wirings formed in a preset pattern in the first wiring layer through protruding electrodes; S4: forming a first solder resist layer on the first wiring layer, wherein the first solder resist layer covers a portion of the first wiring layer except for the semiconductor chip; S5: forming a second wiring layer on the second surface of the insulating substrate, and the orthographic projection of the semiconductor chip falls within the orthographic projection of the second wiring layer, so that the semiconductor chip establishes a heat transfer channel with the outside through the second wiring layer.

[0053] Although step codes such as S1 and S2 are used in the description of this application, their purpose is to express the corresponding content more clearly and concisely, and do not constitute a substantial limitation on the sequence. When technical personnel in this field implement the specific steps, for example, they may execute S5 first and then S2, but these should all be within the scope of protection of this application.

[0054] The above steps S1 to S5 of this embodiment can be used to manufacture a semiconductor packaging device as in any of the previous embodiments, and thus have the beneficial effects produced by the semiconductor packaging device of the corresponding example, which will not be described in detail here.

[0055] It should be noted that the above steps S1 to S5 are only necessary steps for manufacturing the semiconductor package device of any of the above embodiments, but not all the steps. Figure 5 In the semiconductor package device of the second embodiment shown, after performing the step S5, the method further includes a step S6: forming a second solder resist layer covering the second wiring layer on the second surface of the insulating substrate.

[0056] In any of the above-mentioned semiconductor packaging devices, the materials and specific manufacturing processes of each layer can refer to the manufacturing methods of the corresponding layers in the existing semiconductor packaging devices.

[0057] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. For ordinary technicians in this field, all equivalent structural changes made using the contents of this specification and drawings are also included in the patent protection scope of the present application.

[0058] Although the terms "first, second", etc. are used herein to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. In addition, the singular forms "one", "an", and "the" are intended to include plural forms as well. The terms "or" and "and / or" are interpreted as inclusive, or mean any one or any combination. Only when the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way, an exception to this definition will occur.

Claims

1. A COF type semiconductor packaging device, characterized in that: include: An insulating substrate comprising a first surface and a second surface arranged opposite to each other; A first wiring layer is provided on the first surface of the insulating substrate; A semiconductor chip is disposed on the insulating substrate, and the semiconductor chip is electrically connected to wirings formed in a preset pattern in the first wiring layer through protruding electrodes; a first solder resist layer covering a portion of the first wiring layer excluding the semiconductor chip; The second wiring layer is arranged on the second surface of the insulating substrate, and the orthographic projection of the semiconductor chip falls within the orthographic projection of the second wiring layer. The semiconductor chip establishes a heat transfer channel with the outside world via the second wiring layer.

2. The semiconductor package device according to claim 1, characterized in that: Also includes: The second solder resist layer is disposed on the second surface of the insulating substrate and covers the second wiring layer.

3. The semiconductor package device according to claim 2, characterized in that: A concavo-convex structure is provided on one side of the second wiring layer facing the second solder resist layer.

4. The semiconductor package device according to claim 1, wherein: Also includes: The second solder resist layer is arranged on the second surface of the insulating substrate, and the second solder resist layer is provided with an avoidance area, the orthographic projection of the avoidance area falls within the orthographic projection of the second wiring layer, and the second wiring layer is connected to the outside through the exposed part of the avoidance area.

5. The semiconductor package device according to any one of claims 1 to 4, characterized in that: The insulating substrate is provided with a first through hole, and a portion of wirings of the first wiring layer is electrically connected to the second wiring layer through the first through hole.

6. The semiconductor package device according to claim 5, characterized in that: A portion of the wirings in the first wiring layer and the second wiring layer serve together as power pins or ground pins of the semiconductor package device.

7. The semiconductor package device according to claim 5, characterized in that: An orthographic projection of the first through hole falls within an orthographic projection of the semiconductor chip.

8. The semiconductor package device according to claim 7, characterized in that: The insulating substrate is also provided with a second through hole, the orthographic projection of the second through hole falls outside the orthographic projection of the semiconductor chip, part of the wiring of the first wiring layer also extends outside the semiconductor chip, and part of the wiring of the first wiring layer is also electrically connected to the second wiring layer through the second through hole.

9. The semiconductor package device according to claim 1, wherein: The second wiring layer has a mesh structure or a stripe structure.

10. A method for manufacturing a COF type semiconductor packaging device, characterized in that: For manufacturing a semiconductor package device according to any one of claims 1 to 9, the method comprises: Providing an insulating substrate, comprising a first surface and a second surface disposed opposite to each other; forming a first wiring layer on a first surface of the insulating substrate; forming a semiconductor chip on the insulating substrate, wherein the semiconductor chip is electrically connected to wirings formed in a preset pattern in the first wiring layer through protruding electrodes; forming a first solder resist layer on the first wiring layer, the first solder resist layer covering a portion of the first wiring layer excluding the semiconductor chip; A second wiring layer is formed on the second surface of the insulating substrate, and the orthographic projection of the semiconductor chip falls within the orthographic projection of the second wiring layer, so that the semiconductor chip establishes a heat transfer channel with the outside through the second wiring layer.

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