Semiconductor gain chip

Abstract

The invention provides a semiconductor gain chip. The semiconductor gain chip comprises an N-surface metal layer, a substrate, an N-type buffer layer, an N-type waveguide layer, an N-type limiting layer, an active region, a P-type limiting layer, a P-type waveguide layer, a P-type contact layer, a P-surface electrical isolation layer and a P-surface metal layer which are stacked in sequence, a preset area of the P-type waveguide layer is prepared into a ridge waveguide structure and comprises a straight waveguide area and an inclined waveguide area, the P-type contact layer covers the ridge waveguide structure and ridge platforms on the two sides of the double grooves, the P-face electric isolation layer covers the two sides of the ridge waveguide structure, the double grooves and the ridge platforms on the two sides of the double grooves, and the P-face metal layer covers the P-type contact layer and the P-face electric isolation layer. The straight waveguide area reduces transmission loss in the light transmission process and increases the light output power of the chip. Triangular side edge structures are further arranged on the two sides of the straight waveguide area and the inclined waveguide area, the diffraction loss of the gain chip in the optical transmission process is increased through the side edge structures, optical oscillation is reduced, the reflectivity of the chip is reduced, and lasing is restrained.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, in particular to the field of III-V group active chips, and in particular to a semiconductor gain chip. Background Art

[0002] In coherent laser communication systems, the signal modulation format and order are sensitive to the laser linewidth, and narrow linewidth lasers are needed to achieve high-order multi-dimensional modulation, thereby improving the transmission rate and capacity of the communication system. In laser sensing systems and space laser communication systems, since the power of the signal is extremely small when it reaches the receiving end, coherent detection technology is needed to improve the detection sensitivity of the receiving end. Correlated coherent detection can only be achieved with narrow linewidth lasers. At present, these fields require the linewidth to be maintained at a few kHz to a few hundred Hz. At present, narrow linewidth lasers with external cavity structures can achieve this more easily. The chip in the external cavity structure is a gain chip.

[0003] Traditional gain chips mainly rely on curved waveguides and anti-reflection films to reduce reflectivity, eliminate resonance, and suppress lasing, thereby generating spontaneous radiation with a wide spectrum. With the development of coherent laser communications, laser sensing, and space laser communications, new requirements have been put forward for narrow linewidth lasers: while maintaining the existing linewidth, the output power of narrow linewidth lasers needs to be further improved. Based on the above requirements, how to improve the structure of the gain chip and further improve the output power of the gain chip on the basis of existing technology has become a technical problem that needs to be solved at present. Summary of the invention

[0004] In view of the above problems, the present invention provides a semiconductor gain chip.

[0005] A semiconductor gain chip provided according to an embodiment of the present invention comprises: an N-side metal layer, a substrate, an N-type buffer layer, an N-type waveguide layer, an N-type confinement layer, an active region, a P-type confinement layer, a P-type waveguide layer, a P-type contact layer, a P-side electrical isolation layer and a P-side metal layer which are stacked in sequence; a preset area of ​​the P-type waveguide layer is prepared as a ridge waveguide structure, the ridge waveguide structure comprises a straight waveguide area and an inclined waveguide area, the P-type contact layer covers the ridge waveguide structure and ridge terraces on both sides of a double groove, the P-side electrical isolation layer covers both sides of the ridge waveguide structure, the double groove and the ridge terraces on both sides of the double groove, and the P-side metal layer covers the P-type contact layer and the P-side electrical isolation layer.

[0006] According to an embodiment of the present invention, triangular side structures are provided on both sides of the straight waveguide region and the oblique waveguide region, and the side structures are used to increase the diffraction loss of the reflected light during the optical transmission process in the waveguide structure.

[0007] According to an embodiment of the present invention, the length of the straight waveguide region accounts for 1 / 2 to 2 / 3 of the length of the semiconductor gain chip.

[0008] According to an embodiment of the present invention, the material of the P-side metal layer includes Ti / Pt / Au or Ti / Au, with a thickness of 200nm-500nm; the N-side metal layer includes AuGeNi alloy / Au or AuGe alloy / Au, with a thickness of 200nm-500nm.

[0009] According to an embodiment of the present invention, the material of the P-side electrical isolation layer includes SiN x Or SiO x , thickness is 200nm-500nm.

[0010] According to an embodiment of the present invention, the material of the P-type contact layer includes highly doped GaAs or In x Ga 1-x As, doping concentration is 1.5×10 20 cm -3 -3×10 20 cm -3 , thickness is 100nm-200nm.

[0011] According to an embodiment of the present invention, the material of the P-type waveguide layer includes InP with a thickness of 1000nm-3000nm; the material of the N-type waveguide layer is In x Ga 1-x As y P 1-y , thickness is 50nm-300nm.

[0012] According to an embodiment of the present invention, the material of the active region includes In x Ga 1-x As y P 1-y The quantum well / barrier structure has a thickness of 10nm-30nm.

[0013] According to an embodiment of the present invention, the materials of the P-type confinement layer and the N-type confinement layer include In x Ga 1-x As y P 1-y , thickness is 20nm-100nm.

[0014] According to an embodiment of the present invention, the material of the N-type buffer layer includes InP, and the thickness is 50nm-200nm; the material of the substrate includes InP.

[0015] The semiconductor gain chip provided by the present invention has at least the following technical effects:

[0016] The semiconductor gain chip is prepared by preparing a preset area of ​​a P-type waveguide layer into a ridge waveguide structure, wherein the ridge waveguide structure includes a straight waveguide area and an inclined waveguide area, thereby reducing transmission loss during light transmission in the straight waveguide area and increasing the light output power of the chip.

[0017] Adding triangular side structures on both sides of the straight waveguide area and the oblique waveguide area, the reflected light in the triangular side structure cannot propagate in a straight line and generates diffraction loss, which increases the diffraction loss of the gain chip during light transmission and reduces the optical oscillation of the chip itself, thereby reducing the chip reflectivity and suppressing lasing. Since the diffraction loss is increased and the optical oscillation of the chip itself is reduced, the gain chip is less dependent on the transmittance of the anti-reflection film layer.

[0018] By properly setting the length of the straight waveguide area, the transmission loss during light transmission can be further reduced and the light output power of the chip can be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above contents and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0020] Figure 1 Schematically shows a front view of a semiconductor gain chip according to an embodiment of the present invention;

[0021] Figure 2 Schematically shows a top view of a semiconductor gain chip according to an embodiment of the present invention;

[0022] Figure 3 A side view of a semiconductor gain chip according to an embodiment of the present invention is schematically shown.

[0023] Figure numerals: 1: P-side metal layer; 2: P-side electrical isolation layer; 3: P-type contact layer; 4: P-type waveguide layer; 5: upper confinement layer; 6: active area; 7: lower confinement layer; 8: N-type waveguide layer; 9: N-type buffer layer; 10: substrate, 11: N-side metal layer. DETAILED DESCRIPTION

[0024] Below, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of embodiments of the present invention. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of concepts of the present invention.

[0025] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0026] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0027] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0028] Figure 1 Schematically shows a front view of a semiconductor gain chip according to an embodiment of the present invention; Figure 2 Schematically shows a top view of a semiconductor gain chip according to an embodiment of the present invention; Figure 3 A side view of a semiconductor gain chip according to an embodiment of the present invention is schematically shown.

[0029] like Figures 1 to 3 As shown, the semiconductor gain chip may include: an N-side metal layer 11, a substrate 10, an N-type buffer layer 9, an N-type waveguide layer 8, an N-type confinement layer 7, an active region 6, a P-type confinement layer 5, a P-type waveguide layer 4, a P-type contact layer 3, a P-side electrical isolation layer 2 and a P-side metal layer 1, which are stacked in sequence. A preset region of the P-type waveguide layer 4 is prepared as a ridge waveguide structure, the ridge waveguide structure includes a straight waveguide region and an inclined waveguide region, the P-type contact layer 3 covers the ridge waveguide structure and the ridge terraces on both sides of the double grooves, the P-side electrical isolation layer 2 covers both sides of the ridge waveguide structure, the double grooves and the ridge terraces on both sides of the double grooves, and the P-side metal layer 1 covers the P-type contact layer and the P-side electrical isolation layer 2.

[0030] The semiconductor gain chip uses a straight waveguide region to reduce transmission loss during light transmission to increase the chip's output light power.

[0031] On the basis of the above embodiment, triangular side structures are arranged on both sides of the straight waveguide region and the oblique waveguide region, and the side structures are used to increase the diffraction loss of the reflected light during the optical transmission process in the side structures. By using the triangular side structures added on both sides of the straight waveguide region and the oblique waveguide region, the reflected light cannot propagate in a straight line and generates diffraction loss, which increases the diffraction loss in the optical transmission process of the gain chip, reduces the optical oscillation of the chip itself, thereby reducing the chip reflectivity and suppressing lasing.

[0032] On the basis of the above-mentioned embodiment, the length of the straight waveguide region in this embodiment accounts for 1 / 2 to 2 / 3 of the length of the semiconductor gain chip.

[0033] Based on the above embodiments, the material of the P-side metal layer 1 in this embodiment includes Ti / Pt / Au or Ti / Au, with a thickness of 200nm-500nm; the N-side metal layer 11 includes AuGeNi alloy / Au or AuGe alloy / Au, with a thickness of 200nm-500nm.

[0034] Based on the above embodiment, the material of the P-side electrical isolation layer 2 in this embodiment includes SiN x Or SiO x , thickness is 200nm-500nm.

[0035] Based on the above embodiments, the material of the P-type contact layer 3 in this embodiment includes highly doped GaAs or In x Ga 1-x As, the doping concentration can be 1.5×10 20 cm -3 -3×10 20 cm -3 , thickness is 100nm-200nm.

[0036] Based on the above embodiment, the material of the P-type waveguide layer 4 in this embodiment includes InP with a thickness of 1000nm-3000nm; the material of the N-type waveguide layer 8 is InP. x Ga 1-x As y P 1-y , thickness is 50nm-300nm.

[0037] Based on the above embodiment, the material of the active region 6 in this embodiment includes In x Ga 1-x As y P 1-y The quantum well / barrier structure has a thickness of 10nm-30nm.

[0038] Based on the above embodiment, the materials of the P-type confinement layer 5 and the N-type confinement layer 7 in this embodiment include In x Ga 1-x As y P 1-y , thickness is 20nm-100nm.

[0039] On the basis of the above-mentioned embodiment, the material of the N-type buffer layer 9 in this embodiment includes InP, and the thickness is 50nm-200nm; the material of the substrate 10 includes InP.

[0040] A specific example is listed below for illustration. It should be understood that this example is only for clarifying the present invention, and the following parameters are only exemplary and are not intended to limit the present invention.

[0041] In this example, the P-side metal layer 1 is located on the P-side electrical isolation layer 2 composed of SiO2 and is deposited by a metal sputtering device, with a metal thickness of 400nm Ti / Pt / Au.

[0042] The P-side electrical isolation layer 2 covers both sides of the ridge waveguide structure, the double grooves and the ridge platforms on both sides of the double grooves, and serves as a current injection isolation layer. The material is SiO2 and the thickness is 300nm, which is deposited by PECVD.

[0043] The material of the P-type contact layer 3 is highly doped GaAs with a doping concentration of 2×10 20 cm -3 , with a thickness of about 150 nm, and high doping facilitates the formation of good ohmic contact with the electrode formed by the P-side metal layer 1.

[0044] The material of the P-type waveguide layer 4 is InP, with a thickness of about 1800 nm and a doping concentration of 1×10 18 cm -3 .

[0045] The material of the upper confinement layer 5 is In 0.21 Ga 0.79 As 0.3 P 0.7 , thickness is about 50nm, and no doping is performed.

[0046] The material of the active layer 6 is compressively strained In 0.15 Ga 075 As 0.45 P 0.55 The quantum well / barrier structure has a thickness of about 20nm.

[0047] The material of the lower confinement layer 7 is In 0.21 Ga 0.79 As 0.3 P 0.7, thickness is about 20nm, and no doping is performed.

[0048] The material of the N-type waveguide layer 8 is In 0.15 Ga 0.75 As 0.23 P 0.77 , with a thickness of about 230 nm and a doping concentration of 2×10 18 cm -3 .

[0049] The material of the N-type buffer layer 9 is InP, with a thickness of about 100 nm and a doping concentration of 1×10 18 cm -3 .

[0050] The material of the N-type substrate 10 is InP, and the doping concentration is 4×10 18 cm -3 , the thickness of the substrate after thinning is 100 μm.

[0051] The entire length of the semiconductor gain chip is 1000 μm, and the length of the straight waveguide region occupies 1 / 2 of the length of the semiconductor gain chip.

[0052] The waveguide structure of the semiconductor gain chip can be transferred from the mask to the chip by photolithography and etching.

[0053] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems and methods according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram may represent a module, a program segment or a part of a code, and the above-mentioned module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box may also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0054] It will be appreciated by those skilled in the art that the features described in the various embodiments and / or claims of the present invention may be combined and / or combined in various ways, even if such combinations and / or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments and / or claims of the present invention may be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All of these combinations and / or combinations fall within the scope of the present invention.

[0055] The embodiments of the present invention are described above. However, these embodiments are only for the purpose of illustration, and are not intended to limit the scope of the present invention. Although each embodiment is described above, it does not mean that the measures in each embodiment cannot be used in combination. The scope of the present invention is defined by the attached claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A semiconductor gain chip, characterized in that: include: An N-side metal layer, a substrate, an N-type buffer layer, an N-type waveguide layer, an N-type confinement layer, an active region, a P-type confinement layer, a P-type waveguide layer, a P-type contact layer, a P-side electrical isolation layer and a P-side metal layer are sequentially stacked; The preset area of ​​the P-type waveguide layer is prepared as a ridge waveguide structure, and the ridge waveguide structure includes a straight waveguide area and a slanted waveguide area. The P-type contact layer covers the ridge waveguide structure and the ridge platforms on both sides of the double groove. The P-side electrical isolation layer covers both sides of the ridge waveguide structure, the double groove and the ridge platforms on both sides of the double groove. The P-side metal layer covers the P-type contact layer and the P-side electrical isolation layer.

2. The semiconductor gain chip according to claim 1, characterized in that: Triangular side structures are arranged on both sides of the straight waveguide region and the oblique waveguide region, and the side structures are used to increase the diffraction loss of the reflected light during the optical transmission process in the waveguide structure.

3. The semiconductor gain chip according to claim 1, characterized in that: The length of the straight waveguide region accounts for 1 / 2 to 2 / 3 of the length of the semiconductor gain chip.

4. The semiconductor gain chip according to claim 1, characterized in that: The material of the P-side metal layer includes Ti / Pt / Au or Ti / Au, and the thickness is 200nm-500nm; The N-side metal layer includes AuGeNi alloy / Au or AuGe alloy / Au, and has a thickness of 200nm-500nm.

5. The semiconductor gain chip according to claim 1, characterized in that: The material of the P-side electrical isolation layer includes SiN x Or SiO x , thickness is 200nm-500nm.

6. The semiconductor gain chip according to claim 1, characterized in that: The material of the P-type contact layer includes highly doped GaAs or In x Ga 1-x As, doping concentration is 1.5×10 20 cm -3 -3×10 20 cm -3 , thickness is 100nm-200nm.

7. The semiconductor gain chip according to claim 1, characterized in that: The material of the P-type waveguide layer includes InP, and the thickness is 1000nm-3000nm; The material of the N-type waveguide layer is In x Ga 1-x As y P 1-y , thickness is 50nm-300nm.

8. The semiconductor gain chip according to claim 1, characterized in that: The material of the active region includes In x Ga 1- x As y P 1-y The quantum well / barrier structure has a thickness of 10nm-30nm.

9. The semiconductor gain chip according to claim 1, characterized in that: The materials of the P-type limiting layer and the N-type limiting layer include In x Ga 1-x As y P 1-y , thickness is 20nm-100nm.

10. The semiconductor gain chip according to claim 1, characterized in that: The material of the N-type buffer layer includes InP, and the thickness is 50nm-200nm; The material of the substrate includes InP.

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