Clock detection circuit and circuit system

Abstract

The embodiment of the invention discloses a clock detection circuit which is used in the technical field of clock detection. In the circuit, the input end of a level clock discrimination module is connected with a signal input end, and the output end of the level clock discrimination module is connected with a conduction control end of a second switch tube; the first output end of the second switch tube is connected with the input end of the capacitor charging and discharging unit, the second output end of the second switch tube is connected with the second input end of the current mirror, and the current mirror is used for driving a capacitor of the capacitor charging and discharging unit to charge and discharge; the output end of the capacitor charging and discharging unit is connected with the second comparison end of the current comparator module, the output end of the current comparator module is connected with the signal output end, and the current comparator module is used for comparing signals received by the first comparison end and the second comparison end and outputting a level signal of a comparison result. The current mirror is used for driving the capacitor of the capacitor charging and discharging unit to perform charging and discharging, and the current mirror has relatively large resistance, so that the clock detection circuit has a relatively small area under the condition of meeting low power consumption.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of clock detection technology, and in particular, to a clock detection circuit and a circuit system. Background Art

[0002] During the startup process of the existing digital system circuit, the instability of the clock will cause the system to start abnormally or even fail; and the abnormal loss of the clock signal will directly cause the system to stop working suddenly. In order to reduce the impact of clock abnormality on the normal operation of the digital system, it is necessary to design a clock detection circuit to detect the control signal of the digital system. The existing clock detection circuit is used to output a low level or a high level alarm according to the input clock signal.

[0003] The existing clock detection circuit includes: a level clock discrimination module, a capacitor charging and discharging module, a current comparator module, and a bias current module. The bias current module is used to act as a mirror current source of the bias current, and the function of the mirror current source is to generate a bias current to provide a mirror current to other circuits. The signal input to the clock detection circuit outputs a high level or a clock signal through the level clock discrimination module. The signal output by the level clock discrimination module controls the capacitor charging and discharging module to charge and discharge the capacitor. When the output signal is a constant high level, the capacitor is always discharged to the ground potential; when the output signal is a clock signal, the capacitor is charged during the high level period and discharged during the low level period. The voltage output by the capacitor charging and discharging module is compared by the current comparator. When the voltage output by the capacitor charging and discharging module is higher than the flip threshold of the current comparator, the current comparator module outputs a low level; when the voltage output by the capacitor charging and discharging module is lower than the flip threshold of the current comparator, the current comparator module outputs a high level alarm.

[0004] When the existing clock detection circuit needs to meet the low power consumption design, the resistor in the capacitor charging and discharging module corresponding to the clock detection circuit needs to be designed to be very large, so the area of ​​the resistor will be very large, which easily leads to an excessively large area of ​​the clock detection circuit. Summary of the invention

[0005] The embodiments of the present application provide a clock detection circuit and a circuit system, which can enable the clock detection circuit to have a smaller area while meeting the low power consumption condition.

[0006] The embodiment of the present application provides a clock detection circuit, including: a bias current module, a level clock determination module, a capacitor charging and discharging module and a current comparator module; the capacitor charging and discharging module includes: a first switch tube, a second switch tube, a current mirror and a capacitor charging and discharging unit;

[0007] One end of the bias current module is connected to the conduction control end of the first switch tube, and the other end is connected to the first comparison end of the current comparator module, and is used to input bias current to the first switch tube and the current comparator module;

[0008] The input end of the first switch tube is connected to the power supply end, the first output end of the first switch tube is connected to the first input end of the current mirror, and the second output end of the first switch tube is connected to the input end of the second switch tube;

[0009] The input end of the level clock discrimination module is connected to the signal input end, and the output end is connected to the conduction control end of the second switch tube, and is used to output a control signal to the conduction control end of the second switch tube according to the detection signal input from the signal input end;

[0010] The first output end of the second switch tube is connected to the input end of the capacitor charging and discharging unit, and the second output end of the second switch tube is connected to the second input end of the current mirror, and the current mirror is used to drive the capacitor of the capacitor charging and discharging unit to charge and discharge;

[0011] The output end of the capacitor charging and discharging unit is connected to the second comparison end of the current comparator module, and the output end of the current comparator module is connected to the signal output end. The current comparator module is used to compare the signals received by the first comparison end and the second comparison end, and output a level signal corresponding to the comparison result to the signal output end.

[0012] Furthermore, the level clock determination module includes: a first inverter, a delay unit and an XNOR gate unit;

[0013] The input end of the first inverter is connected to the signal input end, and the output end of the first inverter is respectively connected to the input end of the delay unit and the first input end of the XNOR gate unit;

[0014] The output end of the delay unit is connected to the second input end of the XNOR gate unit, and the output end of the XNOR gate unit is connected to the conduction control end of the second switch tube.

[0015] Further, the delay unit includes: a plurality of parallel-connected PMOS tubes, a plurality of groups of MOS tube circuits, a third inverter and a fourth inverter;

[0016] The MOS tube circuit comprises a PMOS tube and an NMOS tube, the drain of the PMOS tube is connected to the drain of the NMOS tube, the gate of the PMOS tube is connected to the gate of the NMOS tube, and the source of the NMOS tube is grounded;

[0017] The gate electrodes of the plurality of parallel PMOS tubes are connected to ground, and the drain electrodes of the plurality of parallel PMOS tubes are respectively connected to the source electrodes of the PMOS tubes of a group of the MOS tube circuits;

[0018] A plurality of groups of the MOS tube circuits are connected in series, and the input end of the first-stage MOS tube circuit connected in series is connected to the output end of the first inverter, and the output end of the last-stage MOS tube circuit connected in series is connected to the input end of the third inverter;

[0019] The output end of the third inverter is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the second input end of the XNOR gate unit.

[0020] Further, the first switch tube includes a third PMOS tube and a fourth PMOS tube, and the second switch tube includes: a second NMOS tube and a fifth PMOS tube;

[0021] The source of the third PMOS tube and the source of the fourth PMOS tube are both connected to the power supply end, and the gate of the third PMOS tube is connected to the gate of the fourth PMOS tube and one end of the bias current module;

[0022] The drain of the fourth PMOS tube is connected to the first input terminal of the current mirror, and the drain of the third PMOS tube is connected to the source of the fifth PMOS tube;

[0023] The gate of the fifth PMOS tube is connected to the gate of the second NMOS tube and the output end of the level clock determination module;

[0024] The drain of the fifth PMOS tube is connected to the drain of the second NMOS tube and the input end of the capacitor charging and discharging unit;

[0025] The source of the second NMOS tube is connected to the second input terminal of the current mirror.

[0026] Further, the current mirror includes: a third NMOS tube and a fourth NMOS tube;

[0027] The drain of the fourth NMOS tube is connected to the drain of the fourth PMOS tube, the gate of the fourth NMOS tube and the gate of the third NMOS tube;

[0028] The drain of the third NMOS tube is connected to the source of the second NMOS tube;

[0029] The source of the third NMOS tube and the source of the fourth NMOS tube are both grounded.

[0030] Further, the capacitor charging and discharging unit includes: a first resistor, a first capacitor, a second capacitor, a sixth PMOS transistor and a seventh PMOS transistor;

[0031] The source of the sixth PMOS tube and the source of the seventh PMOS tube are both connected to the power supply terminal, and the gate of the sixth PMOS tube and the gate of the seventh PMOS tube are both connected to the enable terminal;

[0032] The first end of the first capacitor is connected to the drain of the fifth PMOS transistor, the first end of the first resistor and the drain of the sixth PMOS transistor, and the second end of the first capacitor is grounded;

[0033] The second end of the first resistor is connected to the first end of the second capacitor, the drain of the seventh PMOS tube and the second comparison end of the current comparator module, and the second end of the second capacitor is grounded.

[0034] Further, the bias current module includes: a second PMOS tube and a fifth NMOS tube;

[0035] The source of the second PMOS tube is connected to the power supply end;

[0036] The gate of the second PMOS tube is connected to the drain of the second PMOS tube, the gate of the third PMOS tube, the drain of the fifth NMOS tube and the first comparison terminal of the current comparator module;

[0037] The gate of the fifth NMOS tube is connected to the enable terminal, and the source of the fifth NMOS tube is grounded.

[0038] Furthermore, it also includes: a level controller

[0039] The level controller is connected to the enable end, and is used to control the level signal of the enable end to drive the fifth NMOS tube, the sixth PMOS tube, and the seventh PMOS tube to be turned on or off.

[0040] Further, the current comparator module includes: a first PMOS tube, a first NMOS tube, a Schmitt trigger and a second inverter;

[0041] The source of the first PMOS tube is connected to the power supply end, and the gate of the first PMOS tube is connected to the gate of the second PMOS tube;

[0042] The drain of the first PMOS tube is connected to the drain of the first NMOS tube and the input end of the Schmitt trigger;

[0043] The gate of the first NMOS transistor is connected to the first end of the second capacitor, and the source of the first NMOS transistor is grounded;

[0044] The output end of the Schmitt trigger is connected to the input end of the second inverter, and the output end of the second inverter is connected to the signal output end.

[0045] The embodiment of the present application further provides a circuit system, comprising: the bias current module, the level clock determination module, the capacitor charging and discharging module and the current comparator module as described above.

[0046] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0047] The clock detection circuit of the embodiment of the present application includes: a bias current module, a level clock discrimination module, a capacitor charging and discharging module and a current comparator module; the capacitor charging and discharging module includes: a first switch tube, a second switch tube, a current mirror and a capacitor charging and discharging unit; one end of the bias current module is connected to the conduction control end of the first switch tube, and the other end is connected to the first comparison end of the current comparator module, for inputting bias current to the first switch tube and the current comparator module; the input end of the first switch tube is connected to the power supply end, the first output end of the first switch tube is connected to the first input end of the current mirror, and the second output end of the first switch tube is connected to the input end of the second switch tube; the input end of the level clock discrimination module is connected to the signal The first output end of the second switch tube is connected to the input end of the capacitor charging and discharging unit, and the second output end of the second switch tube is connected to the second input end of the current mirror, and the current mirror is used to drive the capacitor of the capacitor charging and discharging unit to charge and discharge; the output end of the capacitor charging and discharging unit is connected to the second comparison end of the current comparator module, and the output end of the current comparator module is connected to the signal output end, and the current comparator module is used to compare the signals received by the first comparison end and the second comparison end, and output the level signal corresponding to the comparison result to the signal output end. By using the current mirror to drive the capacitor of the capacitor charging and discharging unit to charge and discharge, the current mirror has a large resistance, and there is no need to use a large area of ​​large resistance in the capacitor charging and discharging module, and the area of ​​the current mirror is small, which can make the clock detection circuit have a small area under the condition of meeting low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0049] Figure 1 A circuit diagram of an existing clock detection circuit disclosed in an embodiment of the present application;

[0050] Figure 2 A circuit block diagram of a clock detection circuit disclosed in an embodiment of the present application;

[0051] Figure 3 A circuit structure diagram of a clock detection circuit disclosed in an embodiment of the present application;

[0052] Figure 4 This is a circuit structure diagram of a delay unit disclosed in an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0054] In the description of the embodiments of the present application, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the embodiments of the present application.

[0055] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0056] Existing clock detection circuits such as Figure 1As shown, the clock detection circuit includes a level clock determination module 101, a capacitor charge and discharge module 102, a bias current module 103 and a current comparator module 104; wherein, the inverter INV1, the delay unit Delay module and the XNOR gate XNOR constitute the level clock determination module 101; the PMOS tubes P4, P3, P5, P6, the resistors R1, R2, the capacitors C1, C2 constitute the capacitor charge and discharge module 102; the PMOS tube P2 is the bias current module 103; the PMOS tube P1, the NMOS tube N1 and the inverters INV2, INV3 constitute the current comparator module 104. However, when the existing clock detection circuit needs to meet the low power consumption design, the resistor R2 in the capacitor charge and discharge module corresponding to the clock detection circuit needs to be designed to be very large, so that the area of ​​the resistor will be very large, which easily leads to an excessively large area of ​​the clock detection circuit. Therefore, the embodiment of the present application provides a clock detection circuit, which can make the clock detection circuit have a smaller area while meeting the low power consumption condition, as shown in FIG. Figure 2 as well as Figure 3 shown.

[0057] The clock detection circuit provided in the embodiment of the present application includes: a bias current module 203, a level clock determination module 201, a capacitor charge and discharge module 202 and a current comparator module 204; wherein, the capacitor charge and discharge module 202 includes: a first switch tube 2021, a second switch tube 2022, a current mirror 2023 and a capacitor charge and discharge unit 2024; one end of the bias current module 203 is connected to the conduction control end of the first switch tube 2021, and the other end is connected to the first comparison end of the current comparator module 204, for inputting a bias current to the first switch tube 2021 and the current comparator module 204; it can be understood that the bias current module 203 is used to generate a bias current to provide a mirror current to other circuits. The input end of the first switch tube 2021 is connected to the power supply end VDDDLSE, the first output end of the first switch tube 2021 is connected to the first input end of the current mirror 2023, and the second output end of the first switch tube 2021 is connected to the input end of the second switch tube 2022; the input end of the level clock determination module 201 is connected to the signal input end Isi_fd_clk_in, and the output end is connected to the conduction control end of the second switch tube 2022, and is used to output a control signal to the conduction control end of the second switch tube 2022 according to the detection signal input by the signal input end Isi_fd_clk_in.

[0058] It can be understood that the signal inputted by the signal input terminal Isi_fd_clk_in outputs a high level or a clock signal through the level clock discrimination module 201, and the level clock discrimination module 201 outputs a signal to control the capacitor charging and discharging module 202 to charge and discharge the capacitor. The first output terminal of the second switch tube 2022 is connected to the input terminal of the capacitor charging and discharging unit 2024, and the second output terminal of the second switch tube 2022 is connected to the second input terminal of the current mirror 2023, and the current mirror 2023 is used to drive the capacitor of the capacitor charging and discharging unit 2024 to charge and discharge. It can be understood that when the control signal (A-terminal signal) outputted by the level clock discrimination module 201 is a constant high level, the capacitor of the capacitor charging and discharging unit 2024 is always discharged to the ground potential; when the control signal (A-terminal signal) outputted by the level clock discrimination module 201 is a clock signal, the capacitor of the capacitor charging and discharging unit 2024 is discharged during the high level period, and the capacitor of the capacitor charging and discharging unit 2024 is charged during the low level period. The output end of the capacitor charging and discharging unit 2024 is connected to the second comparison end of the current comparator module 204, and the output end of the current comparator module 204 is connected to the signal output end Isi_fd_out. The current comparator module 204 is used to compare the signals received by the first comparison end and the second comparison end, and output the level signal corresponding to the comparison result to the signal output end. It can be understood that the voltage output by the capacitor charging and discharging module 202 is compared by the current comparator module 204. When the voltage output by the capacitor charging and discharging module 202 is higher than the flip threshold of the current comparator module 204, the current comparator module 204 outputs a low level; when the voltage output by the capacitor charging and discharging module 202 is lower than the flip threshold of the current comparator module 204, the current comparator module 204 outputs a high level alarm.

[0059] It can be seen that the clock detection circuit of the embodiment of the present application includes: a bias current module, a level clock discrimination module, a capacitor charging and discharging module and a current comparator module; the capacitor charging and discharging module includes: a first switch tube, a second switch tube, a current mirror and a capacitor charging and discharging unit; one end of the bias current module is connected to the conduction control end of the first switch tube, and the other end is connected to the first comparison end of the current comparator module, which is used to input the bias current to the first switch tube and the current comparator module; the input end of the first switch tube is connected to the power supply end, the first output end of the first switch tube is connected to the first input end of the current mirror, and the second output end of the first switch tube is connected to the input end of the second switch tube; the input end of the level clock discrimination module The first output end of the second switch tube is connected to the input end of the capacitor charging and discharging unit, and the second output end of the second switch tube is connected to the second input end of the current mirror, and the current mirror is used to drive the capacitor of the capacitor charging and discharging unit to charge and discharge; the output end of the capacitor charging and discharging unit is connected to the second comparison end of the current comparator module, and the output end of the current comparator module is connected to the signal output end, and the current comparator module is used to compare the signals received by the first comparison end and the second comparison end, and output the level signal corresponding to the comparison result to the signal output end. By using the current mirror to drive the capacitor of the capacitor charging and discharging unit to charge and discharge, the current mirror has a large resistance, and there is no need to use a large area of ​​large resistance in the capacitor charging and discharging module, and the area of ​​the current mirror is small, which can make the clock detection circuit have a small area under the condition of meeting low power consumption. The embodiment of the present application proposes a clock detection circuit, which uses a pair of current mirrors to charge and discharge a capacitor according to a certain current ratio. Since the current mirror is used instead of a resistor to discharge the capacitor, the area of ​​the clock detection circuit is effectively reduced, so it can have very low power consumption in a reasonable area. In response to the demand for reducing the power consumption of the clock detection circuit, a low-power clock detection circuit is proposed. This solution has lower power consumption than the traditional clock detection circuit in the same area.

[0060] Further, such as Figure 3As shown, the level clock determination module 201 includes: a first inverter INV1, a delay unit Delay and an XNOR gate unit XNOR; the input end of the first inverter INV1 is connected to the signal input end Isi_fd_clk_in, and the output end of the first inverter INV1 is respectively connected to the input end of the delay unit Delay and the first input end of the XNOR gate unit XNOR; the output end of the delay unit (Delay module) is connected to the second input end of the XNOR gate unit XNOR, and the output end of the XNOR gate unit XNOR is connected to the conduction control end of the second switch tube 2022. It can be understood that when the input signal of the signal input end Isi_fd_clk_in is a low potential or a power supply potential, the level clock determination module 201 outputs a high level to the conduction control end of the second switch tube 2022; when the input signal is a low-frequency clock signal, the level clock determination module 201 outputs a pulse width of t to the conduction control end of the second switch tube 2022. D Low level of time, T / 2-t D The high level clock signal of the time, where T is the input signal clock period, t D When the input signal is a high-frequency clock signal, the level clock determination module 201 outputs a signal with the same frequency and pulse width as the input signal to the conduction control terminal of the second switch tube 2022 .

[0061] Further, such as Figure 4As shown, the delay unit includes: multiple parallel PMOS tubes (P9, P10, P11, P12), multiple groups of MOS tube circuits, a third inverter INV3 and a fourth inverter INV4 and capacitors C3 and C4; the MOS tube circuit includes a PMOS tube and an NMOS tube, the drain of the PMOS tube is connected to the drain of the NMOS tube, the gate of the PMOS tube is connected to the gate of the NMOS tube, and the source of the NMOS tube is grounded; it can be understood that the PMOS tube P13 and the NMOS tube N5, the PMOS tube P14 and the NMOS tube N6, the PMOS tube P15 and the NMOS tube N7, the PMOS tube P8 and the NMOS tube N8, respectively constitute a group of MOS tube circuits. The gates of multiple parallel PMOS tubes are connected to the ground, and the drains of multiple parallel PMOS tubes are respectively connected to the source of the PMOS tube of a group of MOS tube circuits; multiple groups of MOS tube circuits are connected in series, and the input end X of the first-stage MOS tube circuit in series (i.e., the input end of the delay unit) is connected to the output end of the first inverter INV1, and the output end of the series-connected tail-stage MOS tube circuit is connected to the input end of the third inverter INV3; the output end of the third inverter INV3 is connected to the input end of the fourth inverter INV4, and the output end Y of the fourth inverter INV4 (i.e., the output end of the delay unit) is connected to the second input end of the XNOR gate unit XNOR. It can be understood that when the input signal of the input end of the delay unit is a fixed low level, the output end Y of the delay unit outputs a low level, when the input signal of the input end is a fixed high level, the output end Y outputs a high level, and when the input signal of the input end is a low-frequency clock signal, the output end Y outputs a low-frequency clock signal with the same amplitude and pulse width as the input signal, and its signal will be delayed for a time t D The delay time is mainly related to capacitors C3, C4, I1 (the on-current of PMOS tube P9), and I2 (the on-current of PMOS tube P10). When the input signal at the input end is a high-frequency clock signal, the output end Y outputs a high level.

[0062] Furthermore, the first switch tube 2021 in the current charging and discharging module 202 includes a third PMOS tube P3 and a fourth PMOS tube P4, and the second switch tube 2022 includes: a second NMOS tube N2 and a fifth PMOS tube P5; wherein, the source of the third PMOS tube P3 and the source of the fourth PMOS tube P4 are both connected to the power supply terminal VDDDLSE, and the gate of the third PMOS tube P3 is connected to the gate of the fourth PMOS tube P4 and one end of the bias current module 203; it can be understood that the conduction control end of the first switch tube 2021 is the gate of the third PMOS tube P3 and the gate of the fourth PMOS tube P4. The drain of the fourth PMOS tube P4 is connected to the first input terminal of the current mirror 2023, the drain of the third PMOS tube P3 is connected to the source of the fifth PMOS tube P5; the gate of the fifth PMOS tube P5 is connected to the gate of the second NMOS tube N2 and the output terminal of the level clock discrimination module 201; it can be understood that the conduction control terminal of the second switch tube 2022 is the gate of the fifth PMOS tube P5 and the gate of the second NMOS tube N2. The drain of the fifth PMOS tube P5 is connected to the drain of the second NMOS tube N2 and the input terminal of the capacitor charging and discharging unit 2024; the source of the second NMOS tube N2 is connected to the second input terminal of the current mirror 2023.

[0063] Furthermore, the current mirror 2023 in the capacitor charging and discharging module 202 includes: a third NMOS tube N3 and a fourth NMOS tube N4; the drain of the fourth NMOS tube N4 is connected to the drain of the fourth PMOS tube P4, the gate of the fourth NMOS tube N4 and the gate of the third NMOS tube N3; the drain of the third NMOS tube N3 is connected to the source of the second NMOS tube N2; the source of the third NMOS tube and the source of the fourth NMOS tube are both grounded.

[0064] Furthermore, the capacitor charging and discharging unit 2024 in the capacitor charging and discharging module 202 includes: a first resistor R1, a first capacitor C1, a second capacitor C2, a sixth PMOS tube P6 and a seventh PMOS tube P7; the source of the sixth PMOS tube P6 and the source of the seventh PMOS tube P7 are both connected to the power supply end, and the gate of the sixth PMOS tube P6 and the gate of the seventh PMOS tube P7 are both connected to the enable end EN; the first end of the first capacitor C1 is connected to the drain of the fifth PMOS tube P5, the first end of the first resistor R1 and the drain of the sixth PMOS tube P6, and the second end of the first capacitor C1 is grounded; the second end of the first resistor R1 is connected to the first end of the second capacitor C2, the drain of the seventh PMOS tube P7 and the second comparison end of the current comparator module 204, and the second end of the second capacitor C2 is grounded. It can be understood that when the signal input from the output terminal A of the level clock determination module 201 to the capacitor charge and discharge module 202 is a high level, the fifth PMOS tube P5 is turned off, the second NMOS tube N2 is turned on, and the first capacitor C1 is discharged to a low potential through the current branch formed by the third NMOS tube N3 and the second NMOS tube N2; when the signal input from the output terminal A of the level clock determination module 201 to the capacitor charge and discharge module 202 is a clock signal, the first capacitor C1 is charged during the period when the clock signal is a low level, and the first capacitor C1 is discharged during the period when the clock signal is a high level. The function of the first resistor R1 and the second capacitor C2 is to filter the voltage at the input terminal B of the capacitor charge and discharge unit 2024.

[0065] Further, the bias current module 203 includes: a second PMOS tube P2 and a fifth NMOS tube N5; the source of the second PMOS tube P2 is connected to the power supply terminal VDDDLSE; the gate of the second PMOS tube P2 is connected to the drain of the second PMOS tube P2, the gate of the third PMOS tube P3, the drain of the fifth NMOS tube N5 and the first comparison terminal of the current comparator module 204; the gate of the fifth NMOS tube N5 is connected to the enable terminal EN, and the source of the fifth NMOS tube N5 is grounded. That is, the second PMOS tube P2 and the third PMOS tube P3 form a current mirror to provide a mirror current to the third PMOS tube P3; the second PMOS tube P2 and the fourth PMOS tube P4 form a current mirror to provide a mirror current to the fourth PMOS tube P4. It can be understood that the enable terminal of the bias current module 203 and the enable terminal of the capacitor charge and discharge unit 2024 in the embodiment of the present application are generally the same enable terminal, that is, the same signal is enabled.

[0066] Further, the current comparator module 204 includes: a first PMOS tube P1, a first NMOS tube N1, a Schmitt trigger schmitt and a second inverter INV2; the source of the first PMOS tube P1 is connected to the power supply terminal, and the gate of the first PMOS tube P1 is connected to the gate of the second PMOS tube P2; the drain of the first PMOS tube P1 is connected to the drain of the first NMOS tube N1 and the input end of the Schmitt trigger schmitt, and the connection point can be called point D. The gate of the first NMOS tube N1 is connected to the first end of the second capacitor C2, and the connection point is called point C. The source of the first NMOS tube N1 is grounded; the output end of the Schmitt trigger schmitt is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 (i.e., the output end of the current comparator module 204) is connected to the signal output end Isi_fd_out. The current comparator module 204 is used to output a low level at the output end of the current comparator module 204 when the gate voltage of the first NMOS tube N1 (i.e., the second comparison end of the current comparator module 204) is higher than the flip threshold of the current comparator module 204; and output a high level at the output end of the current comparator module 204 when the gate voltage of the first NMOS tube N1 is lower than the flip threshold of the current comparator module 204.

[0067] Further, the clock detection circuit of the embodiment of the present application also includes a level controller, which can be MAX232, CH340G or CH340C, which is not specifically limited here. The level controller is connected to the enable terminal EN, and is used to control the level signal of the enable terminal EN to drive the fifth NMOS tube N5, the sixth PMOS tube P6 and the seventh PMOS tube P7 to be turned on or off. The level controller can control the signal of the enable terminal EN to be disabled, the level of point C is always pulled high, which exceeds the flip threshold of the current comparator module 204, the voltage of point D is pulled low, and the signal output terminal lsi_fd_out outputs a low level without alarming. Specifically, the EN signal is not enabled, which means that the signal of the enable terminal EN is at a low level. At this time, the fifth NMOS tube N5 is turned off, and the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3 and the fourth PMOS tube P4 cannot be turned on; at the same time, the sixth PMOS tube P6 and the seventh PMOS tube P7 are turned on, and the current at the power supply end flows into the point C (the gate of the first NMOS tube N1) through the sixth PMOS tube P6 and the seventh PMOS tube P7, pulling up the level of the point C, so that the first NMOS tube N1 is turned on, and the point D is grounded through the first NMOS tube N1, and the potential of the point D is pulled down.

[0068] The level controller can also control the signal enable of the enable terminal EN, and when the control clock detection circuit works, the bias current module generates a bias current to provide a mirror current to other circuits, and the input signal of the signal input terminal is judged by the level clock judgment module. Specifically, the signal enable of the enable terminal EN is high level, the sixth PMOS tube P6 and the seventh PMOS tube P7 are turned off, the fifth NMOS tube N5 is turned on, and the gate potentials of the first PMOS tube P1, the second PMOS tube P2, the third PMOS tube P3 and the fourth PMOS tube P4 are pulled down and turned on.

[0069] When the signal inputted from the signal input terminal to the level clock determination module 201 is at a low level, the X point is at a high level, the Y point is at a high level, and the level clock determination module 201 outputs a high level, that is, the A point is at a high level. At this time, the fifth PMOS tube P5 is turned off, the second NMOS tube N2 is turned on, and the first capacitor C1 is discharged to the ground potential through the current branch formed by the third NMOS tube N3 and the second NMOS tube N2. The B point and the C point are at a low potential. Since the potential at the C point is lower than the flip threshold of the current comparator module 204, the voltage at the D point is pulled up, and the signal output terminal lsi_fd_out outputs a high level alarm. Specifically, since the first NMOS tube N1 is turned off, the first PMOS tube P1 is turned on, the current at the power supply end flows into the D point, and the voltage at the D point is pulled up.

[0070] When the signal input from the signal input terminal to the level clock determination module 201 is at a high level, point X is at a low level, point Y is at a low level, and the level clock determination module 201 determines and outputs a high level, that is, point A is at a high level. At this time, the fifth PMOS tube P5 is turned off, the second NMOS tube N2 is turned on, and the first capacitor C1 is discharged to the ground potential through the current branch formed by the third NMOS tube N3 and the second NMOS tube N2. Points B and C are at a low potential. Since the potential at point C is lower than the flip threshold of the current comparator module 204, the voltage at point D is pulled up, and the signal output terminal lsi_fd_out outputs a high level alarm.

[0071] When the input signal from the signal input terminal to the level clock determination module 201 is a low-frequency clock signal, the output signal of the level clock determination module 201 is a low-frequency clock signal. In one input clock cycle, the average current flowing through the first capacitor C1, the first resistor R1, and the second capacitor C2 is:

[0072]

[0073] Among them, t D is the delay time of the delay unit to the clock signal, Tin is the clock cycle of the input signal, I REFis the bias reference current, m and n are the size ratios of the fourth PMOS tube P4, the third PMOS tube P3 and the second PMOS tube P2, s is the negative pole of the power supply, and f is the frequency of the input signal. Among them, half a clock cycle Tin is greater than the delay time t of the delay module D .

[0074] It can be seen that when the input signal is a low-frequency clock signal, the output pulse width of the level clock discrimination module is 2t within one cycle of the input signal. D Low level of time, Tin-2t D The clock signal of high level at the time, wherein Tin is the clock period of the input signal. When the frequency f of the input signal is low to a certain value so that the average current is less than 0, the gate voltage VGSN1 (potential at point C) of the first NMOS tube N1 will drop below the flip threshold of the current comparator module 204 over time, the voltage at point D will be pulled up, and the signal output terminal lsi_fd_out of the clock detection circuit will output a high level alarm, that is, at this time, the voltage at point C is less than the conduction voltage of the first NMOS tube N1, the first NMOS tube N1 is turned off, and the potential at point D increases.

[0075] When the input signal from the signal input terminal to the level clock determination module 201 is a high-frequency clock signal, point X is a clock signal with opposite amplitude, point Y outputs a high level, and the level clock determination module 201 outputs the same clock signal as point X, that is, the output signal is a high-frequency clock signal. In one input clock cycle, the average current flowing through the first capacitor C1, the first resistor R1, and the second capacitor C2 is:

[0076]

[0077] Among them, Tin is the clock period of the input signal, I REF is the bias reference current, and m and n are the size ratios of the fourth PMOS tube P4, the third PMOS tube P3 and the second PMOS tube P2. In the clock detection circuit of the embodiment of the present application, m is greater than n, that is, the size ratio m:n of the third PMOS tube P3 and the fourth PMOS tube P4 is greater than 1; at this time, the average current is always greater than 0, that is, the gate voltage VGSN1 of the first NMOS tube N1 is always higher than the flip threshold of the current comparator module 204, that is, the voltage at point C is greater than the turn-on voltage of the first NMOS tube N1, the first NMOS tube N1 is turned on, the voltage at point D is pulled down, and the clock detection circuit outputs a low level without alarming.

[0078] To sum up, in the clock detection circuit of the embodiment of the present application, when the input signal of the signal input end is a high-frequency clock signal, the signal output end lsi_fd_out outputs a low level and no alarm occurs; when the input signal of the signal input end is a low level, a high level, and a low-frequency clock signal, the signal output end lsi_fd_out outputs a high level and an alarm occurs.

[0079] The embodiment of the present application further provides a circuit system, comprising: the bias current module, the level clock determination module, the capacitor charging and discharging module and the current comparator module as described above.

[0080] In the present invention, the terms "first", "second", "third", and "fourth" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more, unless otherwise clearly defined.

[0081] The above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, rather than to limit them. Although the embodiments of the present application are described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and description of the embodiments of the present application.

Claims

1. A clock detection circuit, characterized in that: include: Bias current module, level clock determination module, capacitor charging and discharging module and current comparator module; The capacitor charging and discharging module includes: a first switch tube, a second switch tube, a current mirror and a capacitor charging and discharging unit; One end of the bias current module is connected to the conduction control end of the first switch tube, and the other end is connected to the first comparison end of the current comparator module, and is used to input bias current to the first switch tube and the current comparator module; The input end of the first switch tube is connected to the power supply end, the first output end of the first switch tube is connected to the first input end of the current mirror, and the second output end of the first switch tube is connected to the input end of the second switch tube; The input end of the level clock discrimination module is connected to the signal input end, and the output end is connected to the conduction control end of the second switch tube, and is used to output a control signal to the conduction control end of the second switch tube according to the detection signal input from the signal input end; The first output end of the second switch tube is connected to the input end of the capacitor charging and discharging unit, and the second output end of the second switch tube is connected to the second input end of the current mirror, and the current mirror is used to drive the capacitor of the capacitor charging and discharging unit to charge and discharge; The output end of the capacitor charging and discharging unit is connected to the second comparison end of the current comparator module, and the output end of the current comparator module is connected to the signal output end. The current comparator module is used to compare the signals received by the first comparison end and the second comparison end, and output a level signal corresponding to the comparison result to the signal output end.

2. The clock detection circuit according to claim 1, characterized in that: The level clock determination module comprises: a first inverter, a delay unit and an XNOR gate unit; The input end of the first inverter is connected to the signal input end, and the output end of the first inverter is respectively connected to the input end of the delay unit and the first input end of the XNOR gate unit; The output end of the delay unit is connected to the second input end of the XNOR gate unit, and the output end of the XNOR gate unit is connected to the conduction control end of the second switch tube.

3. The clock detection circuit according to claim 2, characterized in that: The delay unit comprises: a plurality of PMOS tubes connected in parallel, a plurality of groups of MOS tube circuits, a third inverter and a fourth inverter; The MOS tube circuit comprises a PMOS tube and an NMOS tube, the drain of the PMOS tube is connected to the drain of the NMOS tube, the gate of the PMOS tube is connected to the gate of the NMOS tube, and the source of the NMOS tube is grounded; The gates of the plurality of parallel PMOS tubes are connected to ground, and the drains of the plurality of parallel PMOS tubes are respectively connected to the source of a group of PMOS tubes of the MOS tube circuit; A plurality of groups of the MOS tube circuits are connected in series, and the input end of the first-stage MOS tube circuit connected in series is connected to the output end of the first inverter, and the output end of the last-stage MOS tube circuit connected in series is connected to the input end of the third inverter; The output end of the third inverter is connected to the input end of the fourth inverter, and the output end of the fourth inverter is connected to the second input end of the XNOR gate unit.

4. The clock detection circuit according to claim 1, characterized in that: The first switch tube includes a third PMOS tube and a fourth PMOS tube, and the second switch tube includes: a second NMOS tube and a fifth PMOS tube; The source of the third PMOS tube and the source of the fourth PMOS tube are both connected to the power supply end, and the gate of the third PMOS tube is connected to the gate of the fourth PMOS tube and one end of the bias current module; The drain of the fourth PMOS tube is connected to the first input terminal of the current mirror, and the drain of the third PMOS tube is connected to the source of the fifth PMOS tube; The gate of the fifth PMOS tube is connected to the gate of the second NMOS tube and the output end of the level clock determination module; The drain of the fifth PMOS tube is connected to the drain of the second NMOS tube and the input end of the capacitor charging and discharging unit; The source of the second NMOS tube is connected to the second input terminal of the current mirror.

5. The clock detection circuit according to claim 4, characterized in that: The current mirror comprises: a third NMOS tube and a fourth NMOS tube; The drain of the fourth NMOS tube is connected to the drain of the fourth PMOS tube, the gate of the fourth NMOS tube and the gate of the third NMOS tube; The drain of the third NMOS tube is connected to the source of the second NMOS tube; The source of the third NMOS tube and the source of the fourth NMOS tube are both grounded.

6. The clock detection circuit according to claim 5, characterized in that: The capacitor charging and discharging unit includes: a first resistor, a first capacitor, a second capacitor, a sixth PMOS transistor and a seventh PMOS transistor; The source of the sixth PMOS tube and the source of the seventh PMOS tube are both connected to the power supply terminal, and the gate of the sixth PMOS tube and the gate of the seventh PMOS tube are both connected to the enable terminal; The first end of the first capacitor is connected to the drain of the fifth PMOS transistor, the first end of the first resistor and the drain of the sixth PMOS transistor, and the second end of the first capacitor is grounded; The second end of the first resistor is connected to the first end of the second capacitor, the drain of the seventh PMOS tube and the second comparison end of the current comparator module, and the second end of the second capacitor is grounded.

7. The clock detection circuit according to claim 6, characterized in that: The bias current module includes: a second PMOS tube and a fifth NMOS tube; The source of the second PMOS tube is connected to the power supply end; The gate of the second PMOS tube is connected to the drain of the second PMOS tube, the gate of the third PMOS tube, the drain of the fifth NMOS tube and the first comparison terminal of the current comparator module; The gate of the fifth NMOS tube is connected to the enable terminal, and the source of the fifth NMOS tube is grounded.

8. The clock detection circuit according to claim 7, characterized in that: Also includes: Level Controller The level controller is connected to the enable end, and is used to control the level signal of the enable end to drive the fifth NMOS tube, the sixth PMOS tube, and the seventh PMOS tube to be turned on or off.

9. The clock detection circuit according to claim 7, characterized in that: The current comparator module includes: a first PMOS tube, a first NMOS tube, a Schmitt trigger and a second inverter; The source of the first PMOS tube is connected to the power supply end, and the gate of the first PMOS tube is connected to the gate of the second PMOS tube; The drain of the first PMOS tube is connected to the drain of the first NMOS tube and the input end of the Schmitt trigger; The gate of the first NMOS transistor is connected to the first end of the second capacitor, and the source of the first NMOS transistor is grounded; The output end of the Schmitt trigger is connected to the input end of the second inverter, and the output end of the second inverter is connected to the signal output end.

10. A circuit system, characterized in that: include: A bias current module, a level clock determination module, a capacitor charge and discharge module, and a current comparator module as claimed in any one of claims 1 to 9.

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