Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes: a first bit line crossing a memory cell array region in a first direction and extending into an extension region adjacent to the memory cell array region; a second bit line crossing the memory cell array region in the first direction, and extending into the extension region, and adjacent to the first bit line; an insulating pattern within the extension region and contacting an end portion of the second bit line in the first direction; and an insulating spacer within the extension region and contacting an end portion of the first bit line in the first direction, the insulating spacer being different from the insulating pattern.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0087134 filed on July 5, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments relate to a semiconductor device and / or a method for manufacturing a semiconductor device. Background Art

[0004] Research is being conducted to reduce the size of elements constituting semiconductor devices and to improve performance. For example, in DRAM, research is being conducted to reliably and stably form elements with reduced size. Summary of the invention

[0005] Some example embodiments provide a semiconductor device for improving integration.

[0006] Some example embodiments provide a semiconductor device for improving reliability.

[0007] Some example embodiments provide methods for manufacturing semiconductor devices to increase integration and improve reliability.

[0008] According to an example embodiment, a semiconductor device includes: a first bit line, which intersects a memory cell array region in a first direction, and the first bit line extends into an extension region adjacent to the memory cell array region; a second bit line, which intersects the memory cell array region in the first direction, and the second bit line extends into the extension region and is adjacent to the first bit line; an insulating pattern, which is within the extension region and contacts an end of the second bit line in the first direction; and an insulating spacer, which is within the extension region and contacts an end of the first bit line in the first direction, and the insulating spacer is different from the insulating pattern.

[0009] According to an example embodiment, a semiconductor device includes: a substrate including a memory cell array region and an extension region; line structures intersecting the memory cell array region and extending into the extension region, the line structures being parallel to each other; and insulating patterns in the extension region and spaced apart from each other. Each line structure has a linear shape extending in a first direction, the line structure includes a first line structure and a second line structure on both sides of the first line structure, the insulating pattern contacts an end of the second line structure in the first direction in the extension region, and an end of the first line structure in the first direction is between the insulating patterns in the extension region.

[0010] According to an example embodiment, a semiconductor device includes: a substrate including a memory cell array region, a first extension region, and a second extension region; a bit line structure intersecting the memory cell array region and extending into the first extension region and the second extension region, the bit line structures being parallel to each other on the substrate; a first insulating pattern, the first insulating patterns being spaced apart from each other on the substrate in the first extension region; and a second insulating pattern, the second insulating patterns being spaced apart from each other on the substrate in the second extension region, wherein the memory cell array region is between the first extension region and the second extension region, each bit line structure has a linear shape extending in a first direction, the bit line structure includes a first bit line structure and a second bit line structure alternating in a second direction perpendicular to the first direction, in the first extension region, the first insulating pattern contacts an end of the second bit line structure in the first direction, in the second extension region, the second insulating pattern contacts an end of the first bit line structure in the first direction, in the first extension region, the end of the first bit line structure in the first direction is between the first insulating patterns, and in the second extension region, the end of the second bit line structure in the first direction is between the second insulating patterns. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description in conjunction with the accompanying drawings:

[0012] Figures 1 to 3E is a diagram illustrating a semiconductor device according to an example embodiment;

[0013] Figure 4 is a plan view showing a modified example of the semiconductor device according to the example embodiment;

[0014] Figure 5A and Figure 5B is a diagram showing a modified example of the semiconductor device according to the example embodiment;

[0015] Figure 6 and Figure 7 is a diagram showing a modified example of the semiconductor device according to the example embodiment;

[0016] Figure 8 and Fig. 9 is a diagram showing a modified example of the semiconductor device according to the example embodiment;

[0017] Fig. 10A and Fig. 10B is a diagram showing a modified example of the semiconductor device according to the example embodiment;

[0018] Fig.11 is a cross-sectional view illustrating a modified example of the semiconductor device according to the example embodiment; and

[0019] Figures 12 to 18C is a diagram illustrating an example of a method for manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0020] Hereinafter, terms such as "upper", "middle" and "lower" may be replaced by other terms such as "first", "second" and "third", and thus these terms may be used to describe the elements of the specification. Terms such as "first", "second" and "third" may be used to describe various elements, but these elements are not limited by the above terms, and the "first element" may be referred to as the "second element".

[0021] As used herein, expressions such as "at least one of..." follow a list of elements and modify the entire list of elements rather than modifying the individual elements in the list. Thus, for example, "at least one of A, B, or C" and "at least one of A, B, and C" both mean A, B, C, or any combination thereof. Similarly, A and / or B means A, B, or A and B.

[0022] Although the terms "same", "equal" or "identical" are used in the description of the exemplary embodiments, it should be understood that some imprecision may exist. Therefore, when an element is referred to as being the same as another element, it should be understood that the element or value is the same as the other element within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0023] When the term "about" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "about" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the tolerance for the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified to "about" or "substantially", it will be understood that these values ​​and shapes should be interpreted as including a manufacturing or operating tolerance (e.g., ±10%) around the numerical value or shape.

[0024] Will refer to Figures 1 to 3E Examples of semiconductor devices according to example embodiments of the inventive concepts are described. Figures 1 to 3E is a diagram illustrating a semiconductor device according to an example embodiment of the inventive concept, Figure 1 is a plan view showing a semiconductor device according to an example embodiment of the inventive concept, Figure 2 yes Figure 1 A partial enlarged view of area "A" in FIG. Figure 3A is along Figure 2 A cross-sectional view taken along line II' of Figure 3B is along Figure 2A cross-sectional view taken along line II-II', Figure 3C is along Figure 2 The cross-sectional view taken along the center line III-III', Figure 3D is along Figure 2 A cross-sectional view taken along the midline IV-IV', and Figure 3E is along Figure 2 A cross-sectional view taken along line V-V'.

[0025] refer to Figures 1 to 3E , the semiconductor device 1 according to the example embodiment may include a memory cell array area MCA, a first extension area EXTa, and a second extension area EXTb. The first extension area EXTa and the second extension area EXTb may be adjacent to the memory cell array area MCA. The memory cell array area MCA may be an area in which memory cells for storing data are arranged. The memory cell array area MCA may be disposed between the first extension area EXTa and the second extension area EXTb.

[0026] The semiconductor device 1 may further include line structures BLS that are parallel to each other.

[0027] The line structure BLS may intersect the memory cell array area MCA in the first direction X and extend into the first extension area EXTa. The line structure BLS may also include a portion extending from the memory cell array area MCA to the second extension area EXTb. Accordingly, the line structure BLS may intersect the memory cell array area MCA and may extend into the first extension area EXTa and the second extension area EXTb.

[0028] Each of the line structures BLS may have a linear shape extending in the first direction X. The line structures BLS may be spaced apart from each other in a second direction Y perpendicular to the first direction X.

[0029] The line structures BLS may include first line structures BLSa and second line structures BLSb alternately disposed in the second direction.

[0030] Each line structure BLS may include a conductive line BL and a capping pattern 23 on the conductive line BL. Accordingly, each first line structure BLSa may include a conductive line BL and a capping pattern 23 stacked sequentially, and each second line structure BLSb may include a conductive line BL and a capping pattern 23 stacked sequentially.

[0031] In some example embodiments, the conductive lines BL of the first wire structure BLSa may be first conductive lines BLa, and the conductive lines BL of the second wire structure BLSb may be second conductive lines BLb.

[0032] In some example embodiments, the conductive wire BL may be a “bit line.” Hereinafter, the conductive wire BL will be referred to as a “bit line” and will be described, the line structure BLS will be referred to as a “bit line structure” and will be described, the first conductive wire BLa will be referred to as a “first bit line” and will be described, and the second conductive wire BLb will be referred to as a “second bit line” and will be described.

[0033] Each bit line BL may include at least one conductive material layer. For example, each conductive line BL may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, graphene, carbon nanotubes, or a combination thereof, but example embodiments thereof are not limited thereto. Each bit line BL may include a single layer or multiple layers of the above materials. For example, each bit line BL may include a first conductive material layer 17a, a second conductive material layer 19a on the first conductive material layer 17a, and a third conductive material layer 21a on the second conductive material layer 19a. The first to third conductive material layers 17a, 19a, and 21a may include different materials.

[0034] The capping pattern 23 may include a first insulating material layer 24a, a second insulating material layer 33a on the first insulating material layer 24a, and a third insulating material layer 39a on the second insulating material layer 33a. In each capping pattern 23, the thickness of the second insulating material layer 33a may be less than the thickness of each of the first insulating material layer 24a and the third insulating material layer 39a.

[0035] Each capping pattern 23 may include an insulating material such as silicon nitride. The capping pattern 23 may also be referred to as an "insulating capping pattern" or a "bit line capping pattern".

[0036] The semiconductor device 1 may further include an insulating pattern 42 contacting the bit line structure BLS.

[0037] The insulating pattern 42 may include a first insulating pattern 42 a disposed in the first extension region EXTa, and a second insulating pattern 42 b disposed in the second extension region EXTb.

[0038] In the first extension region EXTa, the first insulating pattern 42a may contact an end portion of the second bit line structure BLSb in the first direction X and located in the first extension region EXTa. In the first extension region EXTa, the first insulating pattern 42a may contact an end portion of the second bit line BLb in the first direction X and located in the first extension region EXTa. In the first extension region EXTa, the first insulating pattern 42a may contact an end portion of the second bit line BLb in the first direction X and located in the first extension region EXTa and the capping pattern 23.

[0039] In the second extension region EXTb, the second insulating pattern 42b may contact an end portion of the first bit line structure BLSa in the first direction X in the second extension region EXTb. In the second extension region EXTb, the second insulating pattern 42b may contact an end portion of the first bit line BLa in the first direction X in the second extension region EXTb. In the second extension region EXTb, the second insulating pattern 42b may contact an end portion of the first bit line BLa in the first direction (X) in the second extension region EXTb and the capping pattern 23.

[0040] In the first extension region EXTa, an end portion of the first bit line BLa may be disposed between the first insulating patterns 42a. In the second extension region EXTb, an end portion of the second bit line BLb may be disposed between the second insulating patterns 42b.

[0041] The second bit line BLb and the first insulating pattern 42a may be sequentially arranged in the first direction (X). The first bit line BLa and the second insulating pattern 42b may be sequentially arranged in the first direction (X).

[0042] The insulating patterns 42 may include the same material as at least one material of the capping pattern 23. Each of the insulating patterns 42 may include an insulating material such as silicon nitride.

[0043] Each insulating pattern 42 may include a first portion 42_1 extending in a first direction (X), and a second portion 42_2 extending from the first portion 42_1 and having a width greater than that of the first portion 42_1. The first portion 42_1 of the insulating pattern 42 may contact the bit line BL and may be disposed between the second portion 42_2 of the insulating pattern 42 and the bit line BL. For example, within the first extension region EXTa, the first portion 42_1 of the first insulating pattern 42a may contact the second bit line BLb and may be disposed between the second portion 42_2 of the first insulating pattern 42a and the second bit line BLb.

[0044] In the first and second extension regions EXTa and EXTb, a width of each second portion 42_2 of the insulating pattern 42 may be greater than a width of each bit line BL.

[0045] The insulating pattern 42 can reduce or prevent defects of the bit line structure BLS from occurring in the first extension region EXTa and the second extension region EXTb. For example, in the first extension region EXTa and the second extension region EXTb, the insulating pattern 42 can be used to reduce or prevent deformation of the bit line structure BLS. Therefore, even if the size of the bit line structure BLS is reduced for high integration of the semiconductor device 1, the deformation of the bit line structure BLS can be reduced or prevented by the insulating pattern 42.

[0046] The semiconductor device 1 may further include insulating spacers 30 contacting the bit line structure BLS in the first extension region EXTa and the second extension region EXTb.

[0047] The insulating spacers 30 may be spaced apart from the insulating patterns 42. Each insulating spacer 30 may include at least one insulating material layer. The insulating spacers 30 may include a material different from that of the insulating patterns 42. For example, the insulating patterns 42 may include silicon nitride, and the insulating spacers 30 may include at least one of silicon oxide or a low-k dielectric. The low-k dielectric may be a dielectric having a dielectric constant lower than that of silicon oxide.

[0048] The insulating spacer 30 may include a first insulating spacer 30 a disposed in the first extension region EXTa and a second insulating spacer 30 b disposed in the second extension region EXTb.

[0049] The first insulating spacer 30a may contact an end of the first bit line BLa in the first extension region EXTa. The first insulating spacer 30a may contact an end of the first bit line BLa in the first extension region EXTa and the capping pattern 23 in the first extension region EXTa.

[0050] In the second extension region EXTb, the second insulating spacer 30b may contact the end of the second bit line structure BLSb located in the second extension region EXTb. In the second extension region EXTb, the second insulating spacer 30b may contact the end of the second bit line BLb located in the second extension region EXTb. In the second extension region EXTb, the second insulating spacer 30b may contact the end of the second bit line BLb located in the second extension region EXTb and the capping pattern 23.

[0051] In the first extension region EXTa, an end of the first bit line structure BLSa and the first insulating spacer 30a may be disposed between the first insulating pattern 42a. In the second extension region EXTb, an end of the second bit line structure BLb and the second insulating spacer 30b may be disposed between the second insulating pattern 42b.

[0052] Among the bit lines BL, the insulating pattern 42, and the insulating spacer 30 connected to each other, one bit line BL may be disposed between one insulating pattern 42 and one insulating spacer 30. For example, one first bit line BLa may be connected to one first insulating spacer 30a in the first extension region EXTa, and may be connected to one second insulating pattern 42b in the second extension region EXTb. One second bit line BLb may be connected to one first insulating pattern 42a in the first extension region EXTa, and may be connected to one second insulating spacer 30b in the second extension region EXTb. Accordingly, one first bit line BLa may be disposed between one first insulating spacer 30a and one second insulating pattern 42b, and one second bit line BLb may be disposed between one first insulating pattern 42a and one second insulating spacer 30b.

[0053] In the second direction Y, the insulating spacer 30 may have substantially the same width as the bit line BL.

[0054] The length of the insulating pattern 42 in the first direction X may be greater than the length of the insulating spacer 30 in the first direction X.

[0055] Insulating spacers 30 may be used to mitigate or prevent deformation of the bit line structure BLS within the first extension region EXTa and the second extension region EXTb.

[0056] The semiconductor device 1 may also include a substrate SUB, a cell active region cACT arranged on the substrate SUB within the memory cell array area MCA, a cell device isolation region cSTI arranged on a side surface of the cell active region cACT within the memory cell array area MCA, a peripheral device isolation region pSTI arranged on the substrate within the extension region EXTa, a peripheral active region pACT spaced apart from the memory cell array area MCA, and a gate trench GT intersecting the cell active region cACT and the cell device isolation region cSTI.

[0057] The substrate SUB may be a semiconductor substrate. The substrate SUB may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc. The substrate SUB may include a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the substrate SUB may be a substrate including at least one of silicon, silicon carbide, germanium, or silicon-germanium. For example, the substrate SUB may be a single crystal silicon substrate including a silicon material (e.g., a single crystal silicon material).

[0058] Each of the cell active region cACT and the peripheral active region pACT may protrude from the substrate SUB in the vertical direction Z. The cell active region cACT and the peripheral active region pACT may be formed of the same semiconductor material (e.g., single crystal silicon) as the substrate SUB. In a plan view, each cell active region cACT may have a bar shape extending in a direction inclined relative to the first direction X.

[0059] The cell device isolation region cSTI may be a shallow device isolation trench isolation (STI) defining the cell active region cACT. The cell device isolation region cSTI may be formed of an insulating material including at least one of silicon oxide or silicon nitride.

[0060] The peripheral device isolation region pSTI may include an insulating layer 9, a first insulating pad 3 covering the side surface and the bottom surface of the insulating layer 9, and a second insulating pad 6 between the insulating layer 9 and the first insulating pad 3. The second insulating pad 6 may include a material different from that of the insulating layer 9 and the first insulating pad 3. For example, the second insulating pad 6 may include a nitride, and the insulating layer 9 and the first insulating pad 3 may include an oxide.

[0061] An end portion of the bit line structure BLS may be disposed on the peripheral device isolation region pSTI. An end portion of the bit line BL may be disposed on the peripheral device isolation region pSTI. The bit line BL may not vertically overlap with the peripheral active region pACT.

[0062] The insulating pattern 42 and the insulating spacer 30 may be disposed on the peripheral device isolation region pSTI.

[0063] In the first and second extension regions EXTa and EXTb, lower surfaces of the insulating patterns 42 may be disposed at a lower level than lower surfaces of the bit lines BL.

[0064] In the first and second extension regions EXTa and EXTb, upper surfaces of the insulating patterns 42 may be disposed at a higher level than upper surfaces of the bit lines BL.

[0065] A lower surface of the insulating pattern 42 may be disposed at a lower level than an upper surface of the cell active region cACT.

[0066] Within the first and second extension regions EXTa and EXTb, each insulating pattern 42 may include a lower region 42L disposed at a lower level than the bit line BL, a middle region 42M disposed at the same level as the bit line BL, and an upper region 42U disposed at a higher level than the bit line BL.

[0067] The lower region 42L of the insulating pattern 42 may contact the insulating layer 9 of the peripheral device isolation region pSTI.

[0068] In the first and second extension regions EXTa and EXTb, each lower region 42L of the insulating pattern 42 may have a greater width than each bit line BL.

[0069] In the first and second extension regions EXTa and EXTb, a maximum width of each middle region 42L of the insulation pattern 42 may be greater than a width of each bit line BL.

[0070] In the first and second extension regions EXTa and EXTb, each middle region 42L of the insulation pattern 42 may have a side surface inclined such that the width increases from the top to the bottom.

[0071] The semiconductor device 1 may further include a gate line GS crossing the memory cell array area MCA in the second direction Y. The gate line GS may be disposed in the gate trench GT.

[0072] In example embodiments, the bit line BL may be disposed at a level different from that of the gate line GS. For example, the gate line GS may be disposed at a lower level than the bit line BL.

[0073] The gate line GS may include a dummy gate line GSd adjacent to the first extension region EXTa and the second extension region EXTb.

[0074] The distance between the ends of the dummy gate line GSd and the first bit line BLa adjacent to the first extension region EXTa may be greater than the distance between the ends of the dummy gate line GSd and the second bit line BLb adjacent to the first extension region EXTa and the first extension region EXTa. Similarly, the distance between the ends of the dummy gate line GSd and the second bit line BLb adjacent to the second extension region EXTb and the second extension region EXTb may be greater than the distance between the ends of the dummy gate line GSd and the first bit line BLa adjacent to the second extension region EXTb and the second extension region EXTb.

[0075] In example embodiments, an “end portion” may refer to a “side surface”. For example, an end portion of the first bit line BLa within the first extension region EXTa may refer to a side surface of the end portion of the first bit line BLa. Therefore, hereinafter, even if the “end portion” is not separately defined or explained, it may be understood as a “side surface” or a “side surface of the end portion”.

[0076] In the first extension region EXTa, the first bit line BLa may extend farther from the memory cell array region MCA than the second bit line BLb, and in the second extension region EXTb, the second bit line BLb may extend farther from the memory cell array region MCA than the first bit line BLa.

[0077] The length of the first bit line BLa extending from the memory cell array area MCA to the first extension area EXTa may be greater than the length of the second bit line BLb extending from the memory cell array area MCA to the first extension area EXTa. The length of the second bit line BLb extending from the memory cell array area MCA to the second extension area EXTb may be greater than the length of the first bit line BLa extending from the memory cell array area MCA to the second extension area EXTb.

[0078] At least a portion of each of the first insulation patterns 42 a may face the bit line contact structure 78 in the second direction Y within the first extension region EXTa.

[0079] In the first extension region EXTa, the distance between the end of the first insulating pattern 42a in contact with the end of the second bit line BLb and the memory cell array region MCA may be greater than the distance between the bit line contact structure 78 and the memory cell array region MCA. In the first extension region EXTa, the distance between the end of the first insulating pattern 42a in contact with the end of the second bit line BLb and the dummy gate line GSd may be greater than the distance between the bit line contact structure 78 and the dummy gate line GSd.

[0080] The semiconductor device 1 may further include a gate capping layer GC on the gate line GS. The gate line GS and the gate capping layer GC may be disposed in the gate trench GT.

[0081] Each gate line GS may include a gate dielectric layer Gox and a gate electrode GE. In each gate line GS, the gate dielectric layer Gox may be disposed on the inner wall of the gate trench GT, and the gate electrode GE may partially fill the gate trench GT on the gate dielectric layer Gox. The gate capping layer GC may fill the remaining portion of the gate trench GT on the gate electrode GE. The gate electrode GE and the gate capping layer GC may be stacked sequentially. The upper surface of the gate electrode GE may be disposed at a level lower than the upper surface of the cell active area cACT.

[0082] The gate dielectric layer Gox may be disposed between a bottom surface of the gate electrode GE and a bottom surface of the gate trench GT, between a side surface of the gate electrode GE and a sidewall of the gate trench GT, and between a side surface of the gate capping layer GC and a sidewall of the gate trench GT.

[0083] The semiconductor device 1 may further include first and second source / drain regions SD1 and SD2 in an upper region of the cell active region cACT.

[0084] In example embodiments, the gate electrode GE, the gate dielectric layer Gox, and the first and second source / drain regions SD1 and SD2 may constitute the cell transistor TR.

[0085] The semiconductor device 1 may further include a cell active region cACT, a cell device isolation region cSTI, a peripheral device isolation region pSTI, and a buffer insulating layer 12 on the peripheral active region pACT.

[0086] The buffer insulating layer 12 may include at least one insulating material. For example, the buffer insulating layer 12 may include at least one of silicon oxide or silicon nitride.

[0087] The bit line structure BLS may be disposed on the buffer insulating layer 12. A lower surface of the bit line BL may contact the buffer insulating layer 12.

[0088] The semiconductor device 1 may further include a bit line contact plug BLp penetrating the buffer insulating layer 12 and connecting the first source / drain region SD1 and the bit line BL. The bit line contact plug BLp may include the same material as the first conductive material layer 17a of the bit line BL.

[0089] The semiconductor device 1 may further include a bit line spacer SP_U on a side surface of the bit line structure BLS, and a contact spacer SP_L on a side surface of the bit line contact plug BLp.

[0090] Each bit line spacer SP_U may include an inner spacer 55, an outer spacer 59, and an intermediate spacer 57 between the inner spacer 55 and the outer spacer 59. The inner spacer 55 may contact the side surface of the bit line structure BLS. The inner spacer 55 and the outer spacer 59 may include at least one of SiN and SiCN. The intermediate spacer 57 may be an air spacer, but example embodiments thereof are not limited thereto. For example, the intermediate spacer 57 may include at least one of silicon oxide or a low dielectric material.

[0091] Each of the contact spacers SP_L may include a first spacer 53, and a second spacer 51 covering side and bottom surfaces of the first spacer 53. The second spacer 51 may extend from the inner spacer 55. The first spacer 53 may include at least one of SiN or SiC.

[0092] The semiconductor device 1 may further include a contact plug 75 disposed between the bit line structures BLS.

[0093] The contact plug 75 may include a conductive material. The contact plug 75 may include a cell contact plug 75c disposed in the memory cell array area MCA, and a peripheral contact plug 75d disposed in the first extension area EXTa and the second extension area EXTb. The cell contact plug 75c may be electrically connected to the second source / drain area SD2, and the peripheral contact plug 75d may be disposed on the peripheral device isolation area pSTI.

[0094] Within the first extension region EXTa and the second extension region EXTb, the peripheral contact plug 75d may serve to mitigate or prevent deformation of the bit line structure BLS.

[0095] At least one of the peripheral contact plugs 75d disposed in the first extension region EXTa and the second extension region EXTb may be an electrically isolated dummy contact plug. The peripheral contact plug 75d may contact the peripheral device isolation region pSTI.

[0096] Each contact plug 75 may include a lower conductive layer 63 , an upper conductive layer 73 on the lower conductive layer 63 , and an intermediate conductive layer 66 between the lower conductive layer 63 and the upper conductive layer 73 .

[0097] The lower conductive layer 63 may include doped polysilicon (e.g., polysilicon having N-type conductivity). The intermediate conductive layer 66 may include a metal-semiconductor compound layer. The upper conductive layer 73 may include a conductive layer 72b, and a barrier layer 72a covering the side surface and bottom surface of the conductive layer 72b. The barrier layer 72a may include at least one of TiN, TaN, WN, TiSiN, TaSiN, or RuTiN, and the conductive layer 72b may include a metal material such as W.

[0098] The semiconductor device 1 may further include an upper spacer 69 disposed between the bit line spacer SP_U and the upper conductive layer 73 and between an upper region of the bit line structure BLS and the upper conductive layer 73. The upper spacer 69 may include an insulating material such as silicon oxide or silicon nitride.

[0099] The semiconductor device 1 may further include a bit line contact structure 78. The bit line contact structure 78 may penetrate the capping pattern 23 in the first extension region EXTa and the second extension region EXTb and be electrically connected to the bit line BL. For example, among the bit line contact structures 78, the bit line contact structure 78 disposed in the first extension region EXTa may penetrate the capping pattern 23 and be electrically connected to the first bit line BLa, and among the bit line contact structures 78, the bit line contact structure 78 disposed in the second extension region EXTb may penetrate the capping pattern 23 and be electrically connected to the second bit line BLb.

[0100] Each bit line contact structure 78 may include a first conductive layer 77b and a second conductive layer 77a covering the side surface and the bottom surface of the first conductive layer 77b. The second conductive layer 77a may include at least one of TiN, TaN, WN, TiSiN, TaSiN or RuTiN, and the first conductive layer 72b may include a metal material such as W.

[0101] The semiconductor device 1 may further include an interlayer insulating layer 36 disposed in the first and second extension regions EXTa and EXTb and not covered by the bit line structure BLS, the insulating pattern 42, and the insulating spacer 30. The interlayer insulating layer 36 may include at least one of silicon oxide or a low dielectric material.

[0102] An interlayer insulating layer 36 may be disposed on the peripheral device isolation region pSTI and the peripheral active region pACT. An upper surface of the interlayer insulating layer 36 may be coplanar with an upper surface of the second insulating material layer 33 a of the capping pattern 23 .

[0103] The insulating spacer 30 may cover the end of the bit line BL, and cover the side surface of the second insulating material layer 33 a of the capping pattern 23 .

[0104] Insulating spacers 30 may be disposed between the interlayer insulating layer 36 and the bit line BL, and between the interlayer insulating layer 36 and the first insulating material layer 24 a .

[0105] The upper end of the insulating spacer 30 may be disposed at a level higher than the upper surface of the bit line BL, and the lower end of the insulating spacer 30 may be disposed at a level lower than the lower surface of the bit line BL. The lower end of the insulating spacer 30 may be disposed at a level lower than the upper surfaces of the cell active region cACT and the peripheral active region pACT, and may contact the peripheral device isolation region pSTI.

[0106] The insulating pattern 42 may be disposed between the bit line structure BLS and the interlayer insulating layer 36 .

[0107] The semiconductor device 1 may further include an insulating liner 33 e extending from the second insulating material layer 33 a of the capping pattern 23 disposed between the insulating spacer 30 and the interlayer insulating layer 36 and covering a lower surface of the interlayer insulating layer 36 .

[0108] The semiconductor device 1 may further include an upper insulating layer 39 e disposed on the interlayer insulating layer 36 and disposed at the same level as the third insulating material layer 39 a of the capping pattern 23 .

[0109] The semiconductor device 1 may further include conductive patterns 80c and 80b. Each of the conductive patterns 80c and 80b may include at least one conductive material. Each of the conductive patterns 80c and 80b may include at least one of Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, or NiSi.

[0110] The conductive patterns 80 c and 80 b may include a first conductive pattern 80 c in the memory cell array area MCA, and a second conductive pattern 80 b in the first and second extension regions EXTa and EXTb.

[0111] The first conductive pattern 80c may be electrically connected to the cell contact plug 75c on the cell contact plug 75c. The first conductive pattern 80c may be electrically connected to the second source / drain region SD2 of the cell transistor TR through the cell contact plug 75c.

[0112] The second conductive pattern 80b may be electrically connected to the bit line contact structure 78 in the first extension region EXTa and the second extension region EXTb. For example, among the second conductive patterns 80b, the second conductive pattern 80b disposed in the first extension region EXTa may be electrically connected to the first bit line BLa through the bit line contact structure 78, and among the second conductive patterns, the second conductive pattern 80b disposed in the second extension region EXTb may be electrically connected to the second bit line BLb through the bit line contact structure 78.

[0113] The second conductive pattern 80 b may be an interconnection line for connecting the bit line BL to a peripheral circuit such as a sense amplifier.

[0114] The first conductive pattern 80 c may be referred to as a “conductive pad”, and the second conductive pattern 80 b may be referred to as a “bit line interconnection line” or an “interconnection line”.

[0115] The semiconductor device 1 may further include an insulating isolation pattern 83 , an etch stop layer 87 , and a data storage structure DS.

[0116] The insulating isolation pattern 83 may be disposed on side surfaces of the conductive patterns 80c and 80b and may extend downward. The insulating isolation pattern 83 may be disposed at a higher level than the bit line BL.

[0117] The etch stop layer 87 may be disposed on the insulating isolation pattern 83 and the conductive patterns 80 c and 80 b , and may be formed of an insulating material.

[0118] The data storage structure DS may be disposed within the memory cell array area MCA.

[0119] In one example, the data storage structure DS may be a capacitor for storing data in a DRAM. For example, the data storage structure DS may be a DRAM capacitor including a first electrode 90 penetrating the etch stop layer 87 and electrically connected to the first conductive pattern 80c, a dielectric layer 92 covering the first electrode 90 and the etch stop layer 87, and a second electrode 94 on the dielectric layer 92. The dielectric layer 92 may include a high dielectric, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The high dielectric may be a dielectric having a dielectric constant higher than that of silicon oxide.

[0120] In another example, the data storage structure DS may be a structure for storing DRAM and other memory data. For example, in the data storage structure DS, the dielectric layer 92 may include a ferroelectric layer for recording data using a polarization state.

[0121] According to the above-described embodiment, even if the size of the bit line structure BLS is reduced, at least one of the insulating pattern 42, the insulating spacer 30, and the peripheral contact plug 75d can alleviate or prevent defects such as deformation of the bit line structure BLS. Accordingly, the integration of the semiconductor device 1 can be increased, and the reliability of the semiconductor device 1 can be improved.

[0122] Hereinafter, various modified examples of the above-described exemplary embodiments for increasing the integration degree of the semiconductor device 1 and improving the reliability will be described. Various modified examples of the elements of the above-described exemplary embodiments described below will be described focusing on the modified elements, the replaced elements, or the added elements. In addition, the elements described below that can be modified or replaced are described with reference to the following drawings, but the elements that can be modified or replaced can be combined with each other or with the above-described elements to form semiconductor devices according to some exemplary embodiments of the present invention.

[0123] Will refer to Figure 4 Modified examples of the semiconductor device according to example embodiments of the inventive concepts are described. Figure 4 It is used to show Figure 2 A plan view of a modified example of .

[0124] In the modified example, refer to Figure 4 In the first extension region EXTa, the first bit line BLa may extend to contact the second portion 42_2 of the first insulating pattern 42a. Similarly, in the second extension region EXTb, the second bit line BLb may extend to contact the second portion 42_2 of the second insulating pattern 42b.

[0125] In the first extension region EXTa, the end of the first bit line BLa may have an increased width. For example, in the first extension region EXTa, each first bit line BLa may have a first width between the first portions 42_1 of the first insulating pattern 42a, and may have a second width greater than the first width between the second portions 42_2 of the first insulating pattern 42a.

[0126] The above-mentioned insulating spacer 30 may be modified to be an insulating spacer 30' contacting the insulating pattern 42. For example, the first insulating spacer ( Figure 2 The first insulating spacer 30a) in FIG. 30a may be modified to contact the second portion 42_2 of the first insulating pattern 42a.

[0127] Will refer to Figure 5A and Figure 5B Modified examples of the semiconductor device according to example embodiments of the inventive concepts are described. Figure 5A It is used to explain Figure 2 A plan view of a modified example of Figure 5B is along Figure 5A The cross-sectional view taken along the line V-V' of Figure 3E 's modified example.

[0128] In the modified example, refer to Figure 5A and Figure 5B , the above bit line contact structure ( Figure 2 and Figure 3E 78) can be used as Figure 5A and Figure 5B The bit line contact structure 178 shown in FIG.

[0129] Each bit line contact structure 178 may include a contact portion 178L contacting the bit line BL, and at least one extending portion 178E extending from the contact portion 178L. The at least one extending portion 178E may extend from the contact portion 178L in the second direction Y in a plan view.

[0130] In order to reduce the contact resistance between the bit line BL and the bit line contact structure 178 by increasing the contact area between the bit line BL and the bit line contact structure 178 , each contact portion 178L may have a bar shape extending in the first direction X.

[0131] The contact portion 178L may have substantially the same width as the bit line BL, but example embodiments are not limited thereto. For stable contact between the contact portion 178L and the bit line BL, the contact portion 178L may be modified to have a width greater than that of the bit line BL.

[0132] An upper surface of at least one extending portion 178E of the bit line contact structure 178 may contact the second conductive pattern 80 b .

[0133] Each of the bit line contact structures 178 may include a first conductive layer 177 a , and a second conductive layer 177 b covering side and bottom surfaces of the first conductive layer 177 a .

[0134] The above peripheral contact plug ( Figure 2 , Figure 3D and Figure 3E A portion of the peripheral contact plug 75d) in the bit line contact structure 178 may be modified into a first peripheral contact plug 75d' connected to at least one extension portion 178E of each bit line contact structure 178. Among the peripheral contact plugs 75, the peripheral contact plug 75 not connected to the bit line contact structure 178 may be referred to as a second peripheral contact plug 75d.

[0135] An upper surface of the first peripheral contact plug 75d' may be disposed at a lower level than an upper surface of the second peripheral contact plug 75d. Each first peripheral contact plug 75d' may include a lower conductive layer 63a' and an intermediate conductive layer 66a' respectively corresponding to the lower conductive layer 63a and the intermediate conductive layer 66a described above.

[0136] A lower surface of the contact portion 178L may be disposed at a lower level than an upper surface of the first peripheral contact plug 75d'.

[0137] In each bit line contact structure 178 , at least one extension portion 178E may extend from an upper region of the contact portion 178L to vertically overlap the bit line spacer SP_U and the first peripheral contact plug 75 d ′.

[0138] In each bit line contact structure 178 , the at least one extension portion 178E may be a plurality of extension portions 178E spaced apart from each other in the first direction X.

[0139] Since at least one extension portion 178E can increase the contact area between the bit line contact structure 178 and the second conductive pattern 80b, the contact resistance between the bit line contact structure 178 and the second conductive pattern 80b can be reduced. Accordingly, the performance of the semiconductor device can be improved.

[0140] Next, refer to Figure 6 and Figure 7Modified examples of the semiconductor device according to example embodiments of the inventive concepts are described. Figure 6 It is used to show Figure 2 A plan view of a modified example of Figure 7 is along Figure 6 The cross-sectional view taken along the line V-V' of Figure 3E 's modified example.

[0141] In the modified example, refer to Figure 6 and Figure 7 , the above bit line contact structure ( Figure 2 and Figure 3E 78) can be used as Figure 6 and Figure 7 The bit line contact structure 278 shown in FIG.

[0142] Each bit line contact structure 278 may include a contact portion 278L contacting the bit line BL, at least one first extending portion 278E1 extending from the contact portion 278L to the first side, and at least one second extending portion 278E2 extending from the contact portion 278L to the second side.

[0143] At least one first extension portion 278E1 and at least one second extension portion 278E2 may be disposed at both sides of the contact portion 278L.

[0144] Each of the bit line contact structures 278 may include a first conductive layer 277 a , and a second conductive layer 277 b covering side and bottom surfaces of the first conductive layer 277 a .

[0145] The above-mentioned peripheral contact plug ( Figure 2 , Figure 3D and Figure 3E A portion of 75d) in the bit line contact structure 278 is modified to form a first peripheral contact plug 75d′ connected to at least one first extension portion 278E1 and at least one second extension portion 278E2 of each bit line contact structure 278.

[0146] Among the peripheral contact plugs 75d, the peripheral contact plugs 75d that are not connected to the bit line contact structure 278 may be referred to as second peripheral contact plugs 75d. The upper surfaces of the first peripheral contact plugs 75d' may be disposed at a lower level than the upper surfaces of the second peripheral contact plugs 75d. Each first peripheral contact plug 75d' may include a lower conductive layer 63a' and an intermediate conductive layer 66a' corresponding to the lower conductive layer 63a and the intermediate conductive layer 66a, respectively, as described above.

[0147] In each bit line contact structure 278 , at least one first extension portion 278E1 and at least one second extension portion 278E2 may extend from an upper region of the contact portion 278L to vertically overlap the bit line spacer SP_U and the first peripheral contact plug 75 d ′.

[0148] In each bit line contact structure 278 , at least one first extension portion 278E1 may be a plurality of first extension portions 278E1 spaced apart from each other in the first direction X, and at least one second extension portion 278E2 may be a plurality of second extension portions 278E2 spaced apart from each other in the first direction X.

[0149] Since at least one first extension portion 278E1 and at least one second extension portion 278E2 can increase the contact area between the bit line contact structure 278 and the second conductive pattern 80b, the contact resistance between the bit line contact structure 278 and the second conductive pattern 80b can be reduced. Accordingly, the performance of the semiconductor device can be improved.

[0150] Next, refer to Figure 8 and Fig. 9 Modified examples of the semiconductor device according to example embodiments of the inventive concepts are described. Figure 8 It is used to show Figure 2 A plan view of a modified example of Fig. 9 is along Figure 8 The cross-sectional view taken along the line V-V' of Figure 3E 's modified example.

[0151] In the modified example, refer to Figure 8 and Fig. 9 , the above bit line contact structure ( Figure 2 and Figure 3E 78) can be used as Figure 8 and Fig. 9 The bit line contact structure 378 shown in FIG.

[0152] Each bit line contact structure 378 may include a contact portion 378L contacting the bit line BL, at least one first extension portion 378E1 extending from the contact portion 378L to the first side, and at least one second extension portion 378E2 extending from the contact portion 378L to the second side. The at least one first extension portion 378E1 and the at least one second extension portion 378E2 may be disposed on both sides of the contact portion 378L. Each bit line contact structure 378 may include a first conductive layer 377a, and a second conductive layer 377b covering the side surface and the bottom surface of the first conductive layer 377a.

[0153] The peripheral contact plugs described previously ( Figure 2 , Figure 3D and Figure 3E A portion of the bit line contact structure 378 (75d) may be modified into a first peripheral contact plug 375d connected to at least one first extension portion 378E1 and at least one second extension portion 378E2 of each bit line contact structure 378.

[0154] Among the peripheral contact plugs 375d, the peripheral contact plugs 375d not connected to the bit line contact structure 378 may be referred to as second peripheral contact plugs 75d. Each first peripheral contact plug 375d may include a lower conductive layer 363a and an intermediate conductive layer 366a corresponding to the above-described lower conductive layer 63a and intermediate conductive layer 66a, respectively.

[0155] Each contact portion 378L may have a linear shape extending in the first direction X. The contact portion 378L may have a greater width than the bit line BL. The contact portion 378L may contact the bit line BL and contact the first peripheral contact plug 375d. For example, when viewed based on one bit line BL and one contact portion 378L contacting each other, the contact portion 378L may contact the bit line BL and contact the first peripheral contact plug 375d disposed on both sides of the bit line BL. Accordingly, since the contact portion 378L may stably contact the bit line BL, the reliability of the semiconductor device may be improved.

[0156] In each bit line contact structure 378 , at least one first extension portion 378E1 and at least one second extension portion 378E2 may extend from an upper region of the contact portion 378L to vertically overlap the bit line spacer SP_U and the first peripheral contact plug 75 d ′.

[0157] In each bit line contact structure 378 , at least one first extension portion 378E1 may be a plurality of first extension portions 378E1 spaced apart from each other in the first direction X, and at least one second extension portion 378E2 may be a plurality of second extension portions 378E2 spaced apart from each other in the first direction X.

[0158] Since at least one first extension portion 378E1 and at least one second extension portion 378E2 can increase the contact area between the bit line contact structure 378 and the second conductive pattern 80b, the contact resistance between the bit line contact structure 378 and the second conductive pattern 80b can be reduced. Accordingly, the performance of the semiconductor device can be improved.

[0159] Reference above Figures 1 to 9 In the described example embodiment, in the first extension region EXTa, each bit line contact plug ( Figures 1 to 3E 78 of them Figure 5A and Figure 5B 178 of them Figure 6 and Figure 7 278 of them and Figure 8 and Fig. 9 At least a portion of the bit line contact plug ( 378 in ) may face the adjacent second bit line BLb in the second direction, but example embodiments are not limited thereto. For example, in the first extension region EXTa, the bit line contact plug ( Figures 1 to 3E 78 of them Figure 5A and Figure 5B 178 of them Figure 6 and Figure 7 278 of them, and Figure 8 and Fig. 9 378 in the first extension region EXTa) may not face the second bit line BLb in the second direction Y. For example, in the first extension region EXTa, the first insulating pattern ( Figures 1 to 9 42a) in the figure is modified so that the second bit line BLb does not face the bit line contact plug ( Figures 1 to 3E 78 of them Figure 5A and Figure 5B 178 of them Figure 6 and Figure 7 278 of them, and Figure 8 and Fig. 9 378 in ). Fig. 10A and Fig. 10B Describe the first insulating pattern ( Figures 1 to 9 A modified example of 42a) in FIG.

[0160] Next, refer to Fig. 10A and Fig. 10B Modified examples of the semiconductor device according to example embodiments of the inventive concepts are described. Fig. 10A is a diagram showing a first insulating pattern ( Figure 8 42a) in order to explain the first insulating pattern ( Figures 1 to 9 42a) in the modification example, and Fig. 10B is along Fig. 10A The cross-sectional view taken along the line V-V' is shown Fig. 9 Modified example in .

[0161] In the modified example, refer to Fig. 10A and Fig. 10B , a first insulating pattern ( Figures 1 to 9 42a) in can be modified as follows Fig. 10A and Fig. 10B The first insulating pattern 142a is shown in FIG.

[0162] In the first extension region EXTa, the first insulating pattern 142a may be connected to an end of the second bit line BLb, and the first insulating pattern 142a may face the bit line contact plug ( Figures 1 to 3E 78 of them Figure 5A and Figure 5B 178 of them Figure 6 and Figure 7 278 of them, and Figure 8 and Fig. 9 378 in ).

[0163] In the first extension region EXTa, a distance between an end of the first insulating pattern 142a contacting an end of the second bit line BLb and the memory cell array region MCA may be smaller than a distance between the bit line contact plug ( Figures 1 to 3E 78 of them Figure 5A and Figure 5B 178 of them Figure 6 and Figure 7 278 of them, and Figure 8 and Fig. 9 378) and the distance between the memory cell array area MCA.

[0164] In the first extension region EXTa, a distance between an end of the first insulating pattern 142a contacting an end of the second bit line BLb and the memory cell array region MCA may be smaller than a distance between the bit line contact plug ( Figures 1 to 3E 78 of them Figure 5A and Figure 5B 178 of them Figure 6 and Figure 7 278 of them, and Figure 8 and Fig. 9 378) and the distance between the dummy gate line GSd.

[0165] The second insulating pattern ( 142 a ) in the second extension region EXTb may be modified like the first insulating pattern 142 a . Figure 1 42b).

[0166] Each of the first insulating patterns 142a may include Figure 3D The lower region 42L, Figure 3D The middle area 42M and Figure 3D The upper region 42U in the figure corresponds to the lower region 142L, the middle region 142M and the upper region 142U.

[0167] Since the first insulating pattern 142a can reduce the area in which the first bit line BLa and the second bit line BLb face each other, the parasitic capacitance between the first bit line BLa and the second bit line BLb can be reduced. Accordingly, the performance of the semiconductor device can be improved.

[0168] The bit line contact plug ( Figures 1 to 3E 78 of them Figure 5A and Figure 5B 178 of them Figure 6 and Figure 7 278 of them, and Figure 8 and Fig. 9 378 in the embodiment may form an interface and contact the second conductive pattern ( Figures 1 to 10B 80b in FIG. 80b), but example embodiments are not limited thereto. For example, the bit line contact plug ( Figures 1 to 3E 78 of them Figure 5A and Figure 5B 178 of them Figure 6 and Figure 7 278 of them, and Figure 8 and Fig. 9 378) can be connected with the second conductive pattern ( Figures 1 to 10B As described above, the reference Fig.11 Description of the bit line contact plug ( Figures 1 to 3E 78 of them Figure 5A and Figure 5B 178 of them Figure 6 and Figure 7 278 of them, and Figure 8 and Fig. 9 378 in) and the second conductive pattern ( Figures 1 to 10B A modified example of 80b) in FIG. Fig.11 It shows Figure 3A sectional view of a modified example in which the bit line contact structure 78 and the second conductive pattern 80b are integrally formed to show the bit line contact plug ( Figures 1 to 3E 78 of them Figure 5A and Figure 5B 178 of them Figure 6 and Figure 7 278 of them, and Figure 8 and Fig. 9 378 in) and the second conductive pattern ( Figures 1 to 10B A modified example of 80b) in FIG.

[0169] refer to Fig.11 , bit line contact plug ( Figures 1 to 3E 78 of them Figure 5A and Figure 5B 178 of them Figure 6 and Figure 7 278 of them, and Figure 8 and Fig. 9 378 in) and the second conductive pattern ( Figures 1 to 10B 80b) in the figure can be modified to be integrally formed. For example, the bit line contact plug ( Figures 1 to 3E 78 of them Figure 5A and Figure 5B 178 of them Figure 6 and Figure 7 278 of them, and Figure 8 and Fig. 9 378 in) and the second conductive pattern ( Figures 1 to 10B 80b) in may be modified to have the bit line contact plug 478 and the second conductive pattern 480b formed integrally.

[0170] Among the bit line contact plug 478 and the second conductive pattern 480b, considering one bit line contact plug 478 and one second conductive pattern 480b connected to each other as a reference, the bit line contact plug 478 and the second conductive pattern 480b may be integrally formed. The bit line contact plug 478 and the second conductive pattern 480b may include a first conductive layer 477b and a second conductive layer 477a covering a lower portion of the first conductive layer 477b.

[0171] Next, refer to Figure 1 and Figures 12 to 18C , an illustrative example of a method for manufacturing a semiconductor device according to an example embodiment of the inventive concept will be described. Figures 12 to 18C middle, Fig.12 is a process flow chart for illustrating a method for manufacturing a semiconductor device according to an example embodiment of the inventive concept, Fig.13 , Fig.15 and Fig.17 is with Figure 1 A plan view corresponding to the area indicated by “A” in FIG. 1 is used to illustrate a method for manufacturing a semiconductor device according to an example embodiment of the inventive concept, Fig.14A is along Figure 2 A cross-sectional view taken along line II' of Fig. 14B and Fig.16A is shown along Figure 2 A cross-sectional view of the area cut by line II-II', Fig. 14C and Fig.18A is shown along Figure 2 A cross-sectional view of the area cut along line III-III', Fig.14D , Fig. 16B and Fig.18B is shown along Figure 2 A cross-sectional view of the region taken along line IV-IV', and Fig.18C is shown along Figure 2 A cross-sectional view of the area taken along line V-V'.

[0172] refer to Figure 1 , Fig.12 , Fig.13 as well as FIG. 14A to FIG. 14D, a cell transistor TR may be formed (S10). Forming the cell transistor TR may include: forming device isolation regions cSTI and pSTI defining a cell active region cACT and a peripheral active region pACT on a substrate SUB, forming a gate trench GT crossing the cell device isolation region cST and the cell active region cACT between cSTI and pSTI, and forming gate structures GS and GC in the gate trench GT.

[0173] Forming the cell transistor TR may further include forming a first source / drain region SD1 and a second source / drain region SD2 in the cell active region cACT.

[0174] Each of the gate structures GS and GC may include a gate line GS, and a gate capping layer GC on the gate line GS. Each gate line GS may include a gate dielectric layer Gox and a gate electrode GE. In each gate line GS, the gate dielectric layer Gox may be disposed on the inner wall of the gate trench GT, and the gate electrode GE may partially fill the gate trench GT on the gate dielectric layer Gox. The gate capping layer GC may fill the remaining portion of the gate trench GT on the gate electrode GE.

[0175] The cell transistor TR may include a gate electrode GE, a gate dielectric layer Gox, and first and second source / drain regions SD1 and SD2 .

[0176] The device isolation regions cSTI and pSTI may include a cell device isolation region cSTI in the memory cell array region MCA, and a peripheral device isolation region pSTI in the extension regions EXTa and EXTb. The peripheral device isolation region pSTI may include an insulating layer 9, a first insulating pad 3 covering the side surface and the bottom surface of the insulating layer 9, and a second insulating pad 6 between the insulating layer 9 and the first insulating pad 3.

[0177] A buffer insulating layer 12 may be formed, which covers the cell active region cACT, the device isolation regions cSTI and pSTI, and the gate structures GS and GC, and has an opening exposing the first source / drain region SD1 .

[0178] A plate pattern 27 may be formed ( S20 ). The plate pattern 27 may be formed on the buffer insulating layer 12 , and may contact the first source / drain region SD1 exposed by the buffer insulating layer 12 .

[0179] The plate pattern 27 may include at least one conductive layer 15 , and a lower insulating layer 24 on the at least one conductive layer 15 .

[0180] The at least one conductive layer 15 may include a first conductive material layer 17, a second conductive material layer 19, and a third conductive material layer 21. The at least one conductive layer 15 may include a plug portion 15p penetrating the buffer insulating layer 12 and contacting the first source / drain region SD1.

[0181] The lower insulating layer 24 may include an insulating material such as silicon nitride.

[0182] An end portion of the plate pattern 27 may be located on the peripheral device isolation region pSTI.

[0183] Insulating spacers 30 may be formed on side surfaces of the plate pattern 27. The insulating spacers 30 may include at least one insulating material. For example, the insulating spacers 30 may include at least one of silicon oxide, a low dielectric material, or silicon nitride.

[0184] A conformal insulating liner 33 may be formed on the substrate having the plate pattern 27 and the insulating spacers 30. The insulating liner 33 may include silicon nitride.

[0185] An insulating layer may be formed on the substrate having the insulating liner 33, and may be planarized until the insulating liner 33 on the plate pattern 27 is exposed to form an interlayer insulating layer 36. The interlayer insulating layer 36 may include at least one of silicon oxide or a low dielectric material.

[0186] An insulating layer 39 may be formed on the insulating liner 33 and the interlayer insulating layer 36. The insulating layer 39 may include silicon nitride.

[0187] refer to Figure 1 , Fig.12 , Fig.15 , Fig.16A and Fig. 16B , preliminary insulating patterns 41 may be formed (S30). Each of the preliminary insulating patterns 41 may have a stripe shape extending in the first direction (X).

[0188] The preliminary insulating pattern 41 may pass through the insulating layer 39 , the insulating liner 33 , the insulating spacer 30 , and the plate pattern 27 , and contact the peripheral device isolation region pSTI The preliminary insulating pattern 41 may include silicon nitride.

[0189] refer to Figure 1 , Fig.12 , Fig.17 as well as 18A to 18C , an insulating pattern 42 and a bit line structure BLS may be formed ( S40 ).

[0190] Forming the insulating pattern 42 and the bit line structure BLS may include: Figures 15 to 16B 39), preliminary insulation pattern ( Figures 15 to 16B41) and plate pattern ( Figures 15 to 16B 27) to form openings 43 and structures that are spaced apart from each other by the openings 43 in the second direction Y.

[0191] Each of the openings 43 may have a linear shape extending in the first direction X. As shown in FIG.

[0192] A preliminary insulating pattern can be patterned ( Figures 15 to 16B 41) to form the above Figures 1 to 11 The insulating pattern 42 of any one of the exemplary embodiments.

[0193] The insulating layer can be patterned ( Figures 15 to 16B 39) and plate pattern ( Figures 15 to 16B 27) to form the above Figures 1 to 11 The bit line structure BLS of any one of the exemplary embodiments of the present invention. Accordingly, as described above Figures 1 to 11 In any of the example embodiments of FIG. 1 , each bit line structure BLS may include a bit line BL and a capping pattern 23 that are sequentially stacked.

[0194] Return to reference Figures 1 to 3E , you can open the Fig.17 and 18A to 18C The spacer structures SP_L and SP_U, the contact plugs 75, and the insulating fences may be formed in the openings (43). The insulating fences may be disposed between the contact plugs 75 arranged in the first direction (X). The spacer structures SP_L and SP_U may be formed in the openings ( Fig.17 and 18A to 18C Spacer structures SP_L and SP_U may be formed on side surfaces of the bit line structure BLS and the insulating pattern 42.

[0195] The contact plugs 75 may include cell contact plugs 75c formed in the memory cell array region MCA and peripheral contact plugs 75d formed in the first extension region EXTa and the second extension region EXTb. The cell contact plugs 75c may be electrically connected to the second source / drain region SD2, and the peripheral contact plugs 75d may be disposed on the peripheral device isolation region pSTI.

[0196] A bit line contact structure penetrating the capping pattern 23 and electrically connected to the bit line BL may be formed in the first and second extension regions EXTa and EXTb.

[0197] The bit line contact structure can be made of Figures 1 to 11 The bit line contact structure of any one of the exemplary embodiments is formed. For example, the bit line contact structure may be formed by Figures 1 to 3E A bit line contact structure 78 is formed.

[0198] Conductive patterns 80c and 80b and an insulating isolation pattern 83 may be formed. Forming the conductive patterns 80c and 80b and the insulating isolation pattern 83 may include: forming at least one conductive material layer, forming an opening exposing side surfaces of the conductive patterns 80c and 80b, forming the conductive patterns 80c and 80b by patterning the at least one conductive material layer at the same time, and forming the insulating isolation pattern 83 in the opening.

[0199] The conductive patterns 80c and 80b may include a first conductive pattern 80c in the memory cell array area MCA, and a second conductive pattern 80b in the first extension area EXTa and the second extension area EXTb. The first conductive pattern 80c may be electrically connected to the cell contact plug 75c on the cell contact plug 75c. The second conductive pattern 80b may be electrically connected to the bit line contact structure 78 in the first extension area EXTa and the second extension area EXTb.

[0200] An etch stop layer 87 may be formed on the insulating isolation pattern 83 and the conductive patterns 80 c and 80 b .

[0201] A data storage structure DS may be formed (S50). The data storage structure DS may be formed in the memory cell array area MCA. The data storage structure DS may be formed of a capacitor including a first electrode 90 passing through the etch stop layer 87 and electrically connected to the first conductive pattern 80c, a dielectric layer 92 covering the first electrode 90 and the etch stop layer 87, and a second electrode 94 on the dielectric layer 92.

[0202] As described above, according to some example embodiments of the present invention, an insulating pattern may be provided at one of the ends of the first bit line and the second bit line adjacent to each other, and an insulating spacer different from the insulating pattern may be provided at the other end. Even when the size of the first bit line and the second bit line is reduced, such insulating pattern and insulating spacer may alleviate or prevent deformation of the first bit line and the second bit line. Accordingly, the integration of the semiconductor device may be increased, and the reliability of the semiconductor device may be improved.

[0203] The various advantageous advantages and effects of the inventive concept are not limited to the above description, and can be more easily understood in the process of describing the specific example embodiments of the inventive concept. Although some example embodiments have been shown and described above, it will be clear to those skilled in the art that modifications and changes can be made without departing from the scope of the inventive concept defined by the appended claims.

Claims

1. A semiconductor device, comprising: A first bit line intersecting the memory cell array region in a first direction, the first bit line extending into an extension region adjacent to the memory cell array region; A second bit line intersecting the memory cell array region in the first direction, the second bit line extending into the extension region and adjacent to the first bit line; an insulating pattern in the extension region and contacting an end portion of the second bit line in the first direction; as well as An insulating spacer is in the extension region and contacts an end portion of the first bit line in the first direction, the insulating spacer being different from the insulating pattern.

2. The semiconductor device according to claim 1, wherein The insulating pattern is spaced apart from the first bit line and the insulating spacer.

3. The semiconductor device according to claim 1, wherein A length of the insulating pattern in the first direction is greater than a length of the insulating spacer in the first direction.

4. The semiconductor device according to claim 1, wherein: The insulating spacer includes a material different from that of the insulating pattern.

5. The semiconductor device according to claim 1, wherein In the extension region, a lower surface of the insulation pattern is at a lower level than lower surfaces of the first and second bit lines.

6. The semiconductor device according to claim 1, wherein In the extension region, an upper surface of the insulation pattern is at a higher level than upper surfaces of the first and second bit lines.

7. The semiconductor device according to claim 1, wherein The insulating pattern includes a first portion extending in the first direction, and a second portion extending from the first portion, the second portion having a width greater than a width of the first portion, and The first portion of the insulating pattern is between the second portion of the insulating pattern and the second bit line.

8. The semiconductor device according to claim 7, wherein: In the extension region, a width of the second portion of the insulation pattern is greater than a width of each of the first bit line and the second bit line.

9. The semiconductor device according to claim 1, wherein: In the extension region, the insulating pattern includes a lower region at a level lower than the first bit line and the second bit line, a middle region at the same level as the first bit line and the second bit line, and an upper region at a level higher than the first bit line and the second bit line, and In the extension region, a width of a lower region of the insulation pattern is greater than a width of each of the first bit line and the second bit line.

10. The semiconductor device according to claim 9, wherein In the extension region, a maximum width of the middle region of the insulation pattern is greater than a width of each of the first bit line and the second bit line.

11. The semiconductor device according to claim 1, further comprising: a gate line intersecting the memory cell array region in a second direction perpendicular to the first direction, the gate line being at a different level from the first bit line and the second bit line, Wherein, the gate line includes a dummy gate line adjacent to the extension area, and A distance between the end of the first bit line in the extension region and the dummy gate line in the first direction is greater than a distance between the end of the second bit line in the extension region and the dummy gate line in the first direction.

12. The semiconductor device according to claim 11, further comprising: A substrate, comprising the memory cell array region and the extension region; A cell active region on the substrate and a cell device isolation region defining a side surface of the cell active region, the cell active region and the cell device isolation region being within the memory cell array region; a peripheral device isolation region on the extension region; as well as A gate trench intersecting the cell active region and the cell device isolation region, Wherein, the gate line is in the gate trench, The first bit line and the second bit line are on the cell active region, the cell device isolation region and the peripheral device isolation region, The insulating pattern is on the peripheral device isolation region, and The first bit line and the second bit line and the insulation pattern are within the extension region and on the peripheral device isolation region.

13. A semiconductor device comprising: A substrate including a memory cell array region and an extension region; Line structures intersecting the memory cell array region and extending into the extension region, the line structures being parallel to each other; as well as insulating patterns, within the extension region and spaced apart from each other, wherein each of the line structures has a linear shape extending in a first direction, The line structure includes a first line structure and second line structures on both sides of the first line structure, In the extension region, the insulating pattern contacts an end portion of the second line structure in the first direction, and In the extension region, ends of the first line structure in the first direction are between the insulation patterns.

14. The semiconductor device according to claim 13, wherein: The insulation pattern is spaced apart from the first line structure.

15. The semiconductor device according to claim 13, wherein: Each of the insulating patterns includes a first portion extending in the first direction, and a second portion extending from the first portion, the second portion having a width greater than a width of the first portion, The first portion of the corresponding one of the insulation patterns is between the second portion of the corresponding one of the insulation patterns and the corresponding one of the second line structures, and In the extension region, a width of the second portion is greater than a width of each of the line structures.

16. The semiconductor device according to claim 13, wherein: Each of the line structures includes a conductive line and a capping pattern on the conductive line, In the extension region, each of the insulating patterns includes a lower region at a level lower than the conductive line, a middle region at the same level as the conductive line, and an upper region at a level higher than the conductive line, and In the extension region, the width of the lower region is greater than the width of the conductive line.

17. The semiconductor device according to claim 13, further comprising: an insulating spacer, contacting the end of the first line structure in the first direction and within the extension region, The insulating spacer includes a material different from that of the insulating patterns and is between the insulating patterns.

18. A semiconductor device comprising: A substrate including a memory cell array region, a first extension region, and a second extension region; A bit line structure intersecting the memory cell array region and extending into the first extension region and the second extension region, the bit line structures being parallel to each other on the substrate; first insulating patterns, in the first extension region, the first insulating patterns being spaced apart from each other on the substrate; as well as second insulating patterns, in the second extension region, the second insulating patterns being spaced apart from each other on the substrate, The memory cell array region is between the first extension region and the second extension region. Each of the bit line structures has a linear shape extending in the first direction, The bit line structure includes a first bit line structure and a second bit line structure alternating in a second direction perpendicular to the first direction, In the first extension region, the first insulation pattern contacts an end portion of the second bit line structure in the first direction, In the second extension region, the second insulation pattern contacts an end portion of the first bit line structure in the first direction, In the first extension region, the end of the first bit line structure in the first direction is between the first insulating patterns, and In the second extension region, the end of the second bit line structure in the first direction is between the second insulating patterns.

19. The semiconductor device according to claim 18, further comprising: a first bit line contact structure, within the first extension region; a second bit line contact structure, within the second extension region; as well as a peripheral contact plug between the bit line structures, the peripheral contact plug being within the first extension region and the second extension region, Each of the bit line structures includes a bit line and a capping pattern on the bit line. In the first extension region, each of the first bit line contact structures penetrates the capping pattern of a first corresponding bit line structure among the bit line structures and is electrically connected to the bit line of the first corresponding bit line structure among the bit line structures, and In the second extension region, each of the second bit line contact structures penetrates the capping pattern of a second corresponding one of the bit line structures and is electrically connected to the bit line of the second corresponding one of the bit line structures.

20. The semiconductor device according to claim 19, wherein In the first extension region, the peripheral contact plugs include a first peripheral contact plug connected to the first bit line contact structure and a second peripheral contact plug spaced apart from the first bit line contact structure, Each of the first bit line contact structures includes a contact portion and at least one extending portion extending from the contact portion, The contact portion of each of the first bitline contact structures is connected to a corresponding one of the bitlines of the first bitline structures, and the at least one extending portion of the first bitline contact structure is connected to at least one corresponding one of the first peripheral contact plugs.

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