Small area common voltage antifuse array

Abstract

The invention discloses a small-area common-voltage anti-fuse array, which belongs to the field of memory arrays and comprises a plurality of word lines, a plurality of selection lines, a plurality of common-voltage lines and a plurality of anti-fuse elements. The word lines comprise a first word line and a second word line, the selection lines are perpendicular to the common voltage lines and the word lines, and the selection lines comprise a first selection line. The common voltage lines are directly coupled together and include a first common voltage line and a second common voltage line. The first word line and the second word line are respectively close to the first common voltage line and the second common voltage line. Each anti-fuse element is coupled with two word lines, one selection line and two common voltage lines, and comprises a first anti-fuse memory unit cell and a second anti-fuse memory unit cell. The first anti-fuse memory unit cell is coupled to the first word line, the first selection line and the first common voltage line, and the second anti-fuse memory unit cell is coupled to the second word line, the first selection line and the second common voltage line. According to the invention, the number and the overall area of decoders are reduced.

Description

Technical Field

[0001] The present invention relates to the field of memory arrays, and in particular to a small-area common-voltage anti-fuse array. Background Art

[0002] In today's advanced computer information products, non-volatile memories with the function of electrically writing and erasing data, such as electronically erasable read-only memory (EEPROM) or flash memory (flash), are widely used in electronic products because the stored data will not disappear after the power is turned off. However, the structure of these read-only memories or cache memories is relatively complex, the reliability is relatively low, and the manufacturing cost is high. Therefore, many places can use one-time programmable memory (OTP) with high reliability and low manufacturing cost. OTP using fuses or anti-fuses as components is more flexible in use.

[0003] Traditional fuses mainly include metal fuses and polysilicon fuses. The writing method is mainly to burn out the fuse with high-energy laser or high current. After writing, the resistance value of the fuse will increase, and the power consumption is relatively large. The anti-fuse mainly adds a dielectric layer between two conductors in a capacitive manner. When writing, a bias is applied to each of the two conductors to cause the dielectric layer to collapse and break down. After writing, the resistance value of the anti-fuse will decrease. With the rapid development of integrated circuits, the size of components is shrinking. In recent years, the use of metal oxide semiconductor (MOS) components to make anti-fuse components has been developed. Its writing method is mainly based on the gate dielectric layer collapse mechanism. Anti-fuse (anti-fuse) is a programmable component. When burning, the internal switch element will be disconnected or turned on. In order to program the anti-fuse array, a certain voltage and current need to be applied so that the corresponding switch element can be turned on or off. These programming signals need to be transmitted to the correct position of the anti-fuse array through a decoder. However, the decoder will increase the overall area of ​​the anti-fuse array.

[0004] Therefore, in view of the above-mentioned difficulties, the present invention proposes a small-area common voltage anti-fuse array to solve the problems in the prior art. Summary of the invention

[0005] The invention provides a small-area common voltage anti-fuse array, which can reduce the number and overall area of ​​decoders.

[0006] In one embodiment of the present invention, a small-area common voltage anti-fuse array is provided, which includes a plurality of parallel word lines, a plurality of parallel selection lines, a plurality of parallel common voltage lines and a plurality of anti-fuse elements. All word lines include a first word line and a second word line, all selection lines are perpendicular to all word lines, and all selection lines include a first selection line. All common voltage lines are perpendicular to all selection lines, and all common voltage lines are directly coupled together, and all common voltage lines include a first common voltage line and a second common voltage line. The first word line and the second word line are respectively close to the first common voltage line and the second common voltage line. Each anti-fuse element is coupled to two word lines, a selection line and two common voltage lines. Each anti-fuse element includes a first anti-fuse memory cell and a second anti-fuse memory cell. The first anti-fuse memory cell is coupled to the first word line, the first selection line and the first common voltage line, and the second anti-fuse memory cell is coupled to the second word line, the first selection line and the second common voltage line.

[0007] In one embodiment of the present invention, the first anti-fuse memory cell and the second anti-fuse memory cell are symmetrically arranged.

[0008] In one embodiment of the present invention, a first anti-fuse memory cell and a second anti-fuse memory cell are disposed in a semiconductor region, the semiconductor region has a first conductivity type, and the first anti-fuse memory cell includes a first gate dielectric block, a first anti-fuse gate, a first ion doping region, a second ion doping region, and a third ion doping region. The first gate dielectric block is disposed on the semiconductor region and is located between the first word line and the semiconductor region. The first anti-fuse gate is disposed on the first gate dielectric block and is coupled to the first common voltage line. The first anti-fuse gate is closer to the first common voltage line than the first word line. The first ion doping region, the second ion doping region, and the third ion doping region are disposed in the semiconductor region. The first ion doping region, the second ion doping region, and the third ion doping region have a second conductivity type, and the second conductivity type is opposite to the first conductivity type. The first ion doping region and the second ion doping region are arranged on different sides of the semiconductor region directly below the first word line, the second ion doping region and the third ion doping region are arranged on different sides of the semiconductor region directly below the first anti-fuse gate, and the first ion doping region is coupled to the first selection line.

[0009] In one embodiment of the present invention, the second anti-fuse memory cell includes a second gate dielectric block, a second anti-fuse gate, a fourth ion-doped region, a fifth ion-doped region, and a sixth ion-doped region. The second gate dielectric block is disposed on the semiconductor region and is located between the second word line and the semiconductor region. The second anti-fuse gate is disposed on the second gate dielectric block and is coupled to the second common voltage line. The second anti-fuse gate is closer to the second common voltage line than the second word line. The fourth ion-doped region, the fifth ion-doped region, and the sixth ion-doped region are disposed in the semiconductor region. The fourth ion-doped region, the fifth ion-doped region, and the sixth ion-doped region have a second conductivity type. The fourth ion-doped region and the fifth ion-doped region are disposed on different sides of the semiconductor region directly below the second word line, the fifth ion-doped region and the sixth ion-doped region are disposed on different sides of the semiconductor region directly below the second anti-fuse gate, and the fourth ion-doped region is coupled to the first selection line.

[0010] In one embodiment of the present invention, the first conductivity type is P type, and the second conductivity type is N type.

[0011] In one embodiment of the present invention, when the first anti-fuse memory cell is selected for a write operation, a high voltage is applied to the first common voltage line, a high voltage or a medium voltage is applied to the first word line, and a ground voltage is applied to the first selection line, the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage.

[0012] In one embodiment of the present invention, when the first anti-fuse memory cell is not selected for a write operation, a high voltage is applied to the first common voltage line, a ground voltage is applied to the first word line, a bias voltage is applied to the first selection line or it is electrically floating, the high voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

[0013] In one embodiment of the present invention, when the first anti-fuse memory cell is selected for reading, the first common voltage line is applied with a ground voltage, the first word line is applied with a medium voltage, the first selection line is applied with a bias voltage, the medium voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

[0014] In one embodiment of the present invention, when the first anti-fuse memory cell is not selected for a read operation, a ground voltage is applied to the first common voltage line, a ground voltage is applied to the first word line, and the first selection line is electrically floating.

[0015] In one embodiment of the present invention, when the second anti-fuse memory cell is selected for a write operation, a high voltage is applied to the second common voltage line, a high voltage or a medium voltage is applied to the second word line, and a ground voltage is applied to the first selection line, the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage.

[0016] In one embodiment of the present invention, when the second anti-fuse memory cell is not selected for a write operation, a high voltage is applied to the second common voltage line, a ground voltage is applied to the second word line, a bias voltage is applied to the first selection line or it is electrically floating, the high voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

[0017] In one embodiment of the present invention, when the second anti-fuse memory cell is selected for reading, the second common voltage line is applied with a ground voltage, the second word line is applied with a medium voltage, the first selection line is applied with a bias voltage, the medium voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

[0018] In one embodiment of the present invention, when the second anti-fuse memory cell is not selected for reading, the second common voltage line is applied with a ground voltage, the second word line is applied with a ground voltage, and the first selection line is electrically floating.

[0019] In one embodiment of the present invention, the first conductivity type is N type, and the second conductivity type is P type.

[0020] In one embodiment of the present invention, when the first anti-fuse memory cell is selected for a write operation, a ground voltage is applied to the first common voltage line, a ground voltage or a medium voltage is applied to the first word line, and a high voltage is applied to the first selection line, the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage.

[0021] In one embodiment of the present invention, when the first anti-fuse memory cell is not selected for a write operation, a ground voltage is applied to the first common voltage line, a high voltage is applied to the first word line, a bias voltage is applied to the first selection line or it is electrically floating, the high voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

[0022] In one embodiment of the present invention, when the first anti-fuse memory cell is selected for reading, a high voltage is applied to the first common voltage line, a medium voltage is applied to the first word line, a bias is applied to the first selection line, the medium voltage is less than the bias voltage, and the high voltage is greater than the bias voltage.

[0023] In one embodiment of the present invention, when the first anti-fuse memory cell is not selected for a read operation, a high voltage is applied to the first common voltage line, a high voltage is applied to the first word line, and the first selection line is electrically floating.

[0024] In one embodiment of the present invention, when the second anti-fuse memory cell is selected for a write operation, a ground voltage is applied to the second common voltage line, a ground voltage or a medium voltage is applied to the second word line, and a high voltage is applied to the first selection line, the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage.

[0025] In one embodiment of the present invention, when the second anti-fuse memory cell is not selected for writing, the second common voltage line is applied with a ground voltage, the second word line is applied with a high voltage, the first selection line is applied with a bias voltage or is electrically floating, the high voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

[0026] In one embodiment of the present invention, when the second anti-fuse memory cell is selected for reading, a high voltage is applied to the second common voltage line, a medium voltage is applied to the second word line, a bias is applied to the first selection line, the medium voltage is less than the bias voltage, and the high voltage is greater than the bias voltage.

[0027] In one embodiment of the present invention, when the second anti-fuse memory cell is not selected for reading, a high voltage is applied to the second common voltage line, a high voltage is applied to the second word line, and the first selection line is electrically floating.

[0028] According to the specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0029] Based on the above, the small-area common voltage anti-fuse array directly couples the common voltage lines together to reduce the number of decoders and the overall area. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0031] Figure 1 FIG. 4 is a schematic diagram of a circuit layout of an embodiment of a small-area common-voltage anti-fuse array of the present invention.

[0032] Figure 2 FIG. 4 is a schematic diagram of a circuit layout of an anti-fuse element according to an embodiment of the present invention.

[0033] Figure 3 FIG. 4 is a structural cross-sectional view of an embodiment of a first anti-fuse memory cell of the present invention.

[0034] Figure 4 FIG. 4 is a structural cross-sectional view of an embodiment of a second anti-fuse memory cell of the present invention.

[0035] Figure 5 It is a structural cross-sectional view of another embodiment of the first anti-fuse memory cell of the present invention.

[0036] Figure 6 FIG. 4 is a structural cross-sectional view of another embodiment of the second anti-fuse memory cell of the present invention.

[0037] Explanation of symbols:

[0038] 1: small area common voltage anti-fuse array; 10: anti-fuse element; 100: first anti-fuse memory cell; 1000: first gate dielectric block; 1001: first anti-fuse gate; 1002: first ion doping region; 1003: second ion doping region; 1004: third ion doping region; 1005: first sidewall spacer; 1006: first lightly doped drain region; 1007: second sidewall spacer; 1008: second lightly doped drain region; 101: second anti-fuse memory cell; 1010: second gate dielectric Block; 1011: second antifuse gate; 1012: fourth ion-doped region; 1013: fifth ion-doped region; 1014: sixth ion-doped region; 1015: third sidewall spacer; 1016: third lightly-doped drain region; 1017: fourth sidewall spacer; 1018: fourth lightly-doped drain region; 2: semiconductor region; 3: semiconductor substrate; 4: first conductive metal block; 5: first conductive via; 6: second conductive via; 7: second conductive metal block; 8: third conductive via; 9: fourth conductive via.

[0039] WL: word line; WL1: first word line; WL2: second word line; SL: select line; SL1: first select line; CVL: common voltage line; CVL1: first common voltage line; CVL2: second common voltage line; L: gate dielectric layer; CH1, CH2, CH3, CH4: channel region. DETAILED DESCRIPTION

[0040] The embodiments of the present invention will be further explained below in conjunction with the accompanying drawings. As much as possible, the same reference numerals represent the same or similar components in the drawings and the specification. In the drawings, the shapes and thicknesses may be exaggerated for simplicity and convenience. It is understood that the components not specifically shown in the drawings or described in the specification are in the form known to those skilled in the art. Those skilled in the art may make various changes and modifications based on the contents of the present invention.

[0041] Unless otherwise specified, some conditional sentences or words, such as "can", "could", "might", or "may", are generally intended to express that the present embodiment has, but can also be interpreted as features, components, or steps that may not be required. In other embodiments, these features, components, or steps may not be required.

[0042] The description of "one embodiment" or "an embodiment" in the following text refers to a specific element, structure or feature associated with at least one embodiment. Therefore, multiple descriptions of "one embodiment" or "an embodiment" appearing in multiple places in the following text do not refer to the same embodiment. Furthermore, specific components, structures and features in one or more embodiments may be combined in an appropriate manner.

[0043] Certain words are used in the specification and claims to refer to specific components. However, those with ordinary knowledge in the technical field should understand that the same component may be referred to by different terms. The specification and claims do not use differences in name as a way to distinguish components, but use differences in the functions of the components as a basis for distinction. The term "including" mentioned in the specification and claims is an open-ended term and should be interpreted as "including but not limited to". In addition, "coupling" includes any direct and indirect connection means. Therefore, if the text describes a first component coupled to a second component, it means that the first component can be directly connected to the second component through electrical connection or signal connection methods such as wireless transmission, optical transmission, etc., or indirectly electrically or signal connected to the second component through other components or connection means.

[0044] The following examples are particularly described, and these examples are only used for illustration, because for those skilled in the art, various changes and modifications can be made without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be determined by the scope of the attached claims. Throughout the specification and the claims, unless the content clearly specifies, the meaning of "one" and "the" includes this type of description including "one or at least one" of the elements or components. In addition, as used in the present invention, unless it is obvious from the specific context that more is excluded, the singular article also includes the description of multiple elements or components. Moreover, when applied in this description and the following claims, unless the content clearly specifies, the meaning of "in which" may include "in which" and "on which". The terms used in the specification and the claims, unless otherwise specified, generally have the ordinary meaning of each term used in this field, in the content disclosed herein and in the specific content. Certain terms used to describe the present invention will be discussed below or elsewhere in this specification to provide practitioners with additional guidance on the description of the present invention. Examples anywhere throughout the specification, including the use of examples of any term discussed herein, are provided for illustration only and certainly do not limit the scope and meaning of the invention or any exemplified term. Likewise, the invention is not limited to the various embodiments presented in this specification.

[0045] In the specification and claims, if a first element is described as being located on, above, connected, joined, coupled to, or in contact with a second element, it means that the first element may be directly located on, directly connected, directly joined, or directly coupled to the second element, or it may mean that there are other elements between the first element and the second element. Conversely, if a first element is described as being directly located on, directly connected, directly joined, directly coupled, or directly in contact with a second element, it means that there are no other elements between the first element and the second element.

[0046] In the following description, a small-area common voltage anti-fuse array is provided, which directly couples common voltage lines together to reduce the number of decoders and the overall area.

[0047] Figure 1 FIG. 1 is a schematic diagram of a circuit layout of an embodiment of a small-area common voltage anti-fuse array of the present invention. Figure 2 FIG. 1 is a schematic diagram of a circuit layout of an embodiment of an anti-fuse element of the present invention. Figure 1 and Figure 2 , the small-area common voltage anti-fuse array 1 of the present invention is introduced below. The small-area common voltage anti-fuse array 1 includes a plurality of parallel word lines WL, a plurality of parallel selection lines SL, a plurality of parallel common voltage lines CVL and a plurality of anti-fuse elements 10. All word lines WL include a first word line WL1 and a second word line WL2, all selection lines SL are perpendicular to all word lines WL, and all selection lines SL include a first selection line SL1. All common voltage lines CVL are perpendicular to all selection lines SL, and all common voltage lines CVL are directly coupled together through one end on the same side thereof, and all common voltage lines CVL include a first common voltage line CVL1 and a second common voltage line CVL2. The first word line WL1 and the second word line WL2 are respectively close to the first common voltage line CVL1 and the second common voltage line CVL2. Each anti-fuse element 10 is coupled to two word lines WL, one selection line SL and two common voltage lines CVL. Each anti-fuse element 10 includes a first anti-fuse memory cell 100 and a second anti-fuse memory cell 101. The first anti-fuse memory cell 100 is coupled to the first word line WL1, the first selection line SL1 and the first common voltage line CVL1, and the second anti-fuse memory cell 101 is coupled to the second word line WL2, the first selection line SL1 and the second common voltage line CVL2. In some embodiments of the present invention, the first anti-fuse memory cell 100 and the second anti-fuse memory cell 101 are symmetrically arranged.

[0048] Figure 3 FIG. 1 is a cross-sectional view of a structure of an embodiment of the first anti-fuse memory cell of the present invention. Figure 3 and Figure 2The first anti-fuse memory cell 100 is disposed in a semiconductor region 2, and the semiconductor region 2 has a first conductivity type. For example, the semiconductor region 2 is a doped well region, and the doped well region is disposed in a semiconductor substrate 3. The semiconductor substrate 3 can be a P-type semiconductor substrate or an N-type semiconductor substrate. The first anti-fuse memory cell 100 includes a first gate dielectric block 1000, a first anti-fuse gate 1001, a first ion doping region 1002, a second ion doping region 1003 and a third ion doping region 1004. The first gate dielectric block 1000 is Figure 1 A portion of a gate dielectric layer L in the first anti-fuse gate 1001 and Figure 1 The word lines WL in the diagram are all part of an electrode layer. Figure 1 The selection line SL is a part of a first conductive metal layer, Figure 1 The common voltage line CVL is a part of a second conductive metal layer, and the electrode layer, the first conductive metal layer and the second conductive metal layer are arranged from bottom to top. The first gate dielectric block 1000 is arranged on the semiconductor region 2 and is located between the first word line WL1 and the semiconductor region 2. The first anti-fuse gate 1001 is arranged on the first gate dielectric block 1000 and is coupled to the first common voltage line CVL1, wherein the first anti-fuse gate 1001 is closer to the first common voltage line CVL1 than the first word line WL1. Specifically, the first anti-fuse gate 1001 overlaps with a first conductive metal block 4, and the first conductive metal block 4 is a part of the first conductive metal layer. The first conductive via 5 is located between the first anti-fuse gate 1001 and the first conductive metal block 4. The first anti-fuse gate 1001 is coupled to the first conductive metal block 4 through the first conductive via 5. The first conductive metal block 4 overlaps with the first common voltage line CVL1. The second conductive via 6 is located between the first conductive metal block 4 and the first common voltage line CVL1. The first conductive metal block 4 is coupled to the first common voltage line CVL1 through the second conductive via 6.

[0049] The first ion doping region 1002, the second ion doping region 1003 and the third ion doping region 1004 are arranged in the semiconductor region 2, wherein the first ion doping region 1002, the second ion doping region 1003 and the third ion doping region 1004 have a second conductivity type, and the second conductivity type is opposite to the first conductivity type. The first ion doping region 1002 and the second ion doping region 1003 are arranged on different sides of the semiconductor region 2 directly below the first word line WL1. The second ion doping region 1003 and the third ion doping region 1004 are arranged on different sides of the semiconductor region 2 directly below the first anti-fuse gate 1001, and the first ion doping region 1002 is coupled to the first selection line SL1. The first selection line SL1 is coupled to the first conductive via 5 directly below it, and the first conductive via 5 penetrates the gate dielectric layer L. The first selection line SL1 is coupled to an external voltage through the first conductive via 5.

[0050] The semiconductor region 2, the first word line WL1, the first ion doped region 1002, the second ion doped region 1003 and the first gate dielectric block 1000 form a first selection MOS field effect transistor. Two first sidewall spacers 1005 are respectively provided on both sidewalls of the first word line WL1. The two first sidewall spacers 1005 extend to the sidewalls of the first gate dielectric block 1000. Two first lightly doped drain (LDD) regions 1006 of the second conductivity type are respectively provided directly below the two first sidewall spacers 1005. When the first selection MOS field effect transistor is turned on, a channel region CH1 is formed between the first lightly doped drain regions 1006.

[0051] The semiconductor region 2, the first anti-fuse gate 1001, the second ion-doped region 1003, the third ion-doped region 1004 and the first gate dielectric block 1000 form a first anti-fuse MOSFET. Two second sidewall spacers 1007 are respectively provided on both sidewalls of the first anti-fuse gate 1001. The two second sidewall spacers 1007 extend to the sidewalls of the first gate dielectric block 1000. Two second lightly doped drain regions 1008 of the second conductivity type are respectively provided directly below the two second sidewall spacers 1007. When the first anti-fuse MOSFET is turned on, a channel region CH2 is formed between the second lightly doped drain regions 1008.

[0052] Figure 4 FIG. 1 is a cross-sectional view of a structure of an embodiment of a second anti-fuse memory cell of the present invention. Figure 4 and Figure 2 The second anti-fuse memory cell 101 is also disposed in the semiconductor region 2. The second anti-fuse memory cell 101 includes a second gate dielectric block 1010, a second anti-fuse gate 1011, a fourth ion doping region 1012, a fifth ion doping region 1013 and a sixth ion doping region 1014. The second gate dielectric block 1010 is Figure 1 The second anti-fuse gate 1011 is connected to a portion of the gate dielectric layer L in the Figure 1The word lines WL in the semiconductor region 2 are all part of the electrode layer. The second gate dielectric block 1010 is disposed on the semiconductor region 2 and is located between the second word line WL2 and the semiconductor region 2. The second anti-fuse gate 1011 is disposed on the second gate dielectric block 1010 and is coupled to the second common voltage line CVL2, wherein the second anti-fuse gate 1011 is closer to the second common voltage line CVL2 than the second word line WL2. Specifically, the second anti-fuse gate 1011 overlaps with a second conductive metal block 7, and the second conductive metal block 7 is part of the first conductive metal layer. The third conductive through hole 8 is located between the second anti-fuse gate 1011 and the second conductive metal block 7. The second anti-fuse gate 1011 is coupled to the second conductive metal block 7 through the third conductive through hole 8. The second conductive metal block 7 overlaps with the second common voltage line CVL2. The fourth conductive through hole 9 is located between the second conductive metal block 7 and the second common voltage line CVL2. The second conductive metal block 7 is coupled to the second common voltage line CVL2 through the fourth conductive through hole 9.

[0053] The fourth ion doping region 1012, the fifth ion doping region 1013 and the sixth ion doping region 1014 are disposed in the semiconductor region 2, wherein the fourth ion doping region 1012, the fifth ion doping region 1013 and the sixth ion doping region 1014 have the second conductivity type. The fourth ion doping region 1012 and the fifth ion doping region 1013 are disposed on different sides of the semiconductor region 2 directly below the second word line WL2. The fifth ion doping region 1013 and the sixth ion doping region 1014 are disposed on different sides of the semiconductor region 2 directly below the second anti-fuse gate 1011, and the fourth ion doping region 1012 is coupled to the first selection line SL1.

[0054] The semiconductor region 2, the second word line WL2, the fourth ion-doped region 1012, the fifth ion-doped region 1013 and the second gate dielectric block 1010 form a second selection MOS field effect transistor. Two third sidewall spacers 1015 are respectively provided on both sidewalls of the second word line WL2. The two third sidewall spacers 1015 extend to the sidewalls of the second gate dielectric block 1010. Two third lightly-doped drain regions 1016 of the second conductivity type are respectively provided directly below the two third sidewall spacers 1015. When the second selection MOS field effect transistor is turned on, a channel region CH3 is formed between the third lightly-doped drain regions 1016.

[0055] The semiconductor region 2, the second anti-fuse gate 1011, the fifth ion-doped region 1013, the sixth ion-doped region 1014 and the second gate dielectric block 1010 form a second anti-fuse MOSFET. Two fourth sidewall spacers 1017 are respectively provided on both sidewalls of the second anti-fuse gate 1011. The two fourth sidewall spacers 1017 extend to the sidewalls of the second gate dielectric block 1010. Two fourth lightly-doped drain regions 1018 of the second conductivity type are respectively provided directly below the two fourth sidewall spacers 1017. When the second anti-fuse MOSFET is turned on, a channel region CH4 is formed between the fourth lightly-doped drain regions 1018.

[0056] Assume that the first conductivity type is P type and the second conductivity type is N type. Figure 2 The operation process of the first anti-fuse memory cell 100 and the second anti-fuse memory cell 101 is described below.

[0057] When the first anti-fuse memory cell 100 is selected to perform a write operation, a high voltage is applied to the first common voltage line CVL1, a high voltage or a medium voltage is applied to the first word line WL1, and a ground voltage is applied to the first selection line SL1, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage. When the first anti-fuse memory cell 100 is not selected to perform a write operation, a high voltage is applied to the first common voltage line CVL1, a ground voltage is applied to the first word line WL1, and a first bias is applied to the first selection line SL1 or is electrically floating, wherein the high voltage is greater than the first bias, and the first bias is greater than the ground voltage. When the first anti-fuse memory cell 100 is selected to perform a read operation, a ground voltage is applied to the first common voltage line CVL1, a medium voltage is applied to the first word line WL1, and a first bias is applied to the first selection line SL1, wherein the medium voltage is greater than the first bias, and the first bias is greater than the ground voltage. When the first anti-fuse memory cell 100 is not selected for a read operation, a ground voltage is applied to the first common voltage line CVL1 , a ground voltage is applied to the first word line WL1 , and the first selection line SL1 is electrically floating.

[0058] When the second anti-fuse memory cell 101 is selected to perform a write operation, a high voltage is applied to the second common voltage line CVL2, a high voltage or a medium voltage is applied to the second word line WL2, and a ground voltage is applied to the first selection line SL1, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage. When the second anti-fuse memory cell 101 is not selected to perform a write operation, a high voltage is applied to the second common voltage line CVL2, a ground voltage is applied to the second word line WL2, and a first bias is applied to the first selection line SL1 or is electrically floating, wherein the high voltage is greater than the first bias, and the first bias is greater than the ground voltage. When the second anti-fuse memory cell 101 is selected to perform a read operation, a ground voltage is applied to the second common voltage line CVL2, a medium voltage is applied to the second word line WL2, and a first bias is applied to the first selection line SL1, wherein the medium voltage is greater than the first bias, and the first bias is greater than the ground voltage. When the second anti-fuse memory cell 101 is not selected for a read operation, a ground voltage is applied to the second common voltage line CVL2 , a ground voltage is applied to the second word line WL2 , and the first selection line SL1 is electrically floating.

[0059] Based on the above operation, the common voltage line directly receives the external voltage without passing through the decoder, and is directly coupled to the anti-fuse memory cell, so that the anti-fuse memory cell performs a write action or a read action, so as to reduce the number of decoders and the overall area of ​​the small-area common voltage anti-fuse array. In the above operation, applying a medium voltage or a high voltage to the word line will affect the current size of the component, so it will be adjusted according to different designs and situations. The selection line is biased or electrically floating according to the process characteristics. In addition, the high voltage is greater than the medium voltage, the medium voltage is greater than the first bias voltage, and the high voltage is usually slightly lower than the breakdown voltage of the drain to the source. Specifically, the high voltage is equal to the breakdown voltage of the drain to the source minus the threshold voltage of the field effect transistor, and the medium voltage is equal to the breakdown voltage of the drain to the source × 0.5.

[0060] Assume that the first conductivity type is N type and the second conductivity type is P type. Figure 2 The operation process of the first anti-fuse memory cell 100 and the second anti-fuse memory cell 101 is described below.

[0061] When the first anti-fuse memory cell 100 is selected to perform a write operation, a ground voltage is applied to the first common voltage line CVL1, a ground voltage or a medium voltage is applied to the first word line WL1, and a high voltage is applied to the first selection line SL1, the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage. When the first anti-fuse memory cell 100 is not selected to perform a write operation, a ground voltage is applied to the first common voltage line CVL1, a high voltage is applied to the first word line WL1, and a second bias is applied to the first selection line SL1 or electrically floating, the high voltage is greater than the second bias, and the second bias is greater than the ground voltage. When the first anti-fuse memory cell 100 is selected to perform a read operation, a high voltage is applied to the first common voltage line CVL1, a medium voltage is applied to the first word line WL1, and a second bias is applied to the first selection line SL1, the medium voltage is less than the second bias, and the high voltage is greater than the second bias. When the first anti-fuse memory cell 100 is not selected for a read operation, a high voltage is applied to the first common voltage line CVL1 , a high voltage is applied to the first word line WL1 , and the first selection line SL1 is electrically floating.

[0062] When the second anti-fuse memory cell 101 is selected to perform a write operation, a ground voltage is applied to the second common voltage line CVL2, a ground voltage or a medium voltage is applied to the second word line WL2, and a high voltage is applied to the first selection line SL1, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage. When the second anti-fuse memory cell 101 is not selected to perform a write operation, a ground voltage is applied to the second common voltage line CVL2, a high voltage is applied to the second word line WL2, and a second bias is applied to the first selection line SL1 or is electrically floating, wherein the high voltage is greater than the second bias, and the second bias is greater than the ground voltage. When the second anti-fuse memory cell 101 is selected to perform a read operation, a high voltage is applied to the second common voltage line CVL2, a medium voltage is applied to the second word line WL2, and a second bias is applied to the first selection line SL1, wherein the medium voltage is less than the second bias, and the high voltage is greater than the second bias. When the second anti-fuse memory cell 101 is not selected for a read operation, a high voltage is applied to the second common voltage line CVL2 , a high voltage is applied to the second word line WL2 , and the first selection line SL1 is electrically floating.

[0063] Based on the above operation, the common voltage line directly receives the external voltage without passing through the decoder, and is directly coupled to the anti-fuse memory cell, so that the anti-fuse memory cell performs a write action or a read action, so as to reduce the number of decoders and the overall area of ​​the small-area common voltage anti-fuse array. In the above operation, applying a medium voltage or a ground voltage to the word line will affect the current size of the component, so it will be adjusted according to different designs and situations. The selection line is biased or electrically floating according to the process characteristics. In addition, the high voltage is greater than the second bias, and the second bias is greater than the medium voltage. The high voltage is usually slightly lower than the breakdown voltage of the source to the drain. Specifically, the high voltage is equal to the breakdown voltage of the source to the drain plus the threshold voltage of the field effect transistor, and the medium voltage is equal to the breakdown voltage of the source to the drain × 0.5.

[0064] Figure 5 is a structural cross-sectional view of another embodiment of the first anti-fuse memory cell of the present invention, Figure 6 FIG. 1 is a cross-sectional view of another embodiment of the second anti-fuse memory cell of the present invention. Figure 5 and Figure 6 The first anti-fuse memory cell 100 and the second anti-fuse memory cell 101 can realize the semiconductor region 2 on a semiconductor substrate, and the remaining structures have been described above and will not be repeated here.

[0065] According to the above embodiments, the small-area common voltage anti-fuse array directly couples the common voltage lines together to reduce the number of decoders and the overall area.

[0066] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, all equivalent changes and modifications to the shape, structure, characteristics and spirit described in the scope of the claims of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A small area common voltage anti-fuse array, characterized in that: include: A plurality of parallel word lines, including a first word line and a second word line; A plurality of parallel selection lines are perpendicular to the plurality of word lines, wherein the plurality of selection lines include a first selection line; A plurality of parallel common voltage lines are perpendicular to the plurality of selection lines, and the plurality of common voltage lines are directly coupled together, wherein the plurality of common voltage lines include a first common voltage line and a second common voltage line, and the first word line and the second word line are respectively close to the first common voltage line and the second common voltage line; A plurality of anti-fuse elements, each of which is coupled to two word lines, a selection line and two common voltage lines, wherein each of the anti-fuse elements comprises: A first anti-fuse memory cell is coupled to the first word line, the first selection line and the first common voltage line; and a second anti-fuse memory cell is coupled to the second word line, the first selection line and the second common voltage line.

2. The small area common voltage anti-fuse array according to claim 1, characterized in that: The first anti-fuse memory unit cell and the second anti-fuse memory unit cell are symmetrically arranged.

3. The small area common voltage anti-fuse array according to claim 2, characterized in that: The first anti-fuse memory cell and the second anti-fuse memory cell are disposed in a semiconductor region, and the semiconductor region has a first conductivity type; The first anti-fuse memory cell comprises: a first gate dielectric block disposed on the semiconductor region and between the first word line and the semiconductor region; a first anti-fuse gate, disposed on the first gate dielectric block and coupled to the first common voltage line, wherein the first anti-fuse gate is closer to the first common voltage line than the first word line; A first ion-doped region, a second ion-doped region and a third ion-doped region are arranged in the semiconductor region, wherein the first ion-doped region, the second ion-doped region and the third ion-doped region have a second conductivity type, the second conductivity type and the first conductivity type are opposite conductivity types, the first ion-doped region and the second ion-doped region are arranged on different sides of the semiconductor region directly below the first word line, the second ion-doped region and the third ion-doped region are arranged on different sides of the semiconductor region directly below the first anti-fuse gate, and the first ion-doped region is coupled to the first selection line.

4. The small area common voltage anti-fuse array according to claim 3, characterized in that: The second anti-fuse memory cell comprises: a second gate dielectric block disposed on the semiconductor region and between the second word line and the semiconductor region; a second anti-fuse gate disposed on the second gate dielectric block and coupled to the second common voltage line, wherein the second anti-fuse gate is closer to the second common voltage line than the second word line; A fourth ion doping region, a fifth ion doping region and a sixth ion doping region are arranged in the semiconductor region, wherein the fourth ion doping region, the fifth ion doping region and the sixth ion doping region have the second conductivity type, the fourth ion doping region and the fifth ion doping region are arranged on different sides of the semiconductor region directly below the second word line, the fifth ion doping region and the sixth ion doping region are arranged on different sides of the semiconductor region directly below the second anti-fuse gate, and the fourth ion doping region is coupled to the first selection line.

5. The small area common voltage anti-fuse array according to claim 4, characterized in that: The first conductivity type is P type, and the second conductivity type is N type.

6. The small area common voltage anti-fuse array according to claim 5, characterized in that: When the first anti-fuse memory cell is selected for a write operation, a high voltage is applied to the first common voltage line, the high voltage or the medium voltage is applied to the first word line, and a ground voltage is applied to the first selection line. The high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage.

7. The small area common voltage anti-fuse array according to claim 5, characterized in that: When the first anti-fuse memory cell is not selected for writing, a high voltage is applied to the first common voltage line, a ground voltage is applied to the first word line, a bias voltage is applied to the first selection line or it is electrically floating, the high voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

8. The small area common voltage anti-fuse array according to claim 5, characterized in that: When the first anti-fuse memory cell is selected for reading, a ground voltage is applied to the first common voltage line, a medium voltage is applied to the first word line, and a bias voltage is applied to the first selection line. The medium voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

9. The small area common voltage anti-fuse array according to claim 5, characterized in that: When the first anti-fuse memory cell is not selected for a read operation, a ground voltage is applied to the first common voltage line, the ground voltage is applied to the first word line, and the first selection line is electrically floating.

10. The small area common voltage anti-fuse array according to claim 5, characterized in that: When the second anti-fuse memory cell is selected for a write operation, a high voltage is applied to the second common voltage line, the high voltage or the medium voltage is applied to the second word line, and a ground voltage is applied to the first selection line. The high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage.

11. The small area common voltage anti-fuse array according to claim 5, characterized in that: When the second anti-fuse memory cell is not selected for writing, a high voltage is applied to the second common voltage line, a ground voltage is applied to the second word line, a bias voltage is applied to the first selection line or is electrically floating, the high voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

12. The small area common voltage anti-fuse array according to claim 5, characterized in that: When the second anti-fuse memory cell is selected for reading, a ground voltage is applied to the second common voltage line, a medium voltage is applied to the second word line, a bias voltage is applied to the first selection line, the medium voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

13. The small area common voltage anti-fuse array according to claim 5, characterized in that: When the second anti-fuse memory cell is not selected for a read operation, a ground voltage is applied to the second common voltage line, the ground voltage is applied to the second word line, and the first selection line is electrically floating.

14. The small area common voltage anti-fuse array according to claim 4, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

15. The small area common voltage anti-fuse array according to claim 14, characterized in that: When the first anti-fuse memory cell is selected for a write operation, a ground voltage is applied to the first common voltage line, the ground voltage or the medium voltage is applied to the first word line, and a high voltage is applied to the first selection line, the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage.

16. The small area common voltage anti-fuse array according to claim 14, characterized in that: When the first anti-fuse memory cell is not selected for writing, a ground voltage is applied to the first common voltage line, a high voltage is applied to the first word line, a bias voltage is applied to the first selection line or it is electrically floating, the high voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

17. The small area common voltage anti-fuse array according to claim 14, characterized in that: When the first anti-fuse memory cell is selected for a read operation, a high voltage is applied to the first common voltage line, a medium voltage is applied to the first word line, a bias is applied to the first selection line, the medium voltage is less than the bias, and the high voltage is greater than the bias.

18. The small area common voltage anti-fuse array according to claim 14, characterized in that: When the first anti-fuse memory cell is not selected for a read operation, a high voltage is applied to the first common voltage line, the first word line is applied to the high voltage, and the first selection line is electrically floating.

19. The small area common voltage anti-fuse array according to claim 14, characterized in that: When the second anti-fuse memory cell is selected for a write operation, a ground voltage is applied to the second common voltage line, the ground voltage or the medium voltage is applied to the second word line, and a high voltage is applied to the first selection line, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage.

20. The small area common voltage anti-fuse array according to claim 14, characterized in that: When the second anti-fuse memory cell is not selected for writing, the second common voltage line is applied with a ground voltage, the second word line is applied with a high voltage, the first selection line is applied with a bias voltage or is electrically floating, the high voltage is greater than the bias voltage, and the bias voltage is greater than the ground voltage.

21. The small area common voltage anti-fuse array according to claim 14, characterized in that: When the second anti-fuse memory cell is selected for reading, a high voltage is applied to the second common voltage line, a medium voltage is applied to the second word line, a bias is applied to the first selection line, the medium voltage is less than the bias, and the high voltage is greater than the bias.

22. The small area common voltage anti-fuse array according to claim 14, characterized in that: When the second anti-fuse memory cell is not selected for a read operation, a high voltage is applied to the second common voltage line, the high voltage is applied to the second word line, and the first selection line is electrically floating.

23. The small area common voltage anti-fuse array according to claim 4, characterized in that: The semiconductor region is a semiconductor substrate.

24. The small area common voltage anti-fuse array according to claim 4, characterized in that: The semiconductor region is a doped well region, and the doped well region is arranged in a semiconductor substrate.

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