Silicon carbide floating junction structure with N-type thin layer and improved switching characteristic

Abstract

The invention provides a silicon carbide floating junction structure with an N-type thin layer and improved switching characteristics, and relates to the technical field of semiconductor power devices. Comprising an N-type substrate; the N-type drift region is formed on the N-type substrate; the plurality of P-type floating junctions are formed in the N-type drift region and are arranged at intervals; the N-type thin layers are formed between the P-type floating junctions and on the two sides of the P-type floating junctions, so that the N-type thin layers are in contact connection with the P-type floating junctions; the plurality of P-type doped regions are formed in the N-type drift region and are arranged at intervals, and the plurality of P-type doped regions and the plurality of P-type floating junctions are arranged up and down; the ohmic contact metal is formed on the lower surface of the N-type substrate; and the Schottky contact metal is formed on the N-type drift region and the plurality of P-type doped regions. More N-type carriers are introduced into the plurality of N-type thin layers, the barrier broadening effect at intervals of floating junctions during reverse bias is improved, disappearance of the barrier is accelerated during positive bias, overcharge voltage is not generated, and the starting speed is high when starting is carried out after turn-off.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor power devices, and in particular to a silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics. Background Art

[0002] In recent years, energy conservation, emission reduction and low-carbon development have become the mainstream development model. Semiconductor power devices are an important link in the energy generation-storage-distribution cycle, and are crucial to energy conservation, emission reduction and low-carbon development. Improving the performance of semiconductor power devices has become a feasible way to improve energy conversion efficiency. Among them, silicon carbide power semiconductor devices are expected to become the next generation of mainstream high-power devices due to their high-voltage blocking capability, high-frequency switching characteristics, and high-temperature operation, and have been widely favored by researchers. Commercial silicon carbide devices have now appeared, and these commercial silicon carbide devices are an ideal choice to replace silicon power devices. However, due to the properties of silicon carbide materials, some mature silicon power devices still cannot be prepared using silicon carbide materials for commercial use. In order to make silicon power devices prepared using silicon carbide materials for commercial use, it is necessary to combine floating junction technology with silicon carbide, which can give full play to their respective advantages and break the one-dimensional limit of silicon carbide unipolar devices.

[0003] At present, power devices that break the one-dimensional limit of silicon carbide usually use silicon carbide floating junction junction barrier Schottky diodes (JBS). However, because the floating junction of the silicon carbide floating junction JBS diode is greatly widened toward the drift region under reverse withstand voltage, when the bias voltage changes from reverse to forward, the floating junction depletion region widened under reverse bias is too wide to allow minority carriers to be quickly extracted and depleted, and the switching characteristics of the silicon carbide floating junction JBS diode are greatly affected, resulting in a low turn-on speed when it is turned on again after being turned off. Summary of the invention

[0004] The purpose of the embodiment of the present invention is to provide a silicon carbide floating junction structure with an N-type thin layer to improve the switching characteristics, so as to solve the problem of low turn-on speed when turning on again after being turned off.

[0005] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0006] A first aspect of the present invention provides a silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics, comprising:

[0007] N-type substrate;

[0008] An N-type drift region is formed on an N-type substrate;

[0009] A plurality of P-type floating junctions are formed inside the N-type drift region and arranged at intervals;

[0010] A plurality of N-type thin layers are formed between and on both sides of the plurality of P-type floating junctions, so that the plurality of N-type thin layers are in contact with and connected to the plurality of P-type floating junctions, and the upper surfaces of the plurality of N-type thin layers are in the same horizontal plane as the upper surfaces of the plurality of P-type floating junctions, and the thickness of the plurality of N-type thin layers is less than the thickness of the plurality of P-type floating junctions;

[0011] A plurality of P-type doped regions are formed inside the N-type drift region and are arranged at intervals, and the plurality of P-type doped regions and the plurality of P-type floating junctions are arranged up and down, and the upper surfaces of the plurality of P-type doped regions and the upper surface of the N-type drift region are in the same horizontal plane;

[0012] Ohmic contact metal, formed on the lower surface of the N-type substrate;

[0013] A Schottky contact metal is formed on the N-type drift region and a plurality of P-type doped regions.

[0014] In some modified embodiments of the first aspect of the present invention, the number of the multiple P-type floating junctions is 2, the multiple P-type floating junctions include a first P-type floating junction and a second P-type floating junction, the thickness of the first P-type floating junction is the same as the thickness of the second P-type floating junction, the number of the multiple N-type thin layers is 3, the multiple N-type thin layers include a first N-type thin layer, a second N-type thin layer and a third N-type thin layer, and the thickness of the first N-type thin layer, the thickness of the second N-type thin layer and the thickness of the third N-type thin layer are the same.

[0015] In some modified implementations of the first aspect of the present invention, a first N-type thin layer, a first P-type floating junction, a second N-type thin layer, a second P-type floating junction and a third N-type thin layer are adjacently arranged from left to right in the N-type drift region, and the first N-type thin layer is arranged on one side of the N-type drift region, and the third N-type thin layer is arranged on the other side of the N-type drift region.

[0016] In some modified embodiments of the first aspect of the present invention, the upper surface of the first N-type thin layer, the upper surface of the first P-type floating junction, the upper surface of the second N-type thin layer, the upper surface of the second P-type floating junction and the upper surface of the third N-type thin layer are all in the same horizontal plane, and the thickness of the first N-type thin layer, the thickness of the second N-type thin layer and the thickness of the third N-type thin layer are all smaller than the thickness of the first P-type floating junction.

[0017] In some modified embodiments of the first aspect of the present invention, the number of the multiple P-type doping regions is 2, the multiple P-type doping regions include a first P-type doping region and a second P-type doping region, and the thickness of the first P-type doping region is the same as the thickness of the second P-type doping region.

[0018] In some modified embodiments of the first aspect of the present invention, the implanted ions of the plurality of N-type thin layers are N, the implantation energy ranges from 10 KeV to 1000 KeV, and the doping concentration ranges from 5e16 to 5e17 cm -3 .

[0019] In some modified implementations of the first aspect of the present invention, the implanted ions of the multiple P-type floating junctions are Al, and the implanted ions of the multiple P-type doped regions are Al.

[0020] In some modified embodiments of the first aspect of the present invention, the material of the N-type substrate is silicon carbide.

[0021] A second aspect of the present invention provides a method for preparing a silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics, comprising:

[0022] An N-type substrate is selected, and the material of the N-type substrate is silicon carbide;

[0023] Growing a first N-type drift region on a surface of the N-type substrate;

[0024] Performing ion implantation on the surface of the first N-type drift region to form a plurality of P-type floating junctions, so that the plurality of P-type floating junctions are arranged at intervals;

[0025] Performing ion implantation on the surface of the first N-type drift region having a plurality of P-type floating junctions to form a plurality of N-type thin layers, so that the plurality of N-type thin layers are in contact with and connected to the plurality of P-type floating junctions, and the thickness of the plurality of N-type thin layers is less than the thickness of the plurality of P-type floating junctions;

[0026] Growing a second N-type drift region on the surfaces of the plurality of P-type floating junctions and the plurality of N-type thin layers;

[0027] Performing ion implantation on the surface of the second N-type drift region to form a plurality of P-type doping regions, so that the plurality of P-type doping regions are arranged at intervals;

[0028] Using magnetron sputtering or electron beam evaporation, Ni metal is deposited on the bottom of the N-type substrate, and rapid thermal annealing is performed to form an ohmic contact metal;

[0029] Metal is deposited on the surface of the second N-type drift region and the surfaces of a plurality of P-type doped regions, and Schottky contact metal is obtained by passivating the medium, performing patterning and selective etching.

[0030] In some modified embodiments of the second aspect of the present invention, the implanted ions of the plurality of N-type thin layers are N, the implantation energy range is 10 KeV-1000 KeV, and the doping concentration range is 5e16-5e17 cm -3 .

[0031] Compared with the prior art, the present invention provides a silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics, including an N-type substrate; an N-type drift region formed on the N-type substrate; a plurality of P-type floating junctions formed inside the N-type drift region and arranged at intervals; a plurality of N-type thin layers formed between and on both sides of the plurality of P-type floating junctions, so that the plurality of N-type thin layers are in contact with and connected to the plurality of P-type floating junctions, and the upper surfaces of the plurality of N-type thin layers are in the same horizontal plane as the upper surfaces of the plurality of P-type floating junctions, and the thickness of the plurality of N-type thin layers is less than the thickness of the plurality of P-type floating junctions; a plurality of P-type doped regions are formed inside the N-type drift region and arranged at intervals, and the plurality of P-type doped regions are arranged above and below the plurality of P-type floating junctions, and the upper surfaces of the plurality of P-type doped regions are in the same horizontal plane as the upper surfaces of the N-type drift region; an ohmic contact metal formed on the lower surface of the N-type substrate; and a Schottky contact metal formed on the N-type drift region and the plurality of P-type doped regions. In this way, multiple N-type thin layers are added at multiple floating junctions. The multiple N-type thin layers introduce more N-type carriers, effectively improving the barrier widening effect at the intervals between multiple floating junctions during reverse bias, accelerating the disappearance of the potential barrier during forward bias, and preventing overcharge voltage from being generated, so that the turn-on speed after being turned off is higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] By reading the detailed description below with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0033] Figure 1 A schematic diagram of a silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics is shown;

[0034] Figure 2 A diagram schematically showing the switching characteristics of a silicon carbide floating junction structure with an N-type thin layer for improving the switching characteristics;

[0035] Figure 3 A switching characteristic diagram of a silicon carbide floating junction structure without an N-type thin layer for improving switching characteristics is schematically shown;

[0036] Figure 4 The flowchart schematically shows a method for preparing a silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics.

[0037] Description of reference numerals:

[0038] 1. N-type substrate; 2. N-type drift region; 3. Multiple P-type floating junctions; 4. Multiple N-type thin layers; 5. Multiple P-type doped regions; 6. Ohmic contact metal; 7. Schottky contact metal. DETAILED DESCRIPTION

[0039] The following is a further detailed description of the embodiments of the present invention in conjunction with the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to exemplarily illustrate the principles of the present invention, but cannot be used to limit the scope of the present invention. The present invention can be implemented in many different forms and is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

[0040] A silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics in an embodiment of the present invention is described in detail below.

[0041] See also Figure 1 As shown, Figure 1 A structural diagram of a silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics is schematically shown. An embodiment of the present invention provides a silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics, including:

[0042] N-type substrate 1;

[0043] An N-type drift region 2 is formed on an N-type substrate 1;

[0044] A plurality of P-type floating junctions 3 are formed inside the N-type drift region 2 and arranged at intervals;

[0045] A plurality of N-type thin layers 4 are formed between and on both sides of the plurality of P-type floating junctions 3, so that the plurality of N-type thin layers 4 are in contact with and connected to the plurality of P-type floating junctions 3, and the upper surfaces of the plurality of N-type thin layers 4 are in the same horizontal plane as the upper surfaces of the plurality of P-type floating junctions 3, and the thickness of the plurality of N-type thin layers 4 is less than the thickness of the plurality of P-type floating junctions 3;

[0046] A plurality of P-type doping regions 5 are formed inside the N-type drift region 2 and arranged at intervals, and the plurality of P-type doping regions 5 and the plurality of P-type floating junctions 3 are arranged up and down, and the upper surfaces of the plurality of P-type doping regions 5 and the upper surface of the N-type drift region 2 are in the same horizontal plane;

[0047] Ohmic contact metal 6, formed on the lower surface of the N-type substrate 1;

[0048] The Schottky contact metal 7 is formed on the N-type drift region 2 and the plurality of P-type doping regions 5 .

[0049] Specifically, the plurality of P-type floating junctions 3 and the plurality of N-type thin layers 4 are arranged adjacent to each other in an alternating manner, and the number of the plurality of N-type thin layers 4 is one more than the number of the plurality of P-type floating junctions 3 .

[0050] Multiple P-type doped regions 5 are arranged at intervals at the top of the N-type drift region 2, the upper surfaces of the multiple P-type doped regions 5 are at the same horizontal plane as the upper surface of the N-type drift region 2, and multiple N-type thin layers 4 and multiple P-type floating junctions 3 are all arranged in the N-type drift region 2 and below the multiple P-type doped regions 5.

[0051] The ohmic contact metal 6 may be Ni metal, and the Schottky contact metal 7 may be Al, or Al doped with Si or Cu, or may be Ag or Cu. The Schottky contact metal 7 is not specifically limited.

[0052] Multiple N-type thin layers 4 are added at multiple floating junctions. Multiple N-type thin layers 4 introduce more N-type carriers. When the bias voltage is reversed, the barrier widening effect at the intervals between multiple floating junctions is effectively improved, thereby accelerating the disappearance of the barrier when the bias voltage is forward, and no overcharge voltage is generated.

[0053] In this embodiment, the number of the multiple P-type floating junctions 3 is 2, the multiple P-type floating junctions 3 include a first P-type floating junction and a second P-type floating junction, the thickness of the first P-type floating junction is the same as the thickness of the second P-type floating junction, the number of the multiple N-type thin layers 4 is 3, the multiple N-type thin layers 4 include a first N-type thin layer, a second N-type thin layer and a third N-type thin layer, the thickness of the first N-type thin layer, the thickness of the second N-type thin layer and the thickness of the third N-type thin layer are the same.

[0054] Specifically, the first P-type floating junction and the second P-type floating junction have the same type of implanted particles, the first P-type floating junction and the second P-type floating junction have the same implanted energy range, and the first P-type floating junction and the second P-type floating junction have the same doping concentration. The first N-type thin layer, the second N-type thin layer, and the third N-type thin layer have the same type of implanted particles, the first N-type thin layer, the second N-type thin layer, and the third N-type thin layer have the same implanted energy range, and the first N-type thin layer, the second N-type thin layer, and the third N-type thin layer have the same doping concentration.

[0055] In this embodiment, the material of the N-type substrate 1 is silicon carbide.

[0056] Specifically, since silicon carbide has a mature production technology and good device quality as the N-type substrate 1, silicon carbide has a high thermal conductivity and good stability, and can be used in high-temperature growth processes, silicon carbide has excellent physical and chemical properties, and can realize high-performance high-power power electronic devices, silicon carbide is selected as the material for the N-type substrate 1.

[0057] In this embodiment, a first N-type thin layer, a first P-type floating junction, a second N-type thin layer, a second P-type floating junction and a third N-type thin layer are adjacently arranged from left to right in the N-type drift region 2, and the first N-type thin layer is arranged on one side of the N-type drift region 2, and the third N-type thin layer is arranged on the other side of the N-type drift region 2.

[0058] Specifically, a first N-type thin layer is arranged in an edge region on one side inside the N-type drift region 2, a first P-type floating junction is arranged adjacent to the right side of the first N-type thin layer, a second N-type thin layer is arranged adjacent to the right side of the first P-type floating junction, a second P-type floating junction is arranged adjacent to the right side of the second N-type thin layer, a third N-type thin layer is arranged adjacent to the right side of the second P-type floating junction, and the third N-type thin layer is located in the other edge region inside the N-type drift region 2.

[0059] In this embodiment, the upper surface of the first N-type thin layer, the upper surface of the first P-type floating junction, the upper surface of the second N-type thin layer, the upper surface of the second P-type floating junction and the upper surface of the third N-type thin layer are all in the same horizontal plane, and the thickness of the first N-type thin layer, the thickness of the second N-type thin layer and the thickness of the third N-type thin layer are all smaller than the thickness of the first P-type floating junction.

[0060] Specifically, the thickness of the first N-type thin layer, the thickness of the second N-type thin layer, and the thickness of the third N-type thin layer are all smaller than the thickness of the second P-type floating junction.

[0061] In this embodiment, the number of the plurality of P-type doping regions 5 is 2, and the plurality of P-type doping regions 5 include a first P-type doping region and a second P-type doping region, and the thickness of the first P-type doping region is the same as the thickness of the second P-type doping region.

[0062] Specifically, the first P-type doping region and the second P-type doping region have the same implanted particle type, the same implanted energy range, and the same doping concentration.

[0063] In this embodiment, the implanted ions of the plurality of N-type thin layers 4 are N, the implantation energy range is 10Kev-1000Kev, and the doping concentration range is 5e16-5e17cm -3 .

[0064] Specifically, the implanted ions of the first N-type thin layer, the second N-type thin layer and the third N-type thin layer are all N, the implanted energy range is 10Kev-1000Kev, and the doping concentration range is 5e16-5e17cm -3 .

[0065] In this embodiment, the implanted ions of the plurality of P-type floating junctions 3 are Al, and the implanted ions of the plurality of P-type doping regions 5 are Al.

[0066] Specifically, the implanted ions of the first P-type floating junction and the second P-type floating junction are both Al, and the implanted particles of the first P-type doping region and the second P-type doping region are both Al.

[0067] Figure 2The switching characteristics of the silicon carbide floating junction structure with an N-type thin layer for improving the switching characteristics are schematically shown. Figure 3 The switching characteristics of the silicon carbide floating junction structure without the N-type thin layer for improving the switching characteristics are schematically shown, see Figure 2 and Figure 3 As shown, Figure 2 and Figure 3 The horizontal axis is time, in us, the vertical axis on the left is the gate input voltage of the Metal Oxide Semiconductor Field Effect Transistor (MOS), in V, the vertical axis on the right is the forward conduction voltage, in V, the red line with a triangle is the forward conduction voltage, and the black line with a square is the MOS tube control switch state. The MOS tube controls the circuit switch. When the gate input voltage is 0V, the circuit is turned on and the diode is turned on. When the MOS gate input voltage is 20V, the circuit is disconnected and the diode is turned off. After the circuit switch, the forward conduction voltage of the diode with a silicon carbide floating junction structure with an N-type thin layer to improve the switching characteristics is still 1500V, and no overcharge voltage is generated. However, after repeated switching, the forward conduction voltage of the diode with a silicon carbide floating junction structure without an N-type thin layer to improve the switching characteristics continues to increase, generating an overcharge voltage. Therefore, the diode with a silicon carbide floating junction structure with an N-type thin layer to improve the switching characteristics of the present invention improves the switching characteristics of the device.

[0068] Based on the above Figure 1 It can be seen from the implementation method that a silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics according to an embodiment of the present invention includes an N-type substrate 1; an N-type drift region 2 formed on the N-type substrate 1; a plurality of P-type floating junctions 3 formed inside the N-type drift region 2 and arranged at intervals; a plurality of N-type thin layers 4 formed between and on both sides of the plurality of P-type floating junctions 3, so that the plurality of N-type thin layers 4 are in contact with and connected to the plurality of P-type floating junctions 3, and the upper surfaces of the plurality of N-type thin layers 4 are in contact with the upper surfaces of the plurality of P-type floating junctions 3. The surface is at the same horizontal plane, and the thickness of the multiple N-type thin layers 4 is less than the thickness of the multiple P-type floating junctions 3; multiple P-type doping regions 5 are formed inside the N-type drift region 2 and arranged at intervals, and the multiple P-type doping regions 5 and the multiple P-type floating junctions 3 are arranged up and down, and the upper surfaces of the multiple P-type doping regions 5 and the upper surfaces of the N-type drift region 2 are at the same horizontal plane; the ohmic contact metal 6 is formed on the lower surface of the N-type substrate 1; the Schottky contact metal 7 is formed on the N-type drift region 2 and the multiple P-type doping regions 5. In this way, multiple N-type thin layers 4 are added to multiple floating junctions, and the multiple N-type thin layers 4 introduce more N-type carriers, which effectively improves the barrier widening effect at the intervals of multiple floating junctions during reverse bias, accelerates the disappearance of the barrier during forward bias, does not generate overcharge voltage, and makes the opening speed higher when turning on again after being turned off.

[0069] Figure 4 A flow chart schematically shows a method for preparing a silicon carbide floating junction structure with an N-type thin layer to improve switching characteristics, see Figure 4 As shown, a method for preparing a silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics may include:

[0070] S401 , selecting an N-type substrate 1 .

[0071] The material of the N-type substrate 1 is silicon carbide.

[0072] Specifically, since silicon carbide has a mature production technology and good device quality as the N-type substrate 1, silicon carbide has a high thermal conductivity and good stability, and can be used in high-temperature growth processes, silicon carbide has excellent physical and chemical properties, and can realize high-performance high-power power electronic devices, silicon carbide is selected as the material for the N-type substrate 1.

[0073] S402 , growing a first N-type drift region 2 on the surface of the N-type substrate 1 .

[0074] Specifically, the N-type substrate 1 is an N+ substrate, and the first N-type drift region 2 is grown on the surface of the N+ substrate by a chemical vapor deposition (CVD) method at a growth temperature of 1600° C.-1900° C.

[0075] S403 , performing ion implantation on the surface of the first N-type drift region 2 to form a plurality of P-type floating junctions 3 , so that the plurality of P-type floating junctions 3 are arranged at intervals.

[0076] The implanted ions of the plurality of P-type floating junctions 3 are Al.

[0077] S404. Perform ion implantation on the surface of the first N-type drift region 2 having multiple P-type floating junctions 3 to form multiple N-type thin layers 4, so that the multiple N-type thin layers 4 are in contact with and connected to the multiple P-type floating junctions 3, and the thickness of the multiple N-type thin layers 4 is smaller than the thickness of the multiple P-type floating junctions 3.

[0078] The implanted ions of the multiple N-type thin layers 4 are N, the implantation energy range is 10Kev-1000Kev, and the doping concentration range is 5e16-5e17cm -3 .

[0079] S405 , growing a second N-type drift region 2 on the surfaces of the plurality of P-type floating junctions 3 and the plurality of N-type thin layers 4 .

[0080] Specifically, the second N-type drift region 2 is grown on the surfaces of the plurality of P-type floating junctions 3 and the plurality of N-type thin layers 4 by a CVD method, and the growth temperature is 1600° C.-1900° C.

[0081] S406 , performing ion implantation on the surface of the second N-type drift region 2 to form a plurality of P-type doping regions 5 , so that the plurality of P-type doping regions 5 are arranged at intervals.

[0082] The implanted ions of the plurality of P-type doping regions 5 are Al.

[0083] S407 , depositing Ni metal on the bottom of the N-type substrate 1 by magnetron sputtering or electron beam evaporation, and performing rapid thermal annealing to form an ohmic contact metal 6 .

[0084] The ohmic contact metal 6 is a cathode metal layer.

[0085] S408, depositing metal on the surface of the second N-type drift region 2 and the surfaces of the plurality of P-type doped regions 5, and obtaining Schottky contact metal 7 by passivating the dielectric, performing patterning and selective etching.

[0086] Specifically, an anode metal layer is prepared on the surface of the second N-type drift region 2 and the surfaces of multiple P-type doped regions 5, and the metal is deposited by a deposition method to form the required anode metal, wherein the anode metal can be Al, or Al doped with Si or Cu, or Ag or Cu; and the Schottky contact metal 7 is obtained by passivating the medium, performing patterning and selective etching.

[0087] A silicon carbide floating junction structure with an N-type thin layer for improved switching characteristics in an embodiment of the present invention solves the problem of slow turn-on speed when turning on again after being turned off, making it possible to realize a high-frequency and high-voltage silicon carbide floating junction diode, which can greatly expand the application scope of silicon carbide floating junction devices in the field of future power semiconductor devices.

[0088] Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should be understood by those skilled in the art that the above embodiments may be modified or some technical features may be replaced by equivalents without departing from the scope and spirit of the present invention. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there is no structural conflict.

[0089] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics, characterized in that: The silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics comprises: N-type substrate; An N-type drift region is formed on the N-type substrate; A plurality of P-type floating junctions are formed inside the N-type drift region and arranged at intervals; A plurality of N-type thin layers are formed between and on both sides of the plurality of P-type floating junctions, so that the plurality of N-type thin layers are in contact with and connected to the plurality of P-type floating junctions, and the upper surfaces of the plurality of N-type thin layers are in the same horizontal plane as the upper surfaces of the plurality of P-type floating junctions, and the thickness of the plurality of N-type thin layers is less than the thickness of the plurality of P-type floating junctions; A plurality of P-type doped regions are formed inside the N-type drift region and are arranged at intervals, and the plurality of P-type doped regions are arranged above and below the plurality of P-type floating junctions, and the upper surfaces of the plurality of P-type doped regions and the upper surface of the N-type drift region are in the same horizontal plane; Ohmic contact metal, formed on the lower surface of the N-type substrate; A Schottky contact metal is formed on the N-type drift region and the plurality of P-type doped regions.

2. The silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics according to claim 1, characterized in that: The number of the multiple P-type floating junctions is 2, and the multiple P-type floating junctions include a first P-type floating junction and a second P-type floating junction, and the thickness of the first P-type floating junction is the same as the thickness of the second P-type floating junction. The number of the multiple N-type thin layers is 3, and the multiple N-type thin layers include a first N-type thin layer, a second N-type thin layer, and a third N-type thin layer, and the thickness of the first N-type thin layer, the thickness of the second N-type thin layer, and the thickness of the third N-type thin layer are the same.

3. The silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics according to claim 2, characterized in that: The first N-type thin layer, the first P-type floating junction, the second N-type thin layer, the second P-type floating junction and the third N-type thin layer are adjacently arranged in sequence from left to right inside the N-type drift region, and the first N-type thin layer is arranged on one side inside the N-type drift region, and the third N-type thin layer is arranged on the other side inside the N-type drift region.

4. The silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics according to claim 3, characterized in that: The upper surface of the first N-type thin layer, the upper surface of the first P-type floating junction, the upper surface of the second N-type thin layer, the upper surface of the second P-type floating junction and the upper surface of the third N-type thin layer are all in the same horizontal plane, and the thickness of the first N-type thin layer, the thickness of the second N-type thin layer and the thickness of the third N-type thin layer are all smaller than the thickness of the first P-type floating junction.

5. The silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics according to claim 1, characterized in that: The number of the plurality of P-type doping regions is 2, and the plurality of P-type doping regions include a first P-type doping region and a second P-type doping region, and the thickness of the first P-type doping region is the same as the thickness of the second P-type doping region.

6. The silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics according to claim 1, characterized in that: The implanted ions of the multiple N-type thin layers are N, the implantation energy range is 10Kev-1000Kev, and the doping concentration range is 5e16-5e17cm -3 .

7. The silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics according to claim 1, characterized in that: The implanted ions of the plurality of P-type floating junctions are Al, and the implanted ions of the plurality of P-type doped regions are Al.

8. The silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics according to claim 1, characterized in that: The material of the N-type substrate is silicon carbide.

9. A method for preparing a silicon carbide floating junction structure with an N-type thin layer to improve switching characteristics, characterized in that: The silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics according to any one of claims 1 to 8 comprises: Selecting an N-type substrate, wherein the material of the N-type substrate is silicon carbide; Growing a first N-type drift region on the surface of the N-type substrate; Performing ion implantation on the surface of the first N-type drift region to form a plurality of P-type floating junctions, so that the plurality of P-type floating junctions are arranged at intervals; Performing ion implantation on the surface of the first N-type drift region having the plurality of P-type floating junctions to form a plurality of N-type thin layers, so that the plurality of N-type thin layers are in contact with and connected to the plurality of P-type floating junctions, and the thickness of the plurality of N-type thin layers is less than the thickness of the plurality of P-type floating junctions; Growing a second N-type drift region on the surfaces of the plurality of P-type floating junctions and the plurality of N-type thin layers; Performing ion implantation on the surface of the second N-type drift region to form a plurality of P-type doping regions, so that the plurality of P-type doping regions are arranged at intervals; Depositing Ni metal on the bottom of the N-type substrate by magnetron sputtering or electron beam evaporation, and performing rapid thermal annealing to form an ohmic contact metal; Metal is deposited on the surface of the second N-type drift region and the surfaces of the plurality of P-type doped regions, and a Schottky contact metal is obtained by passivating the dielectric, performing patterning and selective etching.

10. The method for preparing a silicon carbide floating junction structure with an N-type thin layer for improving switching characteristics according to claim 9, characterized in that: The implanted ions of the multiple N-type thin layers are N, the implantation energy range is 10Kev-1000Kev, and the doping concentration range is 5e16-5e17cm -3 .

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