Full-bridge DC-DC conversion pulse width modulation signal driving circuit

Abstract

The utility model provides a full-bridge DC-DC conversion pulse width modulation signal driving circuit. The full-bridge DC-DC conversion pulse width modulation signal driving circuit comprises an input shaping driving circuit, an oscillation isolation circuit and an output driving circuit, the input shaping drive circuit is electrically connected with the oscillation isolation circuit and is used for carrying out filtering shaping on an input PWM control signal; the oscillation isolation circuit is electrically connected with the input shaping drive circuit and the output drive circuit and is used for isolating the PWM control signal; and the output driving circuit is electrically connected with the oscillation isolation circuit and is used for reducing the power loss of the main power MOS tube and improving the working efficiency of the full-bridge DC-DC conversion circuit. The input shaping drive circuit carries out filtering shaping on PWM control signals to improve the drive capability, the oscillation isolation circuit realizes undistorted synchronous isolation transmission of four paths of PWM signals to ensure that the drive circuit is safe and reliable, the output drive circuit is optimally designed to reduce the switching loss of a power MOS tube, and the output drive circuit is optimized. Therefore, the control signal quality, the isolation synchronism and the working efficiency of the full-bridge DC-DC conversion power circuit are improved, and the performance and the reliability of the whole system are effectively improved.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic circuits, in particular to a full-bridge DC-DC conversion pulse width modulation signal driving circuit. Background Art

[0002] With the rapid development of 5G mobile communications in China, the energy consumption of communication equipment loads is large and the power supply quality requirements are getting higher and higher, which puts higher and higher requirements on the output power and efficiency of the rectifier module in the communication power supply system. The full-bridge DC-DC conversion circuit is more and more commonly used in the design of rectifier modules. It replaces the half-bridge DC-DC conversion circuit design with insufficient power. It requires the four MOS tubes of the full-bridge conversion to work more safely and efficiently, which requires more reliable and efficient gate PWM control signals to participate in. The DC-DC conversion circuit is the main power circuit of the rectifier module. By improving the load driving capability of the pulse width modulation signal of the DC-DC conversion circuit of the rectifier module, and quickly discharging the reverse charge of the gate when the MOS tube is turned off, the MOS tube in the DC-DC conversion circuit is prompted to work more efficiently and stably, thereby improving the electrical performance indicators such as power and efficiency of the rectifier module.

[0003] Chinese patent CN217956948U "A PFC pulse width modulation signal control drive circuit" discloses a PFC pulse width modulation signal control drive circuit, which shapes and filters the signal through a shaping circuit, and finally improves the power and efficiency of the rectifier module. However, the circuit is designed for PFC pulse width modulation signals and cannot meet the special requirements of full-bridge DC-DC conversion circuits, resulting in excessive power consumption of the rectifier module, low output power, and low overall circuit efficiency. Utility Model Content

[0004] In view of this, the utility model proposes a full-bridge DC-DC conversion pulse width modulation signal driving circuit, which shapes and filters the PWM signal through an input shaping driving module, isolates the PWM signal through an oscillation isolation circuit, and reduces the power consumption of the main power MOS tube through an output driving circuit, thereby improving the overall efficiency of the full-bridge DC-DC conversion circuit, thereby solving the problem of excessive power consumption and low output power of the existing rectifier module.

[0005] The technical solution of the utility model is implemented as follows: a full-bridge DC-DC conversion pulse width modulation signal driving circuit, including an input shaping driving circuit, an oscillation isolation circuit and an output driving circuit;

[0006] The input shaping drive circuit is electrically connected to the oscillation isolation circuit and is used to filter and shape the input PWM control signal;

[0007] The oscillation isolation circuit is electrically connected to the input shaping drive circuit and the output drive circuit, and is used to isolate the PWM control signal;

[0008] The output drive circuit is electrically connected to the oscillation isolation circuit, and is used to reduce the power loss of the main power MOS tube and improve the working efficiency of the full-bridge DC-DC conversion circuit.

[0009] Preferably, the input shaping drive circuit includes resistors R1, R2, R3, R4, R5, R20, R21, R22, R23, R24, capacitors C1, C2, C3, C12, C13, C14, diodes D1, D2, D5, D6, and drive chips U1 and U2;

[0010] Pin 2 of the driving chip U1 is electrically connected to one end of the capacitor C2, one end of the resistor R4 and one end of the resistor R1, and the other end of the resistor R1 inputs the PWM signal 1, and the pin 3 of the driving chip U1 is electrically connected to the other end of the capacitor C2, the other end of the resistor R4, one end of the capacitor C1 and one end of the resistor R3 to the primary working ground, and the pin 4 of the driving chip U1 is electrically connected to the other end of the capacitor C1, the other end of the resistor R3 and one end of the resistor R2, and the other end of the resistor R2 inputs the PWM signal 2, and the pin 6 of the driving chip U1 is connected to one end of the capacitor C3 and the pin 3 of the diode D1 to the +12V power supply, and the other end of the capacitor C3 is connected to the primary working ground, and the pin 7 of the driving chip U1 is electrically connected to the pin 2 of the diode D1 and the pin 1 of the diode D2, and the pin 5 of the driving chip U1 is electrically connected to the pin 1 of the diode D1 and the pin 2 of the diode D2, and the pin 3 of the diode D2 is electrically connected to one end of the resistor R5, and the other end of the resistor R5 is connected to the primary working ground;

[0011] Pin 2 of the driving chip U2 is electrically connected to one end of the capacitor C13, one end of the resistor R23 and one end of the resistor R20, and the other end of the resistor R20 inputs the PWM signal 3. Pin 3 of the driving chip U2 is electrically connected to the other end of the capacitor C13, the other end of the resistor R23, one end of the capacitor C12 and one end of the resistor R22 to the primary working ground. Pin 4 of the driving chip U2 is electrically connected to the other end of the capacitor C12, the other end of the resistor R22 and one end of the resistor R21, and the other end of the resistor R21 inputs the PWM signal 4. Pin 6 of the driving chip U2 is connected to one end of the capacitor C14 and pin 3 of the diode D5 to the +12V power supply, and the other end of the capacitor C14 is connected to the primary working ground. Pin 7 of the driving chip U2 is electrically connected to pin 2 of the diode D5 and pin 1 of the diode D6. Pin 5 of the driving chip U2 is electrically connected to pin 1 of the diode D5 and pin 2 of the diode D6. Pin 3 of the diode D6 is electrically connected to one end of the resistor R24, and the other end of the resistor R24 ​​is connected to the primary working ground.

[0012] Preferably, the oscillation isolation circuit includes capacitors C4, C5, C15, C16, and transformers T1 and T2;

[0013] One end of the capacitor C4 is electrically connected to one end of the capacitor C5 and to the pin 1 of the transformer T1;

[0014] One end of the capacitor C15 is electrically connected to one end of the capacitor C16 and the pin 1 of the transformer T2.

[0015] Preferably, the other end of the capacitor C4 and the other end of the capacitor C5 are electrically connected to the pin 2 of the diode D1, the pin 1 of the diode D2 and the pin 7 of the driver chip U1, and the pin 2 of the transformer T1 is electrically connected to the pin 1 of the diode D1, the pin 2 of the diode D2 and the pin 5 of the driver chip U1;

[0016] The other end of capacitor C15 and the other end of capacitor C16 are electrically connected to pin 2 of diode D5, pin 1 of diode D6 and pin 7 of driver chip U2, and pin 2 of transformer T2 is electrically connected to pin 1 of diode D5, pin 2 of diode D6 and pin 5 of driver chip U2.

[0017] Preferably, the output drive circuit includes resistors R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, capacitors C6, C7, C8, C9, C10, C11, C17, C18, C19, C20, C21, C22, diodes D3, D4, D7, D8, Zener diodes DZ1, DZ2, DZ3, DZ4, DZ5, DZ6, DZ7, DZ8, and MOS tubes Q1, Q2, Q3, Q4;

[0018] One end of the resistor R6 is electrically connected to one end of the resistor R7 and one end of the resistor R8, the other end of the resistor R7 is electrically connected to the other end of the resistor R8, one end of the resistor R9, the negative electrode of the Zener diode DZ2, one end of the capacitor C7 and one end of the capacitor C6, the other end of the resistor R9 is electrically connected to the drain of the MOS transistor Q1, the other end of the capacitor C6 is electrically connected to the other end of the capacitor C7, the positive electrode of the Zener diode DZ2, one end of the resistor R11 and one end of the capacitor C8, the other end of the capacitor C8 is electrically connected to one end of the resistor R12, the other end of the resistor R12 is electrically connected to the other end of the resistor R11, the positive electrode of the Zener diode DZ1 and the source of the MOS transistor Q1, the negative electrode of the Zener diode DZ1 is electrically connected to the other end of the resistor R6, one end of the resistor R10 and the positive electrode of the diode D3, and the other end of the resistor R10 is electrically connected to the negative electrode of the diode D3 and the gate of the MOS transistor Q1;

[0019] One end of the resistor R13 is electrically connected to one end of the resistor R14 and one end of the resistor R15, the other end of the resistor R14 is electrically connected to the other end of the resistor R15, one end of the resistor R16, the cathode of the Zener diode DZ4, one end of the capacitor C10 and one end of the capacitor C9, the other end of the resistor R16 is electrically connected to the drain of the MOS transistor Q2, the other end of the capacitor C9 is electrically connected to the other end of the capacitor C10, the anode of the Zener diode DZ4, one end of the resistor R18 and one end of the capacitor C11, the other end of the capacitor C11 is electrically connected to one end of the resistor R19, the other end of the resistor R19 is electrically connected to the other end of the resistor R18, the anode of the Zener diode DZ3 and the source of the MOS transistor Q2, the cathode of the Zener diode DZ3 is electrically connected to the other end of the resistor R13, one end of the resistor R17 and the anode of the diode D4, and the other end of the resistor R17 is electrically connected to the cathode of the diode D4 and the gate of the MOS transistor Q2;

[0020] One end of the resistor R25 is electrically connected to one end of the resistor R26 and one end of the resistor R27, the other end of the resistor R26 is electrically connected to the other end of the resistor R27, one end of the resistor R28, the cathode of the Zener diode DZ6, one end of the capacitor C17 and one end of the capacitor C18, the other end of the resistor R28 is electrically connected to the drain of the MOS transistor Q3, the other end of the capacitor C17 is electrically connected to the other end of the capacitor C18, the anode of the Zener diode DZ6, one end of the resistor R30 and one end of the capacitor C19, the other end of the capacitor C19 is electrically connected to one end of the resistor R31, the other end of the resistor R31 is electrically connected to the other end of the resistor R30, the anode of the Zener diode DZ5 and the source of the MOS transistor Q3, the cathode of the Zener diode DZ5 is electrically connected to the other end of the resistor R25, one end of the resistor R29 and the anode of the diode D7, and the other end of the resistor R29 is electrically connected to the cathode of the diode D7 and the gate of the MOS transistor Q3;

[0021] One end of the resistor R32 is electrically connected to one end of the resistor R33 and one end of the resistor R34, the other end of the resistor R33 is electrically connected to the other end of the resistor R34, one end of the resistor R35, the cathode of the Zener diode DZ8, one end of the capacitor C20, and one end of the capacitor C21, the other end of the resistor R35 is electrically connected to the drain of the MOS transistor Q4, the other end of the capacitor C20 is electrically connected to the other end of the capacitor C21, the anode of the Zener diode DZ8, one end of the resistor R37, and one end of the capacitor C22, the other end of the capacitor C22 is electrically connected to one end of the resistor R38, the other end of the resistor R38 is electrically connected to the other end of the resistor R37, the anode of the Zener diode DZ7, and the source of the MOS transistor Q4, the cathode of the Zener diode DZ7 is electrically connected to the other end of the resistor R32, one end of the resistor R36, and the anode of the diode D8, and the other end of the resistor R36 is electrically connected to the cathode of the diode D8 and the gate of the MOS transistor Q4.

[0022] Preferably, pin 4 of transformer T1 is electrically connected to one end of resistor R6, pin 5 of transformer T1 is electrically connected to the other end of resistor R6, pin 8 of transformer T1 is electrically connected to one end of resistor R13, and pin 7 of transformer T1 is electrically connected to the other end of resistor R13;

[0023] Pin 4 of transformer T2 is electrically connected to one end of resistor R25, pin 5 of transformer T2 is electrically connected to the other end of resistor R25, pin 8 of transformer T2 is electrically connected to one end of resistor R32, and pin 7 of transformer T2 is electrically connected to the other end of resistor R32.

[0024] Preferably, the driving chips U1 and U2 use gate drivers of model 2EDN7524F.

[0025] Preferably, the diodes D1 and D5 are BAV70 diodes.

[0026] Preferably, the diodes D2 and D6 are diodes of model BAS40-06LT1.

[0027] Preferably, the Zener diodes DZ1, DZ3, DZ5, and DZ7 are voltage regulator diodes with a model number of BZG03C12, and the Zener diodes DZ2, DZ4, DZ6, and DZ8 are voltage regulator diodes with a model number of BZG05C3V3.

[0028] The full-bridge DC-DC conversion pulse width modulation signal driving circuit provided by the utility model has the following beneficial effects compared with the prior art:

[0029] (1) The PWM control signal is filtered and shaped through the input shaping drive circuit to improve the driving ability. The oscillation isolation circuit realizes the distortion-free synchronous isolation transmission of the 4-way PWM signal to ensure the safety and reliability of the driving circuit. The output drive circuit is optimized to reduce the switching loss of the power MOS tube, thereby improving the control signal quality, isolation synchronization and the working efficiency of the full-bridge DC-DC conversion power circuit, effectively improving the performance and reliability of the entire system;

[0030] (2) By using high-performance driver chips, filter circuits and diode clamp circuits, the 4-channel PWM control signals output by the microcontroller are filtered and shaped, eliminating noise and distortion, improving signal quality and load driving capability, and providing ideal high-quality PWM input signals for the subsequent oscillation isolation circuit and output drive circuit, thereby ensuring the control accuracy and stability of the entire drive circuit system.

[0031] (3) Through the resonant isolation circuit composed of capacitors and transformers, distortion-free, high-frequency, and synchronous isolation transmission of 4-way PWM control signals is achieved, ensuring the accuracy and timing consistency of the control signals, effectively improving the gate control response speed and dynamic performance of the main power MOS tube of the full-bridge DC-DC conversion circuit, and also enhancing the anti-interference ability and reliability of the system;

[0032] (4) Through the optimized design of the discharge circuit and parameter matching circuit, the gate charge of the MOS tube can be quickly charged and discharged, which shortens the turn-off falling edge time and reduces the switching loss. At the same time, the conduction characteristics and switching characteristics of the MOS are optimized, and the power conversion efficiency is improved. The targeted output drive circuit design greatly improves the performance of the full-bridge DC-DC conversion power circuit in switching, rectifying and other working conditions, thereby effectively improving the conversion efficiency and reliability of the entire system. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 This is a structural diagram of a full-bridge DC-DC conversion pulse width modulation signal driving circuit of the utility model;

[0035] Figure 2 This is a circuit wiring diagram of an input shaping drive circuit of a full-bridge DC-DC conversion pulse width modulation signal drive circuit of the utility model;

[0036] Figure 3 This is a circuit wiring diagram of an oscillation isolation circuit of a full-bridge DC-DC conversion pulse width modulation signal driving circuit of the utility model;

[0037] Figure 4 This is a circuit wiring diagram of an output drive circuit of a full-bridge DC-DC conversion pulse width modulation signal drive circuit of the utility model;

[0038] Figure 5 The utility model discloses an overall circuit wiring diagram of a full-bridge DC-DC conversion pulse width modulation signal driving circuit. DETAILED DESCRIPTION

[0039] The following will be combined with the implementation of the utility model to clearly and completely describe the technical solutions in the implementation of the utility model. Obviously, the described implementation is only a part of the implementation of the utility model, not all of the implementations. Based on the implementation of the utility model, all other implementations obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0040] Provide a full-bridge DC-DC conversion pulse width modulation signal drive circuit, such as Figure 1 As shown, it includes an input shaping drive circuit 1, an oscillation isolation circuit 2 and an output drive circuit 3;

[0041] The input shaping drive circuit 1 is electrically connected to the oscillation isolation circuit 2 and is used to filter and shape the input PWM control signal;

[0042] The oscillation isolation circuit 2 is electrically connected to the input shaping drive circuit 1 and the output drive circuit 3, and is used to isolate the PWM control signal;

[0043] The output drive circuit 3 is electrically connected to the oscillation isolation circuit 2 to reduce the power loss of the main power MOS tube and improve the working efficiency of the full-bridge DC-DC conversion circuit.

[0044] It should be noted that:

[0045] A full-bridge DC-DC conversion pulse width modulation signal driving circuit of this embodiment is composed of an input shaping driving circuit 1, an oscillation isolation circuit 2, and an output driving circuit 3.

[0046] The working process is to shape and filter the 4-channel PWM pulse width modulation control signals output by the single-chip microcomputer through the input shaping drive circuit 1 and improve the load driving capability, and then the primary and secondary signals are isolated and synchronously transmitted by the oscillation isolation circuit 2, and finally the PWM pulse width modulation signal is output to the MOS tube gate through the output drive circuit 3 to improve the fast conduction and shutdown performance, so as to control the 4 MOS tubes in the full-bridge DC-DC conversion circuit to work stably and efficiently.

[0047] The above-mentioned 4 output PWM signals have different definitions, and go to the gates of the 4 MOS tubes of the upper left bridge arm, the lower left bridge arm, the upper right bridge arm, and the lower right bridge arm of the full-bridge DC-DC conversion circuit respectively. The models and parameters of the 4 MOS tubes are the same, and the waveforms of the 4 PWM control signals are different. Therefore, although the input shaping drive circuit 1, the oscillation isolation circuit 2, and the output drive circuit 3 are all composed of two identical circuits, the input PWM control signals are different, so the two circuits are substantially different.

[0048] like Figure 2As shown, the input shaping drive circuit 1 includes resistors R1, R2, R3, R4, R5, R20, R21, R22, R23, R24, capacitors C1, C2, C3, C12, C13, C14, diodes D1, D2, D5, D6, and drive chips U1 and U2;

[0049] Pin 2 of the driving chip U1 is electrically connected to one end of the capacitor C2, one end of the resistor R4 and one end of the resistor R1, and the other end of the resistor R1 inputs the PWM signal 1, and the pin 3 of the driving chip U1 is electrically connected to the other end of the capacitor C2, the other end of the resistor R4, one end of the capacitor C1 and one end of the resistor R3 to the primary working ground, and the pin 4 of the driving chip U1 is electrically connected to the other end of the capacitor C1, the other end of the resistor R3 and one end of the resistor R2, and the other end of the resistor R2 inputs the PWM signal 2, and the pin 6 of the driving chip U1 is connected to one end of the capacitor C3 and the pin 3 of the diode D1 to the +12V power supply, and the other end of the capacitor C3 is connected to the primary working ground, and the pin 7 of the driving chip U1 is electrically connected to the pin 2 of the diode D1 and the pin 1 of the diode D2, and the pin 5 of the driving chip U1 is electrically connected to the pin 1 of the diode D1 and the pin 2 of the diode D2, and the pin 3 of the diode D2 is electrically connected to one end of the resistor R5, and the other end of the resistor R5 is connected to the primary working ground;

[0050] Pin 2 of the driving chip U2 is electrically connected to one end of the capacitor C13, one end of the resistor R23 and one end of the resistor R20, and the other end of the resistor R20 inputs the PWM signal 3. Pin 3 of the driving chip U2 is electrically connected to the other end of the capacitor C13, the other end of the resistor R23, one end of the capacitor C12 and one end of the resistor R22 to the primary working ground. Pin 4 of the driving chip U2 is electrically connected to the other end of the capacitor C12, the other end of the resistor R22 and one end of the resistor R21, and the other end of the resistor R21 inputs the PWM signal 4. Pin 6 of the driving chip U2 is connected to one end of the capacitor C14 and pin 3 of the diode D5 to the +12V power supply, and the other end of the capacitor C14 is connected to the primary working ground. Pin 7 of the driving chip U2 is electrically connected to pin 2 of the diode D5 and pin 1 of the diode D6. Pin 5 of the driving chip U2 is electrically connected to pin 1 of the diode D5 and pin 2 of the diode D6. Pin 3 of the diode D6 is electrically connected to one end of the resistor R24, and the other end of the resistor R24 ​​is connected to the primary working ground.

[0051] It should be noted that:

[0052] The input shaping driver circuit 1 uses the driver chip 2EDN7524F as the core of the circuit. It is a fast dual-channel, 5A current output gate driver optimized for driving standard MOS, super junction MOS and GaN power switch devices. The input signal is low voltage TTL and 3.3VCMOS-compatible with extremely wide voltage handling capabilities from +20V to -10VDC. The unique ability to handle -10VDC on the input pin protects the device from ground bounce. Both outputs are able to receive and provide 5A current using a true rail-to-rail output stage, ensuring extremely low impedance of 0.7Ω to the positive rail and 0.55Ω to the negative rail. Excellent channel-to-channel delay matching, typically 1ns, allows risk-free doubling of power supply and receiving capabilities to a peak of 10A by paralleling two channels. The combination of industrial standard pin output and different logic input / output configurations ensures high flexibility and shortens R&D time.

[0053] The driver chips U1 and U2 have the function of improving the gate load driving capability of the four MOS tubes in the full-bridge DC-DC conversion circuit. The resistors R1, R2, R3, R4, R20, R21, R22, R23, and the capacitors C1, C2, C12, and C13 form a four-way PWM signal input filter circuit to perform preliminary filtering on the input PWM signal. The diodes D1, D2, D5, and D6 form four clamping diode circuits to shape and clamp the PWM signal to make the waveform more standard without deformation.

[0054] like Figure 3 As shown, the oscillation isolation circuit 2 includes capacitors C4, C5, C15, C16, and transformers T1 and T2;

[0055] One end of the capacitor C4 is electrically connected to one end of the capacitor C5 and to the pin 1 of the transformer T1;

[0056] One end of the capacitor C15 is electrically connected to one end of the capacitor C16 and the pin 1 of the transformer T2.

[0057] It should be noted that:

[0058] Capacitors C4, C5, transformer T1 and capacitors C15, C16, transformer T2 respectively form a resonant isolation circuit 2, which isolates the primary and secondary resonances of the four-channel PWM signals to achieve a function of distortion-free synchronous transmission.

[0059] like Figure 4As shown, the output drive circuit 3 includes resistors R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, capacitors C6, C7, C8, C9, C10, C11, C17, C18, C19, C20, C21, C22, diodes D3, D4, D7, D8, Zener diodes DZ1, DZ2, DZ3, DZ4, DZ5, DZ6, DZ7, DZ8, and MOS tubes Q1, Q2, Q3, Q4;

[0060] One end of the resistor R6 is electrically connected to one end of the resistor R7 and one end of the resistor R8, the other end of the resistor R7 is electrically connected to the other end of the resistor R8, one end of the resistor R9, the negative electrode of the Zener diode DZ2, one end of the capacitor C7 and one end of the capacitor C6, the other end of the resistor R9 is electrically connected to the drain of the MOS transistor Q1, the other end of the capacitor C6 is electrically connected to the other end of the capacitor C7, the positive electrode of the Zener diode DZ2, one end of the resistor R11 and one end of the capacitor C8, the other end of the capacitor C8 is electrically connected to one end of the resistor R12, the other end of the resistor R12 is electrically connected to the other end of the resistor R11, the positive electrode of the Zener diode DZ1 and the source of the MOS transistor Q1, the negative electrode of the Zener diode DZ1 is electrically connected to the other end of the resistor R6, one end of the resistor R10 and the positive electrode of the diode D3, and the other end of the resistor R10 is electrically connected to the negative electrode of the diode D3 and the gate of the MOS transistor Q1;

[0061] One end of the resistor R13 is electrically connected to one end of the resistor R14 and one end of the resistor R15, the other end of the resistor R14 is electrically connected to the other end of the resistor R15, one end of the resistor R16, the cathode of the Zener diode DZ4, one end of the capacitor C10 and one end of the capacitor C9, the other end of the resistor R16 is electrically connected to the drain of the MOS transistor Q2, the other end of the capacitor C9 is electrically connected to the other end of the capacitor C10, the anode of the Zener diode DZ4, one end of the resistor R18 and one end of the capacitor C11, the other end of the capacitor C11 is electrically connected to one end of the resistor R19, the other end of the resistor R19 is electrically connected to the other end of the resistor R18, the anode of the Zener diode DZ3 and the source of the MOS transistor Q2, the cathode of the Zener diode DZ3 is electrically connected to the other end of the resistor R13, one end of the resistor R17 and the anode of the diode D4, and the other end of the resistor R17 is electrically connected to the cathode of the diode D4 and the gate of the MOS transistor Q2;

[0062] One end of the resistor R25 is electrically connected to one end of the resistor R26 and one end of the resistor R27, the other end of the resistor R26 is electrically connected to the other end of the resistor R27, one end of the resistor R28, the cathode of the Zener diode DZ6, one end of the capacitor C17 and one end of the capacitor C18, the other end of the resistor R28 is electrically connected to the drain of the MOS transistor Q3, the other end of the capacitor C17 is electrically connected to the other end of the capacitor C18, the anode of the Zener diode DZ6, one end of the resistor R30 and one end of the capacitor C19, the other end of the capacitor C19 is electrically connected to one end of the resistor R31, the other end of the resistor R31 is electrically connected to the other end of the resistor R30, the anode of the Zener diode DZ5 and the source of the MOS transistor Q3, the cathode of the Zener diode DZ5 is electrically connected to the other end of the resistor R25, one end of the resistor R29 and the anode of the diode D7, and the other end of the resistor R29 is electrically connected to the cathode of the diode D7 and the gate of the MOS transistor Q3;

[0063] One end of the resistor R32 is electrically connected to one end of the resistor R33 and one end of the resistor R34, the other end of the resistor R33 is electrically connected to the other end of the resistor R34, one end of the resistor R35, the cathode of the Zener diode DZ8, one end of the capacitor C20, and one end of the capacitor C21, the other end of the resistor R35 is electrically connected to the drain of the MOS transistor Q4, the other end of the capacitor C20 is electrically connected to the other end of the capacitor C21, the anode of the Zener diode DZ8, one end of the resistor R37, and one end of the capacitor C22, the other end of the capacitor C22 is electrically connected to one end of the resistor R38, the other end of the resistor R38 is electrically connected to the other end of the resistor R37, the anode of the Zener diode DZ7, and the source of the MOS transistor Q4, the cathode of the Zener diode DZ7 is electrically connected to the other end of the resistor R32, one end of the resistor R36, and the anode of the diode D8, and the other end of the resistor R36 is electrically connected to the cathode of the diode D8 and the gate of the MOS transistor Q4.

[0064] It should be noted that:

[0065] The working principle of the output drive circuit 3 is that R9, R10, R16, R17, R28, R29, R35, R36, diodes D3, D4, D7, D8, Zener diodes DZ1, DZ3, DZ5, DZ7, MOS tubes Q1, Q2, Q3, Q4 form a discharge circuit. When the main power MOS tube is turned off, the gate charge of the MOS tube is quickly discharged, and the shutdown is more sufficient and fast, thereby reducing the internal loss of the main power MOS tube. The circuit composed of other components makes the parameters of the drive circuit match the performance indicators such as the forward switching time and input impedance of the main power MOS tube, so as to achieve a more efficient switching working state of the MOS tube and improve the working efficiency of the full-bridge DC-DC conversion power circuit of the rectifier module.

[0066] like Figure 5, which is an overall circuit wiring diagram of a full-bridge DC-DC conversion pulse width modulation signal driving circuit of this embodiment, from which it can be seen that the connection relationship between the oscillation isolation circuit 2 and the input shaping driving circuit 1 and the output driving circuit 3;

[0067] The other end of capacitor C4 and the other end of capacitor C5 are electrically connected to pin 2 of diode D1, pin 1 of diode D2 and pin 7 of driver chip U1, and pin 2 of transformer T1 is electrically connected to pin 1 of diode D1, pin 2 of diode D2 and pin 5 of driver chip U1;

[0068] The other end of capacitor C15 and the other end of capacitor C16 are electrically connected to pin 2 of diode D5, pin 1 of diode D6 and pin 7 of driver chip U2, and pin 2 of transformer T2 is electrically connected to pin 1 of diode D5, pin 2 of diode D6 and pin 5 of driver chip U2.

[0069] Pin 4 of the transformer T1 is electrically connected to one end of the resistor R6, pin 5 of the transformer T1 is electrically connected to the other end of the resistor R6, pin 8 of the transformer T1 is electrically connected to one end of the resistor R13, and pin 7 of the transformer T1 is electrically connected to the other end of the resistor R13;

[0070] Pin 4 of transformer T2 is electrically connected to one end of resistor R25, pin 5 of transformer T2 is electrically connected to the other end of resistor R25, pin 8 of transformer T2 is electrically connected to one end of resistor R32, and pin 7 of transformer T2 is electrically connected to the other end of resistor R32.

[0071] The driving chips U1 and U2 use gate drivers of model 2EDN7524F.

[0072] The diodes D1 and D5 are BAV70 diodes.

[0073] The diodes D2 and D6 are BAS40-06LT1 diodes.

[0074] The Zener diodes DZ1, DZ3, DZ5, and DZ7 are voltage regulator diodes with a model number of BZG03C12, and the Zener diodes DZ2, DZ4, DZ6, and DZ8 are voltage regulator diodes with a model number of BZG05C3V3.

[0075] It should be noted that:

[0076] The PWM pulse width modulation control signal output by the single chip is filtered and shaped by the input shaping drive circuit 1, and the clutter is removed to make the PWM signal waveform cleaner and smoother. After the diode clamping, the waveform is more standard without deformation, and the performance of the power MOS tube gate drive signal is improved.

[0077] The driver chip 2EDN7524F is used as the core of the input drive circuit. It is a fast dual-channel, 5A current output gate driver optimized for driving MOS and GaN power switch devices. The dual-channel drive circuit based on the 2EDN7524F chip can more effectively improve the gate load drive capability of the main power MOS tube.

[0078] The oscillation isolation circuit 2 is isolated by signal resonance, and the PWM control signal is transmitted synchronously and without distortion. Moreover, the PWM signal isolation of the primary and secondary circuits does not affect each other's performance, thereby achieving a safe and reliable effect of the PWM signal driving circuit.

[0079] The MOS tube fast discharge circuit is adopted. When the main power MOS tube is cut off, the gate charge of the MOS tube is quickly discharged, and the MOS tube is turned off more fully to achieve an efficient switching state, thereby reducing the power consumption of the main power circuit of the module and improving work efficiency.

[0080] The entire circuit is simple and efficient, primary and secondary resonance isolation is independent, stable and distortion-free, PWM signal filtering, shaping, clamping and standard transmission, strong output load driving performance, and MOS tube efficient switching performance.

[0081] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A full-bridge DC-DC conversion pulse width modulation signal driving circuit, characterized in that: It comprises an input shaping drive circuit (1), an oscillation isolation circuit (2) and an output drive circuit (3); The input shaping drive circuit (1) is electrically connected to the oscillation isolation circuit (2) and is used to filter and shape the input PWM control signal; The oscillation isolation circuit (2) is electrically connected to the input shaping drive circuit (1) and the output drive circuit (3) and is used to isolate the PWM control signal; The output drive circuit (3) is electrically connected to the oscillation isolation circuit (2) and is used to reduce the power loss of the main power MOS tube and improve the working efficiency of the full-bridge DC-DC conversion circuit.

2. A full-bridge DC-DC conversion pulse width modulation signal driving circuit as claimed in claim 1, characterized in that: The input shaping drive circuit (1) comprises resistors R1, R2, R3, R4, R5, R20, R21, R22, R23, R24, capacitors C1, C2, C3, C12, C13, C14, diodes D1, D2, D5, D6, and drive chips U1, U2; Pin 2 of the driving chip U1 is electrically connected to one end of the capacitor C2, one end of the resistor R4 and one end of the resistor R1, and the other end of the resistor R1 inputs the PWM signal 1, and the pin 3 of the driving chip U1 is electrically connected to the other end of the capacitor C2, the other end of the resistor R4, one end of the capacitor C1 and one end of the resistor R3 to the primary working ground, and the pin 4 of the driving chip U1 is electrically connected to the other end of the capacitor C1, the other end of the resistor R3 and one end of the resistor R2, and the other end of the resistor R2 inputs the PWM signal 2, and the pin 6 of the driving chip U1 is connected to one end of the capacitor C3 and the pin 3 of the diode D1 to the +12V power supply, and the other end of the capacitor C3 is connected to the primary working ground, and the pin 7 of the driving chip U1 is electrically connected to the pin 2 of the diode D1 and the pin 1 of the diode D2, and the pin 5 of the driving chip U1 is electrically connected to the pin 1 of the diode D1 and the pin 2 of the diode D2, and the pin 3 of the diode D2 is electrically connected to one end of the resistor R5, and the other end of the resistor R5 is connected to the primary working ground; Pin 2 of the driving chip U2 is electrically connected to one end of the capacitor C13, one end of the resistor R23 and one end of the resistor R20, and the other end of the resistor R20 inputs the PWM signal 3. Pin 3 of the driving chip U2 is electrically connected to the other end of the capacitor C13, the other end of the resistor R23, one end of the capacitor C12 and one end of the resistor R22 to the primary working ground. Pin 4 of the driving chip U2 is electrically connected to the other end of the capacitor C12, the other end of the resistor R22 and one end of the resistor R21, and the other end of the resistor R21 inputs the PWM signal 4. Pin 6 of the driving chip U2 is connected to one end of the capacitor C14 and pin 3 of the diode D5 to the +12V power supply, and the other end of the capacitor C14 is connected to the primary working ground. Pin 7 of the driving chip U2 is electrically connected to pin 2 of the diode D5 and pin 1 of the diode D6. Pin 5 of the driving chip U2 is electrically connected to pin 1 of the diode D5 and pin 2 of the diode D6. Pin 3 of the diode D6 is electrically connected to one end of the resistor R24, and the other end of the resistor R24 ​​is connected to the primary working ground.

3. A full-bridge DC-DC conversion pulse width modulation signal driving circuit as claimed in claim 2, characterized in that: The oscillation isolation circuit (2) comprises capacitors C4, C5, C15, C16, and transformers T1 and T2; One end of the capacitor C4 is electrically connected to one end of the capacitor C5 and to the pin 1 of the transformer T1; One end of the capacitor C15 is electrically connected to one end of the capacitor C16 and the pin 1 of the transformer T2.

4. A full-bridge DC-DC conversion pulse width modulation signal driving circuit as claimed in claim 3, characterized in that: The other end of capacitor C4 and the other end of capacitor C5 are electrically connected to pin 2 of diode D1, pin 1 of diode D2 and pin 7 of driver chip U1, and pin 2 of transformer T1 is electrically connected to pin 1 of diode D1, pin 2 of diode D2 and pin 5 of driver chip U1; The other end of capacitor C15 and the other end of capacitor C16 are electrically connected to pin 2 of diode D5, pin 1 of diode D6 and pin 7 of driver chip U2, and pin 2 of transformer T2 is electrically connected to pin 1 of diode D5, pin 2 of diode D6 and pin 5 of driver chip U2.

5. A full-bridge DC-DC conversion pulse width modulation signal driving circuit as claimed in claim 4, characterized in that: The output drive circuit (3) comprises resistors R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, capacitors C6, C7, C8, C9, C10, C11, C17, C18, C19, C20, C21, C22, diodes D3, D4, D7, D8, Zener diodes DZ1, DZ2, DZ3, DZ4, DZ5, DZ6, DZ7, DZ8, and MOS tubes Q1, Q2, Q3, Q4; One end of the resistor R6 is electrically connected to one end of the resistor R7 and one end of the resistor R8, the other end of the resistor R7 is electrically connected to the other end of the resistor R8, one end of the resistor R9, the negative electrode of the Zener diode DZ2, one end of the capacitor C7 and one end of the capacitor C6, the other end of the resistor R9 is electrically connected to the drain of the MOS transistor Q1, the other end of the capacitor C6 is electrically connected to the other end of the capacitor C7, the positive electrode of the Zener diode DZ2, one end of the resistor R11 and one end of the capacitor C8, the other end of the capacitor C8 is electrically connected to one end of the resistor R12, the other end of the resistor R12 is electrically connected to the other end of the resistor R11, the positive electrode of the Zener diode DZ1 and the source of the MOS transistor Q1, the negative electrode of the Zener diode DZ1 is electrically connected to the other end of the resistor R6, one end of the resistor R10 and the positive electrode of the diode D3, and the other end of the resistor R10 is electrically connected to the negative electrode of the diode D3 and the gate of the MOS transistor Q1; One end of the resistor R13 is electrically connected to one end of the resistor R14 and one end of the resistor R15, the other end of the resistor R14 is electrically connected to the other end of the resistor R15, one end of the resistor R16, the cathode of the Zener diode DZ4, one end of the capacitor C10 and one end of the capacitor C9, the other end of the resistor R16 is electrically connected to the drain of the MOS transistor Q2, the other end of the capacitor C9 is electrically connected to the other end of the capacitor C10, the anode of the Zener diode DZ4, one end of the resistor R18 and one end of the capacitor C11, the other end of the capacitor C11 is electrically connected to one end of the resistor R19, the other end of the resistor R19 is electrically connected to the other end of the resistor R18, the anode of the Zener diode DZ3 and the source of the MOS transistor Q2, the cathode of the Zener diode DZ3 is electrically connected to the other end of the resistor R13, one end of the resistor R17 and the anode of the diode D4, and the other end of the resistor R17 is electrically connected to the cathode of the diode D4 and the gate of the MOS transistor Q2; One end of the resistor R25 is electrically connected to one end of the resistor R26 and one end of the resistor R27, the other end of the resistor R26 is electrically connected to the other end of the resistor R27, one end of the resistor R28, the cathode of the Zener diode DZ6, one end of the capacitor C17 and one end of the capacitor C18, the other end of the resistor R28 is electrically connected to the drain of the MOS transistor Q3, the other end of the capacitor C17 is electrically connected to the other end of the capacitor C18, the anode of the Zener diode DZ6, one end of the resistor R30 and one end of the capacitor C19, the other end of the capacitor C19 is electrically connected to one end of the resistor R31, the other end of the resistor R31 is electrically connected to the other end of the resistor R30, the anode of the Zener diode DZ5 and the source of the MOS transistor Q3, the cathode of the Zener diode DZ5 is electrically connected to the other end of the resistor R25, one end of the resistor R29 and the anode of the diode D7, and the other end of the resistor R29 is electrically connected to the cathode of the diode D7 and the gate of the MOS transistor Q3; One end of the resistor R32 is electrically connected to one end of the resistor R33 and one end of the resistor R34, the other end of the resistor R33 is electrically connected to the other end of the resistor R34, one end of the resistor R35, the cathode of the Zener diode DZ8, one end of the capacitor C20, and one end of the capacitor C21, the other end of the resistor R35 is electrically connected to the drain of the MOS transistor Q4, the other end of the capacitor C20 is electrically connected to the other end of the capacitor C21, the anode of the Zener diode DZ8, one end of the resistor R37, and one end of the capacitor C22, the other end of the capacitor C22 is electrically connected to one end of the resistor R38, the other end of the resistor R38 is electrically connected to the other end of the resistor R37, the anode of the Zener diode DZ7, and the source of the MOS transistor Q4, the cathode of the Zener diode DZ7 is electrically connected to the other end of the resistor R32, one end of the resistor R36, and the anode of the diode D8, and the other end of the resistor R36 is electrically connected to the cathode of the diode D8 and the gate of the MOS transistor Q4.

6. A full-bridge DC-DC conversion pulse width modulation signal driving circuit as claimed in claim 5, characterized in that: Pin 4 of the transformer T1 is electrically connected to one end of the resistor R6, pin 5 of the transformer T1 is electrically connected to the other end of the resistor R6, pin 8 of the transformer T1 is electrically connected to one end of the resistor R13, and pin 7 of the transformer T1 is electrically connected to the other end of the resistor R13; Pin 4 of transformer T2 is electrically connected to one end of resistor R25, pin 5 of transformer T2 is electrically connected to the other end of resistor R25, pin 8 of transformer T2 is electrically connected to one end of resistor R32, and pin 7 of transformer T2 is electrically connected to the other end of resistor R32.

7. A full-bridge DC-DC conversion pulse width modulation signal driving circuit as claimed in claim 6, characterized in that: The driving chips U1 and U2 use gate drivers of model 2EDN7524F.

8. A full-bridge DC-DC conversion pulse width modulation signal driving circuit as claimed in claim 6, characterized in that: The diodes D1 and D5 are BAV70 diodes.

9. A full-bridge DC-DC conversion pulse width modulation signal driving circuit as claimed in claim 6, characterized in that: The diodes D2 and D6 are BAS40-06LT1 diodes.

10. A full-bridge DC-DC conversion pulse width modulation signal driving circuit as claimed in claim 6, characterized in that: The Zener diodes DZ1, DZ3, DZ5, and DZ7 are voltage regulator diodes with a model number of BZG03C12, and the Zener diodes DZ2, DZ4, DZ6, and DZ8 are voltage regulator diodes with a model number of BZG05C3V3.

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