Manufacturing method of semiconductor device
By forming alternately stacked sacrificial layers and channel layers on the semiconductor substrate, and isolating germanium atoms through selective etching and dielectric filling layers, the problem of germanium diffusion pollution is solved, and the working performance and yield of semiconductor devices are improved.
Patent Information
- Application Number
- CN202411155409.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-21
- Publication Date
- 2025-01-07
AI Technical Summary
Germanium atoms diffuse during high-temperature treatment, contaminating subsequent process flow and affecting the working performance of semiconductor devices, limiting the yield and performance improvement of semiconductor devices.
An alternately stacked sacrificial layers and channel layers are formed on the semiconductor substrate, wherein at least one layer contains germanium and the sacrificial layer is removed after selective etching by the mask structure, a dielectric fill layer is formed to isolate the diffusion of germanium atoms and to remove the medium by removing the medium The edges of the fill layer form an inner wall, ensuring that germanium cannot diffuse to other areas.
Effectively prevent the diffusion of germanium atoms, improve the formation quality of the channel layer and carrier mobility, improve the working performance and yield of semiconductor devices, and expand the process window.
Smart Images
Figure CN119277802A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Art
[0002] The gate stack included in the ring-gate transistor is not only formed on the top and sidewalls of the channel, but also formed at the bottom of the channel. Therefore, compared with planar transistors and fin field effect transistors, the ring-gate transistor has advantages such as higher gate control capability. Based on this, when the transistor included in the semiconductor device adopts the ring-gate transistor, the working performance of the semiconductor device can be improved. In addition, in the actual manufacturing process, the material of at least one of the sacrificial layer and the channel layer may contain germanium to at least achieve selective release of the channel layer.
[0003] However, germanium atoms diffuse to other areas during high-temperature processing, thereby contaminating subsequent front-end process flows or being extremely detrimental to the formation of high-quality source / drain regions and other structures, limiting the improvement of the working performance of semiconductor devices. Summary of the invention
[0004] The object of the present invention is to provide a method for manufacturing a semiconductor device, so as to improve the yield and working performance of the semiconductor device.
[0005] In order to achieve the above-mentioned object, the present invention provides a method for manufacturing a semiconductor device, which comprises: first, forming a fin-shaped structure on a semiconductor substrate; the fin-shaped structure comprises a sacrificial layer and a channel layer alternately stacked along the thickness direction of the semiconductor substrate; the film layer at the bottom of the alternately stacked sacrificial layer and the channel layer is a sacrificial layer; and the material of at least one of the channel layer and the sacrificial layer contains germanium. Next, forming a mask structure spanning the periphery of a portion of the fin-shaped structure; and selectively etching the fin-shaped structure under the protection of the mask structure. Next, removing each remaining sacrificial layer to form a first filling space. Next, forming a dielectric filling layer in the first filling space; and removing the edge portions of both sides of the dielectric filling layer along the length direction of the fin-shaped structure to form a second filling space. Next, forming an inner sidewall in the second filling space; the material of the inner sidewall is different from the material of the dielectric filling layer. Next, forming a source region and a drain region on both sides of each remaining channel layer, respectively. Next, removing at least part of the mask structure, and removing each remaining dielectric filling layer.
[0006] In the case of adopting the above technical solution, the fin-shaped structure formed on the semiconductor substrate includes a sacrificial layer and a channel layer alternately stacked. Moreover, the material of at least one of the sacrificial layer and the channel layer contains germanium. Among them, when the sacrificial layer contains germanium, and the channel layer does not contain germanium or has a low germanium content, the material difference between the sacrificial layer and the channel layer can be increased, which is conducive to the selective release of the channel layer and improves the formation quality of the channel layer. When the channel layer contains germanium, and the sacrificial layer does not contain germanium or has a low germanium content, it can not only facilitate the selective release of the channel layer, but also improve the carrier mobility of the channel layer, which is conducive to improving the conduction characteristics of the channel layer. In the above case, after forming the mask structure and selectively etching the fin-shaped structure, each remaining sacrificial layer is completely removed, and at this time, each remaining channel layer is suspended above the semiconductor substrate. Then, after the dielectric filling layer is formed in the first filling space, the dielectric filling layer is filled between the adjacent channel layers, and between the bottom channel layer and the semiconductor substrate. Even if the source and drain epitaxy, doping and activation operations are subsequently performed under a higher temperature environment, the germanium in the removed sacrificial layer cannot diffuse into the channel layer to improve the morphology and interface state of the channel layer; and / or, the germanium in the channel layer cannot diffuse into the removed sacrificial layer, so as not to contaminate the subsequent front-end process flow. At the same time, performing source and drain epitaxy, doping and activation operations at a higher temperature is extremely beneficial to the formation of high-quality source / drain regions, further increasing the process window, thereby improving the working performance of semiconductor devices.
[0007] Secondly, compared with the prior art in which a second filling space for filling the inner side wall is obtained by etching a portion of the sacrificial layer of semiconductor material, the manufacturing method provided by the present invention forms a second filling space for filling the inner side wall by removing the edge portions of both sides of the dielectric filling layer. Since the etching selectivity between the dielectric filling layer and the channel layer is greater, the etching process is easier to control, further suppressing the etchant from causing damage to the channel layer. Moreover, when removing the remaining dielectric filling layer to release each remaining channel layer, the etchant that etches the dielectric filling layer can also reduce the damage to the channel layer, reducing the difficulty of selective release while ensuring that the channel layer has a higher quality, further improving the yield and working performance of the semiconductor device.
[0008] In one example, the material of the channel layer or the sacrificial layer includes one of silicon, silicon germanium, and germanium. Furthermore, when the materials of the sacrificial layer and the channel layer both contain germanium, the germanium content in the sacrificial layer is different from the germanium content in the channel layer.
[0009] In one example, the germanium content in the sacrificial layer is greater than the germanium content in the channel layer.
[0010] In an example, the material of the dielectric filling layer includes SiO2 and / or SiOC.
[0011] In one example, the material of the inner sidewall includes at least one of SiN, SiON, SiOCN, SiCN, SiBN and BN.
[0012] In one example, the mask structure includes a sacrificial gate and a gate sidewall. The gate sidewall is at least arranged on both sides of the sacrificial gate along its own length direction. In the above case, removing at least part of the mask structure includes: removing the sacrificial gate.
[0013] In one example, after forming source regions and drain regions on both sides of each remaining channel layer respectively and removing at least a portion of the mask structure, the method for manufacturing a semiconductor device further includes: performing high temperature annealing on the source regions and the drain regions.
[0014] In one example, the temperature of the high temperature annealing treatment is greater than or equal to 950° C. and less than or equal to 1050° C.
[0015] In one example, a wet etching process is used to remove each remaining sacrificial layer.
[0016] In one example, after removing each remaining dielectric filling layer, the method for manufacturing a semiconductor device further includes: forming a gate stack structure surrounding the periphery of each remaining channel layer.
[0017] In one example, after forming a source region and a drain region on both sides of each remaining channel layer, and before removing at least part of the mask structure, the method for manufacturing a semiconductor device further includes: forming an interlayer dielectric layer covering the semiconductor substrate; the top of the interlayer dielectric layer is flush with the top of the mask structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:
[0019] Figure 1 A flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;
[0020] Figure 2 A schematic diagram of the structure of a semiconductor device formed in an embodiment of the present invention during the manufacturing process Figure 1 ;
[0021] Figure 3 A schematic diagram of the structure of a semiconductor device formed in an embodiment of the present invention during the manufacturing process Figure 2 ;
[0022] Figure 4 A schematic diagram of the structure of a semiconductor device formed in an embodiment of the present invention during the manufacturing process Figure 3 ;
[0023] Figure 5 A schematic diagram of the structure of a semiconductor device formed in an embodiment of the present invention during the manufacturing process Figure 4 ;
[0024] Figure 6 A schematic diagram of the structure of a semiconductor device formed in an embodiment of the present invention during the manufacturing process Figure 5 ;
[0025] Figure 7 A schematic diagram of the structure of a semiconductor device formed in an embodiment of the present invention during the manufacturing process Figure 6 ;
[0026] Figure 8 A schematic diagram of the structure of a semiconductor device formed in an embodiment of the present invention during the manufacturing process Figure 7 ;
[0027] Fig. 9 A schematic diagram of the structure of a semiconductor device formed in an embodiment of the present invention during the manufacturing process Figure 8 ;
[0028] Fig.10 A schematic diagram of the structure of a semiconductor device formed in an embodiment of the present invention during the manufacturing process Figure 9 ;
[0029] Fig.11 A schematic diagram of the structure of a semiconductor device formed in an embodiment of the present invention during the manufacturing process Figure 10 ;
[0030] Fig.12 A schematic diagram of the structure of a semiconductor device formed in an embodiment of the present invention during the manufacturing process Figure 10 one;
[0031] Fig.13 A schematic diagram of the structure of a semiconductor device formed in an embodiment of the present invention during the manufacturing process Figure 10 two;
[0032] Fig.14 A schematic diagram of the structure of a semiconductor device formed in an embodiment of the present invention during the manufacturing process Figure 10 three;
[0033] Fig.15 A schematic diagram of the structure of a semiconductor device formed in an embodiment of the present invention during the manufacturing process Figure 10 Four;
[0034] Fig.16 A schematic diagram of the structure of a semiconductor device formed in an embodiment of the present invention during the manufacturing process Figure 10 five;
[0035] Fig.17A schematic diagram of the structure of a semiconductor device formed in an embodiment of the present invention during the manufacturing process Figure 10 six;
[0036] Fig.18 A schematic diagram of the structure of a semiconductor device formed in an embodiment of the present invention during the manufacturing process Figure 10 seven;
[0037] Fig.19 A schematic diagram of the structure of a semiconductor device formed in an embodiment of the present invention during the manufacturing process Figure 10 eight;
[0038] Fig. 20 A schematic diagram of the structure of a semiconductor device formed in an embodiment of the present invention during the manufacturing process Figure 10 Nine.
[0039] Figure numerals: 11 is a semiconductor substrate, 12 is a fin structure, 13 is a sacrificial layer, 14 is a channel layer, 15 is a shallow trench isolation structure, 16 is a mask structure, 17 is a sacrificial gate, 18 is a gate sidewall, 19 is a first filling space, 20 is a dielectric filling layer, 21 is a second filling space, 22 is an inner sidewall, 23 is a source region, 24 is a drain region, 25 is an interlayer dielectric layer, and 26 is a gate stack structure. DETAILED DESCRIPTION
[0040] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.
[0041] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.
[0042] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0043] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.
[0044] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0045] The gate stack included in the ring-gate transistor is not only formed on the top and sidewalls of the channel, but also formed at the bottom of the channel. Therefore, compared with the planar transistor and the fin field effect transistor, the ring-gate transistor has advantages such as higher gate control capability. Based on this, when the transistor included in the semiconductor device adopts the ring-gate transistor, the working performance of the semiconductor device can be improved.
[0046] In the actual manufacture of semiconductor devices including ring-gate transistors, alternating sacrificial layers and channel layers are usually formed on a semiconductor substrate. Among them, the material of at least one of the sacrificial layer and the channel layer may contain germanium. For example: the material of the channel layer is silicon, and the material of the sacrificial layer is germanium silicon or germanium. At this time, the materials of the channel layer and the sacrificial layer are different, so as to achieve the selective release of the channel layer after removing the sacrificial gate. For another example: the material of the channel layer is germanium silicon or germanium, and the material of the sacrificial layer is silicon. At this time, the channel layer contains germanium elements, so that it has a higher carrier mobility, which is beneficial to improve the working performance of the semiconductor device. In the above case, because the material of at least one of the sacrificial layer and the channel layer contains germanium, and because Ge atoms diffuse to other areas during high-temperature treatment, the selective release of the channel layer is affected, and the working performance of the semiconductor device is affected. Based on this, the existing semiconductor devices usually use annealing treatment at about 850°C or lower temperature when manufacturing shallow trench isolation structures to prevent the obvious diffusion of germanium, which will pollute the subsequent front-end process flow. However, in the subsequent manufacturing processes such as source / drain epitaxy, source / drain doping and activation, they are still restricted by thermal planning, which is extremely unfavorable for forming high-quality source / drain regions and improving the working performance of semiconductor devices.
[0047] In order to solve the above technical problems, an embodiment of the present invention provides a method for manufacturing a semiconductor device. In the method for manufacturing a semiconductor device provided by an embodiment of the present invention, after forming a mask structure and selectively etching the fin-shaped structure, each remaining sacrificial layer is completely removed, and at this time, each remaining channel layer is suspended above the semiconductor substrate. Then, after a dielectric filling layer is formed in the first filling space, the dielectric filling layer is filled between adjacent channel layers, and between the bottom channel layer and the semiconductor substrate. Even if source and drain epitaxy, doping, activation and other operations are subsequently performed under a higher temperature environment, the germanium in the removed sacrificial layer cannot diffuse into the channel layer, and / or the germanium in the channel layer cannot diffuse into the removed sacrificial layer.
[0048] like Figure 1 As shown, an embodiment of the present invention provides a method for manufacturing a semiconductor device. Figures 2 to 20 The manufacturing process is described in the perspective view or cross-sectional view of the operation shown. Specifically, the manufacturing method of the semiconductor device includes the following steps:
[0049] First, if Figure 2 As shown, a fin structure 12 is formed on a semiconductor substrate 11; the fin structure 12 includes a sacrificial layer 13 and a channel layer 14 alternately stacked along the thickness direction of the semiconductor substrate 11; the film layer located at the bottom layer among the alternately stacked sacrificial layers 13 and channel layers 14 is the sacrificial layer 13; and the material of at least one of the channel layer 14 and the sacrificial layer 13 contains germanium.
[0050] In actual application, the specific structure of the semiconductor substrate can be set according to the actual application scenario, and is not specifically limited here. Figure 2 As shown, the semiconductor substrate 11 may be a semiconductor substrate such as a silicon substrate, a silicon germanium substrate or a germanium substrate on which no structure is formed. Alternatively, the semiconductor substrate may also be a semiconductor substrate on which some structures are formed. For example, when the semiconductor device in the embodiment of the present invention is a semiconductor device of the second layer or higher layer in an integrated circuit, the semiconductor substrate includes a semiconductor structure located below the semiconductor device, etc.
[0051] As for the fin structure formed on the semiconductor substrate, from a structural point of view, the sacrificial layer and the channel layer that are alternately stacked in the fin structure are located at the bottom layer as the sacrificial layer; the film layer located at the top layer can be a sacrificial layer or a channel layer. The number of layers of the sacrificial layer and the channel layer included in the fin structure can be determined according to the number of layers of the nanostructure formed based on the channel layer included in the semiconductor device in the actual application scenario, and is not specifically limited here.
[0052] From the material aspect, whether the sacrificial layer and the channel layer contain germanium can be determined according to actual needs and the conductivity types of the source region and the drain region included in the semiconductor device, and is not specifically limited here.
[0053] For example, when the conductivity type of the source region and the drain region is P-type, the channel layer may contain germanium to improve the mobility of carriers in the nanostructure formed based on the channel layer and improve the electrical performance of the semiconductor device. For another example, when the conductivity type of the source region and the drain region is N-type, the material of the channel layer may not contain germanium or have a low germanium content to prevent poor interface states.
[0054] Specifically, only one of the sacrificial layer and the channel layer may contain germanium, or both the sacrificial layer and the channel layer may contain germanium. It is understandable that when both the sacrificial layer and the channel layer contain germanium, the germanium content in the sacrificial layer is different from the germanium content in the channel layer. In addition, when both the sacrificial layer and the channel layer contain germanium, the germanium content in the sacrificial layer may be greater than the germanium content in the channel layer; or the germanium content in the channel layer may be greater than the germanium content in the sacrificial layer.
[0055] The specific types of materials of the sacrificial layer and the channel layer can be determined according to actual application scenarios. For example, the material of the channel layer or the sacrificial layer includes one of silicon, silicon germanium, and germanium.
[0056] In the actual manufacturing process, a sacrificial layer and a channel layer that are alternately stacked can be formed on the semiconductor substrate along the thickness direction of the semiconductor substrate by using processes such as epitaxial growth. Then, processes such as photolithography and etching can be used to selectively etch the alternately stacked sacrificial layers and channel layers, as well as part of the semiconductor substrate. Then, as Figure 2 As shown, a shallow trench isolation structure 15 can be formed on the semiconductor substrate 11 by at least deposition and etching processes. The fin structure 12 is exposed outside the shallow trench isolation structure 15 .
[0057] Next, if Figures 3 to 5 As shown, a mask structure 16 is formed across the periphery of a portion of the fin-shaped structure 12. Specifically, the embodiment of the present invention does not specifically limit the structure and material of the mask structure 16, as long as it can play a mask protection role in subsequent operations.
[0058] For example, the mask structure may include only a sacrificial gate, and the material of the sacrificial gate may include polysilicon or the like. Figure 4 and Figure 5 As shown, the mask structure 16 may include a sacrificial gate 17 and a gate spacer 18. The gate spacer 18 is at least arranged on both sides of the sacrificial gate 17 along its own length direction. The material of the gate spacer 18 may include insulating materials such as silicon oxide, silicon nitride or silicon oxynitride.
[0059] In the actual manufacturing process, the mask structure including the sacrificial gate and the gate sidewall is used as an example for explanation: Figure 3 As shown, deposition and etching processes can be used to form a sacrificial gate 17 across the fin structure 12. Then, as shown in FIG. Figure 4 and Figure 5 As shown, a deposition process is used to form a sidewall material covering the formed structure, and then an etching process is used to etch the sidewall material. Since the sidewall material arranged on the sidewall of the sacrificial gate 17 is deposited with a large thickness along the thickness direction of the semiconductor substrate 11, after the etching process, the remaining gate material forms the gate sidewall 18.
[0060] Next, if Figure 6 and Figure 7 As shown, the fin structure 12 is selectively etched by dry etching or wet etching under the protection of the mask structure 16. At this time, both sides of the remaining sacrificial layer 13 and the channel layer 14 along the length direction are exposed.
[0061] Next, if Figure 8 and Fig. 9 As shown, each remaining sacrificial layer is removed to form a first filling space 19 .
[0062] It is understandable that if Figure 8 and Fig. 9 As shown, the operation step is to remove all parts of each remaining sacrificial layer along the length direction, and at this time, each remaining channel layer 14 is suspended above the semiconductor substrate 11. In this case, a wet etching process can be used to remove each remaining sacrificial layer. At this time, the etching selectivity of the etching solution to the sacrificial layer and the channel layer 14 is relatively large, which can improve the formation quality of the channel layer 14, and solve the problem that the dry etching process with relatively low etching selectivity is used in the prior art to retain part of the sacrificial layer, resulting in the exposed edge parts of the channel layer 14 on both sides being easily affected by the etching gas, and further improve the yield of the semiconductor device.
[0063] Next, if Fig.10 and Fig.11 As shown, a dielectric filling layer 20 may be formed in the first filling space by using processes such as deposition and etching.
[0064] The material of the dielectric filling layer may include any dielectric material that is easy to remove, such as SiO2 and / or SiOC.
[0065] Next, if Fig.12 and Fig.13 As shown, a process such as wet etching can be used to remove the edge portions of both sides of the dielectric filling layer 20 along the length direction of the fin structure 12 to form a second filling space 21 .
[0066] Next, if Fig.14 and Fig.15 As shown, deposition and etching processes may be used to form inner sidewalls 22 in the second filling space 21 ; the material of the inner sidewalls 22 is different from the material of the dielectric filling layer 20 .
[0067] The material of the inner sidewall may include any dielectric material different from the material of the dielectric filling layer, such as SiN, SiON, SiOCN, SiCN, SiBN and BN, so as to achieve selective removal of the dielectric filling layer when releasing each remaining channel layer.
[0068] Next, if Fig.16 As shown, epitaxy or other processes may be used to form source regions 23 and drain regions 24 on both sides of each remaining channel layer 14. The source regions 23 and drain regions 24 may be made of any semiconductor material such as silicon, silicon germanium or germanium.
[0069] Exemplarily, after forming the source region and the drain region on both sides of each remaining channel layer, and after removing at least part of the mask structure, the method for manufacturing the semiconductor device may further include: performing high temperature annealing on the source region and the drain region to facilitate the formation of high-quality source region and drain region. As for the specific temperature of the above-mentioned high temperature annealing treatment, it can be set according to actual needs. For example: the temperature of the above-mentioned high temperature annealing treatment can be greater than or equal to 950°C and less than or equal to 1050°C. At this time, the temperature of the high temperature annealing treatment can be compatible with mature silicon-based processes, which is beneficial to increase the doping concentration of the source region and the drain region, and can improve the compatibility between the manufacturing method provided by the embodiment of the present invention and the existing mature silicon-based processes, which is beneficial to improve the yield and working performance of the manufactured semiconductor device.
[0070] Of course, in the actual manufacturing process, the source region and the drain region may also be annealed at a relatively low temperature.
[0071] Next, if Fig.17 As shown, deposition and planarization processes can be used to form an interlayer dielectric layer 25 on the semiconductor substrate 11. The top of the interlayer dielectric layer 25 is flush with the top of the mask structure 16, so that the source region 23 and the drain region 24 are protected by the interlayer dielectric layer 25 in subsequent etching and cleaning operations, thereby improving the yield of the semiconductor device. Of course, in the actual manufacturing process, if the source region 23 and the drain region 24 have a high etching selectivity with the material of at least a portion of the mask structure 16 that needs to be removed later, it is also possible not to form the interlayer dielectric layer 25.
[0072] Next, if Fig.18 and Fig.19 As shown, at least a portion of the mask structure is removed, and each remaining dielectric filling layer 20 is removed.
[0073] Specifically, the portion of the mask structure that needs to be removed can be determined according to its specific structure. For example, when the mask structure only includes a sacrificial gate, the mask structure needs to be completely removed. Another example is when the mask structure includes a sacrificial gate and a gate sidewall, only the mask structure is removed, that is, the sacrificial gate is removed. Then, a process such as wet etching can be used to remove each remaining dielectric filling layer to release each remaining channel layer.
[0074] Next, if Fig. 20As shown, a process such as atomic layer deposition can be used to form a gate stack structure 26 surrounding the periphery of each remaining channel layer 14. The gate stack structure 26 can have at least a gate dielectric layer surrounding the periphery of each remaining channel layer 14, and a gate located on the gate dielectric layer. The material of the gate dielectric layer included in the gate stack structure 26 can include any insulating material such as HfO2, ZrO2, TiO2 or Al2O3. The material of the above-mentioned gate can include any conductive material such as TiN, TaN or TiSiN.
[0075] It should be noted that after removing each remaining dielectric filling layer and before forming the gate stack structure, other operations may be performed on each remaining channel layer. For example: thinning each remaining channel layer, and epitaxially growing a film layer of other semiconductor materials on the periphery of each remaining channel layer after the thinning process. At this time, the gate dielectric layer surrounds the periphery of the film layer of other semiconductor materials mentioned above. Of course, as described above, a gate stack structure surrounding the periphery of each remaining channel layer may be directly formed.
[0076] When the above technical solution is adopted, Figures 2 to 20 As shown, the fin-shaped structure 12 formed on the semiconductor substrate 11 includes a sacrificial layer 13 and a channel layer 14 alternately stacked. Moreover, the material of at least one of the sacrificial layer 13 and the channel layer 14 contains germanium. Among them, when the sacrificial layer 13 contains germanium, and the channel layer 14 does not contain germanium or has a low germanium content, the material difference between the sacrificial layer 13 and the channel layer 14 can be increased, which is conducive to the selective release of the channel layer 14 and improves the formation quality of the channel layer 14. When the channel layer 14 contains germanium, and the sacrificial layer 13 does not contain germanium or has a low germanium content, it is not only conducive to the selective release of the channel layer 14, but also can improve the carrier mobility of the channel layer 14, which is conducive to improving the conduction characteristics of the channel layer 14. In the above case, after the mask structure 16 is formed and the fin-shaped structure 12 is selectively etched, each remaining layer of the sacrificial layer 13 is completely removed, and at this time, each remaining layer of the channel layer 14 is suspended above the semiconductor substrate 11. Then, after the dielectric filling layer 20 is formed in the first filling space 19, the dielectric filling layer 20 is filled between the adjacent channel layers 14, and between the bottom channel layer 14 and the semiconductor substrate 11. Even if the source and drain epitaxy, doping and activation operations are subsequently performed under a higher temperature environment, the germanium in the removed sacrificial layer 13 cannot diffuse into the channel layer 14, so as to improve the morphology and interface state of the channel layer 14; and / or, the germanium in the channel layer 14 cannot diffuse into the removed sacrificial layer 13, so as not to contaminate the subsequent front-end process flow. At the same time, performing source and drain epitaxy, doping and activation operations at a higher temperature is extremely beneficial to the formation of high-quality source regions 23 / drain regions 24, further increasing the process window, thereby improving the working performance of semiconductor devices.
[0077] Secondly, compared with the prior art in which the second filling space 21 for filling the inner sidewall 22 is obtained by etching a portion of the sacrificial layer 13 of semiconductor material, the manufacturing method provided by the present invention forms the second filling space 21 for filling the inner sidewall 22 by removing the edge portions of both sides of the dielectric filling layer 20. Since the etching selectivity between the dielectric filling layer 20 and the channel layer 14 is greater, the etching process is easier to control, further suppressing the etchant from causing damage to the channel layer 14. Moreover, when removing the remaining dielectric filling layer 20 to release each remaining channel layer 14, the etchant for etching the dielectric filling layer 20 can also reduce the damage to the channel layer 14, reducing the difficulty of selective release while ensuring that the channel layer 14 has a higher quality, further improving the yield and working performance of the semiconductor device.
[0078] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.
[0079] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: include: forming a fin structure on a semiconductor substrate; The fin structure comprises sacrificial layers and channel layers alternately stacked in a thickness direction of the semiconductor substrate; the film layer at the bottom of the alternately stacked sacrificial layers and channel layers is the sacrificial layer; the material of at least one of the channel layer and the sacrificial layer contains germanium; forming a mask structure spanning a portion of the periphery of the fin-shaped structure; and selectively etching the fin-shaped structure under the protection of the mask structure; removing each remaining sacrificial layer to form a first filling space; forming a dielectric filling layer in the first filling space; and removing edge portions of both sides of the dielectric filling layer along the length direction of the fin-shaped structure to form a second filling space; forming an inner side wall in the second filling space; the material of the inner side wall is different from the material of the dielectric filling layer; forming a source region and a drain region on both sides of each of the remaining channel layers; At least a portion of the mask structure is removed, and each remaining dielectric filling layer is removed.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the channel layer or the sacrificial layer includes one of silicon, silicon germanium, and germanium; In the case that the materials of the sacrificial layer and the channel layer both contain germanium, the germanium content in the sacrificial layer is different from the germanium content in the channel layer.
3. The method for manufacturing a semiconductor device according to claim 2, wherein: The germanium content in the sacrificial layer is greater than the germanium content in the channel layer.
4. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the dielectric filling layer includes SiO2 and / or SiOC; And / or, the material of the inner sidewall includes at least one of SiN, SiON, SiOCN, SiCN, SiBN and BN.
5. The method for manufacturing a semiconductor device according to claim 1, wherein: The mask structure includes a sacrificial gate and a gate sidewall; the gate sidewall is at least arranged on both sides of the sacrificial gate along its own length direction; The removing at least a portion of the mask structure comprises: removing the sacrificial gate.
6. The method for manufacturing a semiconductor device according to claim 1, wherein: After forming the source region and the drain region on both sides of each remaining channel layer, and removing at least a portion of the mask structure, the method for manufacturing the semiconductor device further includes: The source region and the drain region are subjected to high temperature annealing treatment.
7. The method for manufacturing a semiconductor device according to claim 6, wherein: The temperature of the high temperature annealing treatment is greater than or equal to 950° C. and less than or equal to 1050° C.
8. The method for manufacturing a semiconductor device according to claim 1, wherein: A wet etching process is adopted to remove each remaining sacrificial layer.
9. The method for manufacturing a semiconductor device according to claim 1, wherein: After forming the source region and the drain region on both sides of each remaining channel layer, and before removing at least part of the mask structure, the method for manufacturing the semiconductor device further includes: An interlayer dielectric layer is formed covering the semiconductor substrate; the top of the interlayer dielectric layer is flush with the top of the mask structure.
10. The method for manufacturing a semiconductor device according to any one of claims 1 to 9, characterized in that: After removing each remaining dielectric filling layer, the method for manufacturing the semiconductor device further includes: A gate stack structure is formed around the periphery of each remaining channel layer.