Testing system and method and chip testing equipment

Abstract

The embodiment of the invention discloses a test system and method and chip test equipment. The test system comprises a task flow scheduling module, a plurality of distribution modules and a plurality of test execution modules, the task flow scheduling module is used for splitting and sorting test tasks to obtain a plurality of sub-task flow sequences; the distribution module is used for splitting and sorting the test items in the plurality of sub-task flow sequences to obtain a plurality of test item sequences; and the test execution module is used for controlling the chip test equipment to execute each test item in the plurality of test item sequences so as to perform parallel test on the to-be-tested device to obtain a test result. Therefore, the execution mode of the test task is automatically converted into the parallel execution mode, and the situation that the chip test equipment cannot test the test device due to parallel test item determination errors and test code modification errors caused by manual adjustment to the parallel execution mode is avoided.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a testing system, method and chip testing equipment. Background Art

[0002] During the chip testing process, the chip testing equipment will create a test project based on the business unit of the chip to be tested or the wafer to be tested. The test project includes multiple test items in series according to the test order, and each test item is used to implement the test of a business unit of the chip to be tested or the wafer to be tested. The chip testing equipment executes each test item in the test project in a serial execution manner to obtain the test results of the chip to be tested or the wafer to be tested. However, when executing the test project in a serial execution manner, it is necessary to wait for the previous test item to be completed before the next test item can be started. This makes some of the test resources of the chip testing equipment idle, so that the test resources of the chip testing equipment are not fully and reasonably utilized, resulting in low chip testing efficiency.

[0003] In the process of implementing the present application, it was found through research that in the related art, in order to improve the chip testing efficiency, the execution mode of the test project is usually modified from serial execution to parallel execution. The currently commonly used method of modifying the serial execution mode to the parallel execution mode is that the technical developers determine the test items that need to be executed in parallel, and then modify the test code corresponding to the test project so that the chip testing equipment can execute the test items in the test project in parallel. However, due to the manual modification of the corresponding test code, it is easy to have problems such as test code modification errors, which makes the chip testing equipment unable to test the chip to be tested or the wafer to be tested. Summary of the invention

[0004] In order to solve the above technical problems, the embodiments of the present application provide a testing system, method and chip testing equipment.

[0005] In one aspect of an embodiment of the present application, a test system is provided, which is applied to a chip test device, and the system includes: a task flow scheduling module, multiple allocation modules and multiple test execution modules; the task flow scheduling module is used to split and sort the test task when receiving a test task for a device to be tested, obtain multiple sub-task flow sequences, and allocate the multiple sub-task flow sequences to at least one allocation module among the multiple allocation modules, each of the multiple sub-task flow sequences includes at least one sub-task flow, and each of the at least one sub-task flow includes at least one test item; the at least one allocation module is used to split and sort the test items in the multiple sub-task flow sequences when receiving the multiple sub-task flow sequences, obtain multiple test item sequences, and allocate the multiple test item sequences to the multiple test execution modules, each of the multiple test item sequences includes multiple test items; for the multiple test execution modules, the test execution module is used to control the chip test device to execute each test item in the multiple test item sequences, so as to perform parallel testing on the device to be tested and obtain a test result.

[0006] Another aspect of an embodiment of the present application provides a chip testing device, which includes the above-mentioned testing system.

[0007] Another aspect of the embodiments of the present application provides a testing method, which is applied to a chip testing device, and the method includes: when receiving a test task for a device to be tested, splitting and sorting the test task to obtain multiple sub-task flow sequences, each of the multiple sub-task flow sequences includes at least one sub-task flow, and each of the at least one sub-task flow includes at least one test item; splitting and sorting the test items in the multiple sub-task flow sequences to obtain multiple test item sequences, each of the multiple test item sequences includes multiple test items; controlling the chip testing device to execute each test item in the multiple test item sequences to perform parallel testing on the device to be tested to obtain a test result.

[0008] In another aspect of an embodiment of the present application, an electronic device is provided, comprising: a memory for storing a computer program; a processor for executing the computer program stored in the memory, and when the computer program is executed, the above-mentioned test method is implemented.

[0009] In another aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned test method is implemented.

[0010] In another aspect of the embodiments of the present application, a computer program product is provided, including computer program instructions, which implement a testing method when the computer program instructions are executed by a processor.

[0011] The test system, method and chip test device in the embodiment of the present application. The test system includes: a task flow scheduling module, multiple allocation modules and multiple test execution modules. The test system can be applied to chip test equipment. The task flow scheduling module is used to split and sort the test tasks when receiving the test tasks for the device to be tested, obtain multiple sub-task flow sequences, and allocate the multiple sub-task flow sequences to at least one allocation module, and at least one allocation module is used to split and sort the test items in the multiple sub-task flow sequences when receiving the multiple sub-task flow sequences, obtain multiple test item sequences, and allocate the multiple test item sequences to multiple test execution modules respectively; each test execution module is used to control the chip test equipment to execute each test item in the corresponding test item sequence, so as to perform parallel testing on the device to be tested and obtain test results. In an embodiment of the present application, a task flow scheduling module and an allocation module are used to split and sort the test tasks to obtain multiple test item sequences, and multiple test execution modules are used to control the chip test equipment to execute the multiple test item sequences in parallel, thereby realizing automatic conversion of the execution mode of the test task into a parallel execution mode, avoiding the parallel test item determination errors caused by manual adjustment to the parallel execution mode. At the same time, since the test system generates multiple test item sequences that can be run in parallel, and multiple test execution modules are used to control the chip test equipment to execute the multiple test item sequences in parallel, there is no need to modify the corresponding code of the test task, thereby reducing the difficulty of generating a parallel execution mode for the test task, and avoiding the situation where the chip test equipment cannot test the test device due to test code modification errors.

[0012] The technical solution of the present application is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application.

[0014] The present application can be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0015] Figure 1 is a structural schematic diagram of a test system provided by an exemplary embodiment of the present application;

[0016] Figure 2 is a structural schematic diagram of a test system provided by another exemplary embodiment of the present application;

[0017] Figure 3is a schematic diagram of a test system processing a test task provided by an application example of the present application;

[0018] Figure 4 is a schematic diagram of a chip testing device provided by an exemplary embodiment of the present application;

[0019] Figure 5 is a flow chart of a testing method provided by an exemplary embodiment of the present application;

[0020] Figure 6 The figure is a schematic diagram of the structure of an application embodiment of the electronic device disclosed in the present invention. DETAILED DESCRIPTION

[0021] Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present application.

[0022] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present application are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0023] It should also be understood that in the embodiments of the present application, "plurality" may refer to two or more than two, and "at least one" may refer to one, two or more than two.

[0024] It should also be understood that any component, data or structure mentioned in the embodiments of the present application can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0025] In addition, the term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this application generally indicates that the associated objects before and after are in an "or" relationship.

[0026] It should also be understood that the description of the various embodiments in this application focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0027] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0028] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present application, its application, or uses.

[0029] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0030] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0031] The embodiments of the present application can be applied to electronic devices such as terminal devices, computer systems, servers, etc., which can operate with many other general or special computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, servers, etc. include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, small computer systems, large computer systems, and distributed cloud computing technology environments including any of the above systems, etc.

[0032] Electronic devices such as terminal devices, computer systems, servers, etc. can be described in the general context of computer system executable instructions (such as program modules) executed by computer systems. Generally, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in a distributed cloud computing environment, where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media including storage devices.

[0033] In the process of implementing this application, it is found through research that when the execution mode of the test project is modified to a parallel execution mode, it is usually necessary for technical developers to determine the test items to be executed in parallel, and specify the start node and execution waiting node of the parallel test execution, and then use the data interface provided by the chip test equipment to manually modify the test code corresponding to the test project, so that the chip test equipment can execute the test items in the test project in parallel. However, due to the manual modification of the test code, and the test project usually includes a large number of test items, the dependency relationship between the test items is complex, which leads to problems such as test code modification errors, so that the chip test equipment cannot test the chip to be tested or the wafer to be tested.

[0034] Figure 1 is a schematic diagram of the structure of a test system provided by an exemplary embodiment of the present application. This embodiment can be applied to chip test equipment, such as Figure 1 As shown, the test system includes: a task flow scheduling module 100 , a plurality of allocation modules 110 and a plurality of test execution modules 120 .

[0035] The task flow scheduling module 100 is used to split and sort the test tasks when receiving the test tasks for the device to be tested, obtain multiple subtask flow sequences, and allocate the multiple subtask flow sequences to at least one allocation module 110 among the multiple allocation modules 110.

[0036] Among them, the chip testing equipment is used to test the function and / or performance of the chip. Exemplarily, the chip testing equipment can be an integrated circuit automatic tester (Automatic Test Equipment, ATE), and the test system can be deployed in the host computer of the chip testing equipment. The device to be tested can be a device tested by the chip testing equipment. For example, the device to be tested can include at least one of the following: a chip, a wafer, an integrated circuit, etc. The test task is used to represent the test content and / or test process of the performance, function, quality, etc. of the device to be tested.

[0037] Each subtask flow sequence in the plurality of subtask flow sequences includes at least one subtask flow (Sub Flow), and each subtask flow in at least one subtask flow includes at least one test item (Test Instance). Each test item corresponds to at least one business unit of the device to be tested, and the test item includes a test process for at least one business unit. Each business unit represents the smallest unit that implements a function of the device to be tested. Exemplarily, when the device to be tested is a chip, a test item may be a test process for the Bluetooth function (business unit) or the timing function (business unit) of the chip. The test process in the test item may include: initialization, setting test parameters, inputting chip excitation, detecting chip response output, and finally outputting test results. Among them, the input chip excitation and the output chip response may include: digital signals, analog signals or wireless signals, etc.

[0038] In one embodiment, the test task may include at least one subtask flow. The task flow scheduling module 100 may sort and combine the subtask flows in the test task according to the test order of the subtask flows in the test task to obtain a subtask flow sequence, and each subtask flow sequence may include the same number of subtask flows; or, the task flow scheduling module 100 may sort and combine the subtask flows in the test task according to the numbering and test order of the subtask flows to obtain a subtask flow sequence, for example, a test item sequence may be composed of odd-numbered subtask flows, and another test item sequence may be composed of even-numbered subtask flows. The task flow scheduling module 100 may evenly distribute multiple subtask flow sequences to each allocation module 110, or, according to the preset weight of the allocation module 110, distribute multiple subtask flow sequences to each allocation module 110.

[0039] At least one allocation module 110 is used to split and sort the test items in the multiple subtask flow sequences when receiving multiple subtask flow sequences to obtain multiple test item sequences, and allocate the multiple test item sequences to multiple test execution modules 120 respectively.

[0040] Each of the multiple test item sequences includes multiple test items, and the test items in the test item sequence are sorted according to a test order.

[0041] In a specific implementation, the allocation module 110 can receive the subtask flow sequence sent by the task flow scheduling module 100, and split and sort the subtask flow sequence according to the test order of the test items, the test duration and test information of the test items, etc., to obtain a test item sequence.

[0042] As for the multiple test execution modules 120, the test execution modules 120 are used to control the chip test equipment to execute each test item in the multiple test item sequences, so as to perform parallel tests on the devices to be tested and obtain test results.

[0043] Among them, each test execution module 120 receives a test item sequence and sorts the test item sequence, for example, sorts the test item sequence according to the order in which the test items are received, calls the relevant hardware and software of the chip test device through the User Application Programming Interface (User API) provided by the chip test device driver, and executes each test item in the test item sequence to test the device to be tested. Multiple test execution modules 120 execute the test item sequences they receive in parallel to realize the parallel execution of test tasks. The test execution module 120 can also control the display of the test results on the host computer of the chip test device.

[0044] In the embodiment of the present application, the task flow scheduling module 100 and the allocation module 110 are used to split and sort the test tasks to obtain multiple test item sequences, and multiple test execution modules 120 are used to control the chip test equipment to execute multiple test item sequences in parallel, thereby realizing the automatic conversion of the execution mode of the test task to the parallel execution mode, avoiding the situation where the parallel test item determination error is caused by manual adjustment to the parallel execution mode. At the same time, because the test system generates multiple test item sequences that can be executed in parallel, and multiple test execution modules 120 control the chip test equipment to execute multiple test item sequences in parallel, it is no longer necessary to modify the code corresponding to the test task, thereby reducing the difficulty of generating the parallel execution mode of the test task, and avoiding the situation where the chip test equipment cannot test the test device due to the test code modification error.

[0045] In some optional implementations, in the embodiments of the present application, the test task includes a main task flow for the device to be tested, and the main task flow includes at least one sub-task flow and / or at least one test item.

[0046] The main task flow (Main Flow) is used to represent the test content and test process of the device to be tested. In one embodiment, the test task may include a main task flow, and the main task flow may include at least one subtask flow and / or at least one test item executed in series according to the test sequence.

[0047] Accordingly, in the embodiment of the present application, the task flow scheduling module 100 can split and sort the test tasks in the following manner:

[0048] When the main task flow includes multiple subtask flows and multiple test items, a new subtask flow is constructed from the multiple test items, and the new subtask flow and the multiple subtask flows are split and sorted to obtain multiple subtask flow sequences.

[0049] Among them, the task flow scheduling module 100 can sort and combine multiple test items in the main task flow according to the test order of the test items to obtain new sub-task flows, and sort and split and combine the new sub-task flows and multiple sub-task flows in the main task flow to obtain multiple sub-task flow sequences.

[0050] When the main task flow includes multiple subtask flows, the multiple subtask flows are split and sorted to obtain multiple subtask flow sequences.

[0051] The task flow scheduling module 100 can directly split and sort and combine multiple sub-task flows in the main task flow to obtain multiple sub-task flow sequences.

[0052] When the main task flow includes multiple test items, multiple sub-task flows are constructed from the multiple test items, and the multiple sub-task flows are split and sorted to obtain multiple sub-task flow sequences.

[0053] Among them, the task flow scheduling module 100 can sort the multiple test items in the main task flow according to the test order of the test items, and then construct the sorted multiple test items into a preset number of sub-task flows, and then split and sort the preset number of sub-task flows to obtain multiple sub-task flow sequences.

[0054] In an embodiment of the present application, when the main task flow includes sub-task flows, sub-task flows and test items, or test items, corresponding splitting and sorting methods are performed, which improves the flexibility of splitting and sorting test tasks and improves the efficiency of obtaining sub-task flow sequences.

[0055] In some optional implementations, in the implementation of the present application, the test task includes: the test duration of each test item in the test task, the test order of each test item, the test resources used by each test item and the test order of each subtask flow.

[0056] The test resources used by the test item are used to represent the hardware resources and / or software resources on the chip test equipment used by the test item during the test process. Exemplarily, the test resources used by the test item may include at least one of the following: the corresponding hardware of the analog signal (Analog), the relevant hardware of the digital signal (Digital), the relevant hardware of the radio frequency (RF), and the relevant software for testing, etc. in the chip test equipment.

[0057] Accordingly, in the embodiment of the present application, the task flow scheduling module 100 can split and sort the test tasks in the following manner:

[0058] The test task is split into a first preset number of subtask flow sequences according to at least one of the test duration of each test item, the test order of each test item, the test resources used by each test item, and the test order of each subtask flow.

[0059] The first preset number may be set according to test requirements. For example, the first preset number may be the number of allocation modules 110 or the number of test execution modules 120 .

[0060] In one embodiment, the task flow scheduling module 100 can split multiple subtask flows in the test task into a first preset number of subtask flow sequences based on the test duration of each test item in the test task. Specifically, for each subtask flow in the test task, the sum of the test durations of each test item in the subtask flow can be used as the test duration of the subtask flow, and then the multiple subtask flows can be evenly divided into a first preset number of subtask flow sequences according to the test duration of the subtask flow, and the sum of the test durations of each subtask flow in the subtask flow sequence can be used as the test duration of the subtask flow sequence, and the test durations of each subtask flow sequence are equal. It should be noted that in the embodiment of the present application, numerical values ​​within the preset value difference can be used as equal numerical values.

[0061] In an embodiment of the present application, by efficiently and accurately splitting and sorting the test tasks according to at least one of the test duration, test sequence, test usage resources of each test item, and the test sequence of each sub-task flow, the efficiency of obtaining the sub-task flow sequence is improved.

[0062] In some optional implementations, in the implementation of the present application, each allocation module 110 in the plurality of allocation modules 110 corresponds to at least one test execution module 120 .

[0063] Each allocation module 110 corresponds to one or more test execution modules 120 . Exemplarily, each allocation module 110 may correspond to multiple test execution modules 120 .

[0064] Correspondingly, in an embodiment of the present application, at least one allocation module 110 is specifically used to split and sort the multiple sub-task flow sequences when receiving multiple sub-task flow sequences, obtain multiple test item sequences, and allocate the multiple test item sequences to the test execution module 120 corresponding to the at least one allocation module 110.

[0065] In one embodiment, for each allocation module 110, when the allocation module 110 corresponds to a test execution module 120, the allocation module 110 can allocate multiple test item sequences to the test execution module 120 corresponding to the allocation module 110; when the allocation module 110 corresponds to multiple test execution modules 120, the allocation module 110 can evenly allocate the multiple test item sequences to the multiple test execution modules 120 corresponding to the allocation module 110, or, according to the preset weights of the test execution modules 120, the multiple test item sequences can be allocated to the multiple test execution modules 120 corresponding to the allocation module 110.

[0066] In an embodiment of the present application, at least one test execution module 120 is provided corresponding to each allocation module 110, and the test execution module 120 corresponding to the allocation module 110 processes the test item sequence of the allocation module 110, thereby improving the structurality of the test system and ensuring that each test item sequence has a corresponding test execution module 120 for processing.

[0067] Figure 2 is a schematic diagram of the structure of a test system provided by another exemplary embodiment of the present application. In some optional implementations, such as Figure 2 As shown, in the embodiment of the present application, each allocation module 110 includes: a test allocation submodule 111 and a test scheduling submodule 112 ; the test allocation submodule 111 corresponds to at least one test execution module 120 .

[0068] In one embodiment, each allocation module 110 may include: a test allocation submodule 111 and a test scheduling submodule 112 , and the test allocation submodule 111 corresponds to the plurality of test execution modules 120 .

[0069] Accordingly, in the embodiment of the present application, the test allocation submodule 111 is used to split and sort the multiple subtask flow sequences when receiving multiple subtask flow sequences, obtain multiple test item sequences, and transmit the multiple test item sequences to the test scheduling submodule 112.

[0070] In one embodiment, the first preset number may be the number of test allocation submodules 111 , the task flow scheduling module 100 evenly allocates the first preset number of subtask flow sequences to each test allocation submodule 111 , and the test allocation submodule 111 receives the subtask flow sequences allocated by the task flow scheduling module 100 .

[0071] The test scheduling submodule 112 is used to allocate multiple test item sequences to the test execution modules 120 corresponding to the test allocation submodule 111 .

[0072] In one implementation, the test scheduling submodule 112 may evenly distribute the test item sequences to the test execution modules 120 corresponding to the test allocation submodule 111 .

[0073] In the embodiment of the present application, by having the test allocation submodule 111 and the test scheduling submodule 112 respectively perform the generation and allocation of the test item sequence, the generation efficiency and allocation efficiency of the test item sequence can be effectively improved.

[0074] In some optional embodiments, in an embodiment of the present application, the test allocation submodule 111 is specifically used to split the multiple subtask flow sequences into a second preset number of test item sequences based on at least one of the test duration of each test item in the test task, the test order of each test item, and the test usage resources of each test item when receiving multiple subtask flow sequences.

[0075] The second preset number may be set according to test requirements. For example, the second preset number may be the number of test execution modules 120 .

[0076] In one embodiment, the test allocation submodule 111 may split the plurality of subtask flow sequences into a second preset number of test item sequences according to the test duration of the test items. Specifically, the test items in each subtask flow sequence may be evenly divided into a second preset number of test item sequences according to the test duration of the test items, and the sum of the test durations of the test items in each test item sequence is equal.

[0077] In an embodiment of the present application, the subtask flow sequence can be efficiently and accurately split and sorted through at least one of the test duration, test order, and test usage resources of each test item to obtain a test item sequence, thereby improving the efficiency of obtaining the test item sequence.

[0078] In an optional implementation, in an embodiment of the present application, the test scheduling submodule 112 is specifically used to allocate multiple test item sequences to the test execution modules 120 corresponding to the test allocation submodule 111 according to the workload of the test execution modules 120 corresponding to the test allocation submodule 111.

[0079] In one implementation, the test scheduling submodule 112 may allocate the test item sequence to the corresponding test execution module 120 according to the workload of the test execution module 120 corresponding to the test allocation submodule 111 .

[0080] Exemplarily, the workload may include: low workload and high workload, wherein low workload means that the test execution module 120 is not currently executing or executing a small number of test items and can receive a new test item sequence; high workload means that the test execution module 120 is currently executing a large number of test items and cannot receive a new test item sequence. The test scheduling submodule 112 preferentially transmits the test item sequence to the test execution module 120 (corresponding to the test allocation submodule 111) whose working state is low workload, monitors the test execution module 120 (corresponding to the test allocation submodule 111) with high workload, and transmits the test item sequence to the test execution module 120 (corresponding to the test allocation submodule 111) when the test execution module 120 (corresponding to the test allocation submodule 111) becomes low workload.

[0081] In the embodiment of the present application, the test scheduling submodule 112 allocates the test item sequence to the corresponding test execution module 120 according to the workload of the test execution module 120, thereby making the test item sequence allocation more reasonable, thereby improving the processing efficiency of the test item sequence, and further improving the test efficiency.

[0082] In some optional implementations, in an embodiment of the present application, the test execution module 120 is specifically used to obtain the occupancy status of the test resources used by each test item in the corresponding test item sequence from the chip test device, and based on the occupancy status of the test resources used by each test item, use a preset scheduling algorithm to determine the test item execution queue, and control the chip test device to execute each test item according to the order of each test item in the test item execution queue, so as to test the device to be tested and obtain the test result.

[0083] The occupancy status of the test resources may be used to indicate the workload of the hardware resources and / or software resources in the chip test equipment used when executing the test items. The preset scheduling algorithm may be an algorithm that optimizes the use of the test resources, for example, the preset scheduling algorithm may be a greedy algorithm, etc. The test item execution queue may include multiple test items.

[0084] Exemplarily, the test execution module 120 can obtain the occupancy status of test resources used by each test item in the test item sequence from the chip test device through the UserAPI of the chip test device, and sort the test items in the test item sequence according to the occupancy status of the test resources used by each test item by using a greedy / greedy algorithm to obtain a test item execution queue, and then call the relevant hardware resources and software resources of the chip test device through the UserAPI of the chip test device, execute the test items in the test item execution queue according to the sorting of the test items in the test item execution queue, so as to test the device to be tested.

[0085] In the embodiment of the present application, the execution order of each test item is determined by the occupancy status of the test resources used by each test item, so that the test execution module 120 can control the test equipment to efficiently execute the test items, thereby improving the test efficiency of the device to be tested.

[0086] In some optional implementations, in the embodiments of the present application, the test task includes test parameters for each test item.

[0087] The test parameters of the test items are used to represent the test data used when executing the test items. For example, the test parameters of the test items may include at least one of the following: a test current value, a test voltage value, and a test pulse frequency value.

[0088] Accordingly, in an embodiment of the present application, the test execution module 120 can control the chip test device to execute test items in the following manner: control the chip test device according to the order of each test item in the test item execution queue, use the test parameters of each test item, test configure the chip test device in turn, and execute the corresponding test items after the configuration is completed to test the device to be tested and obtain the test results.

[0089] In one embodiment, the test task may include target test data, which includes: test parameters, test duration, test sequence and test resources used for each test item in the test task, and the test sequence of each subtask flow.

[0090] The task flow scheduling module 100 can obtain the target test data from the test task and store the target test data in the task flow context. The task flow scheduling module 100 can transfer the target test data to the test allocation submodule 111 when allocating the subtask flow sequence; the test allocation submodule 111 can store the received target test data in the test context. The test allocation submodule 111 can transfer the target test data to the test scheduling submodule 112 when allocating the test item sequence. The test scheduling submodule 112 can store the received target test data in the execution context. When the test scheduling submodule 112 allocates the test item sequence, it can transfer the target test data to the corresponding test execution module 120. The test execution module 120 configures the test parameters of each test item in the chip test device in turn according to the test parameters of the received test items and the order of each test item in the test item execution queue through the UserAPI of the chip test device, and controls the chip test device to execute the corresponding test items after the configuration is completed to test the device to be tested and obtain the test results.

[0091] In the embodiment of the present application, the test execution module 120 configures the test parameters of the test items on the chip test device according to the order of the test items in the test item execution queue, thereby ensuring that the chip test device can smoothly execute the test items.

[0092] In some optional implementations, in the embodiment of the present application, the test execution module 120 is further configured to feed back the test status of each test item in the corresponding test item sequence to at least one allocation module 110;

[0093] The test status of the test item is used to indicate the current test stage of the test item. For example, the test status of the test item may include at least one of the following: configuring test parameters, test parameter configuration completed, testing in progress, and test completed.

[0094] Correspondingly, in the embodiment of the present application, at least one allocation module 110 is further configured to update and display the test status of each test item when the test status of each test item is received.

[0095] In one embodiment, the test execution module 120 feeds back the test status of each test item in the test item sequence to the test scheduling submodule 112, and the test scheduling submodule 112 updates the test status of each test item and controls the chip test equipment to display the test status of each test item.

[0096] In an embodiment of the present application, the test execution module 120 feeds back the test status of the test item to the allocation module 110, which updates the test status of the test item and controls the chip testing device to display the test status of the test item, thereby facilitating the user to view the test status.

[0097] In some optional implementations, in the embodiment of the present application, the test execution module 120 is also used to transmit the test results to the task flow scheduling module 100.

[0098] In one embodiment, the test execution module 120 obtains the test results from the chip testing device, and the test execution module 120 can directly transmit the test results to the task flow scheduling module 100, or, it can also transmit the test results to the task flow scheduling module 100 through the test allocation submodule 111 and the test scheduling submodule 112 in sequence, and the task flow scheduling module 100 can store the test results in the task flow context, the test allocation submodule 111 can store the test results in the test context, and the test scheduling submodule 112 can store the test results in the execution context.

[0099] Correspondingly, in an embodiment of the present application, the task flow scheduling module 100 is also used to merge the target test item into the current subtask flow sequence when the test result indicates that the target test item fails and / or the business unit corresponding to the target test item is abnormal.

[0100] Among them, in the implementation of this application, the test items that failed to execute and the test items corresponding to the abnormal business units can be called target test items.

[0101] In one embodiment, the test result may include, for example, whether each test item is successfully executed, relevant data of the business unit obtained by executing each test item, and whether the business unit corresponding to each test item is abnormal, etc. Wherein, if the test item is successfully tested, it means that the chip test equipment successfully executes the test item, and if the test item is failed, it means that the chip test equipment does not successfully execute the test item.

[0102] When the test result indicates the existence of a target test item, the task flow scheduling module 100 incorporates the target test item into the current sub-task flow, and splits and sorts the current sub-task flow to incorporate the target test item into the current sub-task flow sequence, thereby obtaining a first new sub-task flow sequence. The processing method for the first new sub-task flow sequence can refer to the processing method for the sub-task flow sequence, which will not be repeated here. This allows the chip testing equipment to execute the target test item again, so that the business unit corresponding to the target test item can be retested.

[0103] In an embodiment of the present application, the task flow scheduling module 100 is used to reallocate target test items so that test items that have failed tests and / or test items with abnormal business units can be retested by chip testing equipment, thereby ensuring the accuracy of test results.

[0104] In an optional implementation, in the embodiment of the present application, the test execution module 120 is further used to transmit the test result to the test scheduling submodule 112. The test scheduling submodule 112 is further used to merge the target test item into the current test item sequence and assign the current test item to the corresponding test execution module 120 when the test result indicates that the target test item fails and / or the business unit corresponding to the target test item is abnormal.

[0105] In one embodiment, when the test result indicates the existence of a target test item, the test scheduling submodule 112 merges the target test item into the current test item sequence to obtain a new current test item sequence, and assigns the new test item sequence to the corresponding test execution module 120. The test execution module 120 processes the new current test item sequence with reference to the manner in which the test execution module 120 processes the test item sequence, which will not be repeated here. This allows the chip testing device to execute the target test item again and retest the business unit corresponding to the target test item.

[0106] In an embodiment of the present application, the test scheduling submodule 112 is used to merge the target test items into the current test item sequence so that failed test items and / or abnormal test items of business units can be retested by the chip testing equipment, thereby ensuring the accuracy of the test results.

[0107] In some optional implementations, in an embodiment of the present application, the task flow scheduling module 100 is also used to determine the waiting test items based on the test parameters of each test item in the test task; and when the received test results include test data corresponding to the waiting test items, the waiting test items are incorporated into the current subtask flow sequence.

[0108] The waiting test item may be a test item that requires the test results of other test items as test data.

[0109] In one embodiment, the task flow scheduling module 100 may determine the waiting test items according to the test parameters of each test item in the test task before determining the sub-task flow sequence; when the task flow scheduling module 100 receives the test result, it determines whether the test result includes the test data corresponding to the waiting test item. When the test data corresponding to the waiting test item is included, the waiting test item is incorporated into the current sub-task flow, and the current sub-task flow is split and sorted to incorporate the waiting test items into the current sub-task flow sequence to obtain a second new sub-task flow sequence. The processing method for the second new sub-task flow sequence can refer to the processing method for the sub-task flow sequence, which will not be repeated here. In this way, the chip testing equipment can execute the waiting test item so that the business unit corresponding to the waiting test item can be tested; when the test result does not include the test data corresponding to the waiting test item, the waiting test item continues to be in a waiting state.

[0110] In an embodiment of the present application, the task flow scheduling module 100 may first determine the waiting test items in the test task before determining the sub-task flow sequence, and when the test data of the waiting test items are included in the test results, the waiting test items are incorporated into the current sub-task flow sequence, thereby making the splitting and combination of test tasks more reasonable, avoiding the accumulation of waiting test items in the test execution module 120 and affecting the execution of other test items, and improving the test efficiency of the device to be tested.

[0111] Figure 3 FIG. 1 is a schematic diagram of a test system processing a test task provided by an application example of the present application. Figure 3 As shown, the test system is deployed on the chip test equipment, and the test system may include: a task flow scheduling module 100, multiple test allocation submodules 111, multiple test scheduling submodules 112 and multiple test execution modules 120, each test allocation submodule 111 corresponds to multiple test execution modules 120, and each test execution module 120 calls the hardware resources and software resources on the chip test equipment through the User API provided by the chip test equipment to execute the test items. The test project (test task) may include: multiple subtask flows and target test data executed in series, and the target test data may include: the test duration, test sequence, test parameters and test usage resources of each test item, the test sequence of each subtask flow, and the test duration of the serially executed test task, wherein the test usage resources may be represented in the form of a chart. The first preset number may be the number of test allocation submodules 111, and the second preset number may be the number of test execution modules 120.

[0112] The test project is input into the test system, the task flow scheduling module 100 (Flow Scheduler) stores the target test data in the task flow context (Flow Context), determines the waiting test items according to the test parameters of the test items, and splits the task flow except the waiting test items into a first preset number of sub-task flow sequences based on the test duration of the test items in the test task, and then distributes the sub-task flow sequences and the target test data to multiple test allocation sub-modules 111, for example, Figure 3 SubFlow01 to SubFlow8 represent sub-task flows 1 to 8 respectively, subflow.seq1 and subflow.seq2 represent sub-task flow sequence 1 and sub-task flow sequence 2, subflow.seq1 and subflow.seq2 are respectively assigned to two different test assignment submodules 111. In this application example, subflow.seq1 is taken as an example for description;

[0113] Each test allocation submodule 111 (Flow Engine) can store the target test data in the test context (Test Context), and split the multiple subtask flow sequences into a second preset number of test item sequences according to the test duration of the test item, and send the second preset number of test item sequences and the target test data to the corresponding test scheduling submodule 112 (the test scheduling submodule 112 belonging to the same allocation module 110 as the test allocation submodule 111), for example, Figure 3 Test01.01~Test01.n, Test03.01~Test03.n and Test05.01~Test05.n respectively represent test items, test.seq1, test.seq2, test.seq3 respectively represent test item sequence 1, test item sequence 2 and test item sequence 3;

[0114] The test scheduling submodule 112 (Test Scheduler) may store the target test data in the execution context (Execution Context), and according to the workload of the test execution module 120 corresponding to the test allocation submodule 111, respectively allocate the test item sequence of the second preset data volume to the test execution module 120 corresponding to the test allocation submodule 111;

[0115] Each test execution module 120 (Test Engine) obtains the occupancy status of the test resources used by each test item in the corresponding test item sequence from the chip test device, and based on the occupancy status of the test resources used by each test item, uses a greedy / greedy algorithm to determine the test item execution queue, controls the chip test device to perform test configuration on the chip test device in sequence according to the order of each test item in the test item execution queue, and uses the test parameters of each test item. After the configuration is completed, the corresponding test resources on the chip test device are called to execute the corresponding test items to test the device to be tested and obtain the test results, wherein the test resources may include: corresponding hardware for analog signals, related hardware for digital signals, related hardware for radio frequency, and related software for testing, etc. Figure 3 seq1 is assigned to a corresponding test execution module 120 , and other test item sequences are respectively assigned to other test execution modules 120 , which can be referred to here.

[0116] When configuring the test parameters, the test execution module 120 feeds back the test status of each test item in the corresponding test item sequence to the test scheduling submodule 112. When the test scheduling submodule 112 receives the test status of each test item, it updates the test status of each test item and displays it, for example, Figure 3 In the example, Test01.01.set and Test01.02.set indicate that the test parameters of the test items Test 01.01 and Test01.02 are being configured, and Test01.03.run and Test01.n.run indicate that the test parameter configuration of the test items Test01.03.run and Test01.n.run is complete.

[0117] The test execution module 120 may transmit the test result to the task flow scheduling module 100, and the task flow scheduling module 100 stores the test result in the task flow context, and when the test result indicates that the target test item fails and / or the business unit corresponding to the target test item is abnormal, the target test item is incorporated into the current sub-task flow sequence, so that the target test item can be executed again by the chip test device; when the test result includes the test data corresponding to the waiting test item, the task flow scheduling module 100 incorporates the waiting test item into the current sub-task flow sequence, so that the waiting test item can be executed by the chip test device;

[0118] The test execution module 120 can transmit the test results to the test scheduling sub-module 112. The test scheduling sub-module 112 stores the test results in the execution context, and when the test results indicate that the target test item has failed and / or the business unit corresponding to the target test item is abnormal, the target test item is incorporated into the current test item sequence, and the current test item is assigned to the corresponding test execution module 120 so that the target test item can be executed again by the chip testing device.

[0119] Figure 4 2 is a schematic diagram of a chip testing device provided by an exemplary embodiment of the present application. The chip testing device 200 includes the testing system 210 shown above.

[0120] In one implementation, the test system may be deployed in a host computer of the chip testing device 200 .

[0121] The chip testing equipment of the embodiment of the present application corresponds to the embodiment of the above-mentioned testing system of the present application, and the relevant contents can be referenced to each other and will not be repeated here.

[0122] The beneficial technical effects corresponding to the exemplary embodiment of the chip testing equipment of the embodiment of the present application can be referred to the corresponding beneficial technical effects of the above-mentioned corresponding exemplary system part, which will not be repeated here.

[0123] Figure 5 is a flow chart of a test method provided by an exemplary embodiment of the present application. This embodiment can be applied to chip test equipment, such as Figure 5 As shown, the test method may include the following steps:

[0124] Step S400, when receiving a test task for a device to be tested, split and sort the test task to obtain a plurality of subtask flow sequences, each of the plurality of subtask flow sequences respectively including at least one subtask flow, each of the at least one subtask flow respectively including at least one test item;

[0125] Step S410, splitting and sorting the test items in the multiple subtask flow sequences to obtain multiple test item sequences, each of the multiple test item sequences respectively including multiple test items;

[0126] Step S420, controlling the chip testing device to execute each test item in the plurality of test item sequences to perform parallel testing on the devices to be tested and obtain test results.

[0127] In some possible implementations of the present disclosure, the test task in the embodiments of the present disclosure includes a main task flow for the device to be tested, and the main task flow includes a plurality of subtask flows and / or a plurality of test items serially connected in a test order;

[0128] The test tasks are split and sorted to obtain multiple subtask flow sequences, including:

[0129] When the main task flow includes the multiple subtask flows and the multiple test items, constructing a new subtask flow from the multiple test items, and splitting and sorting the new subtask flow and the multiple subtask flows to obtain the multiple subtask flow sequences;

[0130] When the main task flow includes the multiple subtask flows, splitting and sorting the multiple subtask flows to obtain the multiple subtask flow sequences;

[0131] When the main task flow includes the multiple test items, the multiple sub-task flows are constructed from the multiple test items, and the multiple sub-task flows are split and sorted to obtain the multiple sub-task flow sequences.

[0132] In some possible implementations of the present disclosure, the test task in the embodiment of the present disclosure includes the test duration of each test item, the test order of each test item, the test resources used by each test item and the test order of each subtask flow;

[0133] The test tasks are split and sorted to obtain multiple subtask flow sequences, including:

[0134] The multiple subtask flows are split into a first preset number of the subtask flow sequences according to at least one of the test duration of each test item, the test order of each test item, the test usage resources of each test item and the test order of each subtask flow.

[0135] In some possible implementations of the present disclosure, the splitting and sorting of the test items in the multiple subtask flow sequences to obtain multiple test item sequences in the embodiment of the present disclosure includes:

[0136] The multiple subtask flow sequences are split into a second preset number of the test item sequences according to at least one of the test duration of each test item in the test task, the test order of each test item, and the test usage resources of each test item.

[0137] In some possible implementations of the present disclosure, the controlling the chip testing device to execute each test item in the plurality of test item sequences in the embodiment of the present disclosure to perform parallel testing on the device to be tested to obtain a test result includes:

[0138] Acquiring from the chip testing device the occupancy status of the test resources used by each test item in the corresponding test item sequence;

[0139] Based on the occupancy status of the test resources used by each test item, a test item execution queue is determined using a preset scheduling algorithm;

[0140] The chip testing device is controlled to execute each test item according to the order of each test item in the test item execution queue, so as to test the device to be tested and obtain the test result.

[0141] In some possible implementations of the present disclosure, the test task in the embodiments of the present disclosure includes test parameters of each test item;

[0142] The controlling the chip testing device to execute each test item according to the order of each test item in the test item execution queue to test the device under test includes:

[0143] The chip testing device is controlled to perform test configuration on the chip testing device in sequence according to the order of the test items in the test item execution queue, using the test parameters of the test items, and after the configuration is completed, the corresponding test items are executed to test the device to be tested to obtain the test result.

[0144] In some possible implementations of the present disclosure, the testing method in the embodiment of the present disclosure further includes:

[0145] When the current test status of each test item is received, the test status of each test item is updated and displayed.

[0146] Among some possible implementations of the present disclosure, the test method in the embodiments of the present disclosure:

[0147] When the test result indicates that the target test item fails and / or the business unit corresponding to the target test item is abnormal, the target test item is incorporated into the current subtask flow, and the current subtask flow is split and sorted.

[0148] Among some possible implementations of the present disclosure, the test method in the embodiments of the present disclosure:

[0149] When the test result indicates that the target test item fails and / or the service unit corresponding to the target test item is abnormal, the target test item is incorporated into the current test item sequence.

[0150] Among some possible implementations of the present disclosure, the test method in the embodiments of the present disclosure:

[0151] Determine the waiting test items according to the test parameters of each test item in the test task;

[0152] When the received test result includes the test data corresponding to the waiting test item, the waiting test item is incorporated into the current subtask flow, and the current subtask flow is split and sorted.

[0153] The testing method of the embodiment of the present application corresponds to the embodiment of the above-mentioned testing system of the present application, and the relevant contents can be referenced to each other and will not be repeated here.

[0154] The beneficial technical effects corresponding to the exemplary embodiment of the testing method of the embodiment of the present application can be referred to the corresponding beneficial technical effects of the above-mentioned corresponding exemplary system part, which will not be repeated here.

[0155] In addition, an embodiment of the present disclosure further provides an electronic device, including:

[0156] Memory for storing computer programs;

[0157] The processor is used to execute the computer program stored in the memory, and when the computer program is executed, the testing method described in any of the above embodiments of the present disclosure is implemented.

[0158] Figure 6 This is a schematic diagram of the structure of an application embodiment of the electronic device disclosed in the present invention. Figure 6 The electronic device according to the embodiment of the present disclosure is described. The electronic device may be any one or both of the first device and the second device, or a stand-alone device independent of them, and the stand-alone device may communicate with the first device and the second device to receive the collected input signals from them.

[0159] like Figure 6 As shown, the electronic device includes one or more processors and memory.

[0160] The processor may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0161] The memory may include one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor may execute the program instructions to implement the test methods of the various embodiments of the present disclosure described above and / or other desired functions.

[0162] In one example, the electronic device may further include: an input device and an output device, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0163] In addition, the input device may also include, for example, a keyboard, a mouse, and the like.

[0164] The output device can output various information to the outside, including the determined distance information, direction information, etc. The output device can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0165] Of course, to simplify, Figure 6 Only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device may further include any other appropriate components.

[0166] In addition to the above methods and devices, embodiments of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the testing method according to various embodiments of the present disclosure described in the above part of this specification.

[0167] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0168] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enables the processor to execute the steps of the testing method according to various embodiments of the present disclosure described in the above part of this specification.

[0169] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0170] A person of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk, etc., various media that can store program codes.

[0171] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0172] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0173] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0174] The method and apparatus of the present disclosure may be implemented in many ways. For example, the method and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above, unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as a program recorded in a recording medium, which includes machine-readable instructions for implementing the method according to the present disclosure. Therefore, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

[0175] It should also be noted that in the apparatus, device and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0176] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0177] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A testing system, characterized in that: Applied to chip testing equipment, the system includes: a task flow scheduling module, multiple allocation modules and multiple test execution modules; The task flow scheduling module is used for, when receiving a test task for a device to be tested, splitting and sorting the test task to obtain a plurality of subtask flow sequences, and allocating the plurality of subtask flow sequences to at least one allocation module among the plurality of allocation modules, each of the plurality of subtask flow sequences respectively including at least one subtask flow, and each of the at least one subtask flow respectively including at least one test item; The at least one allocation module is used to, upon receiving the multiple subtask flow sequences, split and sort the test items in the multiple subtask flow sequences to obtain multiple test item sequences, and allocate the multiple test item sequences to the multiple test execution modules respectively, wherein each test item sequence in the multiple test item sequences includes multiple test items respectively; With respect to the multiple test execution modules, the test execution modules are used to control the chip testing device to execute each test item in the multiple test item sequences, so as to perform parallel testing on the devices to be tested and obtain test results.

2. The system according to claim 1, characterized in that The test task includes a main task flow for the device under test, and the main task flow includes at least one sub-task flow and / or at least one test item; The test tasks are split and sorted to obtain multiple subtask flow sequences, which are further used for: When the main task flow includes the multiple subtask flows and the multiple test items, constructing a new subtask flow from the multiple test items, and splitting and sorting the new subtask flow and the multiple subtask flows to obtain the multiple subtask flow sequences; When the main task flow includes the multiple subtask flows, splitting and sorting the multiple subtask flows to obtain the multiple subtask flow sequences; When the main task flow includes the multiple test items, the multiple sub-task flows are constructed from the multiple test items, and the multiple sub-task flows are split and sorted to obtain the multiple sub-task flow sequences.

3. The system according to claim 1 or 2, characterized in that: The test task includes the test duration of each test item, the test order of each test item, the test resources used by each test item and the test order of each subtask flow; The test tasks are split and sorted to obtain multiple subtask flow sequences, which are further used for: The test task is split into a first preset number of the subtask flow sequences according to at least one of the test duration of each test item, the test order of each test item, the test usage resources of each test item and the test order of each subtask flow.

4. The system according to any one of claims 1 to 3, characterized in that: Each of the multiple allocation modules corresponds to at least one test execution module; The at least one allocation module is specifically used to split and sort the multiple sub-task flow sequences when receiving the multiple sub-task flow sequences to obtain the multiple test item sequences, and allocate the multiple test item sequences to the test execution module corresponding to the at least one allocation module.

5. The system according to claim 4, characterized in that Each of the allocation modules includes a test allocation submodule and a test scheduling submodule, and the test allocation submodule corresponds to at least one test execution module; The test allocation submodule is used to obtain the multiple test item sequences upon receiving the multiple subtask flow sequences, and transmit the multiple test item sequences to the test scheduling submodule; The test scheduling submodule is used to allocate the multiple test item sequences to the test execution modules corresponding to the test allocation submodule.

6. The system according to claim 5, characterized in that The test allocation submodule is specifically used to split the multiple subtask flow sequences into a second preset number of test item sequences according to at least one of the test duration of each test item in the test task, the test order of each test item and the test usage resources of each test item when receiving the multiple subtask flow sequences.

7. The system according to claim 5 or 6, characterized in that: The test scheduling submodule is specifically configured to allocate the plurality of test item sequences to the test execution modules corresponding to the test allocation submodules according to the workload of the test execution modules corresponding to the test allocation submodules.

8. The system according to any one of claims 1 to 7, characterized in that: The test execution module is specifically used to obtain the occupancy status of the test resources used by each test item in the corresponding test item sequence from the chip testing device, and based on the occupancy status of the test resources used by each test item, use a preset scheduling algorithm to determine the test item execution queue, and control the chip testing device to execute each test item according to the order of each test item in the test item execution queue, so as to test the device to be tested and obtain the test result.

9. The system according to claim 8, characterized in that The test task includes test parameters of each test item; Controlling the chip testing device to execute each test item according to the order of each test item in the test item execution queue to test the device to be tested, and further used for: The chip testing device is controlled to perform test configuration on the chip testing device in sequence according to the order of the test items in the test item execution queue, using the test parameters of the test items, and after the configuration is completed, the corresponding test items are executed to test the device to be tested to obtain the test result.

10. The system according to any one of claims 1 to 9, characterized in that: The test execution module is further configured to feed back the test status of each test item in the corresponding test item sequence to the at least one allocation module; The at least one allocation module is further configured to update and display the test status of each test item when the test status of each test item is received.

11. The system according to any one of claims 1 to 10, characterized in that: The test execution module is further used to transmit the test result to the task flow scheduling module; The task flow scheduling module is further configured to merge the target test item into the current sub-task flow sequence when the test result indicates that the target test item fails and / or the business unit corresponding to the target test item is abnormal.

12. The system according to any one of claims 5 to 7, characterized in that: The test execution module is further used to transmit the test result to the test scheduling submodule; The test scheduling submodule is further configured to, when the test result indicates that the target test item fails and / or the business unit corresponding to the target test item is abnormal, incorporate the target test item into the current test item sequence and assign the current test item to a corresponding test execution module.

13. The system according to any one of claims 1 to 12, characterized in that: The task flow scheduling module is also used to determine the waiting test item according to the test parameters of each test item in the test task; and when the received test result includes the test data corresponding to the waiting test item, the waiting test item is incorporated into the current subtask flow sequence.

14. A chip testing device, comprising the testing system according to claims 1-13.

15. A testing method, characterized in that: Applied to chip testing equipment, the method comprises: When receiving a test task for a device to be tested, the test task is split and sorted to obtain a plurality of subtask flow sequences, each of the plurality of subtask flow sequences respectively includes at least one subtask flow, and each of the at least one subtask flow respectively includes at least one test item; Splitting and sorting the test items in the multiple subtask flow sequences to obtain multiple test item sequences, each of the multiple test item sequences comprising multiple test items; The chip testing device is controlled to execute each test item in the plurality of test item sequences to perform parallel testing on the devices to be tested and obtain test results.

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