Method for eliminating offset voltage and realizing reference high-precision output voltage

Abstract

The invention provides a method for eliminating offset voltage to realize reference high-precision output voltage, and relates to a high-precision output voltage method. According to the method, a reference circuit comprises a starting circuit, a self-biasing circuit, an operational amplifier with a chopping structure, a low-pass filter and a band-gap reference module. The self-biased circuit ensures that follow-up circuits can obtain stable bias current and voltage, the operational amplifier with a chopping structure eliminates offset voltage through the chopping technology, the influence of the offset voltage on amplifier output is reduced, and the output of the amplifier is improved. The low-pass filter filters out the offset voltage modulated to the high frequency, and the band-gap reference module generates reference voltage which does not change along with the temperature. The influence of offset voltage on the operational amplifier is greatly reduced, the low-pass filter is introduced, offset voltage signals modulated to high frequency and high-frequency noise signals are eliminated, high-precision output of the operational amplifier is achieved, and therefore low-offset, high-precision and low-temperature-drift reference voltage output is guaranteed.

Description

Technical Field

[0001] The invention relates to a method for outputting a reference high-precision voltage, and in particular to a method for eliminating an offset voltage and realizing a reference high-precision output voltage. Background Art

[0002] Bandgap reference voltage source plays an important role in the field of analog integrated circuit design and is an indispensable key part. Its core function is to provide other circuit modules with a reference voltage that does not change with temperature. This voltage is not affected by fluctuations in power supply voltage and changes in temperature.

[0003] In analog and mixed analog and digital circuits, the application range of bandgap reference circuit is extremely wide. It provides a solid and reliable stable reference voltage for many circuit modules. Whether it is a precise signal processing circuit or a high-speed data conversion module, it is inseparable from the support of the bandgap reference circuit. The performance of the bandgap reference circuit directly determines the performance of the overall circuit.

[0004] With the large-scale application of integrated circuit products in various fields of modern society, such as consumer electronics, communication equipment, automotive electronics, etc., more stringent requirements are also put forward for the performance of bandgap reference voltage sources. Nowadays, it is not only required to have a lower static current consumption, but also expected that the bandgap reference voltage source has a higher precision. Therefore, the present invention proposes a bandgap reference circuit that generates a reference voltage through a circuit of a low offset operational amplifier. The self-bias design is combined with chopping technology to make the circuit have a very low offset voltage. It can reduce the error caused by the offset voltage and improve the accuracy and reliability of the circuit. In analog and digital-analog hybrid circuits with extremely high precision requirements, this low offset advantage is particularly important. Adapting to low-voltage working environment, low-voltage working ability is particularly important under the trend of miniaturization and low power consumption of electronic equipment today. It can be compatible with low-voltage power supply systems, reduce the power consumption of the entire system, and also create favorable conditions for improving the integration of integrated circuits. In application scenarios where portable devices, Internet of Things devices, etc. have strict restrictions on power supply voltage, the circuit can perform excellent performance. Summary of the invention

[0005] The purpose of the present invention is to provide a method for eliminating offset voltage and realizing reference high-precision output voltage. The method reduces the influence of offset voltage on output voltage through chopping technology, thereby providing low-offset and high-precision reference voltage for other integrated circuit modules.

[0006] The technical solution of the present invention is as follows:

[0007] A method for eliminating offset voltage and realizing reference high-precision output voltage, comprising:

[0008] Start-up circuit: used to drive the circuit out of the degenerate working point at startup;

[0009] Self-bias circuit: ensures that subsequent circuits can obtain stable bias current and voltage;

[0010] Operational amplifier with chopping structure: The chopping technology eliminates the offset voltage and reduces the impact of the offset voltage on the amplifier output;

[0011] Low-pass filter: Filters out the offset voltage modulated to high frequency;

[0012] Bandgap reference module: Generates a reference voltage that does not vary with temperature.

[0013] Optionally, the startup circuit includes: PMOS tubes: MP15, MP16, and a resistor: R10; the source of the PMOS tube MP15 is connected to the power supply voltage, the drain is connected to the gate of the PMOS tube MP16 and one end of the resistor R10, the gate of the PMOS tube MP15 is connected to the gate of the PMOS tube MP1, the other end of the resistor R10 is grounded, the source of the PMOS tube MP16 is connected to the power supply voltage, and the drain of the PMOS tube MP16 serves as the output end of the startup circuit. The substrates of all the PMOS tubes are connected to VDD, and the substrates of all the NMOS tubes are connected to GND.

[0014] Optionally, the self-bias circuit includes: PMOS tubes: MP1, MP2, MP3, MP4, MP5, MP6, NMOS tubes: MN1, MN2, resistors: R1, R2; the source of the PMOS tube MP1 is connected to the power supply voltage, the gate of the PMOS tube MP1 is connected to the gates of the PMOS tubes MP3, MP5, MP7, the drain of the PMOS tube MP1 is connected to the source of the PMOS tube MP2, the gate of the PMOS tube MP3 is connected to the gates of the PMOS tubes MP6 and MP8, the drain of the PMOS tube MP2 is connected to the gate of the PMOS tube MP2 and the drain of the NMOS tube MN1, the source of the NMOS tube MN1 is connected to one end of the resistor R1, the gate of the NMOS tube MN1 is connected to the gates of the NMOS tubes MN2 and MN5, and the other end of the resistor R1 is grounded. The source of the PMOS tube MP3 is connected to the power supply voltage, the drain of the PMOS tube MP3 is connected to the gate of the PMOS tube MP4, one end of the resistor R2 is connected, the other end of the resistor R2 is grounded, the source of the PMOS tube MP4 is connected to the power supply voltage, the drain of the PMOS tube MP4 is connected to the drain of the PMOS tube MP6, and the drain and gate of the NMOS tube MN2 are connected. The source of the PMOS tube MP5 is connected to the power supply voltage, the drain of the PMOS tube MP5 is connected to the source of the PMOS tube MP6. The source of the NMOS tube MN2 is grounded. The substrates of all the PMOS tubes are connected to VDD, and the substrates of all the NMOS tubes are connected to GND.

[0015] Optionally, the operational amplifier with a chopper structure includes: PMOS tubes: MP7, MP8, MP9, MP10, MP11, NMOS tubes: MN3, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12, MN13, and an oscillator M1; the source of the PMOS tube MP7 is connected to the power supply voltage, and the drain of the PMOS tube MP7 is connected to the source of the PMOS tube MP8. The drain of the PMOS tube MP8 is connected to the source of the PMOS tubes MP9 and MP10. The gate of the PMOS tube MP9 is connected to the drain of the NMOS tubes MN12 and MN13, and the drain of the PMOS tube MP9 is connected to the source of the NMOS tube MN6, the source of MN8, and the drain of MN3. The gate of the PMOS tube MP10 is connected to the drain of the NMOS tubes MN10 and MN11, and the drain of the PMOS tube MP10 is connected to the drain of the NMOS tube MN7, the source of MN9, and the drain of MN4. The NMOS tubes MN6-MN13 are all used as switches, and the gates of the NMOS tubes MN6, MN9, MN10, and MN13 are connected to the clock signal CK of the oscillator M1, and the gates of MN7, MN8, MN11, and MN12 are connected to the clock signal CKN of the oscillator M1. The drain of the NMOS tube MN6 is connected to the source of the NMOS tube MN7, the gate of MN3, and the gate of MN4. The sources of the NMOS tubes MN3 and MN4 are grounded. The drain of the NMOS tube MN8 and the drain of MN9 are connected to the gate of the PMOS tube MP11. The source of the NMOS tube MN10 and the source of MN12 are connected to the drain of the PMOS tube MP12, the emitter of the PNP transistor Q1, and one end of the resistor R4. The source of the NMOS tube MN11 and the source of MN13 are connected to the drain of the PMOS tube MP13, one end of the resistor R5, and one end of the resistor R6. The source of the PMOS tube MP11 is connected to the power supply voltage, and the drain of MP11 is connected to the gates of the PMOS tubes MP12, MP13, and MP14, and the drain of the NMOS tube MN5. The source of the NMOS tube MN5 is grounded. The substrates of all the PMOS tubes are connected to VDD, and the substrates of all the NMOS tubes are connected to GND.

[0016] Optionally, the low-pass filter includes: a resistor: R3, a capacitor: C1; one end of the resistor R3 is connected to the drain of the NMOS tubes MN8 and MN9 and the gate of the PMOS tube MP11, and the other end of R3 is connected to the positive electrode of the capacitor C1 and the source of the PMOS tube MP11. The negative electrode of the capacitor C1 is grounded.

[0017] Optionally, the bandgap reference module includes: PMOS tubes: MP12, MP13, MP14, PNP transistors: Q1, Q2, resistors: R4, R5, R6, R7, R8, R9, capacitor: C2; the source of the PMOS tube MP12, the source of MP13, and the source of MP14 are connected to the supply voltage. The other end of the resistor R4 and the other end of R6 are grounded. The other end of the resistor R5 is connected to the emitter of the PNP transistor Q2. The base and collector of the PNP transistor Q1, and the base and collector of Q2 are grounded. The drain of the PMOS tube MP14 is connected to one end of the resistor R7. The other end of the resistor is connected to one end of the resistor R8 and the positive electrode of the capacitor C2. The other end of the resistor R8 is connected to one end of the resistor R9. The other end of the resistor R9 and the negative electrode of the capacitor C2 are grounded. The substrates of all the PMOS tubes are connected to VDD, and the substrates of all the NMOS tubes are connected to GND.

[0018] Compared with the prior art, the present invention has the following advantages:

[0019] (1) Compared with the general bandgap reference circuit, the bandgap reference circuit of the present invention uses the design of self-bias and chopping technology to make the circuit have a lower offset voltage. The low offset characteristic is very important in analog signal processing and high-precision data conversion. It can effectively avoid the error accumulation caused by the offset voltage and improve the linearity and stability of the circuit.

[0020] (2) The general bandgap reference circuit may have degraded performance or fail to work properly in a low-voltage environment. The self-biased low-offset low-voltage bandgap reference circuit based on chopping technology of the present invention is specially designed for low-voltage environments and can work stably under low-voltage conditions. This is particularly important for the trend of modern electronic devices pursuing low power consumption and miniaturization. In application scenarios such as portable electronic devices and wearable devices that have strict restrictions on power supply voltage, this circuit can provide a stable reference voltage for the system at low voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The present invention is a flow chart of the design of a self-biased low-offset low-voltage bandgap reference circuit based on chopping technology;

[0022] Figure 2 A schematic diagram of an operational amplifier using a chopping technique according to the present invention;

[0023] Figure 3 The present invention is a startup and bias circuit diagram of a self-biased low-offset low-voltage bandgap reference circuit based on chopping technology;

[0024] Figure 4 The operational amplifier circuit diagram of the self-biased low-offset low-voltage bandgap reference circuit based on the chopping technology of the present invention;

[0025] Figure 5 A bandgap reference circuit diagram of a self-biased low-offset low-voltage bandgap reference circuit based on chopping technology of the present invention;

[0026] Figure 6 The present invention is an overall circuit diagram of a self-biased low-offset low-voltage bandgap reference circuit based on chopping technology.

[0027] Component number description: 01 startup circuit module, 02 self-bias circuit module, 03 operational amplifier module, 04 low-pass filter, 05 bandgap reference module. DETAILED DESCRIPTION

[0028] The present invention is further described in detail below with reference to examples, but the embodiments of the present invention are not limited thereto.

[0029] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the scope of protection of the present invention. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the invention claimed for protection, but merely represents the selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the scope of protection of the present invention.

[0030] In addition, the illustrations provided in this example are only used to schematically illustrate the basic concept of the present invention. The illustrations only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the shape, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0031] Combination Figure 1 The design process is as follows: the bias circuit is turned on by the startup circuit, and then turned off after the bias circuit is turned on. The bias circuit provides a stable bias voltage and bias current for the subsequent circuit. The input of the operational amplifier is processed by chopping technology, so that its input signal is input into the operational amplifier as a square wave. After being amplified by the operational amplifier and demodulated, the square wave offset voltage is removed by a low-pass filter (LPF) and a stable VREF is obtained by a bandgap reference circuit.

[0032] Combination Figure 2In the figure, the chopping technology is modulated by two sets of switch groups that perform positive and negative flipping, so that the waveform of the output of the operational amplifier is a square wave, and the average value is the offset voltage (Vos) multiplied by the amplification factor of the operational amplifier. After being modulated by the switch group again, the output of the square wave is the input voltage multiplied by the amplification factor of the operational amplifier plus the offset voltage modulated into a square wave. After filtering through a low-pass filter, a high-precision signal with the offset voltage eliminated can be obtained.

[0033] This example provides a bias circuit including a startup circuit 01 and a self-bias circuit 02, which generates a bias current to ensure that the semiconductor device works stably under different working conditions and improve the reliability and accuracy of the circuit.

[0034] As an example, Figure 3 As shown, the startup circuit 01 includes: PMOS tubes: MP15, MP16, and a resistor: R10; the source of the PMOS tube MP15 is connected to the power supply voltage, the drain is connected to the gate of the PMOS tube MP16 and one end of the resistor R10, the gate of the PMOS tube MP15 is connected to the gate of the PMOS tube MP1, the other end of the resistor R10 is grounded, the source of the PMOS tube MP16 is connected to the power supply voltage, and the drain of the PMOS tube MP16 serves as the output end of the startup circuit.

[0035] In this example, PMOS tubes: MP15, MP16, and resistor: R10 form a startup circuit. When the power supply voltage VDD is equal to zero, MP15 tube works in the cut-off region, and the current flowing through R10 is equal to zero; when the power supply VDD rises to greater than VTHP16, MP16 tube is turned on and works in the deep linear region, so that the startup signal increases with the power supply voltage VDD. When the voltage of the startup signal reaches a certain value, MN1 and MN2 are turned on, and the power supply voltage VDD flows current to GND through the path formed by MP1, MP2, MN1, and resistor R1. MP15 tube and MP1 tube form a current mirror. As the current increases, the mirror current of MP15 also increases, causing the gate voltage of MP16 tube to increase; when VG16>VDD-VTHP16, MP16 enters the cut-off region and the startup unit is closed.

[0036] As an example, Figure 3As shown, the self-bias circuit includes: PMOS tubes: MP1, MP2, MP3, MP4, MP5, MP6, NMOS tubes: MN1, MN2, resistors: R1, R2; the source of the PMOS tube MP1 is connected to the power supply voltage, the gate of the PMOS tube MP1 is connected to the gates of the PMOS tubes MP3, MP5, MP7, the drain of the PMOS tube MP1 is connected to the source of the PMOS tube MP2, the gate of the PMOS tube MP3 is connected to the gates of the PMOS tubes MP6 and MP8, the drain of the PMOS tube MP2 is connected to the gate of the PMOS tube MP2 and the drain of the NMOS tube MN1, the source of the NMOS tube MN1 is connected to one end of the resistor R1, the gate of the NMOS tube MN1 is connected to the gates of the NMOS tubes MN2 and MN5, and the other end of the resistor R1 is grounded. The source of the PMOS tube MP3 is connected to the power supply voltage, the drain of the PMOS tube MP3 is connected to the gate of the PMOS tube MP4, one end of the resistor R2 is connected, the other end of the resistor R2 is grounded, the source of the PMOS tube MP4 is connected to the power supply voltage, the drain of the PMOS tube MP4 is connected to the drain of the PMOS tube MP6, and the drain and gate of the NMOS tube MN2 are connected. The source of the PMOS tube MP5 is connected to the power supply voltage, the drain of the PMOS tube MP5 is connected to the source of the PMOS tube MP6. The source of the NMOS tube MN2 is grounded.

[0037] In this example, PMOS transistors: MP1, MP2, MP3, MP4, MP5, MP6, NMOS transistors: MN1, MN2, resistors: R1, R2 form a self-bias circuit. Among them, the width-to-length ratios of MP1, MP3, and MP5 are equal, MP2, MP6, and subsequent MP8 form a current mirror to generate bias current for MP6, and the MP8 drain outputs the bias current to provide bias current for the operational amplifier.

[0038] like Figure 4As shown, this example provides an operational amplifier circuit based on chopping technology, including: PMOS tubes: MP7, MP8, MP9, MP10, MP11, NMOS tubes: MN3, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12, MN13, and an oscillator M1; the source of the PMOS tube MP7 is connected to the power supply voltage, and the drain of the PMOS tube MP7 is connected to the source of the PMOS tube MP8. The drain of the PMOS tube MP8 is connected to the source of the PMOS tubes MP9 and MP10. The gate of the PMOS tube MP9 is connected to the drain of the NMOS tubes MN12 and MN13, and the drain of the PMOS tube MP9 is connected to the source of the NMOS tube MN6, the source of MN8, and the drain of MN3. The gate of the PMOS tube MP10 is connected to the drain of the NMOS tubes MN10 and MN11, and the drain of the PMOS tube MP10 is connected to the drain of the NMOS tube MN7, the source of MN9, and the drain of MN4. The NMOS tubes MN6-MN13 are all used as switches, and the gates of the NMOS tubes MN6, MN9, MN10, and MN13 are connected to the clock signal CK of the oscillator M1, and the gates of MN7, MN8, MN11, and MN12 are connected to the clock signal CKN of the oscillator M1. The drain of the NMOS tube MN6 is connected to the source of the NMOS tube MN7, the gate of MN3, and the gate of MN4. The sources of the NMOS tubes MN3 and MN4 are grounded. The drain of the NMOS tube MN8 and the drain of MN9 are connected to the gate of the PMOS tube MP11. The source of the NMOS tube MN10 and the source of MN12 are connected to the drain of the PMOS tube MP12, the emitter of the PNP transistor Q1, and one end of the resistor R4. The source of the NMOS tube MN11 and the source of MN13 are connected to the drain of the PMOS tube MP13, one end of the resistor R5, and one end of the resistor R6. The source of the PMOS tube MP11 is connected to the power supply voltage, and the drain of MP11 is connected to the gates of the PMOS tubes MP12, MP13, and MP14, and the drain of the NMOS tube MN5. The source of the NMOS tube MN5 is grounded. The chopping technology can refer to Figure 2 .

[0039] like Figure 4 As shown, the 04 low-pass filter includes: a resistor: R3, a capacitor: C1; one end of the resistor R3 is connected to the drain of the NMOS tubes MN8 and MN9 and the gate of the PMOS tube MP11, and the other end of R3 is connected to the positive electrode of the capacitor C1 and the source of the PMOS tube MP11. The negative electrode of the capacitor C1 is grounded.

[0040] like Figure 5As shown, this example provides a reference core module circuit including: PMOS tubes: MP12, MP13, MP14, PNP transistors: Q1, Q2, resistors: R4, R5, R6, R7, R8, R9, capacitor: C2; the source of the PMOS tube MP12, the source of MP13, and the source of MP14 are connected to the power supply voltage. The other end of the resistor R4 and the other end of R6 are grounded. The other end of the resistor R5 is connected to the emitter of the PNP transistor Q2. The base and collector of the PNP transistor Q1, and the base and collector of Q2 are grounded. The drain of the PMOS tube MP14 is connected to one end of the resistor R7. The other end of the resistor R7 is connected to one end of the resistor R8 and the positive electrode of the capacitor C2. The other end of the resistor R8 is connected to one end of the resistor R9. The other end of the resistor R9 and the negative electrode of the capacitor C2 are grounded. The substrates of all the PMOS tubes are connected to VDD, and the substrates of all the NMOS tubes are connected to GND.

[0041] In bipolar transistors, the base-emitter voltage (forward voltage of the pn junction diode) has a negative temperature coefficient, and when two bipolar transistors operate at unequal current densities, the difference in their base-emitter voltages is proportional to the absolute temperature, which gives a positive temperature coefficient. By superimposing the obtained positive and negative temperature coefficients, a reference voltage that is independent of temperature can be obtained.

[0042] In this example, the width-to-length ratios of MP12, MP13, and MP14 are equal, forming a current mirror structure, so I D12 =I D13 , due to the characteristics of the operational amplifier, V X ≈V Y ≈|V BE1 |, so there is

[0043]

[0044] In this example, R4 = R6, so I C1 =I C2 , because |V BE1 |=|V BE2 |+I C2 R5, so we can get I C2 =V T ln(n / R5), so we have

[0045]

[0046] Combining (1) and (2) we can get

[0047]

[0048] In summary, the present invention is a method for eliminating offset voltage and realizing high-precision reference output voltage. By improving the design of a startup circuit, a self-bias circuit, an operational amplifier with a chopping structure, and a bandgap reference circuit, a relatively stable self-bias structure is adopted, and the operational amplifier is chopping, the offset voltage is eliminated, and high-precision output of the reference voltage is realized.

[0049] The content described above is only the specific implementation mode of the present application, and is intended to allow those skilled in the art to understand and implement the present application. For these examples, those skilled in the art can easily make multiple modifications. The general principles defined herein can be implemented in other examples without violating the spirit of the present application or exceeding its scope. Therefore, the present application will not be limited to these examples shown in this article, but will comply with the broadest scope consistent with the principles and novel features applied for herein.

Claims

1. A method for eliminating offset voltage and realizing reference high-precision output voltage, characterized in that: The method includes a startup circuit: used to drive the circuit to get rid of the degenerate working point when starting; a self-bias circuit: to ensure that subsequent circuits can obtain stable bias current and voltage; an operational amplifier with a chopping structure: to eliminate the offset voltage through the chopping technology and reduce the influence of the offset voltage on the amplifier output; a low-pass filter: to filter out the offset voltage modulated to a high frequency; and a bandgap reference module: to generate a reference voltage that does not change with temperature.

2. The method for eliminating offset voltage and realizing reference high-precision output voltage according to claim 1, characterized in that: The startup circuit comprises: PMOS tubes: MP15, MP16, and a resistor: R10; the source of the PMOS tube MP15 is connected to the power supply voltage, the drain is connected to the gate of the PMOS tube MP16 and one end of the resistor R10, the gate of the PMOS tube MP15 is connected to the gate of the PMOS tube MP1, the other end of the resistor R10 is grounded, the source of the PMOS tube MP16 is connected to the power supply voltage, and the drain of the PMOS tube MP16 serves as the output end of the startup circuit; the substrate of the PMOS tube is connected to VDD, and the substrate of the NMOS tube is connected to GND.

3. The method for eliminating offset voltage and realizing reference high-precision output voltage according to claim 1, characterized in that: The self-bias circuit comprises: PMOS tubes: MP1, MP2, MP3, MP4, MP5, MP6, NMOS tubes: MN1, MN2, resistors: R1, R2; the source of the PMOS tube MP1 is connected to the power supply voltage, the gate of the PMOS tube MP1 is connected to the gates of the PMOS tubes MP3, MP5, MP7, the drain of the PMOS tube MP1 is connected to the source of the PMOS tube MP2, the gate of the PMOS tube MP3 is connected to the gates of the PMOS tubes MP6, MP8, the drain of the PMOS tube MP2 is connected to the gate of the PMOS tube MP2, the drain of the NMOS tube MN1 is connected, the source of the NMOS tube MN1 is connected to one end of the resistor R1, the gate of the NMOS tube MN1 is connected to the gate of the PMOS tube MP3, and the drain of the PMOS tube MP2 is connected to the gate of the PMOS tube MP2. The gates of the NMOS tubes MN2 and MN5 are connected, and the other end of the resistor R1 is grounded; the source of the PMOS tube MP3 is connected to the power supply voltage, the drain of the PMOS tube MP3 is connected to the gate of the PMOS tube MP4, one end of the resistor R2 is connected, and the other end of the resistor R2 is grounded, the source of the PMOS tube MP4 is connected to the power supply voltage, the drain of the PMOS tube MP4 is connected to the drain of the PMOS tube MP6, and the drain and gate of the NMOS tube MN2 are connected; the source of the PMOS tube MP5 is connected to the power supply voltage, the drain of the PMOS tube MP5 is connected to the source of the PMOS tube MP6; the source of the NMOS tube MN2 is grounded; the substrate of the PMOS tube is connected to VDD, and the substrate of the NMOS tube is connected to GND.

4. The method for eliminating offset voltage and realizing reference high-precision output voltage according to claim 1, characterized in that: The operational amplifier with a chopper structure comprises: PMOS tubes: MP7, MP8, MP9, MP10, MP11, NMOS tubes: MN3, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12, MN13, and an oscillator M1; the source of the PMOS tube MP7 is connected to the power supply voltage, the drain of the PMOS tube MP7 is connected to the source of the PMOS tube MP8; the drain of the PMOS tube MP8 is connected to the source of the PMOS tubes MP9 and MP10; the PMOS tube MP8 is connected to the source of the PMOS tubes MP9 and MP10; The gate of the S transistor MP9 is connected to the drains of the NMOS transistors MN12 and MN13, and the drain of the PMOS transistor MP9 is connected to the source of the NMOS transistor MN6, the source of MN8, and the drain of MN3; the gate of the PMOS transistor MP10 is connected to the drains of the NMOS transistors MN10 and MN11, and the drain of the PMOS transistor MP10 is connected to the drain of the NMOS transistor MN7, the source of MN9, and the drain of MN4; the NMOS transistors MN6-MN13 are all used as switches, and the NMOS transistors MN6, MN9, MN10, and M The gate of N13 is connected to the clock signal CK of the oscillator M1, and the gates of MN7, MN8, MN11, and MN12 are connected to the clock signal CKN of the oscillator M1; the drain of NMOS tube MN6 is connected to the source of NMOS tube MN7, the gate of MN3, and the gate of MN4; the sources of NMOS tubes MN3 and MN4 are grounded; the drain of NMOS tube MN8 and the drain of MN9 are connected to the gate of PMOS tube MP11; the source of NMOS tube MN10 and the source of MN12 are connected to the drain of PMOS tube MP12, and the drain of PMOS tube MP13. The emitter of the NP-type transistor Q1 is connected to one end of the resistor R4; the source of the NMOS tube MN11 and the source of MN13 are connected to the drain of the PMOS tube MP13, one end of the resistor R5, and one end of the resistor R6; the source of the PMOS tube MP11 is connected to the power supply voltage, the drain of MP11 is connected to the gates of the PMOS tubes MP12, MP13, and MP14, and the drain of the NMOS tube MN5; the source of the NMOS tube MN5 is grounded; the substrate of the PMOS tube is connected to VDD, and the substrate of the NMOS tube is connected to GND.

5. The method for eliminating offset voltage and realizing reference high-precision output voltage according to claim 1, characterized in that: The low-pass filter includes: a resistor: R3, a capacitor: C1; one end of the resistor R3 is connected to the drain of the NMOS tubes MN8 and MN9 and the gate of the PMOS tube MP11, and the other end of R3 is connected to the positive electrode of the capacitor C1 and the source of the PMOS tube MP11; the negative electrode of the capacitor C1 is grounded.

6. The method for eliminating offset voltage and realizing reference high-precision output voltage according to claim 1, characterized in that: The bandgap reference module comprises: PMOS tubes: MP12, MP13, MP14, PNP transistors: Q1, Q2, resistors: R4, R5, R6, R7, R8, R9, and capacitor: C2; the source of the PMOS tube MP12, the source of MP13, and the source of MP14 are connected to the power supply voltage; the other end of the resistor R4 and the other end of R6 are grounded; the other end of the resistor R5 is connected to the emitter of the PNP transistor Q2; the base and collector of the PNP transistor Q1, and the base and collector of Q2 are grounded; the drain of the PMOS tube MP14 is connected to one end of the resistor R7; the other end of the resistor R7 is connected to one end of the resistor R8 and the positive electrode of the capacitor C2; the other end of the resistor R8 is connected to one end of the resistor R9; the other end of the resistor R9 and the negative electrode of the capacitor C2 are grounded; the substrate of the PMOS tube is connected to VDD, and the substrate of the NMOS tube is connected to GND.

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