Memory configuration method and device, electronic equipment and storage medium

Abstract

The invention provides a memory configuration method and device, electronic equipment and a storage medium, and is applied to the technical field of computers, the method configures a memory based on a pressure test result of the memory, if the memory passes a pressure test, a DM function of the memory is enabled, the influence of a non-aligned write request on memory performance is reduced, and on the contrary, the memory performance is improved. If the memory does not pass the pressure test, the DBI function of the memory is enabled, the influence of the high-speed signal crosstalk of the bus on the stability of the memory is reduced by utilizing the characteristics of the DBI function, and meanwhile, the power consumption of the memory is reduced, so that the memory configuration method provided by the invention flexibly adjusts the configuration mode of the memory based on the pressure test result of the memory; the memory is ensured to be matched with the application environment, and the influence of the application environment is overcome, so that the electronic equipment is in a performance optimal state in the application environment, the overall performance of the electronic equipment is ensured to meet the use requirement of a user, and the use experience of the user is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a memory configuration method, device, electronic device and storage medium. Background Art

[0002] With the continuous development of software technology, more and more software programs are installed in electronic devices. The normal operation of these software programs mostly requires the support of memory. The stability and operating status of memory have a direct impact on the overall performance of electronic devices. Therefore, memory has become one of the indispensable components of electronic devices.

[0003] However, in the actual application of electronic devices, the data transmission performance of the memory will be affected by signal crosstalk, and frequent memory access may aggravate the signal crosstalk, which in turn will more seriously affect the memory operation performance, resulting in a decline in the overall performance of the electronic device and affecting the user experience. Summary of the invention

[0004] In view of this, the present application is committed to providing a memory configuration method, device, electronic device and computer-readable storage medium to solve the problem in the prior art that reduced memory performance leads to reduced overall performance of electronic devices, affecting user experience.

[0005] In a first aspect, the present application provides a memory configuration method, comprising:

[0006] Stress test the memory;

[0007] If the memory passes the stress test, enabling a data mask DM function of the memory;

[0008] If the memory fails the stress test, a data bus inversion DBI function of the memory is enabled.

[0009] In an optional implementation, enabling the DBI function of the memory includes:

[0010] Enable the DBI function of the read request of the memory.

[0011] In an optional implementation, the memory configuration method provided in the first aspect of the present application further includes:

[0012] When the read request DBI function is enabled, performing a stress test on the memory;

[0013] If the memory passes the stress test, enabling the DM function of the memory;

[0014] If the memory fails the stress test, a write request DBI function of the memory is enabled.

[0015] In an optional implementation, enabling the DBI function of the memory includes:

[0016] Enable the write request DBI function of the memory.

[0017] In an optional implementation, the memory configuration method provided in the first aspect of the present application further includes:

[0018] When the write request DBI function is enabled, performing a stress test on the memory;

[0019] If the memory fails the stress test, a read request DBI function of the memory is enabled.

[0020] In an optional implementation, the memory configuration method provided in the first aspect of the present application further includes:

[0021] When a DM function of the memory is enabled, performing a bandwidth test on the memory;

[0022] If the test result of the bandwidth test indicates that the read and write performance of the memory is not improved, the DM function is disabled.

[0023] In an optional implementation, the memory configuration method provided in the first aspect of the present application further includes:

[0024] In response to the start-up instruction, the memory is initialized.

[0025] In a second aspect, the present application provides a memory configuration device, comprising:

[0026] Stress test module, used to perform stress test on memory;

[0027] The configuration module is used to enable the data mask DM function of the memory if the memory passes the stress test, and to enable the data bus inversion DBI function of the memory if the memory fails the stress test.

[0028] In a third aspect, the present application provides an electronic device, including:

[0029] Memory and processor;

[0030] Wherein, the memory is used to store programs;

[0031] The processor is used to implement the memory configuration method as described in any one of the first aspects of the present application by running the program in the memory.

[0032] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the memory configuration method as described in any one of the first aspects of the present application is implemented.

[0033] Based on the above content, the memory configuration method provided by the present application configures the memory based on the memory stress test results. If the memory passes the stress test, it means that the bus high-speed signal crosstalk does not have a significant impact on the memory operation. In this case, the DM function of the memory is enabled to reduce the impact of non-aligned write requests on memory performance. On the contrary, if the memory fails the stress test, the DBI function of the memory is enabled, and the characteristics of the DBI function are used to reduce the impact of the bus high-speed signal crosstalk on memory stability, while reducing memory power consumption. It can be seen that the memory configuration method provided by the present application flexibly adjusts the memory configuration method based on the memory stress test results to ensure that the memory matches the application environment and overcomes the impact of the application environment, so that the memory is in the optimal performance state in the application environment, ensuring that the overall performance of the electronic device meets the user's usage needs and improves the user's usage experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 It is a flow chart of a memory configuration method provided by an embodiment of the present invention.

[0036] Figure 2 It is a flowchart of another memory configuration method provided by an embodiment of the present invention.

[0037] Figure 3 This is a flowchart of another memory configuration method provided by an embodiment of the present invention.

[0038] Figure 4 It is a structural block diagram of a memory configuration device provided by an embodiment of the present invention.

[0039] Figure 5 It is a structural block diagram of another memory configuration device provided by an embodiment of the present invention.

[0040] Figure 6 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0042] As mentioned above, with the continuous development of software technology, more and more software programs are installed in electronic devices, and the normal operation of these software programs mostly requires the support of memory. The stability and operating status of the memory have a direct impact on the overall performance of the electronic device.

[0043] In the actual application of electronic devices, memory access requests can be roughly divided into address-aligned access requests and address-unaligned access requests. For address-aligned access requests, the corresponding address space in the memory can be directly read and written, such as directly writing data to a certain memory address or directly reading data stored in a certain memory address. The memory access process is relatively simple; for address-unaligned access requests, multiple access operations will be added. Taking address-unaligned memory write requests as an example, first, it is necessary to read the data stored in the corresponding memory address in an address-aligned manner, and then convert the obtained data into a format in an address-aligned manner, and finally write the format-converted data in an address-aligned manner. It can be seen that address-unaligned access requests will increase the read, modify, and write operations in the memory access process, which will not only increase the bus overhead and reduce the memory performance, but also a large number of read and write operations will result in a huge amount of bus data transmission data, aggravating the adverse effect of signal crosstalk on memory stability, which may further reduce the operating performance of the memory, resulting in a decline in the overall performance of the electronic device and affecting the user's experience.

[0044] To solve the above technical problems, the present application provides a memory configuration method, which configures the memory based on the stress test results of the memory. If the memory passes the stress test, the DM function of the memory is enabled to reduce the impact of non-aligned write requests on memory performance. On the contrary, if the memory fails the stress test, the DBI function of the memory is enabled, and the characteristics of the DBI function are used to reduce the impact of bus high-speed signal crosstalk on memory stability, while reducing memory power consumption. It can be seen that the memory configuration method provided by the present application flexibly adjusts the memory configuration method based on the stress test results of the memory, ensures that the memory matches the application environment, overcomes the influence of the application environment, and is in the optimal performance state in the application environment, ensuring that the overall performance of the electronic device meets the user's usage needs and improves the user's usage experience.

[0045] The memory configuration method provided in this application is applied to a processor that can access a memory controller, for example, a processor in a system on chip, or an independently set processor, of course, other controllers that can configure the working mode and function of the memory, and in some cases, a remote server. Figure 1 , the memory configuration method provided in this application includes the following steps.

[0046] S100, perform a stress test on the memory.

[0047] The stress test mentioned in this application mainly refers to the stress test of the read and write functions of the memory. In the actual testing process, some memory stress test items such as multiple bit flips that are prone to errors can be used to test the memory. Of course, other test items that are prone to quick errors during memory access can also be selected for combination. All test items that can quickly obtain test results and can accurately reflect the stress resistance of the memory are optional. They are not listed one by one here. Please refer to the relevant technical implementation for details.

[0048] S110, determining whether the pressure test is passed according to the pressure test result, if the pressure test is passed, executing S120, if the pressure test is not passed, executing S130.

[0049] After obtaining the stress test result, determine whether the memory has passed the stress test based on the stress test result. It is understandable that different test items will result in different test results, and whether the stress test has passed needs to be determined in combination with the test results of the specific test items selected. As an optional implementation, after completing the test of all test items, obtain the memory data obtained after the memory access. If the obtained memory data is consistent with the expected data, it can be determined that the memory has passed the stress test and continue to execute S120. On the contrary, if the obtained memory data is inconsistent with the expected data, it can be determined that the memory has not passed the stress test and continue to execute S130.

[0050] S120, enable the DM function of the memory.

[0051] When it is determined based on the stress test results that the memory has passed the stress test, it means that the bus high-speed signal crosstalk has little impact on the memory stability, and enabling the DBI (Data Bus Inversion) function does not help much in improving memory performance. Based on this, this method enables the DM (Data Mask) function of the memory.

[0052] The DM function is mainly used to implement data masking of memory write requests. In short, the DM function can be used to mask unnecessary data during data transmission. In some applications, each mask bit corresponds to a byte of memory data. When the corresponding mask bit is 0, the memory data is valid. On the contrary, when the corresponding mask bit is 1, the memory data is masked, that is, invalid. As for other relevant information of the DM function, please refer to the relevant technology. This application does not limit the specific working process of the DM function. By enabling the DM function of the memory, the read, modify, and write operations caused by a large number of address non-aligned memory accesses can be reduced, thereby reducing bus overhead and improving memory access performance.

[0053] In a possible implementation, the DM function of the memory is configured by a preset first mode register. When the first mode register is written with a first value representing that the DM function is turned on, the DM function is enabled. Correspondingly, when the first mode register is written with a second value representing that the DM function is turned off, the DM function is disabled. Based on this, in practical applications, the DM function of the memory can be enabled by writing the first value to the first mode register. Of course, in practical applications, whether the DM function of the memory is enabled can also be achieved by other methods, which also fall within the scope of protection of this application without exceeding the core idea of ​​this application.

[0054] S130, enable the DBI function of the memory.

[0055] Based on the basic principle of data transmission based on the current memory, it can be known that when the data to be transmitted is at a high level, there is no current flow in the data transmission process, and the power consumption is naturally low. On the contrary, when the data to be transmitted is at a low level, current will flow in the data transmission process, and the corresponding power consumption is relatively high. Therefore, in order to reduce power consumption, high levels should be transmitted as much as possible. The DBI function is used to achieve the flipping of low levels to high levels, thereby achieving the purpose of reducing power consumption. Not only that, it also overcomes the influence of high-speed signal crosstalk on the data transmission process. It should be noted that after obtaining the data, the data receiver will also flip the data in the opposite direction to obtain the correct data. The specific working principle and practical application of the DBI function can be realized by referring to the relevant technology, which will not be described in detail here.

[0056] When it is determined based on the stress test results that the memory has failed the stress test, it indicates that the impact of high-speed signal crosstalk on memory operation is very obvious. Therefore, the memory configuration method provided in this application enables the DBI function of the memory to reduce the impact of high-speed signal crosstalk on memory stability through the DBI function of the memory, and at the same time, reduce power consumption during data transmission.

[0057] Different from the DM function, the DBI function can be further subdivided into a write request DBI function and a read request DBI function. Therefore, two mode registers, namely the second mode register and the third mode register, need to be preset to clearly indicate the different enabling states of the write request DBI function and the read request DBI function.

[0058] Based on the above content, in an optional implementation, when the second mode register is written with a first value representing that the read request DBI function is turned on, the read request DBI function is enabled, and correspondingly, when the second mode register is written with a second value representing that the read request DBI function is turned off, the read request DBI function is disabled. Correspondingly, when the third mode register is written with a first value representing that the write request DBI function is turned on, the write request DBI function is enabled, and correspondingly, when the third mode register is written with a second value representing that the write request DBI function is turned off, the write request DBI function is disabled.

[0059] Based on this, the corresponding DM function can be enabled by writing the first value to the second model register and the third model register. Of course, in practical applications, whether the memory DBI function is enabled can also be achieved in other ways, which also fall within the scope of protection of this application without exceeding the core idea of ​​this application.

[0060] It should be noted that, in actual applications, at least one of the read request DBI function and the write request DBI function can be enabled according to configuration requirements. The specific configuration process will be expanded in subsequent embodiments and will not be described in detail here. However, it is certain that whether the read request DBI function or the write request DBI function is enabled, or both the read request DBI function and the write request DBI function are enabled at the same time, the effect of reducing the impact of high-speed signal crosstalk on memory stability and reducing data transmission power consumption can be achieved.

[0061] To sum up, the memory configuration method provided by the present application configures the memory based on the memory stress test results. If the memory passes the stress test, it means that the bus high-speed signal crosstalk has little effect on the memory operation. In this case, the DM function of the memory is enabled to reduce the impact of non-aligned write requests on memory performance. On the contrary, if the memory fails the stress test, the DBI function of the memory is enabled, and the characteristics of the DBI function are used to reduce the impact of the bus high-speed signal crosstalk on memory stability, while reducing memory power consumption. It can be seen that the memory configuration method provided by the present application flexibly adjusts the memory configuration method based on the memory stress test results to ensure that the memory matches the application environment and overcomes the impact of the application environment, so that the memory is in the optimal performance state in the application environment, ensuring that the overall performance of the electronic device meets the user's usage needs and improves the user's usage experience.

[0062] Further, based on the above embodiments, the present application provides another memory configuration method, see Figure 2 As shown, the memory configuration method provided in this embodiment includes the following steps.

[0063] S200, stress test the memory.

[0064] In an optional implementation, S200 may refer to Figure 1 The implementation of the relevant contents of S100 in the illustrated embodiment will not be repeated here.

[0065] S210, determining whether the pressure test is passed according to the pressure test result, if the pressure test is passed, executing S260, if the pressure test is not passed, executing S220.

[0066] After obtaining the stress test results, determine whether the memory has passed the stress test based on the stress test results. As an optional implementation, after completing the testing of all test items, obtain the memory data obtained after the memory access. If the obtained memory data is consistent with the expected data, it can be determined that the memory has passed the stress test and continue to execute S260. On the contrary, if the obtained memory data is inconsistent with the expected data, it can be determined that the memory has not passed the stress test and continue to execute S220.

[0067] S220 , enabling the memory read request DBI function.

[0068] As mentioned above, whether enabling the read request DBI function or the write request DBI function, the impact of high-speed signal crosstalk on memory stability and the power consumption of data transmission can be reduced. Based on this, in this embodiment, when the memory fails the first stress test, the read request DBI function of the memory is enabled. It is hoped that this method can improve the memory's anti-interference ability to high-speed signals, improve the memory's stability and memory access performance.

[0069] For the specific implementation method of enabling the memory read request DBI function, please refer to Figure 1 The relevant contents of S130 in the illustrated embodiment will not be repeated here.

[0070] S230 , performing a stress test on the memory while enabling the read request DBI function.

[0071] After enabling the DBI function of memory read requests, it is necessary to verify whether the memory access performance is effectively improved. Therefore, a second stress test is performed on the memory. For the specific implementation process of the memory stress test, please refer to Figure 1 The relevant contents of S100 in the illustrated embodiment will not be repeated here.

[0072] S240, determining whether the pressure test is passed according to the pressure test result, if the pressure test is passed, executing S260, if the pressure test is not passed, executing S250.

[0073] After obtaining the stress test result, determine whether the memory passes the stress test based on the stress test result. If the memory passes the stress test, it means that when the read request DBI function is enabled alone, the impact of high-speed signal crosstalk on memory stability is already very small. In this case, S260 can be further executed. On the contrary, if the memory fails the stress test, it means that when the read request DBI function is enabled alone, the impact of high-speed signal crosstalk on memory stability is still very large, and the memory stability has not been significantly improved. It is necessary to further execute S250, that is, to enable the write request DBI function of the memory.

[0074] S250, enable the memory write request DBI function.

[0075] When the memory read request DBI function is enabled but the memory fails the second stress test, the memory write request DBI function is further enabled. For the specific implementation method of enabling the write request DBI function, please refer to Figure 1 The relevant contents of the embodiment shown are implemented and will not be repeated here.

[0076] S260, enable the DM function of the memory.

[0077] Combination Figure 2 As shown, during the process of performing stress tests on the memory twice at S210 and S240, if the memory passes any stress test, S260 will be further executed, that is, the DM function of the memory will be enabled. As mentioned above, the DM function and the DBI function can improve memory performance from different dimensions. Therefore, when the memory passes the stress test, this method further enables the DM function to better and more comprehensively improve the memory performance.

[0078] In an optional implementation, the specific implementation steps of S260 can refer to Figure 1 The implementation of the relevant contents of S120 in the illustrated embodiment will not be repeated here.

[0079] It should be noted that, based on the above content and related technologies, the DM function belongs to data shielding in the memory write direction, and the DBI function is subdivided into a write request DBI function and a read request DBI function, that is, bus data flipping can be realized in both the read and write directions. However, the DM function and the write request DBI function are mutually exclusive in the memory write direction and cannot be enabled at the same time. Based on this, this method first enables the read request DBI function when the S210 memory fails the stress test. The purpose is to further enable the DM function if the S240 memory passes the stress test, thereby improving the memory performance more comprehensively.

[0080] Accordingly, if the memory fails the stress test at S240, it indicates that the high-speed signal crosstalk has a great impact on the memory stability, and it is necessary to further execute S250 to enable the memory write request DBI function, thereby fully enabling the DBI function and overcoming the impact of the high-speed signal crosstalk on the memory stability as much as possible. It is understandable that once S250 is executed and the memory write request DBI function is enabled, the DM function can no longer be enabled, and the method ends when it executes to S250.

[0081] Understandably, Figure 2 The illustrated embodiment essentially provides three feasible solutions to improve memory performance. The first is to enable the DM function of the memory when the S210 memory passes the first stress test, and apply it to scenarios where high-speed signal crosstalk has almost no impact, and improve memory performance simply through the DM function; the second is to enable the read request DBI function and the DM function, and apply it to scenarios where high-speed signal crosstalk has a certain impact but can be overcome by enabling the read request DBI function, and improve memory stability and memory performance through the read request DBI function and the DM function; the third is to enable the read request DBI function and the write request DBI function, and apply it to scenarios where high-speed signal crosstalk is obvious, and improve memory stability by fully enabling the DBI function, thereby improving the performance of the memory during data transmission.

[0082] S270: When the DM function is enabled, perform a bandwidth test on the memory.

[0083] Based on the above content, it can be known that after executing S260, the memory configuration method provided in this embodiment has improved the memory performance through any of the above three feasible solutions, and the method corresponding to S200 to S260 can be applied as an independent embodiment. As a preferred implementation, based on the above steps, this embodiment further provides S270 and S280.

[0084] The bandwidth test of the memory can be implemented in a variety of ways. In an optional implementation, the memory can be read and written within a preset time length, and the corresponding memory access data volume can be counted. The ratio of the obtained memory access data volume to the preset time length is the bandwidth test result. In another optional implementation, the memory can be accessed according to the preset data volume, and the statistical time required to complete the access to the preset data volume can be counted. The ratio of the preset data volume to the obtained statistical time length is the bandwidth test result. Of course, the memory bandwidth with the DM function enabled can also be tested in other ways, which will not be described in detail here. This application does not limit the specific implementation process of the memory bandwidth test.

[0085] S280: If the test result of the bandwidth test indicates that the read and write performance of the memory is not improved, disable the DM function.

[0086] As mentioned above, the DM function can reduce the read, modify, and write operations caused by a large number of non-aligned memory accesses, thereby reducing bus overhead and improving memory access performance. However, the DM function will increase the logical overhead of the memory controller to a certain extent. Therefore, if the test results of the bandwidth test indicate that the read and write performance of the memory has not improved, there is no need to enable the DM function, which will cause an unnecessary increase in the logical overhead of the memory controller. Therefore, the DM function needs to be turned off. On the contrary, if the test results of the bandwidth test indicate that the read and write performance of the memory has improved, that is, the bandwidth has increased and the increased logical overhead of the memory controller is acceptable, then the DM function should be kept enabled.

[0087] To summarize, the memory configuration method provided in this embodiment provides three optional memory configuration schemes compared to the previous embodiments, which can flexibly enable the DBI function and the DM function according to the results of the stress test and the bandwidth test during the configuration process, thereby ensuring that the memory matches the application environment and overcomes the influence of the application environment, so as to achieve the optimal performance in the application environment, ensure that the overall performance of the electronic device meets the user's usage requirements, and improve the user's usage experience.

[0088] Furthermore, this application provides another memory configuration method, see Figure 3 As shown, the memory configuration method provided in this embodiment includes the following steps.

[0089] S300, perform a stress test on the memory.

[0090] In an optional implementation, the specific implementation of S300 can refer to Figure 1 The relevant contents of S100 in the illustrated embodiment will not be repeated here.

[0091] S310, determining whether the pressure test is passed according to the pressure test result, if the pressure test is passed, executing S360, if the pressure test is not passed, executing S320.

[0092] In an optional implementation, the specific implementation of S310 can refer to Figure 1 The relevant contents of S110 in the illustrated embodiment will not be repeated here.

[0093] S320, enable the memory write request DBI function.

[0094] As mentioned above, whether enabling the read request DBI function or the write request DBI function, the effect of reducing the impact of high-speed signal crosstalk on memory stability and reducing data transmission power consumption can be achieved. Based on this, in this embodiment, when the memory fails the first stress test, this method first enables the write request DBI function, hoping to improve the memory's anti-interference ability to high-speed signals and improve the memory's stability and memory access performance. As for the specific implementation method of enabling the write request DBI function, please refer to Figure 1 The relevant contents of S130 in the illustrated embodiment will not be repeated here.

[0095] S330: When the write request DBI function is enabled, perform a stress test on the memory.

[0096] When the DBI function of memory write request is enabled, the memory is subjected to a second stress test. The specific implementation of the stress test can also be referred to Figure 1 The relevant contents of S100 in the illustrated embodiment will not be repeated here.

[0097] S340. Determine whether the pressure test is passed according to the pressure test result. If the pressure test is passed, execute S360. If the pressure test is not passed, execute S350.

[0098] In an optional implementation, the specific implementation of S340 can refer to Figure 1 The relevant contents of S110 in the illustrated embodiment will not be repeated here.

[0099] It should be noted that if the memory passes the second stress test when the write request DBI function is enabled, it means that enabling the write request DBI function alone can offset the impact of high-efficiency signal crosstalk on memory stability. In this case, you can exit the current configuration process.

[0100] S350, enable the memory read request DBI function.

[0101] As mentioned above, whether enabling the read request DBI function or the write request DBI function, the effect of reducing the impact of high-speed signal crosstalk on memory stability and reducing data transmission power consumption can be achieved. After the aforementioned steps, that is, the write request DBI function of the memory has been enabled, if the memory still fails the stress test, it means that the impact of high-speed signal crosstalk on memory stability is more obvious. In this case, the method further enables the read request DBI function to better reduce the impact of high-speed signal crosstalk on memory stability and improve memory performance.

[0102] S360, enable the DM function of the memory.

[0103] If the memory passes the stress test during the first stress test of the memory by S310, it means that the influence of high-speed signal crosstalk on the memory stability is negligible. In this case, this method directly enables the memory DM function to improve the memory performance through the DM function.

[0104] It can be understood that, when the memory fails the first stress test, the configuration method provided in this embodiment first enables the write request DBI function. Since the write request DBI function and the DM function cannot be enabled at the same time, after enabling the write request DBI function through S320, if the memory fails the second stress test, only the read request DBI function can be further enabled, and the DM function cannot be enabled. Accordingly, even if the memory passes the second stress test in S320, the DM function cannot be enabled.

[0105] Further, referring to the foregoing content, when the DM function of the memory is enabled, the memory configuration method provided in this embodiment can also further perform a bandwidth test on the memory to verify whether enabling the DM function improves the read and write performance of the memory. If the test result of the bandwidth test indicates that the read and write performance of the memory is not improved, the DM function can be turned off. On the contrary, if the test result of the bandwidth test indicates that the read and write performance of the memory is improved, the DM function is kept enabled.

[0106] To sum up, the memory configuration method provided in this embodiment can enable the DM function only if the memory passes the first stress test. If the memory fails the first stress test, the write request DBI function and the read request DBI function will be enabled according to the subsequent progress. This method flexibly enables the DBI function and the DM function according to the stress test results during the configuration process, ensuring that the memory matches the application environment and overcomes the influence of the application environment, so that the memory is in the optimal performance state in the application environment, ensuring that the overall performance of the electronic device meets the user's usage requirements and improves the user's usage experience.

[0107] Furthermore, for the memory configuration method provided in any of the above embodiments, before the actual execution, especially during the first power-on startup of the memory, the memory can also be initialized in response to the startup instruction of the memory, and after the initialization is completed, the memory configuration method provided in any of the above embodiments can be continued to be executed. As for the specific implementation process of initializing the memory, reference can be made to the relevant technology and will not be described in detail here.

[0108] It should be noted that the memory configuration method provided in any of the above embodiments can be used as a firmware program of the processor or as other forms of executable programs for the processor to call. As long as the implementation method can be reliably called by the processor when needed to improve memory performance, it is optional and also falls within the scope of protection of this application without exceeding the core idea of ​​this application.

[0109] The memory configuration device provided by the present invention is introduced below. The memory configuration device provided by the present invention belongs to the same application concept as the memory configuration method provided by the embodiment of the present application, can execute the memory configuration method provided by any embodiment of the present application, and has the corresponding functional modules and beneficial effects of executing the memory configuration method. For technical details not described in detail in this embodiment, please refer to the memory configuration method provided by the embodiment of the present application, and will not be repeated here.

[0110] See also Figure 4 , Figure 4 : is a structural block diagram of a memory configuration device provided by the present application. The memory configuration device provided by this embodiment includes:

[0111] The stress test module 10 is used to perform stress test on the memory;

[0112] The configuration module 20 is used to enable the data mask DM function of the memory if the memory passes the stress test, and to enable the data bus inversion DBI function of the memory if the memory fails the stress test.

[0113] For further information, see Figure 5 ,exist Figure 4 Based on the embodiment shown, the memory configuration device provided in this embodiment further includes:

[0114] The performance test module 30 is used to test the bandwidth of the memory;

[0115] The initialization module 40 is used to respond to the startup instruction and initialize the memory.

[0116] Below, reference Figure 6To describe the electronic device provided by the embodiment of the present invention, the electronic device provided by the embodiment may include: at least one processor 100, at least one communication interface 200, at least one memory 300 and at least one communication bus 400;

[0117] In the embodiment of the present invention, the number of the processor 100, the communication interface 200, the memory 300, and the communication bus 400 is at least one, and the processor 100, the communication interface 200, and the memory 300 communicate with each other through the communication bus 400; obviously, Figure 6 The communication connections shown for the processor 100, the communication interface 200, the memory 300, and the communication bus 400 are merely optional;

[0118] Optionally, the communication interface 200 may be an interface of a communication module, such as an interface of a GSM module; the processor 100 may be a central processing unit CPU, or an application specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0119] The memory 300 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0120] The processor 100 is specifically used to execute the application program in the memory to implement the steps of the memory configuration method described above.

[0121] In some embodiments, this embodiment further provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash disk, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, etc., in which one or more instructions for implementing the above steps are stored. When the one or more instructions are executed by one or more processors, the processors execute the memory configuration method described above. For the relevant specific implementation, please refer to the above description, which will not be repeated here.

[0122] In addition to the above-mentioned methods and devices, an embodiment of the present application may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the memory configuration method according to various embodiments of the present application described in the above content of this specification.

[0123] The computer program product may be written in any combination of one or more programming languages ​​to write program codes for performing the operations of the embodiments of the present application, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0124] Those skilled in the art will appreciate that the contents disclosed in this disclosure may be subject to various modifications and improvements. For example, the various devices or components described above may be implemented by hardware, or by software, firmware, or a combination of some or all of the three.

[0125] In addition, although the present disclosure makes various references to certain units in the system according to embodiments of the present disclosure, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0126] Flowcharts are used in this disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the preceding or following steps are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may also be added to these processes.

[0127] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, etc. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of a software functional module. The present disclosure is not limited to any particular form of combination of hardware and software.

[0128] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined as such herein.

[0129] The above is an explanation of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure are described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. It should be understood that the above is an explanation of the present disclosure and should not be considered to be limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A memory configuration method, characterized in that: include: Stress test the memory; If the memory passes the stress test, enabling a data mask DM function of the memory; If the memory fails the stress test, a data bus inversion DBI function of the memory is enabled.

2. The memory configuration method according to claim 1, characterized in that: Enable the DBI function of the memory, including: Enable the DBI function of the read request of the memory.

3. The memory configuration method according to claim 2, characterized in that: Also includes: When the read request DBI function is enabled, performing a stress test on the memory; If the memory passes the stress test, enabling the DM function of the memory; If the memory fails the stress test, a write request DBI function of the memory is enabled.

4. The memory configuration method according to claim 1, characterized in that: Enable the DBI function of the memory, including: Enable the write request DBI function of the memory.

5. The memory configuration method according to claim 4, characterized in that: Also includes: When the write request DBI function is enabled, performing a stress test on the memory; If the memory fails the stress test, a read request DBI function of the memory is enabled.

6. The memory configuration method according to claim 1, characterized in that: Also includes: When a DM function of the memory is enabled, performing a bandwidth test on the memory; If the test result of the bandwidth test indicates that the read and write performance of the memory is not improved, the DM function is disabled.

7. The memory configuration method according to any one of claims 1 to 6, characterized in that: Also includes: In response to the start-up instruction, the memory is initialized.

8. A memory configuration device, characterized in that: include: Stress test module, used to perform stress test on memory; The configuration module is used to enable the data mask DM function of the memory if the memory passes the stress test, and to enable the data bus inversion DBI function of the memory if the memory fails the stress test.

9. An electronic device, characterized in that: include: Memory and processor; Wherein, the memory is used to store programs; The processor is used to implement the memory configuration method as described in any one of claims 1 to 7 by running the program in the memory.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the processor, the memory configuration method according to any one of claims 1 to 7 is implemented.

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