Composite communication circuit

Abstract

The invention relates to a composite communication circuit which comprises a first register unit, a second register unit, a timer unit and a state machine circuit. The first register unit is electrically connected to the timer unit, receives a clock signal of the timer unit, and receives and stores external data; the second register unit is electrically connected with the first register unit, receives the data in the first register unit, stores the data and sends the data to the outside; the state machine circuit sends state signals to the first register unit, the second register unit and the timer unit; when the timer unit sends out an overflow signal, the first register unit, the second register unit and the timer unit carry out data processing. The circuit is flexible in configuration, the state machine circuit adjusts the working state of the circuit in real time, switching and combination of different communication protocols are achieved, and hardware resource waste caused by the fact that a traditional MCU supports multiple protocols is avoided.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a composite communication circuit. Background Art

[0002] With the rapid development of information technology, the requirements for data transmission speed, processing power and stability in the field of electronic communications are increasing. Generally, general-purpose microcontrollers (MCUs) need to support various communication protocols such as universal asynchronous serial receiver / transmitter (UART), low-power universal asynchronous serial receiver / transmitter (LPUART), universal synchronous / asynchronous serial receiver / transmitter (USART), serial peripheral interface (SPI), integrated circuit built-in audio bus (I2S), serial audio interface (SAI), integrated circuit bus (I2C), two-wire serial peripheral interface (DSPI), four-wire serial peripheral interface (QSPI) and contact smart card communication interface (ISO7816).

[0003] However, when using it, customers basically only use one or two communication protocols. This will make the entire MCU area very large, causing serious waste, and customers will also pay extra fees for unused circuits. Summary of the invention

[0004] In view of this, the present application proposes a composite communication circuit to solve the above problems.

[0005] According to one aspect of the present application, there is provided a composite communication circuit, comprising: a first register unit, a second register unit, a timer unit and a state machine circuit;

[0006] The first register unit is electrically connected to the timer unit, receives a clock signal of the timer unit, and is adapted to receive and store external data;

[0007] The second register unit is electrically connected to the first register unit, receives data in the first register unit, and is suitable for storing and sending data to the outside;

[0008] The state machine circuit is electrically connected to the first register unit, the second register unit and the timer unit, and sends a state signal to the first register unit, the second register unit and the timer unit;

[0009] When the timer unit issues an overflow signal, the first register unit, the second register unit and the timer unit perform data processing.

[0010] In a possible implementation, the first register unit includes: a receiving shift register;

[0011] The receiving shift register is electrically connected to the SCK interface, the receiving shift register is electrically connected to the SDRX interface, the SCK interface controls the receiving shift register, and receives the data transmitted by the SDRX interface; and the receiving shift register is electrically connected to the timer unit, and receives the clock signal; and the receiving shift register is electrically connected to the state machine circuit, and obtains the state signal,

[0012] When the timer unit sends out an overflow signal, the data in the receiving shift register is processed.

[0013] In a possible implementation, the second register unit includes: a sending shift register;

[0014] The transmitting shift register is electrically connected to the receiving register, and the transmitting shift register is electrically connected to the SCK interface, and the transmitting shift register is electrically connected to the SDTX interface. The SCK interface controls the transmitting shift register to send data to the SDTX interface; and the transmitting shift register is electrically connected to the state machine circuit to obtain a status signal. When the timer unit sends an overflow signal, the data in the transmitting shift register is processed.

[0015] In a possible implementation, the first register unit includes: a receiving buffer register; the receiving buffer register is electrically connected to the state machine circuit to obtain a state signal, and the receiving buffer register is electrically connected to the receiving shift register to store data in the receiving shift register.

[0016] In one possible implementation, the second register unit includes: a sending buffer register; the sending buffer register is electrically connected to the state machine circuit to obtain a state signal, and the sending buffer register is electrically connected to the receiving shift register to store data with a clock signal in the sending buffer register.

[0017] In one possible implementation, the timer unit includes: a first timer, the first timer is electrically connected to the receiving shift register to monitor the data of the receiving shift register; the first timer sends a clock signal and an overflow signal to the first register unit; and the first timer is electrically connected to the state machine circuit to obtain a state signal.

[0018] In a possible implementation, the first timer generates a clock signal according to a change of an internal clock or an external clock, and generates an overflow signal when a count value of the first timer decreases to 0.

[0019] In a possible implementation manner, the data processing includes: direct memory access data processing and interrupt data processing.

[0020] In a possible implementation, the receiving shift register is compatible with synchronous transmission and asynchronous transmission, and reads the clock signal through internal clock sampling and transmits it to the receiving shift register.

[0021] In a possible implementation manner, the state machine circuit is compatible with asynchronous communication and synchronous communication.

[0022] Beneficial effects of this application:

[0023] 1. The configuration of the composite communication circuit of the present application is flexible. By setting a state machine circuit, the working state of the first register unit, the second register unit and the timer unit can be adjusted in real time according to the dynamic configuration through the state machine circuit, so as to realize flexible switching and combination of different communication protocols, and avoid the waste of fixed hardware resources caused by supporting multiple protocols in traditional MCU. Secondly, the state machine circuit can ensure the accuracy and reliability of data transmission. At the same time, by optimizing the state machine, unnecessary power consumption and delay can be further reduced.

[0024] 2. The composite communication circuit of the present application can significantly reduce the chip area of ​​the MCU, reduce production costs, and possibly improve production efficiency by reducing unused hardware components, thereby avoiding resource redundancy and cost waste caused by supporting multiple communication protocols in traditional designs.

[0025] 3. The composite communication circuit of the present application significantly improves the speed of data transmission and processing. During the data transmission process, the first register unit can receive data while the second register unit is preparing to send data at the same time. This parallel operation reduces waiting time and improves system efficiency.

[0026] Other features and aspects of the present application will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present application and, together with the description, serve to explain the principles of the present application.

[0028] Figure 1 A circuit diagram showing a composite communication circuit according to an embodiment of the present application;

[0029] Figure 2 A schematic diagram of a timer unit according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0030] Various exemplary embodiments, features and aspects of the present application will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0031] Among them, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application or simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0032] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0033] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0034] In addition, in order to better illustrate the present application, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0035] like Figure 1As shown, the composite communication circuit includes: a first register unit, a second register unit, a timer unit and a state machine circuit 7; the first register unit is electrically connected to the timer unit, receives the clock signal of the timer unit, and the first register unit is suitable for receiving and storing external data; the second register unit is electrically connected to the first register unit, receives the data in the first register unit, and the second register unit is suitable for storing and sending it outward; the state machine circuit 7 is electrically connected to the first register unit, the second register unit and the timer unit, and sends a state signal to the first register unit, the second register unit and the timer unit; when the timer unit sends an overflow signal, the first register unit, the second register unit and the timer unit perform data processing.

[0036] The composite communication circuit proposed in this embodiment has a flexible configuration. By setting the state machine circuit 7, the working state of the first register unit, the second register unit and the timer unit can be adjusted in real time according to the dynamic configuration through the state machine circuit 7, so as to realize the flexible switching and combination of different communication protocols, and avoid the waste of fixed hardware resources caused by supporting multiple protocols in the traditional MCU. Secondly, the state machine circuit 7 can ensure the accuracy and reliability of data transmission. At the same time, by optimizing the state machine, unnecessary power consumption and delay can be further reduced. Secondly, the composite communication circuit of the present application can significantly reduce the chip area of ​​the MCU, reduce production costs, and may improve production efficiency by reducing unused hardware components, avoiding resource redundancy and cost waste caused by supporting multiple communication protocols in traditional designs. And the composite communication circuit of the present application significantly improves the speed of data transmission and processing. During the data transmission process, the first register unit can receive data, and the second register unit is ready to send data at the same time. This parallel operation reduces waiting time and improves system efficiency.

[0037] In one specific embodiment, the first register unit includes: a receiving shift register 1; the receiving shift register 1 is electrically connected to the SCK interface, the receiving shift register 1 is electrically connected to the SDRX interface, the SCK interface controls the receiving shift register 1, and receives the data transmitted by the SDRX interface; and the receiving shift register 1 is electrically connected to the timer unit to receive the clock signal; and the receiving shift register 1 is electrically connected to the state machine circuit 7 to obtain a status signal, and when the timer unit sends an overflow signal, the data in the receiving shift register 1 is processed.

[0038] Furthermore, in one of the specific embodiments, the first register unit also includes: a receiving buffer register 2; the receiving buffer register 2 is electrically connected to the state machine circuit 7 to obtain a state signal, and the receiving buffer register 2 is electrically connected to the receiving shift register 1 to store data with a clock signal in the receiving shift register 1. In this embodiment, it should be noted that the receiving buffer register 2 is electrically connected to the receiving shift register 1 in a bidirectional manner. It should also be noted that the output end of the receiving buffer register 2 is electrically connected to the data processing unit, and when the timer unit outputs an overflow signal, the output end of the receiving buffer register 2 triggers interrupt data processing or triggers DMA transmission data processing, DMA being direct memory access.

[0039] In one specific embodiment, the second register unit includes: a sending shift register 3; the sending shift register 3 is electrically connected to the receiving register, and the sending shift register 3 is electrically connected to the SCK interface, the sending shift register 3 is electrically connected to the SDTX interface, the SCK interface controls the sending shift register 3 to send data to the SDTX interface; and the sending shift register 3 is electrically connected to the state machine circuit 7 to obtain a status signal, and when the timer unit sends an overflow signal, the data in the sending shift register 3 is processed.

[0040] Further, in one of the specific embodiments, the second register unit further includes: a sending buffer register 4; the sending buffer register 4 is electrically connected to the state machine circuit 7 to obtain a state signal, and the sending buffer register 4 is electrically connected to the receiving shift register 1 to store data with a clock signal in the sending buffer register 4. The sending buffer register 4 is bidirectionally electrically connected to the sending shift register 3, and when the timer unit sends an overflow signal, the sending buffer register 4 performs data processing.

[0041] It should be noted that in the above embodiments, the SDRX interface is used to receive data from an external device, the SCK interface is suitable for synchronous data transmission, and the SDTX interface is suitable for sending data to an external device.

[0042] The SDRX interface is bidirectionally electrically connected to the receiving shift register 1, and the SDRX interface is bidirectionally electrically connected to the transmitting shift register 3. The SCK interface is bidirectionally electrically connected to the receiving shift register 1, and the SCK interface is bidirectionally electrically connected to the transmitting shift register 3. The SDTX interface is bidirectionally electrically connected to the receiving shift register 1, and the SDTX interface is bidirectionally electrically connected to the transmitting shift register 3.

[0043] It should also be noted that the composite communication circuit of the present application further includes: an SCK interface, and the SCK interface is bidirectionally electrically connected to the receiving shift register 1 , and the SCK interface is bidirectionally electrically connected to the transmitting shift register 3 .

[0044] In one specific embodiment, the timer unit includes: a first timer 5, the first timer 5 is electrically connected to the receiving shift register 1, and monitors the data of the receiving shift register 1; the first timer 5 sends a clock signal and an overflow signal to the first register unit; and the first timer 5 is electrically connected to the state machine circuit 7 to obtain the state signal. In this embodiment, it should be noted that when the timer unit sends an overflow signal, the buffer register 4 is sent for data processing. The first timer 5, according to the internal clock or the external clock, automatically decrements 1 at each rising edge of the clock until it is decremented to 0, generates an overflow signal, generates a timeout interrupt, triggers an interrupt or triggers a DMA request, that is, direct memory access data processing.

[0045] It should also be noted that the timer unit further includes: a second timer 6, which is electrically connected to the first timer 5, and the second timer 6 tracks the timing of the first timer 5 to ensure that it does not exceed its capacity.

[0046] It should be further explained that the second timer 6 is a cache timer, and the timer usually includes: a counter and a crystal oscillator. When the timer generates an overflow signal, the hardware automatically loads the contents of the buffer timer into the corresponding counter and counts again. The combination of the second timer 6 and the first timer 5 can also generate PWM output, that is, one timer may be used to control the period (that is, frequency) of PWM, while the other timer is used to adjust the duty cycle. It can also generate an input capture function, which is equivalent to a standard timer circuit, that is, setting the second timer 6 can accurately measure the time interval between external events (such as pin level changes) to a certain extent. The combination of the first timer 5 and the second timer 6 can replace the general timer. That is, at the software level, through reasonable programming and logic design, the two timers can be combined to achieve a function set similar to that of a single general timer. The advantage of this method is that it is highly flexible and the configuration and use of the timer can be adjusted according to specific needs.

[0047] Further, in one of the specific embodiments, the first timer 5 generates a clock signal according to the change of the internal clock or the external clock, and generates an overflow signal when the count value of the first timer 5 decreases to 0. In this embodiment, it should be noted that the output ends of the external trigger, the internal clock, the external clock and the buffer timer are all electrically connected to the counter inside the first timer 5. And the first timer 5 can trigger interrupt processing or trigger DMA transmission according to the actual situation. And the first timer 5 can output PWM. Specifically, each time the sending and receiving data changes, the first timer 5 will reload the value of the buffer timer to the internal counter by hardware. When the data is sent and received normally, the first timer 5 will be loaded normally, and the first timer 5 will not be reduced to 0. When the external receiving data or the internal sending data no longer changes, when the first timer 5 is reduced to 0, an overflow signal is generated, indicating that an erroneous data transmission has occurred, and the CPU will be notified to process the data transmission error information, so that the CPU intervenes in the data transmission processing. The combination of the first timer 5 and the buffer timer can also generate PWM output and input capture function, which is equivalent to the standard timer circuit and can also replace the general timer.

[0048] In one of the specific embodiments, data processing includes: direct memory access data processing and interrupt data processing. In combination with the first register unit and the second register unit, it should be noted that the receiving shift register 1 is divided into synchronous transmission and asynchronous transmission, but whether it is synchronous transmission or asynchronous transmission, it will be sampled by the internal clock, and the receiving shift register 1 reads each received data from the SDRX pin in sequence under the control of each SCK interface. If 8 bits are met, or the 9th bit with parity check, a receiving interrupt will be generated, or a DMA request signal will be triggered, that is, direct memory access data processing, and the data hardware of the receiving shift register 1 is written into the receiving buffer register 2, and the CPU can read it in the interrupt program or when it is needed. The sending shift register 3 outputs each data to be sent to the SDTX interface in sequence under the control of the SCK interface, and if 8 bits are sent, or the 9th bit with parity check is sent, a receiving interrupt data processing will be generated, or a DMA request signal will be triggered, that is, direct memory access data processing.

[0049] In one specific embodiment, the receiving shift register 1 is compatible with synchronous transmission and asynchronous transmission, and reads the clock signal through internal clock sampling and transmits it to the receiving shift register 1. It should also be noted that the number of the receiving shift register 1, receiving buffer register 2, sending shift register 3 and sending buffer register 4 of the present application is not limited and can be adjusted according to actual needs.

[0050] In one of the specific embodiments, the state machine circuit 7 is compatible with asynchronous communication and synchronous communication. In this embodiment, it should be noted that the state machine circuit 7 is electrically connected to both the external clock and the internal clock. And the external clock is electrically connected to the SCK interface. It should also be noted that the state machine circuit 7 is suitable for each sending and receiving protocol state machine, which is the most complex and can be configured to support asynchronous communication and synchronous communication. That is, when configured as UART, LPUART, asynchronous communication processing is performed, and when configured as USART, SPI, I2S, SAI, I2C, DSPI, QSPI, ISO7816, synchronous communication processing is performed. And when different protocols are configured, full-duplex, single-line half-duplex, simplex only send, simplex only receive configuration will also be performed to process the IO port. Configure different interrupt enable, support sending completion interrupt, support receiving completion interrupt, support data empty interrupt, support data frame structure error, flow control signal change interrupt, receiving data match interrupt, address match interrupt, slave selection error interrupt, receiving buffer overflow interrupt, sending buffer underflow interrupt, slave selection interrupt, etc. The state machine circuit 7 can be increased or decreased according to different protocols to increase the cost performance of the MCU. For example, if only the communication protocols such as UART, LPUART, USART, SPI, I2S are included, the area of ​​the overall composite communication interface is about 5000 gates, but if the communication protocols such as SAI, DSPI, QSPI, ISO7816 are included, the overall composite communication interface area is increased to about 8000 gates, and the function of the general timer is added, that is, PWM output, input capture and other functions are added, the overall composite communication interface area is about 8500 gates. Therefore, after using this patent, while meeting the needs of customers for various communication protocols, the circuit cost of the MCU is greatly reduced and the competitiveness of the MCU products is increased.

[0051]

[0052]

[0053] Table 1 Gate circuits of various communication circuits

[0054] According to the data in Table 1, on the one hand, the number of gate circuits of the composite communication circuit of the present application is greater than the number of gate circuits of a single circuit containing other interfaces. Therefore, the composite communication circuit of the present application has a stronger parallel processing capability and greater flexibility than a single other communication circuit. On the one hand, the number of gate circuits of the composite communication circuit of the present application is less than the number of gate circuits of the circuits containing the other communication protocols in the table. It can be seen that the composite communication circuit of the present application greatly reduces the circuit cost of the MCU and increases the competitiveness of the MCU product while meeting the customer's needs for various communication protocols.

[0055] It should also be noted that the composite communication circuit of the present application is not limited to the architecture of the general MCU communication protocol shown in this patent, and can include any integrated circuit in the form of MCU, ASIC, or MPU with a CPU. It is not limited to the standard communication protocols contained in the composite communication interface circuit architecture shown in this patent, such as UART, LPUART, USART, SPI, I2S, SAI, I2C, DSPI, QSPI, ISO7816, etc., and can also include any form of IO, shift register group, cache register group, timer, interrupt, and trigger DMA. Other standard communication protocols.

[0056] It should be noted that although the composite communication circuit is introduced as an example in this application, those skilled in the art will appreciate that this application should not be limited thereto. In fact, users can flexibly set parameters according to personal preferences and / or actual application scenarios, as long as they are reasonable.

[0057] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A composite communication circuit, characterized in that: include: A first register unit, a second register unit, a timer unit and a state machine circuit; The first register unit is electrically connected to the timer unit, receives a clock signal of the timer unit, and is adapted to receive and store external data; The second register unit is electrically connected to the first register unit, receives data in the first register unit, and is suitable for storing and sending data to the outside; The state machine circuit is electrically connected to the first register unit, the second register unit and the timer unit, and sends a state signal to the first register unit, the second register unit and the timer unit; When the timer unit issues an overflow signal, the first register unit, the second register unit and the timer unit perform data processing.

2. The composite communication circuit according to claim 1, characterized in that: The first register unit comprises: a receiving shift register; The receiving shift register is electrically connected to the SCK interface, the receiving shift register is electrically connected to the SDRX interface, the SCK interface controls the receiving shift register, and receives the data transmitted by the SDRX interface; and the receiving shift register is electrically connected to the timer unit, and receives the clock signal; and the receiving shift register is electrically connected to the state machine circuit, and obtains the state signal, When the timer unit sends out an overflow signal, the data in the receiving shift register is processed.

3. The composite communication circuit according to claim 1, characterized in that: The second register unit includes: a transmission shift register; The transmitting shift register is electrically connected to the receiving register, and the transmitting shift register is electrically connected to the SCK interface, and the transmitting shift register is electrically connected to the SDTX interface. The SCK interface controls the transmitting shift register to send data to the SDTX interface; and the transmitting shift register is electrically connected to the state machine circuit to obtain a status signal. When the timer unit sends an overflow signal, the data in the transmitting shift register is processed.

4. The composite communication circuit according to claim 2, characterized in that: The first register unit further includes: a receiving buffer register; the receiving buffer register is electrically connected to the state machine circuit to obtain a state signal, and the receiving buffer register is electrically connected to the receiving shift register to store data in the receiving shift register.

5. The composite communication circuit according to claim 3, characterized in that: The second register unit further includes: a sending buffer register; the sending buffer register is electrically connected to the state machine circuit to obtain a state signal, and the sending buffer register is electrically connected to the receiving shift register to store data in the sending buffer register.

6. The composite communication circuit according to claim 1, characterized in that: The timer unit includes: a first timer, the first timer is electrically connected to the receiving shift register to monitor the data of the receiving shift register; the first timer sends a clock signal and an overflow signal to the first register unit; and the first timer is electrically connected to the state machine circuit to obtain a state signal.

7. The composite communication circuit according to claim 6, characterized in that: The first timer generates a clock signal according to changes in an internal clock or an external clock, and generates an overflow signal when the count value of the first timer decreases to 0.

8. The composite communication circuit according to any one of claims 1 to 7, characterized in that: The data processing includes: direct memory access data processing and interrupt data processing.

9. The composite communication circuit according to claim 4, characterized in that: The receiving shift register is compatible with synchronous transmission and asynchronous transmission, and reads the clock signal through internal clock sampling and transmits it to the receiving shift register.

10. The composite communication circuit according to any one of claims 1 to 7, characterized in that: The state machine circuit is compatible with asynchronous communication and synchronous communication.

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