Multi-device ARINC818-to-PCIE communication system

Abstract

The invention provides a multi-device ARINC818-to-PCIE communication system, which belongs to the technical field of data transmission and comprises a PCIE EP device based on an FPGA, a PCIE RC device and an ARINC818 optical fiber device. The PCIE EP equipment comprises a PCIE protocol interface module, an ARINC818 protocol interface module, a PCIE short message analysis module, a PCIE read polling module, a PCIE write polling module, an ARINC818 coding module, an ARINIC818 decoding module, a state monitoring and reporting module and a parameter calculation module. And protocol conversion between PCIE DMA polling reading / writing and ARINIC818 encoding / decoding is realized by actively initiating PCIE DMA polling reading / writing and ARINIC818 encoding / decoding modes. According to the system, the data link topology can be optimized while the requirements of high-speed, large-data-volume and low-delay real-time communication are met, and the system overhead is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of data transmission, and in particular to a multi-device ARINC818 to PCIE communication system. Background Art

[0002] With the rapid development of embedded technology, embedded systems have put forward higher requirements for large data volume interaction, as well as higher and higher requirements for bus transmission rate and data integrity. Therefore, in order to meet the requirements of high-speed, large data volume and low-latency data transmission, PCIE and ARINC818 buses are usually used for data transmission and communication in the field of airborne optoelectronics. Among them, PCIE bus is used for the communication interface of the main control, and ARINC818 bus is used for the communication interface of the sensor and realizes its cross-linking with remote devices through optical fiber.

[0003] The characteristic of PCIE bus serial transmission is that it is transmitted in the form of messages. Each data message is encapsulated in one or more TLP data packets in the transaction layer of PCIE, and PCIE devices communicate data through these data packets. Since the TLP data packet contains information such as TLP prefix, TLP header and TLP summary, when the device is performing a single data transmission, the performance advantage of PCIE bus is not obvious, and its transmission speed is even lower than that of traditional buses. In order to obtain higher transmission efficiency, DMA transmission method is often required when using PCIE bus for data transmission.

[0004] Aviation Digital Video Bus (ADVB, also known as ARINC818) is an avionics video transmission standard based on the FC-AV standard. The protocol implements the transmission and exchange of video stream data in the optical fiber network and specifies the mapping rules between video streams and FC frames.

[0005] In the field of airborne optoelectronics, the data communication architecture is usually a PCIE data processing unit + multiple ARINC818 sensors. However, the protocol conversion between PCIE and ARINC818 cannot be directly realized, and the current PCIE DMA controller cannot meet the real-time communication requirements of high speed, large data volume and low latency in terms of data transmission flexibility and transmission efficiency. Summary of the invention

[0006] In view of this, an embodiment of the present application provides a multi-device ARINC818 to PCIE communication system, which at least partially solves the problem in the prior art that direct protocol conversion between PCIE and ARINC818 is not possible.

[0007] The embodiment of the present application provides a multi-device ARINC818 to PCIE communication system, the system includes a PCIE EP device based on FPGA, a PCIE RC device communicating with the PCIE EP device, and multiple ARINC818 optical fiber devices communicating with the PCIE EP device, the PCIE EP device includes a PCIE protocol interface module, an ARINC818 protocol interface module, a PCIE short message parsing module, a PCIE read polling module, a PCIE write polling module, an ARINC818 encoding module, an ARINIC818 decoding module, a status monitoring and reporting module, and a parameter calculation module;

[0008] The PCIE protocol interface module is communicatively connected with the PCIE RC device and is used to implement the PCIE protocol interface;

[0009] The ARINC818 protocol interface module is communicatively connected with the ARINC818 optical fiber device and is used for conversion between the ARINC818 protocol and the GT interface;

[0010] The PCIE short message parsing module is used to receive the short message of the PCIE RC device, parse the short message to generate a control instruction, and control the PCIE write polling module, the PCIE read polling module, the status monitoring and reporting module and the parameter calculation through the control instruction;

[0011] The ARINC818 encoding module is used to package and encode the internal synchronous timing data into ARINC818 data;

[0012] The ARINIC818 decoding module is used to receive, decode and convert the ARINC818 data of the multiple ARINC818 optical fiber devices into internal synchronous timing data;

[0013] The PCIE write polling module is used to convert the multi-channel internal synchronous timing data output by the ARINC818 decoding module into AXI Stream timing data through a DMA polling write mode according to the control instruction and send it to the PCIERC device;

[0014] The PCIE read polling module is used to actively initiate DMA polling read mode data reading to the PCIE RC device according to the control instruction, and convert the read data into internal synchronous timing data;

[0015] The status monitoring and reporting module is used to monitor the data transmission status of the PCIE DMA reading and writing process and the data transmission status of the ARINC818 encoding and decoding process, and report the monitored data transmission status to the PCIE RC device;

[0016] The parameter calculation module is used to calculate the relevant parameters of the PCIE DMA reading and writing process and the ARINC818 communication process.

[0017] According to a specific implementation of an embodiment of the present application, the multi-channel internal synchronous timing data output by the ARINC818 decoding module is converted into AXI Stream timing data through a DMA polling write mode and sent to the PCIE RC device, including:

[0018] Through the cooperation of multi-channel polling and DMA write state machine and single-channel internal synchronous timing to AXI Stream state machine, the multi-channel internal synchronous timing data output by the ARINC818 decoding module is converted into AXI Stream timing data through DMA polling write mode and sent to the PCIE RC device.

[0019] According to a specific implementation of the embodiment of the present application, the workflow of converting the single-channel internal synchronous timing to the AXI Stream state machine includes:

[0020] The single-channel internal synchronous timing conversion AXI Stream state machine waits for data transmission to be enabled in IDLE and INIT states;

[0021] When the data transmission is enabled, the state switches to the CHECK_HEADER state to wait for the data to arrive;

[0022] When the arrival of data is detected, it jumps to the WR_VIDEO_DATA state. In this state, the internal synchronization timing data is written into the FIFO cache, and the FIFO empty and full signals are output to the multi-channel polling and DMA write state machine and wait for the AXIS_Tready signal to be pulled high. When the AXIS_Tready signal returned by the multi-channel polling and DMA write state machine is pulled high, the single-channel internal synchronization timing is converted to the AXI Stream state machine according to the single DMA write length output by the short message parsing module and the data in the FIFO is read out according to the AXIStream timing control;

[0023] When a frame of data transmission is completed, it jumps to the ENCODE_STS_CHECK state. If it is detected in this state that the data transmission enable is turned off, it jumps to the IDLE state, otherwise it jumps to the CHECK_HEADER state.

[0024] According to a specific implementation of an embodiment of the present application, the workflow of the multi-channel polling and DMA write state machine includes:

[0025] The multi-channel polling and DMA write state machine waits in the IDLE state, and when the PCIE link LINK is detected and the data transmission enable is turned on, it jumps to the WAIT_DATA state;

[0026] In the WAIT_DATA state, the state machine determines whether there is data to be sent based on the empty and full signals output by the front-end FIFO. If so, it jumps to the CHANNEL_SEL state.

[0027] In the CHANNEL_SEL state, the empty and full signals output by each data FIFO are determined by polling and dynamic priority adjustment, and the data channel number for initiating DMA write is selected;

[0028] In the DES_CONFIG state, the PCIE descriptor is generated according to the current DMA write data channel number and the PCIE DMA write data base address and length output by the PCIE short message parsing module, and the base address and data length of this DMA write data are dynamically calculated;

[0029] When the descriptor configuration is completed, it jumps to the WAIT_TREADY state to wait for the AXIS_Tready signal fed back by the PCIE RC device. If AXIS_Tready is pulled high, it jumps to the RD_START state, and after several cycles, it jumps to the CHN_TRANS state;

[0030] In the CHN_TRNAS state, the multi-channel polling and DMA write state machine generates a CHN_AXIS_Tready signal according to the AXIS_Tready signal fed back by the PCIE RC device and the data channel number currently to be sent, and sends the CHN_AXIS_Tready signal to the single-channel internal synchronous timing conversion AXI Stream state machine corresponding to the data channel number, thereby generating a DMA write data;

[0031] When a DMA write is completed and a frame of data is sent, it jumps to the CHN_DONE state, otherwise it jumps to the WAIT_DATA state;

[0032] When the entire frame of data on the current CHN channel is sent, it is determined whether the interrupt transmission is enabled. If yes, it jumps to the INTR_GEN state, otherwise it jumps to the IDLE state.

[0033] In the INTR_GEN state, the multi-channel polling and DMA write state machine sends an interrupt request signal intr_req to the PCIE RC device, and at the same time sends the base address of the current frame data to the PCIE RC device through the state monitoring and reporting module, and then jumps to the INTR_ACK_WAIT state to wait for a reply;

[0034] When the multi-channel polling and DMA write state machine receives the interrupt reply signal intr_ack returned by the PCIE RC device, it indicates that the interrupt is sent successfully and jumps back to the IDLE state.

[0035] According to a specific implementation of an embodiment of the present application, the method of actively initiating a DMA polling read mode data reading to a PCIE RC device and converting the read data into internal synchronization timing data includes:

[0036] Through the cooperation of multi-channel polling and DMA read state machine and single-channel AXI Stream to internal synchronous timing state machine, DMA polling read mode data reading is actively initiated to the PCIE RC device, and the read data is converted into internal synchronous timing data.

[0037] According to a specific implementation of an embodiment of the present application, the workflow of the multi-channel polling and DMA read status includes:

[0038] The multi-channel polling and DMA read state machine waits in the IDLE state, and when the PCIE link LINK is detected, it jumps to the WAIT_START state;

[0039] In the WAIT_START state, if the receive enable is detected, it jumps to the RECV_CHNUM_SEL state, selects the data channel number corresponding to the data read by this DMA and jumps to the DES_CONFIG state;

[0040] In the DES_CONFIG state, according to the data channel number corresponding to the data currently sent by the DMA read, the base address and length of the PCIE DMA read data output by the PCIE short message parsing module, a PCIE descriptor is generated, and the base address and data length of the current DMA read data are dynamically calculated;

[0041] When the PCIE descriptor configuration is completed, it jumps to the RECV_START state, and jumps to the CHN_RECV state after reaching the counting cycle;

[0042] In the CHN_RECV state, the multi-channel polling and DMA read state machine generates an AXIS_Tready signal and returns it to the PCIE RC device to implement a DMA read operation of the data;

[0043] When this DMA read is completed, jump to RECV_CHNUM_SEL to initiate the next DMA read.

[0044] According to a specific implementation of an embodiment of the present application, the workflow of converting a single-channel AXI Stream to an internal synchronous timing state machine includes:

[0045] The single-channel AXI Stream internal synchronization timing state machine waits in the IDLE and INIT states, and jumps to the CHECK_HEADER state when it detects that the receiving enable is turned on;

[0046] After the CHECK_HEADER state logic detects the arrival of data, it jumps to the WR_VIDEO_DATA state, generates a read signal according to the resolution and bit width, and reads the data from the FIFO. After the data is received, it jumps to the ENCODE_STS_CHECK state.

[0047] When the receive enable is turned off, it jumps to the IDLE state, otherwise it jumps to the CHECK_HEADER state.

[0048] According to a specific implementation method of an embodiment of the present application, the short message includes a multi-channel data base address written by PCIE DMA polling, a circular buffer size written by PCIE DMA polling, and a number of circular buffers written by PCIE DMA polling, a multi-channel data base address read by PCIE DMA polling, a circular buffer size read by PCIE DMA polling, and a number of circular buffers read by PCIE DMA polling, a multi-channel interrupt generation enable, a Source_ID sent by ARINC818 multi-channel, an enable of ARINC818 multi-channel sending, a data length sent by ARINC818 multi-channel, a bit width sent by ARINC818 multi-channel, a Source_ID received by ARINC818 multi-channel, an enable of ARINC818 multi-channel receiving, a data length received by ARINC818 multi-channel, and a bit width received by ARINC818 multi-channel, wherein each channel of the multi-channel corresponds to an ARINC818 optical fiber device.

[0049] According to a specific implementation method of an embodiment of the present application, the data transmission status of the PCIE DMA read and write process includes: PCIE LINK status, PCIE DMA read and write data frame count, PCIE DMA read and write data error frame count, PCIE DMA read and write timeout count, PCIE DMA interrupt send request and interrupt response count;

[0050] The data transmission status in the ARINC818 encoding and decoding process includes: ARINC818 receiving / sending FC0 frame count, ARINC818 receiving / sending FCN frame count, ARINC818 receiving / sending FC0 frame CRC error count and ARINC818 receiving / sending FCN frame CRC error count.

[0051] According to a specific implementation method of an embodiment of the present application, the relevant parameters of the PCIE DMA read and write process include the address and length of the PCIE DMA read and write, and the relevant parameters of the ARINC818 communication process include the Source_ID, resolution, bit width and FCN frame Payload length received or sent by ARNIC818.

[0052] Beneficial effects:

[0053] The multi-device ARINC818 to PCIE communication system in the embodiment of the present application uses FPGA as a PCIE EP device to perform PCIE communication with the PCIE RC device, and at the same time performs ARINC818 communication with multiple ARINC818 optical fiber devices through optical fiber. FPGA realizes the protocol conversion between the two by actively initiating PCIE DMA polling read / write and ARINIC818 encoding / decoding. The system of the present application can optimize the data link topology and reduce system overhead while meeting the requirements of high-speed, large data volume, and low-latency real-time communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0055] Figure 1 It is an architecture diagram of a multi-device ARINC818 to PCIE communication system according to an embodiment of the present invention;

[0056] Figure 2 A schematic diagram of a single-channel internal synchronous timing conversion AXI Stream state machine according to an embodiment of the present invention;

[0057] Figure 3 A schematic diagram of a multi-channel polling and DMA write state machine according to an embodiment of the present invention;

[0058] Figure 4 A schematic diagram of a multi-channel polling and DMA read state machine according to an embodiment of the present invention;

[0059] Figure 5 A schematic diagram of a single-channel AXI Stream internal synchronization timing state machine according to an embodiment of the present invention;

[0060] Figure 6 A schematic diagram of an ARINC818 encoding state machine according to an embodiment of the present invention;

[0061] Figure 7FIG. 4 is a schematic diagram of an ARINC818 decoding state machine according to an embodiment of the present invention. DETAILED DESCRIPTION

[0062] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0063] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0064] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0065] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show the components related to the present application rather than being drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0066] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0067] The present application embodiment provides a multi-device ARINC818 to PCIE communication system. Figures 1 to 7 Describe in detail.

[0068] Reference Figure 1, a multi-device ARINC818 to PCIE communication system includes an FPGA-based PCIE EP device, a PCIE RC device communicating with the PCIE EP device, and multiple ARINC818 optical fiber devices communicating with the PCIE EP device, wherein the PCIE EP device includes a PCIE protocol interface module, an ARINC818 protocol interface module, a PCIE short message parsing module, a PCIE read polling module, a PCIE write polling module, an ARINC818 encoding module, an ARINIC818 decoding module, a status monitoring and reporting module, and a parameter calculation module;

[0069] The PCIE protocol interface module is communicatively connected with the PCIE RC device and is used to implement the PCIE protocol interface;

[0070] The ARINC818 protocol interface module is communicatively connected with the ARINC818 optical fiber device and is used for conversion between the ARINC818 protocol and the GT interface;

[0071] The PCIE short message parsing module is used to receive the short message of the PCIE RC device, parse the short message to generate a control instruction, and control the PCIE write polling module, the PCIE read polling module, the status monitoring and reporting module and the parameter calculation through the control instruction;

[0072] The ARINC818 encoding module is used to package and encode the internal synchronous timing data into ARINC818 data;

[0073] The ARINIC818 decoding module is used to receive, decode and convert the ARINC818 data of the multiple ARINC818 optical fiber devices into internal synchronous timing data;

[0074] The PCIE write polling module is used to convert the multi-channel internal synchronous timing data output by the ARINC818 decoding module into AXI Stream (AXI Stream is a standard interface for data stream transmission) timing data through a DMA polling write mode according to the control instruction and send it to the PCIE RC device;

[0075] The PCIE read polling module is used to actively initiate DMA polling read mode data reading to the PCIE RC device according to the control instruction, and convert the read data into internal synchronous timing data;

[0076] The status monitoring and reporting module is used to monitor the data transmission status of the PCIE DMA reading and writing process and the data transmission status of the ARINC818 encoding and decoding process, and report the monitored data transmission status to the PCIE RC device;

[0077] The parameter calculation module is used to calculate the relevant parameters of the PCIE DMA reading and writing process and the ARINC818 communication process.

[0078] In specific implementation, PCIE EP (Endpoint Complex) is the terminal device in the PCIE system, and PCIE RC (Root Complex) is the core controller in the PCIE system. ARINC818 optical fiber devices are usually sensors. FPGA, as a PCIE EP device, communicates with multiple sensors through optical fiber in ARINC818. FPGA realizes protocol conversion between the two by actively initiating PCIE DMA polling read / write and ARINIC818 encoding / decoding. This method can optimize the data link topology and reduce system overhead while meeting the requirements of high-speed, large data volume, and low-latency real-time communication.

[0079] In one embodiment, the PCIE short message parsing module is mainly responsible for receiving and parsing short messages such as instructions and status from the PCIE RC device, and controls the PCIE write polling module, PCIE read polling module, parameter calculation and status monitoring and reporting module through instructions to realize data DMA reading and writing, interrupt sending, read and write address and length dynamic control and other functions.

[0080] Specifically, the PCIE short message parsing module realizes the mapping of the FPGA status register to the PCIEBAR0 space through the AXI4LITE interface, thereby realizing the function of the FPGA receiving and parsing the short message sent by the PCIE RC device. The short message includes the multi-channel data base address written by PCIE DMA polling, the circular buffer size written by PCIE DMA polling, the number of circular buffers written by PCIE DMA polling, the multi-channel data base address read by PCIE DMA polling, the circular buffer size read by PCIE DMA polling, the number of circular buffers read by PCIE DMA polling, the multi-channel interrupt generation enable, the Source_ID sent by ARINC818 multi-channel, the enable of ARINC818 multi-channel sending, the data length sent by ARINC818 multi-channel, the bit width sent by ARINC818 multi-channel, the Source_ID received by ARINC818 multi-channel, the enable of ARINC818 multi-channel receiving, the data length received by ARINC818 multi-channel and the bit width received by ARINC818 multi-channel, wherein each channel of the multi-channel corresponds to an ARINC818 optical fiber device.

[0081] Taking the communication between 6 ARINC818 fiber optic devices and one PCIE RC device as an example, the short messages mainly involved include the CH0~CH5 data base address, circular buffer size, and number of circular buffers written by PCIE DMA polling, the CH0~CH5 data base address, circular buffer size, and number of circular buffers read by PCIE DMA polling, CH0~CH5 interrupt generation enable, ARINC818 CH0~CH5 sending Source_ID, enable, data length and bit width, ARINC818 CH0~CH5 receiving Source_ID, enable, data length and bit width, etc. Among them, CH0~CH5 are 6 data channel numbers, each corresponding to a sensor.

[0082] In one embodiment, the method of converting the multi-channel internal synchronous timing data output by the ARINC818 decoding module into AXI Stream timing data through a DMA polling write mode and sending the data to the PCIE RC device includes:

[0083] Through the cooperation of multi-channel polling and DMA write state machine and single-channel internal synchronous timing to AXI Stream state machine, the multi-channel internal synchronous timing data output by the ARINC818 decoding module is converted into AXI Stream timing data through DMA polling write mode and sent to the PCIE RC device.

[0084] Specifically, the PCIE write polling module mainly implements data write control and interrupt generation for PCIE RC devices. It implements DMA write polling operations from FPGA to PCIE RC devices through the instructions output by the PCIE short message parsing module, and sends the internal synchronization timing data to be sent to the PCIE RC device. Therefore, this module converts the multi-channel internal synchronization timing data output by the ARINC818 decoding module into AXI Stream timing data through polling and sends it to the PCIE RC device. The above functions are mainly realized through the cooperation of two state machines, namely the single-channel internal synchronization timing to AXI Stream state machine, and the multi-channel polling and DMA write state machine, such as Figure 2 and Figure 3 shown.

[0085] Reference Figure 2 , the workflow of converting single-channel internal synchronous timing to AXI Stream state machine includes:

[0086] The single-channel internal synchronous timing conversion AXI Stream state machine waits for data transmission to be enabled in IDLE and INIT states;

[0087] When the data transmission is enabled, the state switches to the CHECK_HEADER state to wait for the data to arrive;

[0088] When the arrival of data is detected, it jumps to the WR_VIDEO_DATA state. In this state, the internal synchronization timing data is written into the FIFO cache, and the FIFO empty and full signals are output to the multi-channel polling and DMA write state machine and wait for the AXIS_Tready signal to be pulled high. When the AXIS_Tready signal returned by the multi-channel polling and DMA write state machine is pulled high, the single-channel internal synchronization timing is converted to the AXI Stream state machine according to the single DMA write length output by the short message parsing module and the data in the FIFO is read out according to the AXIStream timing control;

[0089] When a frame of data transmission is completed, it jumps to the ENCODE_STS_CHECK state. If it is detected in this state that the data transmission enable is turned off, it jumps to the IDLE state, otherwise it jumps to the CHECK_HEADER state.

[0090] Reference Figure 3 , the workflow of multi-channel polling and DMA write state machine includes:

[0091] The multi-channel polling and DMA write state machine waits in the IDLE state, and when the PCIE link LINK is detected and the data transmission enable is turned on, it jumps to the WAIT_DATA state;

[0092] In the WAIT_DATA state, the state machine determines whether there is data to be sent based on the empty and full signals output by the front-end FIFO. If so, it jumps to the CHANNEL_SEL state.

[0093] In the CHANNEL_SEL state, the empty and full signals output by each data FIFO are determined by polling and dynamic priority adjustment, and the data channel number for initiating DMA write is selected;

[0094] In the DES_CONFIG state, the PCIE descriptor is generated according to the current DMA write data channel number and the PCIE DMA write data base address and length output by the PCIE short message parsing module, and the base address and data length of this DMA write data are dynamically calculated;

[0095] When the descriptor configuration is completed, it jumps to the WAIT_TREADY state to wait for the AXIS_Tready signal fed back by the PCIE RC device. If AXIS_Tready is pulled high, it jumps to the RD_START state. After several cycles, it jumps to the CHN_TRANS state (if the number of data channels is M, the data channel number N is 0≤N≤M-1);

[0096] In the CHN_TRNAS state, the multi-channel polling and DMA write state machine generates a CHN_AXIS_Tready signal according to the AXIS_Tready signal fed back by the PCIE RC device and the data channel number currently to be sent, and sends the CHN_AXIS_Tready signal to the single-channel internal synchronous timing conversion AXI Stream state machine corresponding to the data channel number, thereby generating a DMA write data;

[0097] When a DMA write is completed and a frame of data is sent, it jumps to the CHN_DONE state, otherwise it jumps to the WAIT_DATA state;

[0098] When the entire frame of data on the current CHN channel is sent, it is determined whether the interrupt transmission is enabled. If yes, it jumps to the INTR_GEN state, otherwise it jumps to the IDLE state.

[0099] In the INTR_GEN state, the multi-channel polling and DMA write state machine sends an interrupt request signal intr_req to the PCIE RC device, and at the same time sends the base address of the current frame data to the PCIE RC device through the state monitoring and reporting module, and then jumps to the INTR_ACK_WAIT state to wait for a reply;

[0100] When the multi-channel polling and DMA write state machine receives the interrupt reply signal intr_ack returned by the PCIE RC device, it indicates that the interrupt is sent successfully and jumps back to the IDLE state.

[0101] In one embodiment, actively initiating a DMA polling read mode data reading to a PCIE RC device and converting the read data into internal synchronization timing data includes:

[0102] Through the cooperation of multi-channel polling and DMA read state machine and single-channel AXI Stream to internal synchronous timing state machine, DMA polling read mode data reading is actively initiated to the PCIE RC device, and the read data is converted into internal synchronous timing data.

[0103] In specific implementation, the PCIE read polling module mainly implements the data read control of the PCIE RC device, realizes the multi-address reading from the PCIE RC device through the instructions output by the PCIE short message parsing module, and converts it into internal synchronous timing output. Specifically, by actively initiating DMA polling reading from the PCIE RC device, the data received from the M_AXIS_H2C interface of the PCIE XDMA is received to the PCIE RC device by configuring the PCIE descriptor. The above functions are mainly realized through the cooperation of two state machines, namely the multi-channel polling and DMA read state machine, and the single-channel AXI Stream to internal synchronous timing state machine, such as Figure 4-5 shown.

[0104] Reference Figure 4 , the workflow of multi-channel polling and DMA read status includes:

[0105] The multi-channel polling and DMA read state machine waits in the IDLE state, and when the PCIE link LINK is detected, it jumps to the WAIT_START state;

[0106] In the WAIT_START state, if the receive enable is detected, it jumps to the RECV_CHNUM_SEL state, selects the data channel number corresponding to the data read by this DMA and jumps to the DES_CONFIG state;

[0107] In the DES_CONFIG state, according to the data channel number corresponding to the data currently sent by the DMA read, the base address and length of the PCIE DMA read data output by the PCIE short message parsing module, a PCIE descriptor is generated, and the base address and data length of the current DMA read data are dynamically calculated;

[0108] When the PCIE descriptor configuration is completed, it jumps to the RECV_START state, and jumps to the CHN_RECV state after reaching the counting cycle;

[0109] In the CHN_RECV state, the multi-channel polling and DMA read state machine generates an AXIS_Tready signal and returns it to the PCIE RC device to implement a DMA read operation of the data;

[0110] When this DMA read is completed, jump to RECV_CHNUM_SEL to initiate the next DMA read.

[0111] Reference Figure 5 The workflow of converting a single-channel AXI Stream to an internal synchronous timing state machine includes:

[0112] The single-channel AXI Stream internal synchronization timing state machine waits in the IDLE and INIT states, and jumps to the CHECK_HEADER state when it detects that the receiving enable is turned on;

[0113] After the CHECK_HEADER state logic detects the arrival of data, it jumps to the WR_VIDEO_DATA state, generates a read signal according to the resolution and bit width, and reads the data from the FIFO. After the data is received, it jumps to the ENCODE_STS_CHECK state.

[0114] When the receive enable is turned off, it jumps to the IDLE state, otherwise it jumps to the CHECK_HEADER state.

[0115] In one embodiment, the status monitoring and reporting module is mainly responsible for monitoring the data transmission status during PCIE DMA read / write and ARINC818 encoding and decoding, and realizes the status reporting function to the PCIE RC device through the AXI4LITE interface. The data transmission status of the PCIE DMA read / write process includes: PCIE LINK status, PCIE DMA read / write data frame count, PCIE DMA read / write data error frame count, PCIE DMA read / write timeout count, PCIE DMA interrupt transmission request and interrupt response count. The data transmission status during the ARINC818 encoding and decoding process includes: ARINC818 receive / send FC0 frame count, ARINC818 receive / send FCN frame count, ARINC818 receive / send FC0 frame CRC error count, ARINC818 receive / send FCN frame CRC error count.

[0116] In one embodiment, the parameter calculation module is mainly responsible for the calculation of PCIE DMA and ARINC818 communication related parameters. The relevant parameters of the PCIE DMA read / write process include PCIE DMA read / write address and length, and the relevant parameters of the ARINC818 communication process include ARNIC818 receive / send Source_ID, resolution, bit width, and calculation of FCN frame Payload length. FCN frame Payload length refers to the length of the payload part in the FCN frame, that is, the size of the data field. In the FCN frame structure, Payload is the actual data content to be transmitted.

[0117] In specific implementation, the PCIE protocol interface module is mainly responsible for the implementation of the PCIE link physical layer protocol, for example, it is implemented by using DMA / Bridge Subsystem for PCI Express IP (an IP core used to implement PCI Express (PCIE) interface functions in the system. This IP core usually includes a direct memory access (DMA) controller and bridge logic to connect the PCIExpress bus with other system buses or devices).

[0118] In one embodiment, the ARINC818 encoding module is mainly responsible for the packaging process of converting the internal synchronization timing data to the ARINC818 data timing. Figure 6 As shown, the state machine waits for data in the CONT_IDLE and CONT_READY states. When the data arrives, the state machine starts to generate ARINC818 frames according to the FC0 and FCN frame formats specified by ARINC818. It should be noted that in order to realize the communication between the PCIE device and multiple ARINC818 devices, this embodiment fills different Source_IDs in the ARINC818 FC0 and FCN frame HEADER according to the data channel number CHN, see Table 1 and Table 2 below for details, to realize the binding between different channel ARINC818 devices and PCIE DMA addresses, so as to achieve the purpose of real-time communication between ARINC818 devices and PCIE devices.

[0119] Table 1 ARINC818 protocol packet format (I)

[0120] Character Byte 0 Byte 1 Byte 2 Byte 3 1 44 DEST_ID DEST_ID DEST_ID 2 00 Source_ID Source_ID Source_ID 3 61 VAR 00 00 4 VAR 00 VAR VAR 5 FF FF FF FF 6 00 00 00 00

[0121] Table 2 ARINC818 protocol packet format (II)

[0122] Data Types Source_ID Encoding CHO Data 0xab0001 CH1 Data 0xab0002 ...... ...... CHN Data 0xab000N

[0123] In one embodiment, Figure 7 As shown, decoding is the reverse process of encoding, and the principle is similar to the encoding process, which will not be repeated here. The difference is that after receiving the FCO frame, the receiving state machine needs to determine whether the current data is the communication data sent by the ARINC818 device to the PCIE RC device according to the agreed Source_ID in the FCO_HEAD state. If so, it is decoded, otherwise it returns to the FCO_IDLE state; similarly, after receiving the FCN frame, it is also necessary to determine whether the current data is the communication data according to the Source_ID in the FCN_HEADER state. If so, it is decoded, otherwise it returns to the FCN_IDLE state.

[0124] In specific implementation, the ARINC818 protocol interface module mainly realizes the conversion between the ARINIC818 protocol and the GT interface. For example, it is implemented using the 7Series FPGAs Transceivers Wizard IP (an integrated design tool provided by Xilinx for the 7 series FPGAs). This tool is mainly used to help designers configure and generate the IP core (Intellectual Property Core) of Transceivers (transceivers) to realize the function of a high-speed serial communication interface.

[0125] In the embodiment provided by the present invention, FPGA is used as a PCIE EP device to perform PCIE communication with a PCIE RC device, and ARINC818 communication is performed with multiple ARINC818 optical fiber devices through optical fiber. FPGA realizes protocol conversion between the two by actively initiating PCIE DMA polling read / write and ARINIC818 encoding / decoding. The system of the present application can optimize the data link topology and reduce system overhead while meeting the requirements of high-speed, large data volume, and low-latency real-time communication.

[0126] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A multi-device ARINC818 to PCIE communication system, characterized in that: The system includes an FPGA-based PCIE EP device, a PCIE RC device communicating with the PCIE EP device, and a plurality of ARINC818 optical fiber devices communicating with the PCIE EP device, wherein the PCIE EP device includes a PCIE protocol interface module, an ARINC818 protocol interface module, a PCIE short message parsing module, a PCIE read polling module, a PCIE write polling module, an ARINC818 encoding module, an ARINIC818 decoding module, a status monitoring and reporting module, and a parameter calculation module; The PCIE protocol interface module is communicatively connected with the PCIE RC device and is used to implement the PCIE protocol interface; The ARINC818 protocol interface module is communicatively connected with the ARINC818 optical fiber device and is used for conversion between the ARINC818 protocol and the GT interface; The PCIE short message parsing module is used to receive the short message of the PCIE RC device, parse the short message to generate a control instruction, and control the PCIE write polling module, the PCIE read polling module, the status monitoring and reporting module and the parameter calculation through the control instruction; The ARINC818 encoding module is used to package and encode the internal synchronous timing data into ARINC818 data; The ARINIC818 decoding module is used to receive, decode and convert the ARINC818 data of the multiple ARINC818 optical fiber devices into internal synchronous timing data; The PCIE write polling module is used to convert the multi-channel internal synchronous timing data output by the ARINC818 decoding module into AXI Stream timing data through a DMA polling write mode according to the control instruction and send it to the PCIE RC device; The PCIE read polling module is used to actively initiate DMA polling read mode data reading to the PCIE RC device according to the control instruction, and convert the read data into internal synchronous timing data; The status monitoring and reporting module is used to monitor the data transmission status of the PCIE DMA reading and writing process and the data transmission status of the ARINC818 encoding and decoding process, and report the monitored data transmission status to the PCIE RC device; The parameter calculation module is used to calculate the relevant parameters of the PCIE DMA reading and writing process and the ARINC818 communication process.

2. The multi-device ARINC818 to PCIE communication system according to claim 1, characterized in that: The method of converting the multi-channel internal synchronous timing data output by the ARINC818 decoding module into AXI Stream timing data through a DMA polling write mode and sending the data to the PCIE RC device includes: Through the cooperation of multi-channel polling and DMA write state machine and single-channel internal synchronous timing to AXI Stream state machine, the multi-channel internal synchronous timing data output by the ARINC818 decoding module is converted into AXI Stream timing data through DMA polling write mode and sent to the PCIE RC device.

3. The multi-device ARINC818 to PCIE communication system according to claim 2, characterized in that: The workflow of converting the single-channel internal synchronous timing to the AXI Stream state machine includes: The single-channel internal synchronous timing conversion AXI Stream state machine waits for data transmission to be enabled in IDLE and INIT states; When the data transmission is enabled, the state switches to the CHECK_HEADER state to wait for the data to arrive; When the arrival of data is detected, it jumps to the WR_VIDEO_DATA state. In this state, the internal synchronization timing data is written into the FIFO cache, and the FIFO empty and full signals are output to the multi-channel polling and DMA write state machine and wait for the AXIS_Tready signal to be pulled high. When the AXIS_Tready signal returned by the multi-channel polling and DMA write state machine is pulled high, the single-channel internal synchronization timing is converted to the AXI Stream state machine according to the single DMA write length output by the short message parsing module and the data in the FIFO is read out according to the AXI Stream timing control; When a frame of data transmission is completed, it jumps to the ENCODE_STS_CHECK state. If it is detected in this state that the data transmission enable is turned off, it jumps to the IDLE state, otherwise it jumps to the CHECK_HEADER state.

4. The multi-device ARINC818 to PCIE communication system according to claim 2, characterized in that: The workflow of the multi-channel polling and DMA write state machine includes: The multi-channel polling and DMA write state machine waits in the IDLE state, and when the PCIE link LINK is detected and the data transmission enable is turned on, it jumps to the WAIT_DATA state; In the WAIT_DATA state, the state machine determines whether there is data to be sent based on the empty and full signals output by the front-end FIFO. If so, it jumps to the CHANNEL_SEL state; In the CHANNEL_SEL state, the empty and full signals output by each data FIFO are determined by the polling and priority dynamic adjustment method, and the data channel number for initiating DMA write is selected; In the DES_CONFIG state, the PCIE descriptor is generated according to the current DMA write data channel number and the PCIE DMA write data base address and length output by the PCIE short message parsing module, and the base address and data length of this DMA write data are dynamically calculated; When the descriptor configuration is completed, it jumps to the WAIT_TREADY state to wait for the AXIS_Tready signal fed back by the PCIE RC device. If AXIS_Tready is pulled high, it jumps to the RD_START state, and after several cycles, it jumps to the CHN_TRANS state; In the CHN_TRNAS state, the multi-channel polling and DMA write state machine generates a CHN_AXIS_Tready signal according to the AXIS_Tready signal fed back by the PCIE RC device and the data channel number currently to be sent, and sends the CHN_AXIS_Tready signal to the single-channel internal synchronous timing conversion AXI Stream state machine corresponding to the data channel number, thereby generating a DMA write data; When a DMA write is completed and a frame of data is sent, it jumps to the CHN_DONE state, otherwise it jumps to the WAIT_DATA state; When the entire frame of data on the current CHN channel is sent, it is determined whether the interrupt transmission is enabled. If yes, it jumps to the INTR_GEN state, otherwise it jumps to the IDLE state. In the INTR_GEN state, the multi-channel polling and DMA write state machine sends an interrupt request signal intr_req to the PCIE RC device, and at the same time sends the base address of the current frame data to the PCIE RC device through the state monitoring and reporting module, and then jumps to the INTR_ACK_WAIT state to wait for a reply; When the multi-channel polling and DMA write state machine receives the interrupt reply signal intr_ack returned by the PCIE RC device, it indicates that the interrupt is sent successfully and jumps back to the IDLE state.

5. The multi-device ARINC818 to PCIE communication system according to claim 1, characterized in that: The method of actively initiating a DMA polling read mode to read data from a PCIE RC device and converting the read data into internal synchronization timing data includes: Through the cooperation of multi-channel polling and DMA read state machine and single-channel AXI Stream to internal synchronous timing state machine, DMA polling read mode data reading is actively initiated to the PCIE RC device, and the read data is converted into internal synchronous timing data.

6. The multi-device ARINC818 to PCIE communication system according to claim 1, characterized in that: The workflow of the multi-channel polling and DMA read status includes: The multi-channel polling and DMA read state machine waits in the IDLE state, and when the PCIE link LINK is detected, it jumps to the WAIT_START state; In the WAIT_START state, if the receive enable is detected, it jumps to the RECV_CHNUM_SEL state, selects the data channel number corresponding to the data read by this DMA and jumps to the DES_CONFIG state; In the DES_CONFIG state, according to the data channel number corresponding to the data currently sent by the DMA read, the base address and length of the PCIE DMA read data output by the PCIE short message parsing module, a PCIE descriptor is generated, and the base address and data length of the current DMA read data are dynamically calculated; When the PCIE descriptor configuration is completed, it jumps to the RECV_START state, and jumps to the CHN_RECV state after reaching the counting cycle; In the CHN_RECV state, the multi-channel polling and DMA read state machine generates an AXIS_Tready signal and returns it to the PCIERC device to implement the DMA read operation of the data; When this DMA read is completed, jump to RECV_CHNUM_SEL to initiate the next DMA read.

7. The multi-device ARINC818 to PCIE communication system according to claim 1, characterized in that: The workflow of converting a single-channel AXIStream to an internal synchronous timing state machine includes: The single-channel AXI Stream internal synchronization timing state machine waits in the IDLE and INIT states, and jumps to the CHECK_HEADER state when it detects that the receiving enable is turned on; After the CHECK_HEADER state logic detects the arrival of data, it jumps to the WR_VIDEO_DATA state, generates a read signal according to the resolution and bit width, and reads the data from the FIFO. After the data is received, it jumps to the ENCODE_STS_CHECK state. When the receive enable is turned off, it jumps to the IDLE state, otherwise it jumps to the CHECK_HEADER state.

8. The multi-device ARINC818 to PCIE communication system according to claim 1, characterized in that: The short message includes a multi-channel data base address written by PCIE DMA polling, a circular buffer size written by PCIE DMA polling, a number of circular buffers written by PCIE DMA polling, a multi-channel data base address read by PCIE DMA polling, a circular buffer size read by PCIE DMA polling, a number of circular buffers read by PCIE DMA polling, a multi-channel interrupt generation enable, a Source_ID sent by ARINC818 multi-channel, an enable of ARINC818 multi-channel sending, a data length sent by ARINC818 multi-channel, a bit width sent by ARINC818 multi-channel, a Source_ID received by ARINC818 multi-channel, an enable of ARINC818 multi-channel receiving, a data length received by ARINC818 multi-channel, and a bit width received by ARINC818 multi-channel, wherein each channel of the multi-channel corresponds to an ARINC818 optical fiber device.

9. The multi-device ARINC818 to PCIE communication system according to claim 1, characterized in that: The data transmission status of the PCIE DMA read and write process includes: PCIE LINK status, PCIE DMA read and write data frame count, PCIE DMA read and write data error frame count, PCIE DMA read and write timeout count, PCIE DMA interrupt transmission request and interrupt response count; The data transmission status in the ARINC818 encoding and decoding process includes: ARINC818 receiving / sending FC0 frame count, ARINC818 receiving / sending FCN frame count, ARINC818 receiving / sending FC0 frame CRC error count and ARINC818 receiving / sending FCN frame CRC error count.

10. The multi-device ARINC818 to PCIE communication system according to claim 1, characterized in that: The relevant parameters of the PCIEDMA read and write process include the address and length of PCIE DMA read and write, and the relevant parameters of the ARINC818 communication process include the Source_ID, resolution, bit width and FCN frame Payload length received or sent by ARNIC818.

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