IEC task data consistency synchronization method and device, electronic equipment and storage medium

Abstract

The invention provides an IEC task data consistency synchronization method and device, electronic equipment and a storage medium. The method comprises the following steps of: setting a uniformly addressed public data area and a plurality of IEC tasks, wherein each IEC task is allocated with an independent mapping data area; in the operation period of each IEC task, each IEC task is controlled to independently execute data processing operation in the corresponding distributed mapping data area; after each IEC task completes the operation in the operation period, controlling the IEC tasks to synchronize effective data in respective mapping data areas to a public data area by using a predetermined critical area synchronization mechanism; and when the IEC task enters the critical zone to execute data synchronization, controlling the execution time of the critical zone synchronization operation within a preset time range by utilizing a preset extremely short critical zone mechanism so as to control the time of the data writing operation of the IEC task on the public data zone. According to the method and the device, the consistency of the data among a plurality of IEC tasks is kept, so that the operation efficiency and the reliability of the controller are improved.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to an IEC task data consistency synchronization method, device, electronic device and storage medium. Background Art

[0002] In the field of programmable logic controllers (PLCs), tasks that execute programming specifications that comply with the International Electrotechnical Commission IEC 61131-3 standard are called IEC tasks. In a multi-task controller environment, these IEC tasks usually need to operate and update shared data areas. To ensure the accuracy and reliability of the control system, data area consistency is critical.

[0003] However, existing technologies face several challenges in dealing with data consistency of multiple IEC tasks. For example, some solutions allow controllers to share data areas when executing multiple IEC tasks, but do not guarantee data consistency, which increases the difficulty of engineers coordinating business logic. Other solutions try to maintain data consistency by locking the IEC task and treating its entire operation as a critical area. Although this is simple, it greatly reduces the system's task concurrency characteristics and overall performance.

[0004] Another solution allows each IEC task to operate an independent data area to ensure data consistency, but this increases the complexity of the design and has low efficiency in variable interaction between tasks, especially in large-scale data interaction scenarios. At the same time, some solutions divide the data area of ​​each task into sub-areas during the configuration phase, but once the configuration project changes, the data area needs to be re-divided, which affects the flexibility and maintainability of the system.

[0005] In view of the problems existing in the prior art, a new technical solution is urgently needed that can improve the operating efficiency of the controller while ensuring the consistency of the data area, simplify the writing of multi-IEC task programs, adapt to complex control scenarios, and reduce the number of equipment in industrial sites, save deployment costs, and reduce the complexity of system maintenance. This application aims to solve the above problems and provide an improved mechanism for ensuring the consistency of the data area when the controller executes multiple IEC tasks. Summary of the invention

[0006] In view of this, an embodiment of the present application provides an IEC task data consistency synchronization method, device, electronic device and storage medium to solve the problem that the data consistency processing method in the prior art is complex, resulting in reduced controller operation efficiency.

[0007] According to a first aspect of an embodiment of the present application, a method for synchronizing data consistency of IEC tasks is provided, comprising: setting a common data area with uniform addressing and a plurality of IEC tasks, each IEC task being allocated an independent mapping data area; in an operation cycle of each IEC task, controlling each IEC task to independently perform data processing operations in its allocated mapping data area; after each IEC task completes the operation in the operation cycle, using a predetermined critical section synchronization mechanism, controlling the IEC tasks to synchronize valid data in their respective mapping data areas to the common data area; when the IEC task enters the critical area to perform data synchronization, using a predetermined extremely short critical section mechanism, controlling the execution time of the critical section synchronization operation within a preset time range, so as to control the time of the IEC task's data writing operation to the common data area.

[0008] According to a second aspect of an embodiment of the present application, an IEC task data consistency synchronization device is provided, comprising: a setting module, configured to set a common data area and multiple IEC tasks with unified addressing, each IEC task being allocated an independent mapping data area; a processing module, configured to control each IEC task to independently perform data processing operations in its respective allocated mapping data area within an operation cycle of each IEC task; a synchronization module, configured to control the IEC tasks to synchronize valid data in their respective mapping data areas to the common data area using a predetermined critical area synchronization mechanism after each IEC task completes operations within the operation cycle; and a control module, configured to control the execution time of the critical area synchronization operation within a preset time range using a predetermined extremely short critical area mechanism when the IEC task enters the critical area to perform data synchronization, so as to control the time of the IEC task's data write operation to the common data area.

[0009] According to a third aspect of an embodiment of the present application, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the steps of the above method are implemented when the processor executes the computer program.

[0010] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, which stores a computer program, and when the computer program is executed by a processor, the steps of the above method are implemented.

[0011] At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects:

[0012] By setting a common data area with unified addressing and multiple IEC tasks, each IEC task is allocated an independent mapping data area; in the operation cycle of each IEC task, each IEC task is controlled to independently perform data processing operations in the mapping data area allocated to it; after each IEC task completes the operation in the operation cycle, a predetermined critical section synchronization mechanism is used to control the IEC tasks to synchronize the valid data in their respective mapping data areas to the common data area; when the IEC task enters the critical area to perform data synchronization, a predetermined extremely short critical section mechanism is used to control the execution time of the critical section synchronization operation within a preset time range, so as to control the time of the IEC task's data writing operation to the common data area. The present application realizes the maintenance of data consistency among multiple IEC tasks, thereby improving the operation efficiency and reliability of the controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0014] Figure 1 It is a schematic diagram of the principle of the critical area of ​​multiple IEC tasks in the related art;

[0015] Figure 2 It is a schematic diagram of the overall system architecture involved in the controller running multiple IEC tasks provided in an embodiment of the present application;

[0016] Figure 3 It is a flowchart of the IEC task data consistency synchronization method provided by an embodiment of the present application;

[0017] Figure 4 It is a schematic diagram of the principle of multi-IEC task data synchronization provided by an embodiment of the present application;

[0018] Figure 5 It is a structural diagram of an IEC task data consistency synchronization device provided in an embodiment of the present application;

[0019] Figure 6 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0021] IEC tasks refer to tasks used to execute user-configurable projects in a programmable logic controller (hereinafter referred to as the controller). They comply with the programming specifications of the International Electrotechnical Commission IEC61131-3 standard and are referred to as IEC tasks or tasks.

[0022] Users configure these tasks through configuration software running on a personal computer. This software allows users to compile and generate control projects, set PLC parameters and forms, and monitor the operating status of the PLC online. In order to download these configurations to the PLC, the configuration software communicates with the PLC through a serial port or Ethernet and provides a software scheduling interface.

[0023] Data consistency means that within a controller cycle of sampling input, calculation, and control output, the data involved cannot be accidentally modified by external communications, ensuring that the data used in each execution link in the same cycle is consistent.

[0024] In the operation of PLC, the execution of background management tasks and IEC tasks needs to be precisely scheduled. In addition to meeting the requirements of the embedded hardware and software platform, IEC tasks also need to handle the read and write operations of the data area to ensure data consistency. Throughout the input, calculation and control output cycle, data consistency ensures that data will not be accidentally changed by external communications, thereby ensuring that all control and detection operations are based on the same, untampered data set.

[0025] When the controller runs multiple IEC tasks, due to the uniqueness of the data area and control object associated with the configuration project, the consistency of the data area needs to be guaranteed. The following is a detailed introduction to the methods and problems of maintaining the consistency of IEC task data in the prior art with reference to the accompanying drawings. Figure 1 Schematic diagram of the principle of the critical area of ​​multiple IEC tasks in the related art. Figure 1 As shown, the principle of multi-IEC task critical area in the prior art includes the following contents:

[0026] according to Figure 1 You can see the distribution and overlap of different IEC tasks on the timeline, as well as their relationship with the critical section. These IEC tasks are activated and occupy critical sections at different time periods, showing possible interlocking situations between tasks and how to avoid data consistency issues. Specifically, Figure 1It shows that at a specific moment, one IEC task may be in execution while other IEC tasks are in standby state, waiting to access the critical section. This schematic diagram reflects a technical challenge in the existing multi-IEC task execution, that is, how to effectively schedule multiple IEC tasks to optimize the performance of the PLC while ensuring data consistency.

[0027] based on Figure 1 The principle of the critical section of multiple IEC tasks is shown, and the existing method for implementing the data consistency of multiple IEC tasks may include the following methods:

[0028] The first method: The embedded controller accesses the uniformly addressed data area when continuously executing multiple IEC tasks. The consistency of the data is not guaranteed and it relies on the coordination of the business logic by the configuration engineer, which brings certain difficulties to the configuration.

[0029] The second method: When the embedded controller continuously executes multiple IEC tasks, it accesses the data area with unified addressing, sets the properties of the IEC task according to the configuration project, and locks the entire IEC task operation as a critical area. However, this method will greatly reduce the task concurrency characteristics, and the system performance cannot be guaranteed.

[0030] The third method: When the embedded controller continuously executes multiple IEC tasks, it operates in an independent data area to ensure data consistency. However, data access between tasks can only be achieved through inter-task communication. This method introduces greater design complexity, and the efficiency of inter-task variable reference is low, which is inadequate in large-scale data interaction scenarios.

[0031] The fourth method: When the embedded controller continuously executes multiple IEC tasks, it accesses the data area with unified addressing, determines the sub-area division of each task in the configuration stage, and the actual operation area of ​​each IEC task is independent when it is executed. However, this method will bring greater complexity to the design of the configuration software, and after the configuration project is changed, the data area is re-divided, resulting in the inability to achieve incremental downloading and non-interference downloading between tasks.

[0032] In view of the problems existing in the prior art, the present application proposes a multi-IEC task mechanism based on data area mapping and extremely short critical sections to solve the deficiencies of the existing multi-IEC task mechanism in ensuring data consistency. By limiting the operation time of the critical section to an extremely short time of about 10 microseconds to 200 microseconds, the present solution allows each IEC task to run independently, reducing the need for long waits for the critical section and improving operating efficiency. In addition, due to the decoupling between tasks in the data area, it eliminates the uncertainty of accessing data, thereby improving the reliability of the operation of the controller device.

[0033] Before describing the embodiments of the present application in detail, the system architecture involved in the technical solution of the present application in the actual application scenario is described in detail with reference to the accompanying drawings. Figure 2 Schematic diagram of the overall system architecture involved in the controller running multiple IEC tasks provided in the embodiment of the present application. Figure 2 As shown, the system is mainly divided into two parts: a personal computer and a controller. The personal computer runs configuration software and a TCP client (TCP-Client), and the controller runs multiple IEC tasks, data area management tasks, and background management tasks. The following is a detailed description of the composition and functions of the personal computer and the controller, which may include the following:

[0034] 1) The personal computer terminal mainly includes the following contents:

[0035] Configuration software: The configuration software running on a personal computer is responsible for configuration programming, configuration compilation, configuration downloading, and operation monitoring. Configuration software refers to a software installed on a personal computer that can compile and generate user-configurable projects (hereinafter referred to as configuration projects), configure the form and parameters of the controller system, and monitor the operation status of the configuration project online.

[0036] Configuration programming: Users use configuration software to write IEC tasks, which are programmed according to the IEC 61131-3 standard.

[0037] Configuration compilation: The written IEC tasks are compiled through the configuration software to ensure that they can run on the controller.

[0038] Configuration download: The compiled IEC task is downloaded to the controller, which is usually completed through TCP / IP communication, where the personal computer acts as a TCP client (TCP-Client) and the service program running on the controller acts as a TCP server (TCP-Server). Configuration download operation refers to the configuration software downloading the configuration project to the controller through the serial port or Ethernet, and providing the controller software scheduling interface, referred to as downloading.

[0039] Operation monitoring: The configuration software can also monitor the running status of IEC tasks on the controller in real time.

[0040] 2) The controller side mainly includes the following contents:

[0041] Multiple IEC tasks: Multiple IEC tasks are run in the controller, and each task executes specific control logic according to engineering requirements. The execution of IEC tasks, while complying with the embedded hardware and software platform, also requires coordination of the reading and modification of the user data area (hereinafter referred to as the data area) of the configuration project to ensure reliable detection and control of devices other than the controller.

[0042] Data area management task: This task is responsible for managing the data area of ​​each IEC task to ensure the independence and consistency of data between them. The user data area of ​​the controller is presented to the outside of the controller as a unique data area with unified addressing; each IEC task has an independent mapping area when running.

[0043] Background management tasks: It is the basis for the normal operation of the controller and is responsible for scheduling and managing the execution of all tasks, including IEC tasks and data area management tasks. Background management tasks are automatically scheduled based on the embedded software and hardware platform.

[0044] It can be seen that in the technical solution of the present application, the system framework consists of configuration software, multiple IEC tasks in the controller, data area management tasks and background management tasks. The processing process includes configuration programming, compilation, downloading and operation monitoring, and in the controller, it involves a series of operations such as concurrent execution of tasks, independent mapping and synchronous update of data. Through this mechanism, the controller can efficiently and reliably execute multiple IEC tasks while ensuring data consistency and system stability.

[0045] In addition, in the technical solution of the present application, the user data area of ​​the controller is presented to the outside as a uniformly addressed data area, but each IEC task actually operates its own independent mapping area during operation. This means that although for external devices, they access the same data area, in fact, each IEC task operates its own independent copy of the data. This design allows IEC tasks to be executed concurrently without affecting each other. At the same time, after the task is completed, it is necessary to synchronize the respective data mapping areas to the unified data area. This step is completed in the critical area to ensure data consistency.

[0046] Based on the above overall system architecture, the contents of the technical solution of the present application are described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0047] Figure 3 It is a flowchart of the IEC task data consistency synchronization method provided in an embodiment of the present application. Figure 3 The IEC task data consistency synchronization method can be executed by the controller program. Figure 3 As shown, the IEC task data consistency synchronization method may specifically include:

[0048] S301, setting a common data area with unified addressing and multiple IEC tasks, each IEC task is allocated with an independent mapping data area;

[0049] S302, in the operation cycle of each IEC task, controlling each IEC task to independently perform data processing operations in the respective allocated mapping data areas;

[0050] S303, after each IEC task completes the operation in the operation cycle, using a predetermined critical area synchronization mechanism, controlling the IEC tasks to synchronize the valid data in their respective mapped data areas to the common data area;

[0051] S304, when the IEC task enters the critical section to perform data synchronization, the predetermined extremely short critical section mechanism is used to control the execution time of the critical section synchronization operation within a preset time range to control the time of the IEC task's data writing operation on the public data area.

[0052] In some embodiments, a common data area with unified addressing and multiple IEC tasks are set, and each IEC task is allocated an independent mapping data area, including: setting a common data area with unified addressing in a programmable logic controller, and configuring multiple IEC tasks, and allocating an independent mapping data area to each IEC task, wherein the mapping data area has the same size as the common data area, and the bytes correspond to each other.

[0053] Specifically, each IEC task is allocated an independent configuration data area mapping, which is consistent in size with the public mapping area and corresponds one-to-one in bytes. During the operation of the IEC, it does not interfere with the data access of other IEC tasks to their own exclusive mapping area, nor does it access the public data area with the only unified addressing of the entire controller. The implementation process and principle of the method for mapping the configuration task to the data area in the embodiment of the present application are described in detail below in conjunction with the accompanying drawings. Figure 4 Schematic diagram of the principle of data synchronization of multiple IEC tasks provided by the embodiment of the present application. Figure 4 As shown, the mapping of the configuration task to the data area of ​​this application may include the following contents:

[0054] First, a common data area with unified addressing is set up in the PLC system architecture. This common data area is the central warehouse for all IEC tasks to access and update data. All tasks update their results to this area during the data synchronization phase.

[0055] Next, multiple IEC tasks are configured, each of which executes specific control logic as needed. For each IEC task, an independent mapped data area with the same size and byte correspondence as the common data area is allocated. This design ensures that at any given time, the data operations of one task are independent of other tasks, avoiding data competition and conflict issues.

[0056] When running each IEC task, the task will perform all read and write operations in its independent mapping area. These mapping areas serve as private copies of the public data area, ensuring data isolation during task execution.

[0057] When an IEC task completes the operation of its control logic, it will enter the data synchronization stage. In this stage, the task is responsible for synchronizing the valid data in its mapping area - that is, the data that has changed in the most recent operation cycle - back to the public data area. To this end, the embodiment of the present application adopts a carefully designed critical area synchronization mechanism, which ensures the exclusivity and consistency of the synchronization operation through methods such as locking or semaphores.

[0058] The synchronization mechanism pays special attention to efficiency, and the duration of the critical section is strictly controlled within a very short time window, usually at the microsecond level. This design minimizes the waiting time for the synchronization lock, optimizes the performance of the PLC, and maintains a high degree of data consistency.

[0059] Finally, when data synchronization is completed, the IEC task releases the critical section, allowing other waiting tasks to enter and perform their synchronization operations. The repetition of this process ensures that data integrity and real-time performance are maintained in the PLC multi-tasking environment.

[0060] Through the above-mentioned embodiments of the present application, the present application not only provides an efficient data synchronization method, but also realizes strict control of data consistency, so that when the PLC executes multiple IEC tasks, it can maintain high operating efficiency and ensure the accuracy and reliability of the control logic.

[0061] In some embodiments, during the operation cycle of each IEC task, each IEC task is controlled to independently perform data processing operations in its respective assigned mapping data area, including: during the execution of the IEC task, each IEC task is controlled to independently perform data processing operations in its respective mapping data area during its respective operation cycle, wherein the data processing operations include the IEC task performing data reading operations and data writing operations in its respective mapping data area.

[0062] Specifically, each IEC task is controlled to perform data processing operations independently of other IEC tasks during its operation cycle. These operations specifically include reading and writing data in its assigned mapping area. In order to ensure the independence of operations, the mapping area of ​​each task is logically isolated to ensure that during the execution of the task, it will not be interfered by other tasks or cause data conflicts.

[0063] During this process, each IEC task runs in parallel, using its own processor core or time slicing on a single core to independently access its own mapping area. Since the data processing operations of each task are performed in an independent mapping area, even if multiple IEC tasks run simultaneously in physical time, they are logically isolated.

[0064] Further, in order to improve the efficiency of the system, especially in PLCs with multi-core processors, this method can take advantage of parallel computing and allow multiple IEC tasks to process data simultaneously without affecting each other. This independent data processing method simplifies the synchronization requirements between tasks, because each task only needs to synchronize its own data changes to the common data area at the end of its own operation cycle.

[0065] The independent data processing method of the above embodiment optimizes the performance and reliability of PLC in processing complex industrial control systems. By providing an independent data processing space for each IEC task, not only data consistency is ensured, but also synchronization conflicts are significantly reduced, and system response time and processing capabilities are improved.

[0066] In some embodiments, a predetermined critical section synchronization mechanism is used to control IEC tasks to synchronize valid data in their respective mapped data areas to a common data area, including: whenever an IEC task completes an operation within an operation cycle, the valid data in the mapped data area corresponding to the IEC task after the operation is completed is synchronized to the common data area, wherein the valid data includes data actually used and modified within the operation cycle of the IEC task.

[0067] Specifically, the embodiment of the present application adopts a predetermined critical area synchronization mechanism to ensure that each IEC task can effectively synchronize data to the common data area, thereby maintaining the stable operation of the control system. First, in the initialization phase of the PLC, a common data area with a unified address is set. In addition, an independent mapping data area of ​​the same size is allocated to each IEC task in the PLC, and it is ensured that the location of these areas in the memory corresponds to the common data area.

[0068] Furthermore, each IEC task executes independently in its own operation cycle, processing the data in its own mapping area. This includes reading and writing operations on data required by specific control logic. At the end of each IEC task's operation cycle, the system identifies the data actually used and modified by the task in the mapping area, which constitutes the valid data. Next, this part of the valid data needs to be synchronized to the common data area.

[0069] Furthermore, through the critical section synchronization mechanism, when any IEC task completes its operation cycle, it will immediately try to synchronize its valid data to the common data area. During the synchronization process, a lock mechanism or semaphore is used to control exclusive access to the common data area to prevent data competition in the synchronization operation.

[0070] The embodiment of the present application ensures the consistency and real-time performance of data when multiple IEC tasks are executed in parallel through effective critical section management and fast data synchronization mechanism. This method not only improves the reliability of the control system, but also optimizes the overall performance of the system, especially in high-concurrency control tasks. Through such implementation, the technical solution can adapt to various complex industrial control applications and ensure the accurate execution of control instructions.

[0071] In some embodiments, the critical section synchronization mechanism adopts locking or semaphore control technology, and the method also includes: when the current IEC task enters the critical section synchronization operation, detecting whether there are other IEC tasks that are in the process of critical section synchronization operation, when there are other IEC tasks that are in the process of critical section synchronization operation, controlling the current IEC task to wait to enter the critical section synchronization operation, and after waiting for other IEC tasks to complete data synchronization, controlling the current IEC task to perform the critical section synchronization operation.

[0072] Specifically, the embodiment of the present application provides a critical section synchronization mechanism based on locking or semaphore control technology. This mechanism is used to manage the data synchronization operation of multiple IEC tasks in a programmable logic controller (PLC) to ensure data consistency and smooth synchronization operation. The following are the detailed steps of the synchronization method:

[0073] Critical section mechanism initialization: When the PLC system starts, a critical section synchronization mechanism is initialized to provide a synchronization lock or semaphore control mechanism for all IEC tasks.

[0074] Synchronization detection and queuing: When any IEC task completes its operation cycle and is ready to synchronize data to the common data area, it first checks the status of the synchronization lock or semaphore. If it finds that the synchronization lock is already held by other IEC tasks, the current task enters the waiting state until the lock is released.

[0075] Synchronous waiting mechanism: During the waiting process, the task enters a dormant or polling state and continuously monitors the synchronization lock. This waiting process prioritizes ensuring that the data synchronization of tasks already in the critical section can be completed without interference.

[0076] Data synchronization execution: Once the critical area becomes available, that is, no other IEC task is performing data synchronization operations, the currently waiting IEC task will obtain the synchronization lock and start synchronizing the valid data in its mapping area to the common data area. The synchronization operation is performed quickly to ensure that other waiting tasks can get the synchronization opportunity as soon as possible.

[0077] Through the method of the above embodiment, multiple IEC tasks running in the PLC can efficiently synchronize their data while ensuring data consistency. The locking or semaphore mechanism simplifies the critical section management, so that the synchronization operation can be coordinated in an environment where multiple tasks are executed concurrently. In addition, the method in this embodiment also takes into account the potential impact of the synchronization operation on the performance of the PLC system, and minimizes this impact through a carefully designed waiting and release strategy.

[0078] In some embodiments, the extremely short critical section mechanism includes: setting the execution time of the critical section synchronization operation within a preset time range to minimize the waiting time of other IEC tasks, wherein the execution time of the critical section synchronization operation is much shorter than the operation cycle time of the IEC task.

[0079] Specifically, the embodiment of the present application also provides a very short critical section mechanism for data synchronization of multiple IEC tasks in a programmable logic controller (PLC). The mechanism is intended to ensure that even when multiple tasks are executed concurrently, efficient data synchronization can be achieved while minimizing the impact on system performance. The following are the implementation steps of the mechanism:

[0080] Critical section time preset: The system presets a critical section synchronization operation execution time range. This time range is designed to be extremely short to ensure that any IEC task waits to enter the critical section after completing the operation to minimize the time.

[0081] Independent operation and synchronization preparation: Multiple IEC tasks configured in the PLC perform parallel operations in independent mapping areas. At the end of the operation cycle of each task, the system will prepare to synchronize the mapping area data of the task to the common data area.

[0082] Perform extremely short critical section synchronization: When the IEC task enters the data synchronization phase, the critical section control mechanism will be triggered. If the critical section is not currently occupied by any task, the IEC task will immediately perform data synchronization operations. This operation is limited to a preset extremely short time. For example, a typical embedded system synchronizes typical configuration data scale data, which takes about 10us to 100us; the task single cycle running time in a typical configuration is about 3ms to 500ms. This is based on the fact that synchronization only involves memory data copy operations, and its operation speed is much higher than conventional data processing.

[0083] Minimize resource contention: The time required for synchronization operations is much shorter than a single operation cycle of the IEC task. Therefore, even when multiple tasks request synchronization at the same time, the waiting time and waste of CPU resources are minimized due to the extremely short critical section time.

[0084] Distributed synchronization time: To further optimize system performance, synchronization operations are not performed at fixed times, but are distributed according to the actual time each IEC task completes the operation. This approach reduces the possibility of multiple IEC tasks competing for critical sections at the same time.

[0085] Minimize conflicts: Since the time for each IEC task to complete the operation is not exactly the same, and the synchronization operation is very fast, the probability of conflicts between tasks when synchronizing data is very low. Even if a conflict occurs, the impact on CPU resources is very small because the synchronization process is very short.

[0086] Ensure data consistency: By precisely controlling the operation duration and synchronization mechanism of the critical area, it ensures that even in the case of multiple tasks concurrently, each task's update of the common data area can maintain data integrity and consistency, avoiding data corruption or errors.

[0087] Through the method of the above embodiment, the technical solution realizes fast and effective data synchronization in a high-concurrency controller environment, while ensuring the efficient operation of the entire system, which is crucial for industrial control applications with extremely high real-time requirements. In addition, the technical solution effectively reduces the performance bottleneck caused by data synchronization and optimizes the performance and reliability of the controller.

[0088] In some embodiments, after the IEC task completes data synchronization, the method further includes: releasing the critical section of the IEC task that completes data synchronization so that other IEC tasks can perform data synchronization operations.

[0089] Specifically, the embodiment of the present application also describes in detail how to effectively release critical section resources after performing data synchronization operations in a multi-IEC task environment to ensure that other IEC tasks can smoothly perform their data synchronization operations. This process is crucial to maintaining the efficiency and consistency of data synchronization.

[0090] Furthermore, in the PLC system, after each IEC task completes its data synchronization operation, the system will immediately detect whether the operation is successfully completed. This detection process ensures that all necessary data has been accurately copied from the mapping area to the common data area.

[0091] Furthermore, once the data synchronization operation of the IEC task is confirmed to be completed, the task will immediately release the critical section resources it holds, such as synchronization locks or semaphores. The release operation is fast to ensure that no unnecessary delay is caused by resource release.

[0092] Furthermore, at the same time as releasing the critical section resources, the system will update the relevant status information, indicating that the critical section is now available, and other IEC tasks that are waiting for synchronization operations can start to perform their data synchronization.

[0093] Furthermore, after releasing the critical section resources, the system checks whether there are other IEC tasks waiting for data synchronization. If there are waiting tasks, the system will activate these tasks according to a predetermined strategy (such as first-come, first-served), allowing them to enter the critical section and perform their data synchronization. This process ensures that each task has an independent operating space when entering the critical section, and will not have data overwriting or synchronization conflicts with other tasks, thus ensuring the integrity and consistency of data synchronization.

[0094] Furthermore, as each task completes data synchronization and releases critical section resources in turn, the PLC system forms an efficient continuous synchronization process, allowing all IEC tasks to complete data synchronization at the appropriate time, thereby maintaining the stability and response speed of the system.

[0095] Through the method of the above embodiment, multiple IEC tasks in the PLC system can achieve efficient and coordinated data synchronization, ensuring the consistency and accuracy of the system processing logic, especially in complex industrial control applications with frequent data synchronization requirements.

[0096] It should be noted that the technical solutions of the above embodiments of the present application are applicable to a variety of fields, not only limited to the field of industrial control, but can also be applied to the field of IT information technology.

[0097] The implementation process of the IEC task data consistency synchronization method of the present application is described below with reference to an example in a specific scenario, which may specifically include the following contents:

[0098] The embodiment of the present application describes a process for data synchronization of multiple IEC tasks in a programmable logic controller (PLC). The process takes into account the periodicity of task operation, the differences in computational time consumption, and the uncertainty of synchronization time, and aims to optimize the synchronization mechanism to reduce the impact on CPU resources and improve overall system efficiency.

[0099] First, three IEC tasks in the PLC system are set up, each with different operation cycles and time consumption. These tasks need to synchronize data to a common data area with unified addressing at the end of their respective operation cycles. The synchronization operation relies on the critical section mechanism, which is usually achieved by locking or using semaphores.

[0100] Before the synchronization operation begins, each IEC task will check the status of the critical section. If no other task occupies the critical section, the task will immediately perform data synchronization, that is, copy the valid data from its independent mapping area to the common data area. Valid data refers only to the data part actually used and modified by the task during this operation cycle.

[0101] from Figure 4It can be observed that the synchronization operation of IEC Task 2 has no time overlap with other tasks, so its data synchronization operation does not cause waiting or waste of CPU resources. However, there is a time conflict when IEC Task 1 and IEC Task 3 perform data synchronization. Specifically, when IEC Task 3 is ready to synchronize its data, it finds that the critical section has been occupied by IEC Task 1, so IEC Task 3 enters the waiting state.

[0102] It is worth noting that, despite the existence of conflicts, the waiting time of IEC Task 3 is extremely short because the data synchronization operation takes only a few tens of microseconds. This is because the data synchronization operation is essentially a memory data copy process, which is much faster than the calculation process. The data size is between 1 Byte and 4 MBytes, with 200 KBytes as a typical value.

[0103] After the data synchronization operation is completed, IEC Task 1 releases the critical section, which allows IEC Task 3 to immediately enter the critical section and perform its synchronization operation. Due to the short execution time of the synchronization operation, the waiting of IEC Task 3 has almost no effect on the multitasking concurrency of the controller.

[0104] Through such a synchronization process design, multiple IEC tasks in the PLC system can efficiently synchronize their data with minimal impact on system performance. This embodiment provides an efficient and reliable data synchronization method suitable for industrial control scenarios requiring high concurrency and data consistency.

[0105] According to the technical solution provided by the embodiment of the present application, the technical solution of the present application effectively realizes the guarantee of data consistency of multiple IEC tasks by innovatively introducing data area mapping technology. This mapping technology provides an independent data operation space for each IEC task, thereby solving the common problem of data access conflict between tasks in the prior art. Through this method, not only the complexity of interaction between tasks is reduced, but also the overall system hardware architecture design is significantly simplified. Thereby, the real-time cost of the project is reduced, and the reliability and maintainability of the system are enhanced.

[0106] Furthermore, the technical solution of the present application utilizes the extremely small critical section technology to finely control the resource usage during the data synchronization process. Compared with the conventional long critical section method, the extremely small critical section technology significantly reduces the waiting time of CPU resources, thereby avoiding the waste of resources. This efficient synchronization mechanism improves the utilization rate of the controller CPU, allowing it to be more efficient when processing other tasks, especially in scenarios where multiple tasks are processed in parallel. In addition, due to the significant reduction in the critical section operation time, the response time of the controller is also improved, thereby providing more efficient data processing capabilities for real-time control applications.

[0107] Therefore, in summary, the technical solution of the present application not only enhances the protection of data consistency, but also effectively improves the performance and efficiency of the entire control system by optimizing the critical section synchronization mechanism, bringing significant technological progress to complex industrial automation control systems.

[0108] The following is an embodiment of the device of the present application, which can be used to execute the embodiment of the method of the present application. For details not disclosed in the embodiment of the device of the present application, please refer to the embodiment of the method of the present application.

[0109] Figure 5 Schematic diagram of the structure of the IEC task data consistency synchronization device provided by the embodiment of the present application. Figure 5 As shown, the IEC task data consistency synchronization device includes:

[0110] A setting module 501 is configured to set a common data area with unified addressing and a plurality of IEC tasks, each IEC task is allocated with an independent mapping data area;

[0111] The processing module 502 is configured to control each IEC task to independently perform data processing operations in the respective allocated mapping data areas during the operation cycle of each IEC task;

[0112] The synchronization module 503 is configured to control the IEC tasks to synchronize the valid data in their respective mapped data areas to the common data area using a predetermined critical area synchronization mechanism after each IEC task completes the operation in the operation cycle;

[0113] The control module 504 is configured to control the execution time of the critical section synchronization operation within a preset time range by using a predetermined extremely short critical section mechanism when the IEC task enters the critical section to perform data synchronization, so as to control the time of the IEC task's data writing operation on the common data area.

[0114] In some embodiments, Figure 5 The setting module 501 sets a common data area with unified addressing in the programmable logic controller, configures multiple IEC tasks, and allocates an independent mapping data area to each IEC task, wherein the mapping data area has the same size as the common data area, and the bytes correspond to each other.

[0115] In some embodiments, Figure 5 During the execution of the IEC tasks, the processing module 502 controls each IEC task to independently perform data processing operations in the corresponding mapped data area within its own operation cycle, wherein the data processing operations include the IEC tasks performing data reading operations and data writing operations in their own mapped data areas.

[0116] In some embodiments, Figure 5The synchronization module 503 synchronizes the valid data in the mapping data area corresponding to the IEC task after the operation is completed to the common data area whenever an IEC task completes the operation within the operation cycle, wherein the valid data includes the data actually used and modified within the operation cycle of the IEC task.

[0117] In some embodiments, the critical section synchronization mechanism uses locking or semaphore control technology. Figure 5 The synchronization module 503 is used to detect whether there are other IEC tasks in the process of critical section synchronization operation when the current IEC task enters the critical section synchronization operation. When there are other IEC tasks in the process of critical section synchronization operation, the current IEC task is controlled to wait for entering the critical section synchronization operation, and after waiting for other IEC tasks to complete data synchronization, the current IEC task is controlled to perform the critical section synchronization operation.

[0118] In some embodiments, Figure 5 The control module 504 sets the execution time of the critical section synchronization operation within a preset time range to minimize the waiting time of other IEC tasks, wherein the execution time of the critical section synchronization operation is much shorter than the operation cycle time of the IEC task.

[0119] In some embodiments, Figure 5 After the IEC task completes data synchronization, the control module 504 releases the critical section of the IEC task that has completed data synchronization, so that other IEC tasks can perform data synchronization operations.

[0120] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0121] Figure 6 Schematic diagram of an electronic device 6 provided in an embodiment of the present application. Figure 6 As shown, the electronic device 6 of this embodiment includes: a processor 601, a memory 602, and a computer program 603 stored in the memory 602 and executable on the processor 601. When the processor 601 executes the computer program 603, the steps in the above-mentioned method embodiments are implemented. Alternatively, when the processor 601 executes the computer program 603, the functions of the modules / units in the above-mentioned device embodiments are implemented.

[0122] The electronic device 6 may be a desktop computer, a notebook, a PDA, a cloud server, or other electronic device. The electronic device 6 may include, but is not limited to, a processor 601 and a memory 602. Those skilled in the art will appreciate that Figure 6The electronic device 6 is merely an example and does not limit the electronic device 6 . The electronic device 6 may include more or less components than those shown in the figure, or different components.

[0123] The processor 601 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0124] The memory 602 may be an internal storage unit of the electronic device 6, for example, a hard disk or memory of the electronic device 6. The memory 602 may also be an external storage device of the electronic device 6, for example, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 6. The memory 602 may also include both an internal storage unit of the electronic device 6 and an external storage device. The memory 602 is used to store computer programs and other programs and data required by the electronic device.

[0125] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units.

[0126] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium (e.g., a computer-readable storage medium). Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. The computer program may include computer program code, which may be in source code form, object code form, executable file or some intermediate form. Computer-readable storage media may include: any entity or device capable of carrying computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc.

[0127] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A method for synchronizing IEC task data consistency, characterized in that: include: Setting a common data area with unified addressing and a plurality of IEC tasks, each of the IEC tasks being allocated with an independent mapping data area; In a calculation cycle of each of the IEC tasks, controlling each of the IEC tasks to independently perform data processing operations in the respectively allocated mapping data areas; After each of the IEC tasks completes the operation in the operation cycle, using a predetermined critical area synchronization mechanism, the IEC tasks are controlled to synchronize valid data in their respective mapped data areas to the common data area; When the IEC task enters the critical section to perform data synchronization, the predetermined extremely short critical section mechanism is used to control the execution time of the critical section synchronization operation within a preset time range to control the time of the IEC task's data writing operation on the public data area.

2. The method according to claim 1, characterized in that The common data area and multiple IEC tasks with unified addressing are set, and each IEC task is allocated with an independent mapping data area, including: A common data area with unified addressing is set in the programmable logic controller, and a plurality of the IEC tasks are configured, and an independent mapping data area is allocated to each of the IEC tasks, wherein the mapping data area has the same size as the common data area, and the bytes correspond to each other.

3. The method according to claim 1, characterized in that The step of controlling each IEC task to independently perform data processing operations in a respective allocated mapping data area during a calculation cycle of each IEC task comprises: During the execution of the IEC tasks, each of the IEC tasks is controlled to independently perform data processing operations in the corresponding mapped data area within its own operation cycle, wherein the data processing operations include the IEC tasks performing data reading operations and data writing operations in their own mapped data areas.

4. The method according to claim 1, characterized in that: The method of utilizing a predetermined critical area synchronization mechanism to control the IEC tasks to synchronize valid data in respective mapped data areas to the common data area comprises: Whenever one of the IEC tasks completes the operation within the operation cycle, the valid data in the mapping data area corresponding to the IEC task after the operation is completed is synchronized to the common data area, wherein the valid data includes the data actually used and modified within the operation cycle of the IEC task.

5. The method according to claim 4, characterized in that The critical section synchronization mechanism adopts locking or semaphore control technology, and the method further includes: When the current IEC task enters the critical section synchronization operation, it is detected whether there are other IEC tasks that are in the critical section synchronization operation process. When there are other IEC tasks that are in the critical section synchronization operation process, the current IEC task is controlled to wait for entering the critical section synchronization operation, and after waiting for the other IEC tasks to complete data synchronization, the current IEC task is controlled to perform the critical section synchronization operation.

6. The method according to claim 1, characterized in that The very short critical section mechanism includes: The execution time of the critical section synchronization operation is set within a preset time range to minimize the waiting time of other IEC tasks, wherein the execution time of the critical section synchronization operation is much shorter than the operation cycle time of the IEC task.

7. The method according to claim 1, characterized in that After the IEC task completes data synchronization, the method further includes: The critical section of the IEC task after completing data synchronization is released so that other IEC tasks can perform data synchronization operations.

8. An IEC task data consistency synchronization device, characterized in that: include: A setting module is configured to set a common data area with unified addressing and a plurality of IEC tasks, each of the IEC tasks being allocated with an independent mapping data area; A processing module, configured to control each of the IEC tasks to independently perform data processing operations in the respective allocated mapping data areas during a calculation cycle of each of the IEC tasks; a synchronization module configured to control the IEC tasks to synchronize valid data in their respective mapped data areas to the common data area using a predetermined critical area synchronization mechanism after each of the IEC tasks completes the operation in the operation cycle; The control module is configured to control the execution time of the critical section synchronization operation within a preset time range by using a predetermined extremely short critical section mechanism when the IEC task enters the critical section to perform data synchronization, so as to control the time of the data writing operation of the IEC task to the common data area.

9. An electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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