Chip halving method, halving system, equipment and storage medium

Abstract

The invention provides a chip halving method, a halving system, equipment and a storage medium. The method comprises the following steps: acquiring a parameter file and initial data; the parameter file comprises ISP pipeline parameters; the ISP pipeline parameters comprise calculation parameters and non-calculation parameters; the ISP assembly line parameters describe functions of an ISP assembly line; configuring the Cmodel based on the initial data and the calculation parameters, and controlling the Cmodel to process the initial data based on the non-calculation parameters to obtain a reference result; configuring a target chip based on the initial data, the calculation parameters and the non-calculation parameters, and starting the target chip to obtain an actual result; the actual result is obtained by processing the initial data by the target chip based on the calculation parameter and the non-calculation parameter; based on the actual result and the reference result, obtaining a bipartition result; the bipartition result indicates that bipartition of the target chip succeeds or fails. According to the technical scheme, the halving process of the target chip running the ISP assembly line can be simplified.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a chip bisection method, bisection system, device and storage medium. Background Art

[0002] Simulation tools are mainly used to verify the functions and evaluate the performance of chips before hardware implementation. Simulation tools are usually written in programming languages ​​and can simulate the functions of chips. Bisection in the chip development process means that the results of chip hardware processing can be aligned bit by bit with the results of simulation tools. Bisection is crucial for chip development, and the ability to bisection means that the actual functions of the chip are consistent with the design goals.

[0003] In the related art, chip results are often obtained by running a chip SDK (Software Development Kit), and then running a simulation tool to obtain results, and finally the two results are divided into two halves.

[0004] However, the SDK contains all software components related to the chip functions, with a huge amount of code, and extremely complex logic calls and parameter conversions. In addition, the ISP (Image Signal Processor) pipeline processing involves multiple modules, and the specific processing flow and processing parameters are also relatively complex. Therefore, the bisection process of the chip running the ISP pipeline is very complicated. Summary of the invention

[0005] The embodiment of the present application provides a chip bisection method, bisection system, device and storage medium, which can simplify the bisection process of the target chip running the ISP pipeline. The technical solution is as follows:

[0006] According to a first aspect of an embodiment of the present application, a chip bisection method is provided, the method comprising:

[0007] Obtain a parameter file and initial data; the parameter file includes ISP pipeline parameters; the ISP pipeline parameters include calculation parameters and non-calculation parameters; the ISP pipeline parameters describe the function of the ISP pipeline; the calculation parameters participate in the calculation process; the non-calculation parameters do not participate in the calculation;

[0008] The Cmodel is configured based on the initial data and the calculation parameters, and the Cmodel is controlled to process the initial data based on the non-calculation parameters to obtain a reference result; the Cmodel processes the initial data based on the calculation parameters;

[0009] The target chip is configured based on the initial data, the calculation parameters and the non-calculation parameters, and the target chip is started to obtain an actual result; the actual result is obtained by the target chip processing the initial data based on the calculation parameters and the non-calculation parameters;

[0010] Based on the actual result and the reference result, a bisection result is obtained; the bisection result indicates whether the target chip is bisected successfully or failed.

[0011] In some embodiments, the obtaining of initial data includes:

[0012] Generate the initial data; or search for the initial data.

[0013] In some embodiments, the method further includes: preprocessing the initial data to obtain preprocessed data.

[0014] In some embodiments, the Cmodel includes a plurality of modules;

[0015] The method further comprises:

[0016] parsing the calculation parameters to obtain operation parameters, mode parameters and image parameters; and

[0017] Parsing the non-calculation parameters to obtain connection relationship parameters;

[0018] The operating parameters are used to describe the operating mode of each module in the Cmoel;

[0019] The mode parameter is used to describe the operation mode of each module in the Cmodel;

[0020] The connection relationship parameters are used to describe the data interaction mode between the modules;

[0021] The image parameters are used to describe image features.

[0022] In some embodiments, configuring the Cmodel based on the initial data and the calculation parameters includes:

[0023] Creating a class object of each module based on the operation parameters, mode parameters and image parameters;

[0024] configuring each of said class objects based on target portion parameters;

[0025] Each class object configures the corresponding module based on the target part parameters to obtain each target module; the target part is the part of the operation parameters, mode parameters and image parameters corresponding to the class object;

[0026] The initial data is transferred to the target module.

[0027] In some embodiments, controlling the Cmodel to process the initial data based on the non-computational parameters to obtain a reference result includes:

[0028] Based on the connection relationship parameters, the i-th target module is controlled to output the i-th processing result to the i+1-th target module; the i-th processing result is obtained based on the i-th target module processing the initial data; the i-th target module processes the initial data based on the corresponding target part parameters; i is an integer greater than or equal to 1;

[0029] The reference result is obtained by processing the i-th processing result based on the i+1-th target module.

[0030] In some embodiments, the target chip includes a runtime module, a driver module, a register, and an operation module;

[0031] The configuring the target chip based on the initial data, the calculation parameters and the non-calculation parameters includes:

[0032] Controlling the runtime module to call the driver module to configure the register; the driver module configures the register based on the initial data, the calculation parameters and the non-calculation parameters;

[0033] The driving module is controlled to call the initial data, the calculation parameters and the non-calculation parameters in the register to configure the operation module.

[0034] In some embodiments, the step of starting the target chip to obtain an actual result includes:

[0035] The driving module is controlled to start the running module to obtain the actual result; the actual result is obtained by the running module processing the initial data based on the calculation parameters and the non-calculation parameters.

[0036] In some embodiments, obtaining a bisection result based on the actual result and the reference result includes:

[0037] Processing the reference result based on a cryptographic hash function to obtain a first hash value; and

[0038] Processing the actual result based on the cryptographic hash function to obtain a second hash value;

[0039] The bisection result is obtained based on the first Hash value and the second Hash value.

[0040] In some embodiments, obtaining the bisection result based on the first hash value and the second hash value includes:

[0041] When the first Hash value matches the second Hash value, a first bisection result is obtained; the first bisection result indicates that the target chip is successfully bisected; or

[0042] When the second Hash value does not match the second Hash value, a second bisection result is obtained; the second bisection result indicates that the target chip bisection fails.

[0043] According to a second aspect of an embodiment of the present application, a chip splitting system is provided, the system comprising:

[0044] An acquisition module, used for acquiring a parameter file and initial data; the parameter file includes ISP pipeline parameters; the ISP pipeline parameters include calculation parameters and non-calculation parameters; the ISP pipeline parameters describe the function of the ISP pipeline; the calculation parameters participate in the calculation process; the non-calculation parameters do not participate in the calculation;

[0045] A first processing module is used to configure the Cmodel based on the initial data and the calculation parameters, and control the Cmodel to process the initial data based on the non-calculation parameters to obtain a reference result; the Cmodel processes the initial data based on the calculation parameters;

[0046] A second processing module is used to configure the target chip based on the initial data, the calculation parameters and the non-calculation parameters, start the target chip, and obtain an actual result; the actual result is obtained by the target chip processing the initial data based on the calculation parameters and the non-calculation parameters;

[0047] A calculation module is used to obtain a bisection result based on the actual result and the reference result; the bisection result indicates whether the target chip is successfully bisected or failed.

[0048] According to a third aspect of an embodiment of the present application, a computer device is provided, comprising a processor and a memory, wherein the memory is used to store at least one program, and the at least one program is loaded by the processor and executes the chip bisection method as described above.

[0049] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which at least one program is stored. The at least one program is loaded and executed by a processor to implement the chip bisection method as described above.

[0050] In the embodiment of the present application, the embodiment of the present application provides a chip bisection method, which describes the ISP pipeline parameters in the form of a file, so that the ISP pipeline parameters can be flexibly connected and configured. And only a small amount of code needs to be provided for the driver and Cmodel. Even if new ISP pipeline parameters are added later, there is no need to change the code, only the file needs to be modified, thereby greatly simplifying the bisection process of the target chip running the ISP pipeline, thereby reducing the workload of developers and improving the efficiency of developers. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0052] Figure 1 is a schematic diagram of an implementation environment provided according to an embodiment of the present application;

[0053] Figure 2 It is a schematic diagram of a process of a chip bisection method provided according to an embodiment of the present application;

[0054] Figure 3 is a flow chart of step 202 provided according to an embodiment of the present application;

[0055] Figure 4 is a flow chart of step 203 provided according to an embodiment of the present application;

[0056] Figure 5 is a flow chart of step 204 provided according to an embodiment of the present application;

[0057] Figure 6 It is a schematic diagram of the structure of a chip subsystem provided according to an embodiment of the present application;

[0058] Figure 7 is a schematic diagram of the structure of a terminal provided according to an embodiment of the present application;

[0059] Figure 8 It is a structural diagram of a server provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0060] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0061] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0062] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items with substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there a limitation on the quantity and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms.

[0063] These terms are only used to distinguish one element from another element. For example, without departing from the scope of various examples, a first action can be referred to as a second action, and similarly, a second action can also be referred to as a first action. Both the first action and the second action can be actions, and in some cases, can be separate and different actions.

[0064] Here, at least one means one or more than one, for example, at least one action can be one action, two actions, three actions, or any other action that is an integer greater than or equal to one. And multiple means two or more than two, for example, multiple actions can be two actions, three actions, or any other action that is an integer greater than or equal to two.

[0065] Figure 1 It is a schematic diagram of an implementation environment provided according to an embodiment of the present application, and the implementation environment may include a terminal 101 and a server 102.

[0066] In the terminal 101, Cmodel (C-Model, C language model), chip and subsystem are provided. Cmodel is a C language model of chip design, which is used for functional verification and performance evaluation before chip manufacturing. Cmodel can simulate chip functions and help developers to develop software and locate problems before hardware implementation. Cmodel usually includes algorithm model, internal structure and timing definition, etc.

[0067] For example, a Cmodel, a chip, and a subsystem are set on a computer or a smart phone. The subsystem can obtain a first result based on the Cmodel; and the chip obtains a second result; based on the first result and the second result, a subsystem can obtain a subsystem result; and based on the subsystem result, the function of the chip can be verified and the performance can be evaluated.

[0068] The terminal 101 may be a smart phone with a Cmodel, a chip and a subsystem, a wearable device, a personal computer, a laptop, a tablet computer, a smart TV and a vehicle-mounted terminal, etc.

[0069] The server 102 may be a single server, a server cluster consisting of multiple servers, or a cloud processing center.

[0070] The terminal 101 is connected to the server 102 via a wired or wireless network.

[0071] In some embodiments, the wireless network or wired network uses standard communication technology and / or protocol. The network is usually the Internet, but it can also be any network, including but not limited to any combination of local area network (LAN), metropolitan area network (MAN), wide area network (WAN), mobile, wired or wireless network, private network or virtual private network. In some embodiments, the data exchanged through the network is represented by technology and / or format including HyperText Mark-up Language (HTML), Extensible Markup Language (XML), etc. In addition, conventional encryption technologies such as Secure Socket Layer (SSL), Transport Layer Security (TLS), Virtual Private Network (VPN), Internet Protocol Security (IPsec) can also be used to encrypt all or some links. In other embodiments, customized and / or dedicated data communication technology can also be used to replace or supplement the above data communication technology.

[0072] In the related technology, SDK contains all software components related to chip functions, with a huge amount of code, and extremely complex logic calls and parameter conversions. Using SDK for splitting requires software coding development and debugging, which is complex to operate, and the code is difficult to reuse, which is inefficient. In addition, using SDK also requires debugging the function to the actual application state. However, in actual application, the ISP pipeline often turns on dozens of functional modules, and the functional modules are coupled with each other. The parameters are calculated through layers of logic, making it difficult to effectively identify specific modules and specific reasons, which is often time-consuming and labor-intensive. Moreover, the splitting results of SDK cannot be subjected to regression verification testing, which will lead to repeated problems in subsequent software development that cannot be detected and intercepted, resulting in repeated workload.

[0073] In order to simplify the bisection process of a target chip running an ISP pipeline, an embodiment of the present application provides a chip bisection method.

[0074] The ISP pipeline is a process consisting of a series of modules used to process image signals in a camera system. These modules are usually connected end to end and work simultaneously driven by a high-speed clock to post-process the raw image signals output by the front-end image sensor to optimize the image quality. Specifically, the ISP pipeline is an image processing flow consisting of multiple processing modules, each of which performs a specific task to improve the quality and usability of the image. These modules are usually connected in series to form an efficient image processing system, which is widely used in digital cameras, smartphone cameras, security monitoring and other fields.

[0075] Cmodel is an important tool in the chip design process. It is usually a model written in high-level programming languages ​​such as C or C++, and is used to simulate the functions of a chip or system. Cmodel can help developers verify the correctness of the design through software before hardware implementation, thereby improving design efficiency and accuracy.

[0076] Specifically, first, according to the design requirements, use programming languages ​​such as C or C++ to build a Cmodel. The Cmodel needs to accurately reflect the key functions and behaviors of the chip or system. Run the built Cmodel in a simulation environment, and get the output of the Cmodel by inputting specific test data or scenarios. This process can simulate the behavior of the chip or system in actual work. Based on the output of the Cmodel, analyze the performance indicators of the chip, such as response time, throughput, etc., to evaluate the effectiveness and feasibility of the chip.

[0077] Figure 2 is a flow chart of a chip bisection method provided according to an embodiment of the present application, such as Figure 2 As shown, in the embodiment of the present application, the application is described by taking the application on a terminal with a subsystem as an example. The method comprises the following steps:

[0078] In step 201, the terminal obtains a parameter file and initial data; the parameter file includes ISP pipeline parameters; the ISP pipeline parameters include calculation parameters and non-calculation parameters; the ISP pipeline parameters describe the function of the ISP pipeline; the calculation parameters participate in the calculation process; the non-calculation parameters do not participate in the calculation.

[0079] In some embodiments, the parameter file can be obtained through a data description protocol. The data description protocol is not restricted by language and platform. For example, the data description protocol is Portocol Buffers.

[0080] It is important to understand that Protocol Buffers is a language- and platform-independent, extensible mechanism for serializing structured data. Protocol Buffers is not dependent on a specific language or platform, is highly extensible, and can generate code based on multiple programming languages. Protocol Buffers is widely used for data storage and inter-server communication.

[0081] For example, developers generate parameter files based on Protocol Buffers according to actual needs.

[0082] In one example, the parameter file can also be understood as a test case. For a test case after use, if the same function needs to be verified, the test case can be used again. If a new function needs to be verified, these parameters are used for verification. If the split fails, the test case is debugged. That is, the test cases can be accumulated to form a verification test case library.

[0083] In the embodiment of the present application, the ISP pipeline parameters are described by parameter files, and no coding is required, and the ISP pipeline can be verified only by the parameter files. Moreover, the parameter files can be freely configured and then connected according to actual needs, and the configuration is flexible and convenient.

[0084] In addition, the test cases formed by the files can be used for subsequent development. When the code is submitted and deployed, the code changes can be monitored by checking whether the test cases are successfully divided, so as to achieve the purpose of continuous integration and have a high degree of test cases.

[0085] Furthermore, in the embodiments of the present application, the parameter file runs at the user level, and has few dependencies, few levels, and few code function dependencies. Only a small amount of driver configuration code and runtime code is required, and once development is completed, no changes are required, which is low-cost and easy to debug and troubleshoot.

[0086] In some embodiments, the initial data in step 201 above can be obtained by the following two implementation methods:

[0087] The first implementation method is to generate initial data. The second implementation method is to find initial data.

[0088] In one example, the function of generating initial data is implemented based on the encoding.

[0089] In some embodiments, various random data may be generated and used as initial data. For example, the random data may be RAW, RGB, or YUV data. RAW is an unprocessed, uncompressed original image format. RGB is an additive color model that generates various colors by combining different intensities of red, green, and blue. YUV is a color encoding method for representing an image, which stores the color information and brightness information of the image separately.

[0090] In one example, the initial data actually needed can be searched and obtained from the outside. For example, the specified data is searched from the external memory, and the searched data is used as the initial data. Multiple initial data can be stored in the external memory for easy calling at any time, thereby reducing the work of generating the initial data.

[0091] In one example, the function of searching for initial data is implemented based on the encoding.

[0092] In step 202, the terminal configures Cmodel based on the initial data and calculation parameters, controls Cmodel to process the initial data based on non-calculation parameters, and obtains a reference result; Cmodel processes the initial data based on the calculation parameters.

[0093] In some embodiments, before step 202, the initial data may be preprocessed to obtain preprocessed data.

[0094] In one example, when the initial data cannot be directly recognized by the Cmodel or the target chip, the initial data needs to be preprocessed first to obtain preprocessed data, and the preprocessed data is output to the Cmodel or the target chip.

[0095] In one example, before transferring the initial data to Cmodel, the terminal outputs the initial data to DMA (Direct Memory Access) for pre-processing.

[0096] For example, when the format of the initial data is a compressed format, the initial data needs to be decompressed and the compressed data is output to Cmodel or the target chip. Or when the initial data does not meet the alignment requirements, the initial data needs to be aligned and the aligned data is output to Cmodel or the target chip. Or when the initial data does not meet the parity requirements, the parity of the initial data is adjusted and the adjusted data is output to Cmodel or the target chip.

[0097] In some embodiments, Cmodel includes multiple modules, and after the above step 201, further includes:

[0098] Analyze the calculation parameters to obtain the operation parameters, mode parameters and image parameters; and analyze the non-computational parameters to obtain the connection relationship parameters; the operation parameters are used to describe the operation mode of each module in Cmoel; the mode parameters are used to describe the operation mode of each module in Cmodel; the connection relationship parameters are used to describe the data interaction mode between each module; the image parameters are used to describe the image features.

[0099] Among them, the operating parameters and mode parameters of the ISP pipeline are key factors to ensure efficient and accurate image processing. Operating parameters refer to the specific values ​​or settings required by the ISP pipeline when processing images. Operating parameters directly affect the effect and performance of image processing. For example, operating parameters may include exposure time, gain (ISO), white balance, and color saturation.

[0100] Mode parameters refer to the specific modes or strategies used by the ISP pipeline when processing images. These modes or strategies determine the process and effect of image processing. For example, mode parameters may include preview mode, photo mode, video recording mode, and low power mode.

[0101] Image parameters include the total input image size and image resolution.

[0102] The data interaction method describes the flow of data between modules. The order in which data is transferred between modules in Cmodel can be determined by connecting relationship parameters.

[0103] In addition, non-computational parameters may also include clock parameters and environmental parameters.

[0104] It should be understood that since each module in Cmodel is independent of each other, data interaction and the order of data transmission between modules are required to achieve the normal operation of Cmodel, so that Cmodel can simulate the operation of the ISP pipeline.

[0105] In some embodiments, Cmodel is encapsulated based on coding. Specifically, Python is used to encapsulate and call the binary executable modules compiled by each module in Cmodel; at the same time, configuration interfaces for updating parameters and input / output are reserved. Optionally, the encapsulated Cmodel exists in the form of a class for easy calling. It should be noted that Python is a widely used high-level programming language.

[0106] Figure 3 It is a flowchart of step 202 provided according to an embodiment of the present application.

[0107] Combination Figure 3 Step 202 is exemplarily described.

[0108] In some embodiments, the above step 202 may include the following steps 2021 to 2024:

[0109] In step 2021, the terminal creates a class object of each module based on the operation parameters, mode parameters, and image parameters.

[0110] It is important to understand that a class is a template for creating objects with the same attributes and methods. In Python, classes are defined using the class keyword. The definition of a class includes the class name, one or more attributes (data), and zero or more methods (special or ordinary). Once a class is defined, it can be used to create class objects. Class objects provide an interface for creating instances, as well as all the methods defined in the class.

[0111] In step 2022, the terminal configures each class object based on the target part parameters.

[0112] In some embodiments, while parsing the calculation parameters and non-calculation parameters, class objects of each module are created, and the target part parameters are configured to the corresponding class objects. The class objects call the update parameter interface of the module to call the target part parameters, and then configure the target part parameters to the corresponding module.

[0113] The embodiments of the present application, combined with the parsing code, can automatically create and configure various modules in the ISP, thereby realizing the function of simulating the ISP pipeline based on Cmodel.

[0114] In step 2023, each class object configures a corresponding module based on target part parameters to obtain each target module; the target part is the part of the operating parameters, mode parameters and image parameters corresponding to the class object.

[0115] Among them, the target part parameters are the parameters required by the module for calculation.

[0116] In step 2024, the terminal transmits the initial data to the target module.

[0117] In some embodiments, the terminal may determine, based on the data transfer order determined by the connection relationship parameters, which target module in Cmodel to which the initial data is transferred first.

[0118] In some embodiments, the above step 202 may further include the following steps 2025 to 2026, including:

[0119] In step 2025, the terminal controls the i-th target module to output the i-th processing result to the i+1-th target module based on the connection relationship parameters; the i-th processing result is obtained based on the i-th target module processing the initial data; the i-th target module processes the initial data based on the corresponding target part parameters; i is an integer greater than or equal to 1.

[0120] In some embodiments, since the operation of the ISP pipeline involves dozens of modules, one module is taken as an example for explanation. In the parameter file of this application, the parameters related to the module include the ID (Identifier) ​​of the module, the ID of each input module and the target part parameters of the module; the input module is used to receive the processing result of the module.

[0121] In one example, the data transmission between modules adopts the distributed communication mechanism of request / publish, so as to achieve the purpose of decoupling each module. Decoupling allows modules to be combined and replaced more flexibly. The reason why the request / publish communication mechanism can promote the decoupling between modules is that under the distributed communication mechanism of request / publish, each module only needs to care about how to respond to requests and send responses, without knowing the specific implementation of other modules. This mechanism makes the dependency between modules very loose, thereby improving the maintainability and scalability of Cmodel.

[0122] It should be noted that in the actual operation of a chip running the ISP pipeline, each module may store data interactions with multiple modules, that is, each module may correspond to multiple input modules.

[0123] In step 2026, the terminal processes the i-th processing result based on the i+1-th target module to obtain a reference result.

[0124] In some embodiments, the processing result of the last module in Cmodel is used as a reference result. The last module refers to the last module that processes data. The last module is determined based on the above data transmission order. That is, the last module is the last module to receive the data of the processing result of the previous module. The processing result of the last module is not transmitted in Cmodel, but is directly output and used as a reference result.

[0125] In step 203, the terminal configures the target chip based on the initial data, the calculation parameters and the non-calculation parameters, starts the target chip, and obtains the actual result; the actual result is obtained by the target chip processing the initial data based on the calculation parameters and the non-calculation parameters.

[0126] Figure 4 It is a flowchart of step 203 provided according to an embodiment of the present application.

[0127] Combination Figure 4 Step 203 is exemplarily described.

[0128] In some embodiments, the target chip includes a runtime module, a driver module, a register, and an operation module; the above step 203 may include the following steps 2031 to 2032:

[0129] In step 2031, the terminal control runtime module calls the driver module to configure registers; the driver module configures registers based on initial data, calculation parameters and non-calculation parameters.

[0130] In step 2032, the terminal driver module calls the initial data, calculation parameters and non-calculation parameters in the register to configure the operation module.

[0131] In some embodiments, the runtime module and the driver module can be obtained by coding. The driver module includes an interface for configuring registers. The runtime module can be used to implement functions such as module parameter conversion, parameter configuration, and scheduling.

[0132] In one example, the runtime module calls the driver module to configure the registers. The driver module responds to the call instruction of the runtime module and configures the initial data, calculation parameters and non-calculation parameters to the registers based on the interface.

[0133] In some embodiments, the above step 203 may further include the following step 2033:

[0134] In step 2033, the terminal control driving module starts the operation module to obtain the actual result; the actual result is obtained by the operation module processing the initial data based on the calculation parameters and non-calculation parameters.

[0135] In some embodiments, the runtime module calls the driver module to drive the operation module. The driver module responds to the call instruction of the runtime module, calls the initial data, calculation parameters and non-calculation parameters from the register, and sends the start instruction, the initial data, the calculation parameters and the non-calculation parameters to the operation module. The operation module responds to the start instruction, processes the initial data based on the calculation parameters and the non-calculation parameters, and obtains the actual result.

[0136] It should be noted that the terminal only needs to control the data transfer between various modules in Cmodel based on non-computational parameters, and does not need to control the data transfer between various target modules in the target chip.

[0137] Because the operation module includes a hardware circuit part, the operation module configures the hardware circuit based on the non-computational parameters, so that the operation module can realize the function of the ISP pipeline by itself. Among them, the hardware circuit includes a clock circuit and the like.

[0138] In the above embodiment, executing step 202 first and then executing step 203 is only one implementation method. In addition, in other embodiments, step 203 may be executed first and then step 202.

[0139] In step 204, the terminal obtains a bisection result based on the actual result and the reference result; the bisection result indicates whether the target chip is successfully bisected or failed.

[0140] Figure 5 It is a flowchart of step 204 provided according to an embodiment of the present application.

[0141] Combination Figure 5 Step 204 is exemplarily described.

[0142] In some embodiments, the above step 204 includes the following steps 2041 and 2042:

[0143] In step 2041, the terminal processes the reference result based on the cryptographic hash function to obtain a first hash value; and processes the actual result based on the cryptographic hash function to obtain a second hash value.

[0144] In some embodiments, the terminal processes the reference result based on the cryptographic hash function to obtain a 128-bit first hash value. The terminal processes the actual result based on the cryptographic hash function to obtain a 128-bit second hash value.

[0145] For example: the cryptographic hash function is MD5 (Message-Digest Algorithm 5, Message Digest Algorithm Fifth Edition).

[0146] In step 2042, the terminal obtains a bisection result based on the first hash value and the second hash value.

[0147] In some embodiments, the above step 2042 can be implemented in the following two ways:

[0148] The first implementation method: when the first hash value matches the second hash value, a first bisection result is obtained; the first bisection result indicates that the target chip is successfully bisected.

[0149] The second implementation manner: when the second hash value does not match the second hash value, a second bisection result is obtained; the second bisection result indicates that the target chip bisection fails.

[0150] In one example, when the first hash value is consistent with the second hash value, the target chip is successfully split, that is, the function of the target chip meets expectations. Or when the first hash value is inconsistent with the second hash value, the target chip fails to split, that is, the function of the target chip does not meet expectations.

[0151] The embodiment of the present application determines the bisection result by comparing the hash value. Due to the fixed length, unidirectionality and sensitivity of the hash value, the data changes can be quickly captured and the problem can be quickly located in the regression test. At the same time, the hash value calculation process is simple and efficient, and can be easily integrated into the automated testing framework to improve the test efficiency and accuracy. Therefore, the hash value can achieve high-efficiency regression testing and automatic bisection.

[0152] In some embodiments, the intermediate results generated by the target chip and Cmodel during operation are uploaded to OSS (Object Storage Service) for storage. Actual results and reference results are also uploaded to OSS for storage. OSS is a data storage service provided over the network that allows users to store and access large amounts of unstructured data, such as documents, pictures, videos, backup files, log files, etc.

[0153] In some embodiments, the terminal generates an HTML (HyperText Markup Language) report corresponding to the split result, including ISP pipeline information, running time, WEB (World Wide Web) visualization link, and hash value comparison results of all running output files.

[0154] In some embodiments, the split result is notified in the form of an instant messaging software message, which is convenient and quick; for example, the split result is notified in the form of a text message.

[0155] In some embodiments, the bisection process is triggered in the form of a script, that is, the bisection process can be automatically run on the terminal by calling the script, thereby obtaining the bisection result and the message.

[0156] It should be noted that the embodiments of the present application are explained by taking the application in a terminal as an example. In addition, the embodiments of the present application can also be applied to a server.

[0157] The embodiment of the present application describes the ISP pipeline parameters in the form of a file, so that the ISP pipeline parameters can be flexibly connected and configured. And only a small amount of code needs to be provided for the driver and Cmodel. Even if new ISP pipeline parameters are added later, there is no need to change the code, only the file needs to be modified, which greatly simplifies the bisection process of the target chip running the ISP pipeline, thereby reducing the workload of developers and improving the efficiency of developers.

[0158] Figure 6 6 is a schematic diagram of a chip subsystem 600 according to an embodiment of the present application. The subsystem includes:

[0159] The acquisition module 601 is used to acquire a parameter file and initial data; the parameter file includes ISP pipeline parameters; the ISP pipeline parameters include calculation parameters and non-calculation parameters; the ISP pipeline parameters describe the function of the ISP pipeline; the calculation parameters participate in the calculation process; the non-calculation parameters do not participate in the calculation;

[0160] The first processing module 602 is used to configure Cmodel based on the initial data and the calculation parameters, and control Cmodel to process the initial data based on the non-calculation parameters to obtain a reference result; Cmodel processes the initial data based on the calculation parameters;

[0161] The second processing module 603 is used to configure the target chip based on the initial data, the calculation parameters and the non-calculation parameters, start the target chip, and obtain an actual result; the actual result is obtained by the target chip processing the initial data based on the calculation parameters and the non-calculation parameters;

[0162] The calculation module 604 is used to obtain a bisection result based on the actual result and the reference result; the bisection result indicates whether the target chip is successfully bisected or failed.

[0163] In some embodiments, the apparatus further comprises:

[0164] Generate initial data; or find initial data.

[0165] In some embodiments, it also includes: preprocessing the initial data to obtain preprocessed data.

[0166] In some embodiments, Cmodel includes a plurality of modules;

[0167] The device further comprises:

[0168] Parsing the calculation parameters to obtain the operation parameters, mode parameters and image parameters; and

[0169] Parse non-calculation parameters to obtain connection relationship parameters;

[0170] Operation parameters, which are used to describe the operation mode of each module in Cmoel;

[0171] Mode parameters, used to describe the operation mode of each module in Cmodel;

[0172] Connection relationship parameters are used to describe the data interaction mode between modules;

[0173] Image parameters are used to describe image characteristics.

[0174] In some embodiments, the apparatus further comprises:

[0175] Create class objects for each module based on run parameters, mode parameters, and image parameters;

[0176] Configure each class object based on the target part parameters;

[0177] Each class object configures the corresponding module based on the target part parameters to obtain each target module; the target part is the part of the operation parameters, mode parameters and image parameters corresponding to the class object;

[0178] Transfer the initial data to the target module.

[0179] In some embodiments, the apparatus further comprises:

[0180] Based on the connection relationship parameters, the i-th target module is controlled to output the i-th processing result to the i+1-th target module; the i-th processing result is obtained based on the i-th target module processing the initial data; the i-th target module processes the initial data based on the corresponding target part parameters; i is an integer greater than or equal to 1;

[0181] The i-th processing result is processed based on the i+1-th target module to obtain a reference result.

[0182] In some embodiments, the target chip includes a runtime module, a driver module, a register, and an operation module;

[0183] The device further comprises:

[0184] The control runtime module calls the driver module to configure registers; the driver module configures registers based on initial data, calculation parameters and non-calculation parameters;

[0185] The control driving module calls the initial data, calculation parameters and non-calculation parameters in the register to configure the running module.

[0186] In some embodiments, the apparatus further comprises:

[0187] The control driving module starts the running module to obtain the actual result; the actual result is obtained by the running module processing the initial data based on the calculation parameters and non-calculation parameters.

[0188] In some embodiments, based on the actual result and the reference result, a bisection result is obtained, including:

[0189] Processing the reference result based on the cryptographic hash function to obtain a first hash value; and

[0190] Processing the actual result based on the cryptographic hash function to obtain a second hash value;

[0191] A bisection result is obtained based on the first Hash value and the second Hash value.

[0192] In some embodiments, the apparatus further comprises:

[0193] When the first hash value matches the second hash value, a first bisection result is obtained; the first bisection result indicates that the target chip is successfully bisected; or

[0194] When the second hash value does not match the second hash value, a second bisection result is obtained; the second bisection result indicates that the target chip bisection fails.

[0195] It should be noted that: when the chip subsystem provided in the above embodiment performs the corresponding steps, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the chip subsystem and chip subdivision method embodiments provided in the above embodiment belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be repeated here.

[0196] The embodiment of the present application describes the ISP pipeline parameters in the form of a file, so that the ISP pipeline parameters can be flexibly connected and configured. And only a small amount of code needs to be provided for the driver and Cmodel. Even if new ISP pipeline parameters are added later, there is no need to change the code, only the file needs to be modified, which greatly simplifies the bisection process of the target chip running the ISP pipeline, thereby reducing the workload of developers and improving the efficiency of developers.

[0197] An embodiment of the present application further provides a computer device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the above method when executing the computer program.

[0198] Taking computer equipment as the terminal as an example, Figure 7 This is a schematic diagram of the structure of a terminal provided in an embodiment of the present application, see Figure 7 The terminal 700 may be a smart phone, a tablet computer, an MP3 player (Moving Picture Experts Group Audio Layer III), an MP4 player (Moving Picture Experts Group Audio Layer IV), a laptop computer or a desktop computer. The terminal 700 may also be called a user device, a portable terminal, a laptop terminal, a desktop terminal or other names.

[0199] Typically, the terminal 700 includes a processor 701 and a memory 702 .

[0200] The processor 701 may include one or more processing cores, such as a 4-core processor, a 5-core processor, etc. The processor 701 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 701 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 701 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 701 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0201] The memory 702 may include one or more computer-readable storage media, which may be non-transitory. The memory 702 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 702 is used to store at least one program code, which is used to be executed by the processor 701 to implement the process for terminal execution in the above method provided by the method embodiment of the present application.

[0202] In some embodiments, the terminal 700 may further optionally include: a peripheral device interface 703 and at least one peripheral device. The processor 701, the memory 702 and the peripheral device interface 703 may be connected via a bus or a signal line. Each peripheral device may be connected to the peripheral device interface 703 via a bus, a signal line or a circuit board. Specifically, the peripheral device includes: at least one of a display screen 704, a camera assembly 705, an audio circuit 706 and a power supply 707.

[0203] The peripheral device interface 703 may be used to connect at least one peripheral device related to I / O (Input / Output) to the processor 701 and the memory 702. In some embodiments, the processor 701, the memory 702, and the peripheral device interface 703 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 701, the memory 702, and the peripheral device interface 703 may be implemented on a separate chip or circuit board, which is not limited in the embodiments of the present application.

[0204] The display screen 704 is used to display the UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen 704 is a touch display screen, the display screen 704 also has the ability to collect touch signals on the surface or above the surface of the display screen 704. The touch signal can be input to the processor 701 as a control signal for processing. At this time, the display screen 704 can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen 704 can be one, set on the front panel of the terminal 700; in other embodiments, the display screen 704 can be at least two, respectively set on different surfaces of the terminal 700 or in a folding design; in other embodiments, the display screen 704 can be a flexible display screen, set on the curved surface or folding surface of the terminal 700. Even, the display screen 704 can also be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen 704 can be made of materials such as LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode, organic light-emitting diode).

[0205] The camera assembly 705 is used to capture images or videos. In some embodiments, the camera assembly 705 includes a front camera and a rear camera. Typically, the front camera is disposed on the front panel of the terminal, and the rear camera is disposed on the back of the terminal. In some embodiments, there are at least two rear cameras, which are any one of a main camera, a depth of field camera, a wide-angle camera, and a telephoto camera, so as to realize the fusion of the main camera and the depth of field camera to realize the background blur function, the fusion of the main camera and the wide-angle camera to realize the panoramic shooting and VR (Virtual Reality) shooting function or other fusion shooting functions. In some embodiments, the camera assembly 705 may also include a flash. The flash can be a monochrome temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm light flash and a cold light flash, which can be used for light compensation at different color temperatures.

[0206] The audio circuit 706 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals and input them into the processor 701 for processing. For the purpose of stereo acquisition or noise reduction, there may be multiple microphones, which are respectively arranged at different parts of the terminal 700. The microphone may also be an array microphone or an omnidirectional acquisition microphone. The speaker is used to convert the electrical signal from the processor 701 into sound waves. The speaker may be a traditional film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can not only convert the electrical signal into sound waves audible to humans, but also convert the electrical signal into sound waves inaudible to humans for purposes such as ranging. In some embodiments, the audio circuit 706 may also include a headphone jack.

[0207] The power supply 707 is used to power various components in the terminal 700. The power supply 707 can be an alternating current, a direct current, a disposable battery, or a rechargeable battery. When the power supply 707 includes a rechargeable battery, the rechargeable battery can support wired charging or wireless charging. The rechargeable battery can also be used to support fast charging technology.

[0208] Those skilled in the art will understand that Figure 7 The structure shown in the figure does not constitute a limitation on the terminal 700, and the terminal 700 may include more or less components than those shown in the figure, or combine some components, or adopt a different component arrangement.

[0209] Take the computer device as a server as an example. Figure 8 This is a schematic diagram of the structure of a server provided in an embodiment of the present application. The server 800 may have relatively large differences due to different configurations or performances, and may include one or more processors (Central Processing Units, CPU) 801 and one or more memories 802, wherein the one or more memories 802 store at least one computer program, and the at least one computer program is loaded and executed by the one or more processors 801 to implement the above-mentioned chip splitting method. Of course, the server 800 may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output. The server 800 may also include other components for implementing device functions, which will not be described here.

[0210] The embodiment of the present application also provides a computer-readable storage medium, the computer-readable storage medium includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the above-mentioned method for generating an image processing model. Optionally, the computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0211] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0212] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A chip bisection method, characterized in that: include: Obtain a parameter file and initial data; the parameter file includes ISP pipeline parameters; the ISP pipeline parameters include calculation parameters and non-calculation parameters; the ISP pipeline parameters describe the function of the ISP pipeline; the calculation parameters participate in the calculation process; the non-calculation parameters do not participate in the calculation; Configure the Cmodel based on the initial data and the calculation parameters, and control the Cmodel to process the initial data based on the non-calculation parameters to obtain a reference result; The Cmodel processes the initial data based on the calculation parameters; Configure the target chip based on the initial data, the calculation parameters and the non-calculation parameters, start the target chip, and obtain actual results; The actual result is obtained by the target chip processing the initial data based on the calculation parameters and the non-calculation parameters; Based on the actual result and the reference result, obtaining a bisection result; The bisection result indicates whether the target chip is successfully bisected or failed.

2. The method according to claim 1, characterized in that The obtaining of initial data comprises: Generate the initial data; or search for the initial data.

3. The method according to claim 1, characterized in that: Also includes: The initial data is preprocessed to obtain preprocessed data.

4. The method according to claim 1, characterized in that: The Cmodel includes multiple modules; The method further comprises: parsing the calculation parameters to obtain operation parameters, mode parameters and image parameters; and Parsing the non-calculation parameters to obtain connection relationship parameters; The operating parameters are used to describe the operating mode of each module in the Cmoel; The mode parameter is used to describe the operation mode of each module in the Cmodel; The connection relationship parameters are used to describe the data interaction mode between the modules; The image parameters are used to describe image features.

5. The method according to claim 4, characterized in that The configuring the Cmodel based on the initial data and the calculation parameters includes: Creating a class object of each module based on the operation parameters, mode parameters and image parameters; configuring each of said class objects based on target portion parameters; Each class object configures the corresponding module based on the target part parameters to obtain each target module; the target part is the part of the operation parameters, mode parameters and image parameters corresponding to the class object; The initial data is transferred to the target module.

6. The method according to claim 5, characterized in that The step of controlling the Cmodel to process the initial data based on the non-calculation parameters to obtain a reference result includes: Based on the connection relationship parameters, the i-th target module is controlled to output the i-th processing result to the i+1-th target module; the i-th processing result is obtained based on the i-th target module processing the initial data; the i-th target module processes the initial data based on the corresponding target part parameters; i is an integer greater than or equal to 1; The reference result is obtained by processing the i-th processing result based on the i+1-th target module.

7. The method according to claim 1, characterized in that The target chip includes a runtime module, a driver module, a register and an operation module; The configuring the target chip based on the initial data, the calculation parameters and the non-calculation parameters includes: Controlling the runtime module to call the driver module to configure the register; the driver module configures the register based on the initial data, the calculation parameters and the non-calculation parameters; The driving module is controlled to call the initial data, the calculation parameters and the non-calculation parameters in the register to configure the operation module.

8. The method according to claim 7, characterized in that The starting the target chip to obtain an actual result includes: The driving module is controlled to start the running module to obtain the actual result; the actual result is obtained by the running module processing the initial data based on the calculation parameters and the non-calculation parameters.

9. The method according to claim 1, characterized in that: The obtaining of a bisection result based on the actual result and the reference result includes: Processing the reference result based on a cryptographic hash function to obtain a first hash value; and Processing the actual result based on the cryptographic hash function to obtain a second hash value; The bisection result is obtained based on the first Hash value and the second Hash value.

10. The method according to claim 9, characterized in that The obtaining the bisection result based on the first Hash value and the second Hash value includes: When the first Hash value matches the second Hash value, a first bisection result is obtained; the first bisection result indicates that the target chip is successfully bisected; or When the second Hash value does not match the second Hash value, a second bisection result is obtained; the second bisection result indicates that the target chip bisection fails.

11. A chip splitting system, characterized in that: include: An acquisition module, used for acquiring a parameter file and initial data; the parameter file includes ISP pipeline parameters; the ISP pipeline parameters include calculation parameters and non-calculation parameters; the ISP pipeline parameters describe the function of the ISP pipeline; the calculation parameters participate in the calculation process; the non-calculation parameters do not participate in the calculation; A first processing module, configured to configure the Cmodel based on the initial data and the calculation parameters, and to control the Cmodel to process the initial data based on the non-calculation parameters to obtain a reference result; The Cmodel processes the initial data based on the calculation parameters; A second processing module, configured to configure a target chip based on the initial data, the calculation parameters and the non-calculation parameters, start the target chip, and obtain an actual result; The actual result is obtained by the target chip processing the initial data based on the calculation parameters and the non-calculation parameters; A calculation module, used for obtaining a bisection result based on the actual result and the reference result; The bisection result indicates whether the target chip is successfully bisected or failed.

12. A computer device, characterized in that: The computer device includes a processor and a memory, wherein the memory is used to store at least one program, and the at least one program is loaded by the processor and executes the chip bisection method according to any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one program, and the at least one program is loaded and executed by the processor to implement the chip bisection method according to any one of claims 1 to 10.

Images