FPGA layout method, storage medium and electronic device based on data flow planning

Abstract

The present application provides an FPGA layout method, device and electronic device based on data flow planning, including: dividing the circuit netlist structure layer by layer until the number of units of the divided module reaches below the division threshold, and the currently divided module is connected to at most one other module at the same level, and the division is stopped; the input and output ports are arranged on both sides of the module respectively, and a data flow direction is formed between the input port and the output port; in each level, according to the data flow direction, the signal set with the circuit data input as the starting point is counted, and the signal path including the starting point signal is found. For the starting point signal with the most endpoints on the signal path, the endpoint signals with interconnected relationships and fan-out numbers below the fan-out threshold are arranged in the same logic cluster position, and a wiring path is generated according to the starting point signal and the endpoint signal, and a layout plan is determined. The present application can reduce the use of wiring resources and reduce wiring congestion through the hierarchical relationship and data flow direction of the circuit netlist.

Description

Technical Field

[0001] The present application belongs to the field of FPGA technology, and in particular relates to an FPGA layout method, storage medium and electronic device based on data flow planning. Background Art

[0002] Currently, field programmable gate arrays (FPGAs) have become an indispensable implementation method in the field of digital circuits. They have obvious advantages in development cycle and programmable flexibility. Their application areas are becoming increasingly broad, involving communications, aerospace, medical treatment, mathematical computing, image processing, consumer products and many other fields.

[0003] In the FPGA CAD process, when faced with large and complex circuits, general layout and routing algorithms often cause routing congestion and difficulty in routing during the timing convergence process. Summary of the invention

[0004] The present application discloses an FPGA layout method, device and electronic device based on data flow planning, which can reduce the use of wiring resources and reduce wiring congestion through the hierarchical relationship and data flow of the circuit netlist.

[0005] Other purposes and advantages of the present application can be further understood from the technical features disclosed in the present application.

[0006] To achieve one or part or all of the above purposes or other purposes, in a first aspect, the present application provides an FPGA layout method based on data flow planning, including: dividing the circuit netlist structure layer by layer until the number of units of the module in the divided area reaches below the division threshold, and the currently divided module is connected to at most one other module at the same level, then stopping the division; arranging the input port and the output port on both sides of the module respectively, and forming a data flow direction from the input port to the output port; in each level, according to the data flow direction, counting the signal set with the circuit data input as the starting point, finding the signal path including the starting point signal, for the starting point signal with the most endpoints on the signal path, arranging the endpoint signals with interconnection relationships and fan-out numbers lower than the fan-out threshold in the same logic cluster position, generating a routing path according to the starting point signal and the endpoint signal, and determining the layout plan.

[0007] In one implementation, the circuit netlist structure is divided layer by layer, including obtaining the top-level instance of the circuit netlist, and dividing the logical units with the same prefix name in the top-level instance into the same module; presetting the module division threshold, if the number of units in the current divided module exceeds the division threshold, dividing the current divided module into several sub-modules or leaf units.

[0008] In one implementation, the method also includes: if the currently divided module is connected to at least two other modules at the same level, using a hypergraph partitioning algorithm to divide the upper instance of the current module into K modules; wherein K is the same as the number of modules obtained by layer-by-layer partitioning of the upper instance; respectively calculating the edge cut costs of the modules divided using the layer-by-layer partitioning and hypergraph partitioning algorithms, and taking the module with the lower edge cut cost as the final divided module; the method for calculating the edge cut cost includes: traversing each signal in the top-level instance, and when the starting point and end point of the signal are not in the same module, determining the edge cut, combining each edge cut with the timing criticality of the corresponding signal, and obtaining the edge cut cost of the signal; adding the edge cut costs corresponding to all signals in the module to obtain the edge cut cost corresponding to the module.

[0009] In one implementation, the method further includes: arranging the input port on the left side of the chip and the output port on the right side of the chip to form a data flow from left to right; laying out in sequence according to the forward direction of the data flow, and after completing the layout of the previous level, searching to the right within a preset distance according to the central position of the layout block of the previous level, determining the central position of the module to be laid out at the current level, and starting from the central position, laying out the modules to be laid out at the current level until the layout of all modules is completed.

[0010] In one implementation, at each level, the starting point signal is placed at a central position, the endpoints are searched from the module position, all endpoint signals are placed around the central position in descending order of the endpoint signal fan-out number, and the logic cluster position is placed on the right side of the starting point signal.

[0011] In one implementation, the method further includes: traversing the signals in the circuit netlist, and if the signal density exceeds a preset congestion threshold, iteratively optimizing the layout solution using a density penalty function.

[0012] In one implementation, the method further includes: for any endpoint signal to be wired, finding the endpoint signal farthest from the starting point signal, and giving priority to wiring the farthest endpoint signal, wiring each endpoint signal in turn from far to near, and at the same time, adding the path direction of the endpoint signal that has completed wiring to the wiring path prediction set; for any endpoint signal to be wired, searching from the wiring path prediction set whether there is a reusable wiring path, and if there is a reusable wiring path, selecting the wiring path with the longest reusable path length, and adding a new path to the endpoint signal on the basis of the reused path; adding 0.5 to the layout block wiring resource usage of the wiring path that has not been reused, and adding 1 to the layout block wiring resource usage of the reused wiring path.

[0013] In the second aspect, the present application provides an FPGA layout device based on data flow planning, the device comprising: a netlist partitioning module, used to divide the circuit netlist structure layer by layer until the number of units of the module in the partitioned area reaches below the partition threshold, and the currently divided module is connected to at most one other module at the same level, then the partitioning is stopped; a planning module, used to arrange the input port and the output port on both sides of the module respectively, and form a data flow direction from the input port to the output port; a layout module, used to count the signal set with the circuit data input as the starting point in each level according to the data flow direction, find the signal path including the starting point signal, and for the starting point signal with the most endpoints on the signal path, the endpoint signals with interconnected relationships and fan-out numbers lower than the fan-out threshold are arranged in the same logic cluster position, and a routing path is generated according to the starting point signal and the endpoint signal, and a layout plan is determined.

[0014] In a third aspect, the present application provides a computer-readable storage medium, in which a program code is stored, and the program code is called by a processor to execute an FPGA layout method based on data flow planning according to any one of the first aspects.

[0015] In a fourth aspect, the present application also provides an electronic device comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute an FPGA layout method based on data flow planning as described in any one of the first aspects.

[0016] The above-mentioned FPGA layout method, device, storage medium and electronic device based on data flow planning reduce the resource usage occupied by wiring and reduce wiring congestion by decomposing the circuit netlist into smaller, easier to manage and optimize modules, locating the hierarchical relationship and forming an orderly and clear data flow according to the input and output signals of the circuit netlist.

[0017] In order to make the above and other purposes, features and advantages of the present application more obvious and understandable, preferred embodiments are specifically listed below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 The figure is a flowchart of an FPGA layout method based on data flow planning in one embodiment.

[0020] Figure 2 A schematic diagram of a flow chart of a module for obtaining circuit netlist partitioning in an embodiment.

[0021] Figure 3 The figure is a schematic diagram of the layout of data flow in one embodiment.

[0022] Figure 4 The figure is a schematic diagram of a process of performing layout according to data flow planning in an embodiment.

[0023] Figure 5 The figure is a schematic diagram of a process of obtaining signal density in an embodiment.

[0024] Figure 6 FIG. 1 is a schematic diagram of predicting a routing path based on a layout solution in an embodiment. DETAILED DESCRIPTION

[0025] The aforementioned and other technical contents, features and effects of the present application will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances. This is just a way of distinguishing objects with the same attributes when describing the embodiments of the present application.

[0026] Embodiment 1 provides an FPGA layout method based on data flow planning. First, the circuit netlist structure is divided layer by layer until the number of units of the module in the divided area reaches below the division threshold, and the currently divided module is connected to at most one other module at the same level, so as to stop the division, thereby decomposing the circuit netlist into smaller modules that are easier to manage and optimize. Then, the input port and the output port are arranged on both sides of the module respectively, and a data flow direction is formed between the input port and the output port, thereby forming an orderly and clear data flow direction, so as to simplify the subsequent layout and wiring process. Then, in each level, according to the data flow direction, the signal set with the circuit data input as the starting point is counted, and the signal path including the starting point signal is found. For the starting point signal with the most endpoints on the signal path, the endpoint signals with interconnected relationships and fan-out numbers below the fan-out threshold are arranged in the same logic cluster position, and the wiring path is generated according to the starting point signal and the endpoint signal, and the layout scheme is determined, so that the hierarchical relationship is located by the input and output signals of the circuit netlist for sequential wiring, so that the resource usage occupied by the wiring is reduced, thereby reducing wiring congestion. Furthermore, the layout scheme can be iteratively optimized through signal density to further reduce wiring congestion and ensure that signals can be transmitted correctly and efficiently.

[0027] Specifically, refer to Figure 1 , the method comprises the following steps:

[0028] Step S1, divide the circuit netlist into modules: divide the circuit netlist structure layer by layer until the number of units in the module in the divided area reaches below the division threshold, and the currently divided module is connected to at most one other module at the same level, then stop dividing. The circuit netlist is a text file that describes the circuit connection relationship, usually containing all components in the circuit and their connection information. The set number can be determined based on historical experience or multiple tests. For example, until the modules divided by the circuit netlist structure contain less than 1260 units, and each divided module is connected to at most one other module at the same level, stop dividing, thereby decomposing the circuit into smaller, easier to manage and optimize modules, which is convenient for subsequent processing and layout.

[0029] More specifically, see Figure 2 , partitioning the circuit netlist includes the following steps:

[0030] Step S11: Obtain the top-level instance of the circuit netlist, and divide the logic units with the same prefix name in the top-level instance into the same module.

[0031] Step S12: preset the module division threshold.

[0032] Step S13, determine whether the number of units in the currently divided module exceeds the division threshold; if so, execute step S14, if not, execute step S15.

[0033] Step S14: divide the currently divided module into a number of sub-modules or leaf units until the number of units in the currently divided module exceeds the division threshold, and then execute step S15.

[0034] Specifically, each circuit netlist has a top-level instance, and each instance may have sub-instances. If an instance has sub-instances, and the resource usage of the current instance is greater than the partition threshold, its sub-instances will be further partitioned. For example, assuming that there are 2000 logic units in a top-level instance moduleA, the sub-modules of this top-level instance moduleA are searched and divided into three parts: module moduleB, module moduleC, and the leaf units of module moduleA itself.

[0035] Step S15, determine whether the currently divided module is connected to at most one other module at the same level; if so, stop dividing, if not, execute step S16.

[0036] Step S16: Divide the upper instance of the current module into K modules; wherein K is the same as the number of modules obtained by dividing the upper instance layer by layer.

[0037] Step S17, calculate the edge cutting cost of the divided modules, and take the module with the lower edge cutting cost as the final divided module.

[0038] For example, for the top-level instance moduleA, if the divided module has a complex connection relationship with other modules, the hypergraph partitioning algorithm is used to divide the top-level instance moduleA into 3 (i.e., K=3) parts, so that 3 small modules are obtained. The edge cut costs of the two partitions are calculated respectively, and the module with the lower edge cut cost is taken as the final partitioned module. In addition, the two partitioning methods can also be processed in parallel to reduce the total time of sequential processing.

[0039] The method for calculating the edge cut cost specifically includes: traversing each signal in the top-level instance, and when the starting point and the end point of the signal are not in the same module, determining the edge cut, combining each edge cut with the timing criticality of the corresponding signal, and obtaining the edge cut cost of the signal; adding the edge cut costs corresponding to all signals in the module to obtain the edge cut cost corresponding to the module. Among them, the edge cut can be multiplied by the timing criticality of the corresponding signal, or the weight of the timing criticality can be determined using a weighted summation method. For example, if the timing criticality is equal to 0, it means that there is no timing relationship, and the cost of the current edge cut does not need to be calculated, so that the edge cut cost can better reflect the timing performance of the signal.

[0040] By limiting the size of each module in the above way, the layout process can be ensured to be both efficient and easy to manage, which is convenient for subsequent processing and layout. In addition, the impact of timing is taken into account, and the timing criticality of the corresponding signal is multiplied for each edge cut. In this way, the higher the timing criticality, the greater the edge cut cost will be. Then, the edge cut with the smallest cost is taken as the final partition result, thereby optimizing the timing performance.

[0041] Step S2, determine the data flow direction: arrange the input port and the output port on both sides of the module respectively, and form a data flow direction from the input port to the output port. Specifically, the module that has a direct connection relationship with the input port is taken as the first level, and so on, so as to form an orderly and clear data flow direction, which can simplify the subsequent layout and wiring process.

[0042] refer to Figure 3 , the input port and the output port are arranged parallel to the module position, the input port and the output port are arranged on the left and right sides of the module, from the input port to the output port, the input data processing, core data processing register, output data processing and other logic units are connected in sequence to form a data flow from left to right, ensuring that the data can flow smoothly from the input port to the output port, so that the data can be efficiently transmitted and processed inside the module, and the reliability and stability of the module are also improved.

[0043] Step S3, generating a wiring path according to the data flow direction: In each level, according to the data flow direction, count the signal set with the circuit data input as the starting point, find the signal path including the starting point signal, and for the starting point signal with the most endpoints on the signal path, arrange the endpoint signals with interconnected relationships and fan-out numbers lower than the fan-out threshold in the same logic cluster position, generate a wiring path based on the starting point signal and the endpoint signal, and determine the layout plan. Specifically, the fan-out number refers to the number of other signals that can be driven by a signal, and the fan-out threshold can ensure that the logic cluster is not too large or complex, thereby improving the stability and reliability of the circuit. Moreover, arranging the endpoint signals with interconnected relationships in the same logic cluster position can improve the functionality of multiple logic units.

[0044] refer to Figure 4 , the method of data flow layout specifically includes the following steps:

[0045] Step S31: Arrange the input port and the output port in parallel with the module position, arrange the input port on the left side of the chip, and arrange the output port on the right side of the chip, so as to form a data flow from left to right.

[0046] Step S32: In each level, according to the data flow direction, take out the signal set with the input as the starting point, and layout the signal paths including the starting point signal one by one.

[0047] Step S33: Layout the starting point signal at the central position.

[0048] Step S34, searching for endpoints from the module position, arranging all endpoint signals in order from high to low in terms of endpoint signal fan-out numbers around the central position, and arranging the logic cluster position to the right of the starting point signal.

[0049] Step S35: After completing the layout of the previous level, search to the right within a preset distance according to the central position of the layout block of the previous level to determine the central position of the module to be laid out at the current level. Starting from the central position, repeat steps S32 to S34 to lay out the modules to be laid out at the current level.

[0050] Step S36: Repeat step S35 until the layout of all modules is completed.

[0051] Through the above method, the signal transmission time can be reduced and the overall performance of the circuit can be improved by optimizing the position of the module, and a reasonable signal path layout and logic cluster arrangement can be achieved to minimize connection delays and reduce signal transmission distances, thereby reducing wiring congestion and improving the efficiency and quality of signal transmission within the chip.

[0052] It should be noted that forward layout and reverse layout can also be performed simultaneously according to the data flow direction to improve layout efficiency. Specific reference is made to the above steps and no further description is given here.

[0053] After the layout plan is initially generated, the routing paths in the layout plan can also be iteratively optimized: the signals in the circuit netlist are traversed, and if the signal density generated in a certain routing area exceeds a preset congestion threshold, the layout plan is iteratively optimized.

[0054] refer to Figure 5 , iterative optimization of the layout scheme specifically includes the following steps:

[0055] Step S41: preset a congestion threshold.

[0056] Specifically, the total number of routing channel resources under each coordinate is obtained through the hardware interface, and the actual circuit routing resource usage is used to count, and the coordinates where the routing channel resources are used are found, that is, the congested area. The congested area is found to be a specific range bin, and then the signals in the circuit netlist are traversed to find the number of routing path connections passing through this congested area. The average statistics are used as the congestion threshold. In addition, the congestion threshold can also be tested multiple times to obtain a better empirical value to ensure the reliability of subsequent steps.

[0057] Step S42: for any endpoint signal to be routed, find the endpoint signal farthest from the starting point signal, and route the farthest endpoint signal first, route each endpoint signal in sequence from far to near, and at the same time, add the routed endpoint signal path direction to the routing path prediction set.

[0058] Step S43: for any endpoint signal to be routed, search the routing path prediction set to see if there is a reusable routing path, and if there is a reusable routing path, select the routing path with the longest reusable path length, and add a new path to the endpoint signal based on the reusable path.

[0059] Step S44: add 0.5 to the layout block wiring resource usage of the unreused wiring path, and add 1 to the layout block wiring resource usage of the reused wiring path.

[0060] Exemplary, reference Figure 6, the red dot is the starting point, the blue dot is the endpoints, and the green is the wireframe. Starting from the farthest endpoint endpoint3, as shown in the orange line in the figure, the routing path first reaches the edge of the wireframe to the right and then reaches the endpoint endpoint3 downward. In this way, the next endpoint from far to near is endpoint5, and the previous path cannot be reused. Then there is endpoint endpoint2. The direction of traversing the starting point is the upper right, so there is a path to the right that can be reused; similarly, the next endpoint is endpoint4, which is in the lower right direction. The routing path to the right or downward can be reused. It is necessary to calculate the direction of the longest path that can be reused, or the way to make the newly added routing path for this endpoint endpoint the shortest, which is to reuse the routing path of endpoint endpoint5 downward first and then to the right. Finally, the routing of endpoint endpoint1 is completed, which cannot be reused. In the end, the routing resource usage of the layout blocks where these orange lines are located is +0.5 each, and the reused path is +1.

[0061] Step S45, calculating the ratio of the usage of the wiring channel resources to the total number of the wiring channel resources to obtain the signal density.

[0062] Step S46, traverse the signals in the circuit netlist, and if the signal density generated in a certain layout area exceeds the preset congestion threshold, use the density penalty function to iteratively optimize the layout scheme. For example, genetic algorithms, simulated annealing algorithms, particle swarm optimization algorithms, etc. can be used to adjust the layout scheme so that the optimized wiring path reduces the signal density as much as possible, thereby reducing wiring congestion.

[0063] In this way, routing from the farthest endpoint can ensure the coverage of the entire routing area, while the reused path can reduce the consumption of routing resources, thereby improving routing efficiency. At the same time, when the signal density of the routing area exceeds the preset congestion threshold, the layout scheme is iteratively optimized to reduce the signal density, reduce routing congestion, and improve the performance and reliability of the circuit.

[0064] Embodiment 2 provides an FPGA layout device based on data flow planning, which includes: a netlist partitioning module, which is used to partition the circuit netlist structure layer by layer until the number of units of the module in the partitioned area reaches below the partition threshold, and the currently divided module is connected to at most one other module at the same level, then the partitioning is stopped; a planning module, which is used to arrange the input port and the output port on both sides of the module respectively, and form a data flow direction from the input port to the output port; a layout module, which is used to count the signal set with the circuit data input as the starting point according to the data flow direction at each level, find out the signal path including the starting point signal, for the starting point signal with the most endpoints on the signal path, the endpoint signals with interconnected relationships and fan-out numbers lower than the fan-out threshold are arranged in the same logic cluster position, and a wiring path is generated according to the starting point signal and the endpoint signal to determine the layout plan.

[0065] It should be noted that the information interaction, execution process, etc. between the modules / units of the above-mentioned device are based on the same concept as the method embodiment of the present application, and the technical effects brought by them are the same as those of the method embodiment of the present application. For specific contents, please refer to the description of the method embodiment shown in the above-mentioned embodiment of the present application, and no further description is given here. It should also be noted that the device embodiment described above is only illustrative, and some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0066] Embodiment 3 provides a computer-readable storage medium, in which a program code is stored. The program code is called by a processor to execute any one of the above-mentioned FPGA layout methods based on data flow planning.

[0067] Embodiment 4 provides an electronic device, which includes one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute any of the above-mentioned FPGA layout methods based on data flow planning.

[0068] It should be noted that, for those of ordinary skill in the art, several improvements and modifications may be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application. It should be understood that certain features of the present disclosure described in the context of a separate embodiment for the sake of clarity may also be provided in a single embodiment by combination. Conversely, various features of the present disclosure described in the context of a single embodiment for the sake of clarity may also be provided individually or in any suitable combination or as any other described embodiment of the present disclosure.

Claims

1. A FPGA layout method based on data flow planning, characterized in that: The method comprises: The circuit netlist structure is divided layer by layer until the number of units in the module in the divided area reaches below the division threshold, and the currently divided module is connected to at most one other module at the same level, then the division stops; The input port and the output port are arranged on both sides of the module respectively, and a data flow direction is formed from the input port to the output port; wherein the input port is arranged on the left side of the chip, and the output port is arranged on the right side of the chip, and the data flow direction is formed from left to right; In each level, layout is performed in the forward direction of data flow, and the signal set starting from the circuit data input is counted to find the signal path including the starting signal. For the starting signal with the most endpoints on the signal path, the endpoint signals with interconnected relationships and fan-out numbers lower than the fan-out threshold are arranged in the same logic cluster position, and the wiring path is generated according to the starting signal and the endpoint signal; After completing the layout of the previous level, search to the right within a preset distance based on the central position of the layout block of the previous level to determine the central position of the module to be laid out at the current level. Starting from the central position, lay out the modules to be laid out at the current level until the layout of all modules is completed and the layout plan is determined.

2. The FPGA layout method based on data flow planning according to claim 1, characterized in that: Dividing the circuit netlist structure layer by layer, including obtaining a top-level instance of the circuit netlist, and dividing logic units with the same prefix name in the top-level instance into the same module; A division threshold of a module is preset, and if the number of units in a currently divided module exceeds the division threshold, the currently divided module is divided into a number of sub-modules or leaf units.

3. The FPGA layout method based on data flow planning according to claim 2, characterized in that: The method further includes: if the currently divided module is connected to at least two other modules at the same level, using a hypergraph partitioning algorithm to partition the upper instance of the current module into K modules; wherein K is the same as the number of modules obtained by partitioning the upper instance layer by layer; Calculate the edge cut costs of the modules divided by layer-by-layer partitioning and hypergraph partitioning algorithms respectively, and take the module with the lowest edge cut cost as the final partitioned module; The method for calculating the edge cut cost includes: traversing each signal in the top-level instance, and when the starting point and the end point of the signal are not in the same module, determining the edge cut, combining each edge cut with the timing criticality of the corresponding signal, and obtaining the edge cut cost of the signal; adding the edge cut costs corresponding to all signals in the module to obtain the edge cut cost corresponding to the module.

4. The FPGA layout method based on data flow planning according to claim 3, characterized in that: In each level, the starting point signal is placed in the central position, the endpoints are searched from the module position, all the endpoint signals are placed around the central position in descending order of the endpoint signal fan-out number, and the logic cluster position is placed on the right side of the starting point signal.

5. The FPGA layout method based on data flow planning according to claim 1, characterized in that: The method further includes: traversing the signals in the circuit netlist, and if the signal density exceeds a preset congestion threshold, iteratively optimizing the layout scheme using a density penalty function.

6. The FPGA layout method based on data flow planning according to claim 5, characterized in that: The method further comprises: For any endpoint signal to be routed, find the endpoint signal farthest from the starting point signal, and route the farthest endpoint signal first, route each endpoint signal in order from far to near, and at the same time, add the routed endpoint signal path direction to the routing path prediction set; For any endpoint signal to be routed, find out whether there is a reusable routing path in the routing path prediction set, and if there is a reusable routing path, select the routing path with the longest reusable path length, and add a new path to the endpoint signal based on the reusable path; The layout block routing resource usage of the unreused routing path is increased by 0.5, and the layout block routing resource usage of the reused routing path is increased by 1.

7. An FPGA layout device based on data flow planning, characterized in that: The device is used to execute the FPGA layout method based on data flow planning according to any one of claims 1 to 6, and the device includes: The netlist partitioning module is used to partition the circuit netlist structure layer by layer until the number of units in the module in the partition area reaches below the partition threshold, and the currently partitioned module is connected to at most one other module at the same level, then the partitioning stops; A planning module, used to arrange the input port and the output port on both sides of the module, respectively, to form a data flow from the input port to the output port; wherein the input port is arranged on the left side of the chip, and the output port is arranged on the right side of the chip, to form a data flow from left to right; The layout module is used to layout in each level in the forward direction of data flow, count the signal set with circuit data input as the starting point, find the signal path including the starting point signal, and for the starting point signal with the most endpoints on the signal path, layout the endpoint signals with interconnected relationships and fan-out numbers lower than the fan-out threshold in the same logic cluster position, and generate a wiring path according to the starting point signal and the endpoint signal; the layout module is also used to, after completing the layout of the previous level, search to the right within a preset distance according to the central position of the layout block of the previous level, determine the central position of the module to be laid out at the current level, start from the central position, layout the modules to be laid out at the current level, until the layout of all modules is completed and the layout plan is determined.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program code, and the program code is called by a processor to execute the FPGA layout method based on data flow planning as described in any one of claims 1 to 6.

9. An electronic device, characterized in that: comprising one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute an FPGA layout method based on data flow planning as described in any one of claims 1-6.

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