Light-emitting control circuit and display panel

Abstract

The embodiment of the invention provides a light-emitting control circuit and a display panel, the light-emitting control circuit comprises a plurality of cascaded light-emitting control sub-circuits, each light-emitting control sub-circuit correspondingly controls a row of sub-pixels, each sub-pixel comprises a first light-emitting diode and a second light-emitting diode, each light-emitting control sub-circuit comprises two output modules, and two light-emitting signals can be output through two output ends to control the first light-emitting diode and the second light-emitting diode respectively. By means of the arrangement, the problem that the space occupied by the circuits is large due to the fact that each row of sub-pixels in the peep-proof OLED display panel needs to be provided with two light-emitting control circuits and output two light-emitting control signals respectively is at least solved, the occupied space of a border is effectively saved, and further narrow frame design is achieved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a light-emitting control circuit and a display panel. Background Art

[0002] An organic light emitting diode (OLED) display panel with an anti-peeping function generally divides a sub-pixel into two areas, and a light-emitting diode is set in each area. In the anti-peeping mode, one of the light-emitting diodes emits light under the control of the light-emitting control signal, and in the normal mode, the other light-emitting diode emits light under the control of the light-emitting control signal. Therefore, two light-emitting control circuits need to be set for each row of sub-pixels, and two light-emitting control signals are output respectively. At the same time, at least 4 sets of clock drive signals are required, resulting in a larger space occupied by the circuit, that is, the border of the display panel is wider. Summary of the invention

[0003] The embodiments of the present application provide a light emitting control circuit and a display panel to at least solve the problem that two light emitting control circuits need to be provided for each row of sub-pixels in an anti-peeping OLED display panel, resulting in a large space occupied by the circuits.

[0004] In a first aspect, an embodiment of the present application provides a light-emitting control circuit, the light-emitting control circuit comprising a plurality of cascaded light-emitting control subcircuits, each of the light-emitting control subcircuits corresponding to controlling a row of sub-pixels, each of the sub-pixels comprising a first light-emitting diode and a second light-emitting diode, and each of the light-emitting control subcircuits comprising: an input module, receiving an input signal and a first clock signal, and connecting a first node and a second node, configured to control the potential of the first node and the second node according to the input signal and the first clock signal; a first output module, receiving a first preset high potential and a first preset low potential, and connecting the first node and the second node, the first output module being configured to output the first preset low potential to a first output terminal under the control of the first node, or to output the first preset low potential to a first output terminal under the control of the second node. The first output module is configured to output the first preset high potential to the first output terminal under the control of the third node, or to output the second preset low potential to the second output terminal under the control of the fourth node; the first output terminal is connected to the first light-emitting diode, and the second output terminal is connected to the second light-emitting diode.

[0005] In one embodiment, the first control transistor and the second control transistor maintain a turned-on state under the control of the preset potential.

[0006] In one embodiment, the first output module includes: a first output transistor, including a control electrode connected to the first node, a first electrode connected to a first preset low potential, and a second electrode connected to the first output terminal; a second output transistor, including a control electrode connected to the second node, a first electrode connected to a first preset high potential, and a second electrode connected to the first output terminal.

[0007] In one embodiment, the second output module includes: a third output transistor, including a control electrode connected to the third node, a first electrode connected to the second preset high potential, and a second electrode connected to the second output terminal; a fourth output transistor, including a control electrode connected to the fourth node, a first electrode connected to the second preset low potential, and a second electrode connected to the second output terminal.

[0008] In one embodiment, the light emitting control subcircuit further includes: a first capacitor, including a first end connected to the first clock signal, and a second end connected to the fourth node.

[0009] In one embodiment, the light-emitting control subcircuit also includes: a second capacitor, including a first end connected to the fifth node and a second end connected to the fourth node; a third control transistor, including a control electrode connected to the fourth node, a first electrode connected to the first clock signal, and a second electrode connected to the fifth node; a fourth control transistor, including a control electrode connected to the second clock signal, a first electrode connected to a preset potential, and a second electrode connected to the fifth node; wherein the first clock signal is inverted with the second clock signal.

[0010] In one embodiment, the light-emitting control subcircuit also includes: a coupling pull-down module, which is connected to the second clock signal and the preset high potential, and connects the first node and the second node, and the coupling pull-down unit is configured to couple the voltage difference between the first node and the preset high potential under the control of the second node; a coupling pull-up module, which is connected to the preset low potential, and connects the second node, and the coupling pull-up unit is configured to couple the voltage difference between the second node and the preset low potential.

[0011] In one embodiment, the light emitting control subcircuit also includes: a high potential output maintaining module, which is connected to the first clock signal, the second clock signal and the preset low potential, and connects the first node and the second node, and the high potential output maintaining module is configured to control the potential of the second node according to the first clock signal, the second clock signal, the preset low potential and the potential of the first node.

[0012] In one embodiment, the light emitting control subcircuit further includes: an output short circuit prevention module, which is connected to the preset high potential and connects the first node and the second node.

[0013] In one embodiment, the light emitting control subcircuit also includes: an ultra-low potential blocking module, including a first blocking transistor and a second blocking transistor; wherein the first blocking transistor is arranged between the high potential output maintaining module and the second node, and the second blocking transistor is arranged between the input module and the first node.

[0014] In a second aspect, an embodiment of the present application further provides a display panel, comprising any of the light emitting control circuits described above.

[0015] The beneficial effects provided by the embodiments of the present application include at least:

[0016] The embodiment of the present application provides a light-emitting control circuit and a display panel, wherein the light-emitting control circuit includes a plurality of cascaded light-emitting control subcircuits, each light-emitting control subcircuit corresponding to a row of sub-pixels, each sub-pixel includes a first light-emitting diode and a second light-emitting diode, and each light-emitting control subcircuit includes two output modules, which can output two light-emitting signals through two output terminals to respectively control the first light-emitting diode and the second light-emitting diode. Through the above arrangement, at least the problem that two light-emitting control circuits need to be set for each row of sub-pixels in the anti-peep OLED display panel, and two light-emitting control signals are output respectively, resulting in a large space occupied by the circuit is solved, which effectively saves border space occupation and realizes a further narrow border design.

[0017] Other beneficial effects of the embodiments of the present application will be further described in the following specific implementation manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic structural diagram of a display panel provided in an optional embodiment of the present application;

[0019] Figure 2 is a schematic diagram of an anti-peeping pixel arrangement provided in an optional embodiment of the present application;

[0020] Figure 3 is a structural schematic diagram of a light emitting control subcircuit provided in an optional embodiment of the present application;

[0021] Figure 4 is a structural schematic diagram of another light emitting control subcircuit provided in an optional embodiment of the present application;

[0022] Figure 5 is an output timing diagram of a light emitting control subcircuit provided in an optional embodiment of the present application;

[0023] Figure 6 is a structural schematic diagram of another light emitting control subcircuit provided in an optional embodiment of the present application;

[0024] Figure 7 It is a control timing diagram of another light emitting control subcircuit provided in an optional embodiment of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. The described technical solutions are only used to explain and illustrate the ideas of the present application and should not be regarded as limiting the scope of protection of the present application.

[0026] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0027] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0028] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0029] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. As another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of the embodiments of the present application.

[0030] The various embodiments provided in this application are similar, and features in different embodiments may be combined with each other.

[0031] The use of "configured to" in the embodiments of the present application is meant to be open and inclusive language, which does not exclude devices adapted for or configured to perform additional tasks or steps.

[0032] The order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0033] Reference Figure 1 As shown, an embodiment of the present application provides a display panel 1000, which can be integrated in a display device, which can be a TV, a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, etc., but is not limited thereto. A display panel refers to a component for displaying an image, which may include many pixel units, each of which may emit light, display a color, or reflect light to produce an image. The type of display panel can be set according to actual conditions. For example, the display panel may be a liquid crystal panel (LCD), an organic light-emitting diode panel (OLED), a mini light-emitting diode display panel (Mini-LED), or a micro light-emitting diode display panel (Micro-LED). The embodiments of the present application are not limited here. The pixel units included in the display panel may exist in the form of rows and / or columns.

[0034] The display panel 1000 includes an effective display area AA and a peripheral area NA located around the effective display area AA. A circuit board 1100 is provided in the peripheral area of ​​the display panel 1000 for providing a clock signal to the circuit inside the display panel 1000. The above-mentioned effective display area AA includes a plurality of sub-pixels 1500. For the convenience of explanation, the above-mentioned plurality of sub-pixels 1500 in the present application are described as an example of a matrix arrangement. In this case, the sub-pixels arranged in a row along the first direction (X direction) are called a row of sub-pixels, and the sub-pixels arranged in a row along the second direction (Y direction) are called a column of sub-pixels. A row of sub-pixels can be connected to a gate signal line GL and a light-emitting control signal line EM, and a column of sub-pixels can be connected to a data line DL, and the X direction intersects the Y direction perpendicularly.

[0035] Each sub-pixel 1500 may include a pixel driving circuit 1510 and a light emitting device (eg, Figure 1 The first light emitting diode 1520 and the second light emitting diode 1530 are shown. The light emitting device can emit at least three primary colors, such as red (Red, R), green (Green, G) and blue (Blue, B).

[0036] The pixel driving circuit 1510 , the gate driving circuit 1200 , and the data driving circuit 1300 in the embodiment of the present application can be implemented using any circuit in the art that can realize corresponding functions, and will not be elaborated on in detail.

[0037] The display panel 1000 also includes a gate driving circuit 1200, a data driving circuit 1300 and a light emitting control circuit 1400 arranged in the NA region. The gate driving circuit 1200 includes a plurality of cascaded gate driving sub-circuits 1210, and the light emitting control circuit 1400 includes a plurality of cascaded light emitting control sub-circuits 1410. Each column of sub-pixels is connected to the data driving circuit 1300 via at least one DL, each row of sub-pixels is connected to at least one gate driving sub-circuit 1210 via at least one GL, and each row of sub-pixels is connected to at least one light emitting control sub-circuit 1410 via at least one EM. It should be noted that, according to different circuit application scenarios, a row of sub-pixels can be connected to two or three or more gate driving sub-circuits via two or three or more GLs, and a row of sub-pixels can be connected to two or three or more light emitting control sub-circuits via two or three or more EMs. Figure 1 Only one signal line is used as an example for illustrative description, which is not intended to limit the scope of the present application.

[0038] For example, in some anti-peep OLED display panels, a sub-pixel is generally divided into two areas, and a light-emitting diode is set in each area. Figure 1 and Figure 2 As shown, each sub-pixel 1500 includes two light-emitting diodes. In the anti-peeping mode, one of the light-emitting diodes (for example, the first light-emitting diode 1520) emits light, and in the normal display mode, the other light-emitting diode (for example, the second light-emitting diode 1530) emits light. By setting some shielding layers, the visibility at a large viewing angle in the anti-peeping mode can be made weaker, thereby realizing the anti-peeping function. In the current related technology, generally one light-emitting control subcircuit 1410 controls one light-emitting diode. When one sub-pixel 1500 contains two light-emitting diodes, two light-emitting control subcircuits 1410 need to be set to output corresponding light-emitting signals respectively. Correspondingly, the setting of the clock signal line also needs to be doubled, which will increase the power consumption of the display panel, and at the same time increase the border area (border) and layout space, affecting the aesthetics of the display screen.

[0039] In order to solve the above technical problems, an embodiment of the present application provides a light emitting control circuit. Figure 1 and Figure 3As shown, the light emitting control circuit 1400 provided in the embodiment of the present application includes a plurality of cascaded light emitting control subcircuits (EM subcircuits) 1410, each of which controls a row of subpixels. For the sake of simplicity, the following signal ports and corresponding received or transmitted signals are described using the same symbols, for example, the first clock signal terminal and the first clock signal are both represented by XCK, the second clock signal terminal and the second clock signal are both represented by CK, the input terminal and the input signal are both represented by IN, and the output terminal and the output signal are both represented by OUT.

[0040] Reference Figure 3 As shown, each light-emitting control subcircuit 1410 may include: an input module 1411, a first output module 1412, and a second output module 1413. The input module 1411 is connected to the input signal IN and the first clock signal XCK, and is connected to the first node Q and the second node P, and is configured to control the potential P of the first node Q and the second node according to the input signal IN and the first clock signal XCK. The first output module 1412 is connected to the first preset high potential VGH 1 and the first preset low potential VGL 1, and is connected to the first node Q and the second node P. The first output module 1412 is configured to output the first preset low potential to the first output terminal OUT 1 under the control of the first node Q, or to output the first preset high potential to the first output terminal OUT1 under the control of the second node P. The second output module 1413 is connected to the second preset high potential VGH 2 and the second preset low potential VGL 2, and is connected to the third node Q1 and the fourth node P1.

[0041] In some embodiments, the light emitting control subcircuit further includes a first control transistor T16 and a second control transistor T17. The first control transistor T16 includes a transistor connected to a preset potential (reference Figure 3 The second control transistor T17 includes a control electrode connected to a preset potential (reference voltage VGL), a first electrode connected to the first node Q, and a second electrode connected to the third node Q1; Figure 3 The second output module 1413 is configured to output a second preset high potential VGH2 to the second output terminal OUT 2 under the control of the third node Q1, or to output a second preset low potential VGL 2 to the second output terminal OUT 2 under the control of the fourth node P1. The first output terminal OUT 1 is connected to the first light emitting diode 1520, and the second output terminal OUT 2 is connected to the second light emitting diode 1530.

[0042] The light-emitting control circuit provided in the embodiment of the present application includes a plurality of cascaded light-emitting control subcircuits, each of which controls a row of sub-pixels, each of which includes a first light-emitting diode and a second light-emitting diode, and each of which includes two output modules, which can output two light-emitting signals through two output terminals to respectively control the first light-emitting diode and the second light-emitting diode. Through the above arrangement, at least the problem that two light-emitting control circuits need to be set for each row of sub-pixels in the anti-peep OLED display panel, and two light-emitting control signals are output respectively, resulting in a large space occupied by the circuit is solved, which effectively saves border space occupation and realizes a further narrow border design.

[0043] It should be noted that the implementation of each unit and control switch in the light emitting control circuit may be a single transistor, a combination of multiple transistors, a capacitor, or a combination of a transistor and a capacitor. The transistors used in all embodiments of the present application may be thin film transistors (TFT), field effect transistors (MOS), or other devices with the same characteristics, and the embodiments of the present application do not limit this.

[0044] Exemplarily, the transistor may be a TFT. The TFT may be manufactured using an a-Si process, an oxide semiconductor process, a low temperature polysilicon (LTPS) process, or a high temperature polysilicon (HTPS) process. The embodiments of the present application are not limited thereto.

[0045] The embodiments of the present application do not limit the type of transistor. The transistor may be an N-type transistor, or a P-type transistor, or an enhancement-type transistor, or a depletion-type transistor. In the embodiments of the present application, the present application is exemplarily described by taking all transistors as P-type transistors as an example. The P-type transistor is turned on by a low-level voltage signal and turned off by a high-level voltage signal; that is, the operating voltage of the P-type transistor is a low-level voltage, and the turn-off voltage is a high-level voltage.

[0046] In the embodiments of the present application, the gate of the transistor is the control electrode. At the same time, in order to distinguish the two electrodes of the transistor other than the gate, one of the electrodes is directly described as the first electrode and the other electrode is the second electrode. At this time, the first electrode of the transistor can be one of the source and the drain of the transistor, and the second electrode can be the other of the source and the drain of the transistor. Since the source and the drain of the transistor can be symmetrical in structure, the source and the drain can be indistinguishable in structure.

[0047] The capacitor in the embodiment of the present application can be a capacitor device made separately through a process, for example, a capacitor device is realized by making a special capacitor electrode, and each capacitor electrode (first plate and second plate) of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc. The capacitor can also be a parasitic capacitor between transistors, or realized by the transistor itself and other devices and circuits, or by using the parasitic capacitor between the circuits of the circuit itself.

[0048] Each of the above transistors may also include at least one switch connected in parallel with each of the transistors. The embodiments of the present application are merely examples of the pixel driving circuit and the gate driving circuit, and other structures with the same functions as the pixel driving circuit and the gate driving circuit are not described one by one, but should all fall within the protection scope of the present application.

[0049] The “first node”, “second node”, etc. in the embodiments of the present application do not represent actual existing components, but represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0050] In one embodiment, the first control transistor T16 and the second control transistor T17 maintain a turned-on state under the control of a preset potential. Figures 3 to 5 The first control transistor T16 and the second control transistor T17 are both implemented by PMOS, so the control electrodes are connected to the preset low potential VGL. If the first control transistor T16 or the second control transistor T17 is implemented by NMOS, the control electrodes are connected to the preset high potential VGH.

[0051] Reference Figure 4 As shown, in some embodiments, the input module can be implemented by a transistor T3, wherein the control electrode of T3 is connected to the first clock signal XCK, the first electrode is connected to the input signal IN, and the second electrode is connected to the first node Q.

[0052] In some embodiments, the first output module may include: a first output transistor T9 and a second output transistor T10. T9 includes a control electrode connected to the first node Q, a first electrode connected to the first preset low potential VGL 1, and a second electrode connected to the first output terminal OUT 1; the second output transistor T10 includes a control electrode connected to the second node P, a first electrode connected to the first preset high potential VGH 1, and a second electrode connected to the first output terminal OUT 1. When the potential of the point P is low and the potential of the point Q is high, T10 is turned on, T9 is turned off, OUT 1 outputs VGH 1, and the corresponding first light-emitting diode is not illuminated; when the potential of the point P is high and the potential of the point Q is low, T9 is turned on, T10 is turned off, OUT 1 outputs VGL 1, and the corresponding first light-emitting diode is illuminated.

[0053] In some embodiments, the second output module includes a third output transistor T14 and a fourth output transistor T15. The third output transistor T14 includes a control electrode connected to the third node Q1, a first electrode connected to the second preset high potential VGH 2, and a second electrode connected to the second output terminal OUT 2; the fourth output transistor T15 includes a control electrode connected to the fourth node P1, a first electrode connected to the second preset low potential VGL 2, and a second electrode connected to the second output terminal OUT 2. When the potential of the point P is low and the potential of the point Q is high, T10 is turned on, T9 is turned off, OUT 1 outputs VGH 1, and the corresponding first light-emitting diode is not illuminated; at the same time, the potential of the point P1 is low and the potential of the point Q1 is high, T15 is turned on, T16 is turned off, OUT 2 outputs VGL 2, and the corresponding second light-emitting diode is illuminated. When the potential at point P is high and the potential at point Q is low, T9 is turned on, T10 is turned off, OUT 1 outputs VGL 1, and the corresponding controlled first light-emitting diode emits light; at the same time, the potential at point P1 is high and the potential at point Q1 is low, T15 is turned off, T16 is turned on, OUT2 outputs VGH 2, and the corresponding controlled second light-emitting diode does not emit light.

[0054] It should be noted that VGL1 and VGL2 in the embodiment of the present application can be connected to the same VGL or different VGLs, and VGH1 and VGH2 can be connected to the same VGH or different VGHs. They can be freely selected according to usage requirements, and the embodiment of the present application does not limit this.

[0055] In some embodiments, the light emitting control subcircuit may further include a first capacitor C4, the first capacitor C4 includes a first end connected to the first clock signal XCK, and a second end connected to the fourth node P4. When VGL 2 is the same as the low potential of XCK, due to the existence of the threshold voltage of T15, the low potential output by OUT 2 is much higher than VGL 2. By setting the first capacitor C4, one end of which is connected to XCK, the potential of the P1 node can be further lowered, so that the low potential output by the second output terminal OUT 2 is substantially consistent with VGL.

[0056] In some embodiments, the light emitting control subcircuit further includes a coupling pull-down module (including Figure 4 The coupling pull-down unit is configured to couple the voltage difference between the first node Q and the preset high potential VGH under the control of the second node P. The coupling pull-up module (including Figure 4 C2) is connected to a preset low potential VGL and is connected to the second node P, and the coupling pull-up unit is configured to couple a voltage difference between the second node P and the preset low potential VGL.

[0057] In some embodiments, the light emitting control subcircuit further includes: a high potential output maintaining module (including Figure 4 The high potential output maintaining module is configured to control the potential of the second node P according to the first clock signal XCK, the second clock signal CK, the preset low potential VGL and the potential of the first node Q.

[0058] In some embodiments, the light emitting control subcircuit further includes: an output short circuit prevention module (including Figure 4 As shown in T8), a preset high potential VGH is connected, and the first node Q and the second node P are connected.

[0059] In one embodiment, the light emitting control subcircuit further includes an ultra-low potential blocking module, which includes a first blocking transistor T11 and a second blocking transistor T12. The first blocking transistor T11 is arranged between the high potential output maintaining module and the second node P, and the second blocking transistor T12 is arranged between the input module and the first node Q. The ultra-low potential blocking module is used to block the ultra-low potential transmitted to the first node or the second node to prevent the gate from being broken down.

[0060] pass Figure 3 to Figure 4 The circuit structure shown in FIG. 1 can realize that a light-emitting control subcircuit outputs two light-emitting control signals to control two light-emitting diodes to emit light alternately. Figure 5As shown, OUT 1 and OUT 2 can output control signals of the same radial direction and opposite phase.

[0061] According to another embodiment of the present application, the light emitting control subcircuit can also be implemented by another structure. Figure 6 As shown, the structure of the light emitting control subcircuit in this embodiment is similar to the light emitting control subcircuit described in the above embodiment. Figure 4 The difference of the circuit structure shown is that the first capacitor C4 is replaced by the second capacitor C5, and two transistors T18 and T19 are added. The light-emitting control subcircuit in this embodiment includes a second capacitor C5, a third control transistor T18 and a fourth control transistor T19. The second capacitor C5 includes a first end connected to the fifth node W and a second end connected to the fourth node P1; the third control transistor T18 includes a control electrode connected to the fourth node P1, a first electrode connected to the first clock signal XCK, and a second electrode connected to the fifth node W; the fourth control transistor T19 includes a control electrode connected to the second clock signal CK, a first electrode connected to the preset potential VGH, and a second electrode connected to the fifth node W. Among them, the first clock signal XCK is inverted with the second clock signal CK. Figure 6 The functional modules in the light emitting control subcircuit are shown in FIG. Figure 4 The structures and functions of the functional modules in the light-emitting control subcircuit shown are the same, and the contents that have been described will not be repeated here. Figure 6 The second capacitor C5 is not directly connected to CK or XCK, but is connected to CK or XCK only when T18 or T19 is turned on, which can save the power consumption of the clock signal.

[0062] Figure 7 The output timing simulation diagram of the light-emitting control subcircuit in the embodiment of the present application is shown. It can be seen that in the light-emitting control subcircuit provided in the embodiment of the present application, when the Q point outputs a normal pulse signal, the potentials of the P point and the P1 node remain consistent and are high potentials; when P1 outputs a normal pulse signal, the potentials of the Q point and the Q1 point remain consistent and are high potentials. The CK signal and the XCK signal are inverted, and the signals output by OUT 1 and OUT 2 are inverted. Therefore, two light-emitting signals can be output through the two output ends of a light-emitting control subcircuit to control the first light-emitting diode and the second light-emitting diode respectively. Through the above-mentioned setting, at least the problem that two light-emitting control circuits need to be set for each row of sub-pixels in the anti-peep OLED display panel, and two light-emitting control signals are output respectively, resulting in a large space occupied by the circuit is solved, which effectively saves the border space occupation and realizes a further narrow border design.

[0063] In the embodiments of the present application, specific examples are used to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

[0064] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A light emitting control circuit, characterized in that: The light emitting control circuit includes a plurality of cascaded light emitting control subcircuits, each of which controls a row of sub-pixels, each of which includes a first light emitting diode and a second light emitting diode, and each of which includes: An input module receives an input signal and a first clock signal, connects a first node and a second node, and is configured to control the potentials of the first node and the second node according to the input signal and the first clock signal; A first output module is connected to a first preset high potential and a first preset low potential, and is connected to the first node and the second node, wherein the first output module is configured to output the first preset low potential to the first output terminal under the control of the first node, or to output the first preset high potential to the first output terminal under the control of the second node; The second output module is connected to the second preset high potential and the second preset low potential, and is connected to the third node and the fourth node; A first control transistor, comprising a control electrode connected to a preset potential, a first electrode connected to the first node, and a second electrode connected to the third node; A second control transistor includes a control electrode connected to a preset potential, a first electrode connected to the second node, and a second electrode connected to the fourth node; Wherein, the second output module is configured to output the second preset high potential to the second output end under the control of the third node, or to output the second preset low potential to the second output end under the control of the fourth node; the first output end is connected to the first light-emitting diode, and the second output end is connected to the second light-emitting diode.

2. The light emitting control circuit according to claim 1, characterized in that: The first control transistor and the second control transistor maintain a turned-on state under the control of the preset potential.

3. The light emitting control circuit according to claim 1, characterized in that: The first output module comprises: A first output transistor, comprising a control electrode connected to the first node, a first electrode connected to a first preset low potential, and a second electrode connected to the first output terminal; The second output transistor includes a control electrode connected to the second node, a first electrode connected to a first preset high potential, and a second electrode connected to the first output terminal.

4. The light emitting control circuit according to claim 1, characterized in that: The second output module comprises: a third output transistor, comprising a control electrode connected to the third node, a first electrode connected to the second preset high potential, and a second electrode connected to the second output terminal; The fourth output transistor includes a control electrode connected to the fourth node, a first electrode connected to the second preset low potential, and a second electrode connected to the second output terminal.

5. The light emitting control circuit according to claim 1, characterized in that: The light emitting control subcircuit further includes: The first capacitor includes a first end connected to the first clock signal and a second end connected to the fourth node.

6. The light emitting control circuit according to claim 1, characterized in that: The light emitting control subcircuit further includes: a second capacitor, comprising a first end connected to the fifth node and a second end connected to the fourth node; a third control transistor, comprising a control electrode connected to the fourth node, a first electrode connected to the first clock signal, and a second electrode connected to the fifth node; A fourth control transistor, comprising a control electrode connected to the second clock signal, a first electrode connected to a preset potential, and a second electrode connected to the fifth node; The first clock signal is in phase opposition with the second clock signal.

7. The light emitting control circuit according to claim 1, characterized in that: The light emitting control subcircuit further includes: A coupling pull-down module is connected to the second clock signal and the preset high potential, and connects the first node and the second node, wherein the coupling pull-down unit is configured to couple the voltage difference between the first node and the preset high potential under the control of the second node; The coupling pull-up module is connected to a preset low potential and connected to the second node, and the coupling pull-up unit is configured to couple the voltage difference between the second node and the preset low potential.

8. The light emitting control circuit according to claim 7, characterized in that: The light emitting control subcircuit further includes: A high potential output maintaining module is connected to the first clock signal, the second clock signal and the preset low potential, and connects the first node and the second node. The high potential output maintaining module is configured to control the potential of the second node according to the first clock signal, the second clock signal, the preset low potential and the potential of the first node.

9. The light emitting control circuit according to claim 8, characterized in that: The light emitting control subcircuit further includes: The output short circuit prevention module is connected to the preset high potential and connects the first node and the second node.

10. The light emitting control circuit according to claim 8, characterized in that: The light emitting control subcircuit further includes: The ultra-low potential blocking module comprises a first blocking transistor and a second blocking transistor; wherein the first blocking transistor is arranged between the high potential output maintaining module and the second node, and the second blocking transistor is arranged between the input module and the first node.

11. A display panel, characterized in that: The light emitting control circuit comprises the light emitting control circuit according to any one of claims 1 to 10.

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