SRAM (Static Random Access Memory) protection circuit, method and chip

Abstract

The invention discloses an SRAM (Static Random Access Memory) protection circuit, an SRAM protection method and a chip. The SRAM protection circuit comprises an MBIST control circuit, a DFLASH, an ECC generation circuit, a fault address recording circuit, an MUX gating circuit and an OR gate, and further comprises an ECC detection circuit, an MBIST result circuit, a Remap circuit and a fault address comparison circuit. The SRAM storage region includes a first data storage region and a second data storage region. According to the embodiment of the invention, based on the ECC detection circuit, the MBIST control circuit, the fault address comparison circuit and the Remap circuit, whether the storage area in the SRAM is invalid or not can be comprehensively and accurately detected, the invalid storage area is processed, and the storage area which is permanently invalid and used for storing data is replaced by a blank storage area.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an SRAM protection circuit, method and chip. Background Art

[0002] A static random access memory (SRAM) is usually provided inside the chip. The SRAM contains multiple storage areas. During the operation of the chip, other modules in the chip can store data in the storage area in the SRAM, and can also read the data stored in the storage area in the SRAM. Abnormal conditions in the operation of the chip may cause the storage area in the SRAM to fail. Storage area failure may mean that after the data is stored in the storage area, the data stored in the storage area cannot be read normally. In order to ensure the normal storage of the chip, it is necessary to protect the SRAM provided in the chip, detect whether the storage area in the SRAM fails during the operation of the chip, and process the failed storage area after detecting the failure of the storage area in the SRAM.

[0003] In the related art, the commonly used SRAM protection scheme is: through the error correction code (Error Correcting Code, ECC) algorithm, detect whether there are erroneous data bits in the data stored in the storage area of ​​the SRAM, after detecting that there are erroneous data bits in the data stored in the storage area, determine that the storage area is invalid, correct the erroneous data bits, and restore the correct data. If the number of erroneous data bits in the data does not exceed the upper limit of the number corresponding to the ECC algorithm, all erroneous data bits in the data can be corrected and the correct data can be restored. If the number of erroneous data bits in the data exceeds the upper limit of the number corresponding to the ECC algorithm, all erroneous data bits in the data cannot be corrected, the correct data cannot be restored, and the invalid storage area cannot be processed. The SRAM protection scheme in the related art can only detect whether the storage area in the SRAM is invalid based on the ECC algorithm, and process the invalid storage area. It is impossible to comprehensively and accurately detect whether the storage area in the SRAM is invalid and process the invalid storage area. Summary of the invention

[0004] The present invention provides an SRAM protection circuit, method and chip to solve the problem that the SRAM protection scheme in the related art cannot comprehensively and accurately detect whether a storage area in the SRAM is invalid and process the invalid storage area.

[0005] According to one aspect of the present invention, there is provided an SRAM protection circuit, comprising an MBIST control circuit, a DFLASH, an ECC generation circuit, a fault address recording circuit, a MUX gating circuit and an OR gate, and further comprising: an ECC detection circuit, an MBIST result circuit, a Remap circuit and a fault address comparison circuit;

[0006] Wherein, the SRAM storage area includes a first data storage area and a second data storage area;

[0007] Described ECC checkout circuit detects the failure mode of the first data storage area of ​​the SRAM storage area, and the failure fault address detected is stored in the described DFLASH and is marked as low fault address, and triggers the described MBIST control circuit to detect; Described MBIST control circuit, when detecting that there is SRAM failure condition in the described failure fault address, defines the described failure fault address as the MBIST failure fault address, and is stored in the described MBIST result circuit; Described fault address comparison circuit compares the described MBIST failure fault address of storing in the described MBIST result circuit with the described failure fault address of storing in the described DFLASH, if both are identical, then determines that the described failure fault address of storing in the described DFLASH is a permanent failure fault address, and described failure fault address is marked as high fault address;

[0008] The remap circuit reads the DFLASH after reset and at each power-on stage, and remaps the failed fault address marked as a high fault address in the DFLASH to the second data storage area of ​​the SRAM storage area to repair the permanent failed fault address.

[0009] After receiving a data read request corresponding to the first data storage area of ​​the SRAM storage area, the ECC detection circuit detects whether the storage area mapped to the address to be read of the data read request is invalid according to the error correction code stored in the first data storage area; if so, the address to be read is defined as a failed fault address, the failed fault address is stored in the DFLASH and marked as a low fault address, and the MBIST control circuit is triggered to detect the failed fault address.

[0010] After receiving the detection trigger information corresponding to the failure fault address, the MBIST control circuit writes the test data to the storage area mapped with the failure fault address through the MUX selection circuit and the Remap circuit, and detects whether the failure fault address has an SRAM failure condition according to the data stored in the storage area mapped with the failure fault address, and if so, defines the failure fault address as the MBIST failure fault address and stores it in the MBIST result circuit.

[0011] The fault address comparison circuit reads the MBIST failure fault address stored in the MBIST result circuit and the failure fault address stored in the DFLASH, compares whether the MBIST failure fault address is the same as the failure fault address, and if so, determines that the failure fault address stored in the DFLASH is a permanent failure fault address, and marks the failure fault address stored in the DFLASH as a high fault address.

[0012] According to another aspect of the present invention, there is provided an SRAM protection method, which is applied to the SRAM protection circuit provided by the present invention, comprising:

[0013] The ECC detection circuit detects the failure mode of the first data storage area of ​​the SRAM storage area, stores the detected failure fault address in the DFLASH and marks it as a low fault address, and triggers the MBIST control circuit to perform detection;

[0014] When detecting that there is SRAM failure condition in the described failure fault address, the MBIST control circuit defines the described failure fault address as the MBIST failure fault address, and is stored in the MBIST result circuit;

[0015] Fault address comparison circuit compares the described MBIST failure fault address stored in the described MBIST result circuit with the described failure fault address stored in the described DFLASH, if both are identical, then determines that the described failure fault address stored in the described DFLASH is a permanent failure fault address, and described failure fault address is marked as high fault address;

[0016] The remap circuit reads the DFLASH after reset and at each power-on stage, and remaps the failed fault addresses marked as high fault addresses in the DFLASH to the second data storage area of ​​the SRAM storage area to repair the permanent failed fault addresses.

[0017] The ECC detection circuit detects the failure mode of the first data storage area of ​​the SRAM storage area, stores the detected failure fault address in the DFLASH and marks it as a low failure address, and triggers the MBIST control circuit to perform detection, including:

[0018] After receiving a data read request corresponding to a first data storage area of ​​the SRAM storage area, the ECC detection circuit detects whether the storage area mapped to the address to be read of the data read request is invalid according to the error correction code stored in the first data storage area. If so, the address to be read is defined as a failed fault address, the failed fault address is stored in DFLASH and marked as a low fault address, and the MBIST control circuit is triggered to detect the failed fault address.

[0019] When the MBIST control circuit detects that the failure fault address has an SRAM failure condition, the failure fault address is defined as an MBIST failure fault address and stored in an MBIST result circuit, including:

[0020] After receiving the detection trigger information corresponding to the failure fault address, the MBIST control circuit writes the test data to the storage area mapped to the failure fault address through the MUX selection circuit and the Remap circuit, and detects whether the failure fault address has an SRAM failure according to the data stored in the storage area mapped to the failure fault address. If so, the failure fault address is defined as the MBIST failure fault address and stored in the MBIST result circuit.

[0021] The fault address comparison circuit compares the described MBIST failure fault address stored in the described MBIST result circuit with the described failure fault address stored in the described DFLASH, if both are identical, then determines that the described failure fault address stored in the described DFLASH is a permanent failure fault address, and the described failure fault address is marked as a high fault address, comprising:

[0022] A fault address comparison circuit reads the MBIST failure fault address stored in the MBIST result circuit and the failure fault address stored in the DFLASH, compares whether the MBIST failure fault address is the same as the failure fault address, and if so, determines that the failure fault address stored in the DFLASH is a permanent failure fault address, and marks the failure fault address stored in the DFLASH as a high fault address.

[0023] It also includes: the MBIST control circuit detects whether there is an SRAM failure in the first data storage area of ​​the SRAM storage area according to a preset cycle, stores the storage address with the SRAM failure in the DFLASH and marks it as a high fault address.

[0024] According to another aspect of the present invention, a chip is provided, comprising the SRAM protection circuit described in any embodiment of the present invention.

[0025] In the technical scheme of the embodiment of the present invention, an ECC detection circuit detects the failure mode of a first data storage area of ​​an SRAM storage area, stores the detected failure fault address in a DFLASH and marks it as a low failure address, and triggers an MBIST control circuit for detection; when the MBIST control circuit detects that the failure fault address has an SRAM failure situation, the failure fault address is defined as an MBIST failure fault address and stored in an MBIST result circuit; a failure address comparison circuit compares the MBIST failure fault address stored in the MBIST result circuit with the failure fault address stored in the DFLASH, and if the two are the same, determines that the failure fault address stored in the DFLASH is a permanent failure fault address, and marks the failure fault address as a low failure address. The address is marked as a high fault address; the Remap circuit reads the DFLASH after reset and at each power-on stage, and remaps the failed fault address marked as a high fault address in the DFLASH to the second data storage area of ​​the SRAM storage area, repairs the permanent failed fault address, solves the problem that the SRAM protection scheme in the related art cannot comprehensively and accurately detect whether the storage area in the SRAM is failed, and process the failed storage area. Based on the ECC detection circuit, the MBIST control circuit, the fault address comparison circuit and the Remap circuit, it is possible to comprehensively and accurately detect whether the storage area in the SRAM is failed, process the failed storage area, and replace the permanently failed storage area for storing data with a blank storage area.

[0026] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1A schematic structural diagram of an SRAM protection circuit provided by an embodiment of the present invention.

[0029] Figure 2 A schematic diagram of the structure of an SRAM provided by an embodiment of the present invention.

[0030] Figure 3 A flow chart of a SRAM protection method provided by an embodiment of the present invention.

[0031] Figure 4 A schematic diagram of the structure of a chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0033] It should be noted that the terms "target", "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprise", "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] Figure 1 The present invention provides a schematic diagram of the structure of an SRAM protection circuit. This embodiment is applicable to protecting the SRAM set in the chip, detecting whether the storage area in the SRAM fails during the operation of the chip, and processing the failed storage area after detecting the failure of the storage area in the SRAM. Figure 1As shown, the SRAM protection circuit can specifically include: an MBIST control circuit 101, a DFLASH 102, an ECC generation circuit 103, a fault address recording circuit 104, a MUX gating circuit 105, an OR gate 106, an ECC detection circuit 107, an MBIST result circuit 108, a Remap circuit 109 and a fault address comparison circuit 110, and its structure and function are described below.

[0035] The SRAM storage area includes a first data storage area and a second data storage area.

[0036] ECC detection circuit 107 detects the failure mode of the first data storage area of ​​the SRAM storage area, stores the detected failure fault address among the DFLASH 102 and is marked as low fault address, and triggers MBIST control circuit 101 to detect; MBIST control circuit 101, when detecting that there is SRAM failure condition in the described failure fault address, defines the described failure fault address as the MBIST failure fault address, and is stored in the MBIST result circuit 108; Fault address comparison circuit 110 compares the described MBIST failure fault address stored in the MBIST result circuit 108 with the described failure fault address stored in the DFLASH 102, if both are identical, then determines that the described failure fault address stored among the DFLASH 102 is a permanent failure fault address, and the described failure fault address is marked as high fault address.

[0037] The remap circuit 109 reads the DFLASH 102 after reset and at each power-on stage, and remaps the failed fault addresses marked as high fault addresses in the DFLASH 102 to the second data storage area of ​​the SRAM storage area to repair the permanent failed fault addresses.

[0038] Optionally, the SRAM protection circuit is provided in the chip. The chip may be a vehicle-grade chip for vehicle control. The chip is provided with SRAM. The SRAM storage area is all storage areas in the SRAM. The SRAM storage area includes a first data storage area and a second data storage area.

[0039] Optionally, the first data storage area is a storage area in the SRAM for storing data. The SRAM storage area includes a plurality of first data storage areas. Each first data storage area is provided with a mapped storage address. The storage address mapped to the first data storage area may be a pre-set number for uniquely identifying the first data storage area. The storage addresses mapped to different first data storage areas are different.

[0040] Optionally, the second data storage area is a blank storage area in the SRAM used to replace the permanently failed first data storage area. The SRAM storage area includes multiple second data storage areas. The permanently failed first data storage area may refer to a first data storage area where the stored data cannot be read normally and the stored data cannot be restored.

[0041] Optionally, ECC generation circuit 103 is connected to the first input end of MUX gating circuit 105, MBIST control circuit 101 is connected to the second input end of MUX gating circuit 105, the output end of MUX gating circuit 105 is connected to Remap circuit 109, the first input end of OR gate 106 is connected to the periodic enable signal output port, the second input end of OR gate 106 is connected to ECC detection circuit 107, the output end of OR gate 106 is connected to the control end of MUX gating circuit 105, Remap circuit 109 is connected to the SRAM in the chip, ECC detection circuit 107 is connected to DFLASH 102, fault address recording circuit 104, fault address comparison circuit 110 and MBIST control circuit 101, MBIST control circuit 101 is connected to MBIST result circuit 108, MBIST result circuit 108 is connected to fault address comparison circuit 110, DFLASH 102 is connected to fault address comparison circuit 110 and Remap circuit 109.

[0042] Optionally, DFLASH 102 is a DFLASH for storing a failed fault address and a flag of the failed fault address. The flag is 0 or 1. The flag of the storage address may be identification information for characterizing whether the storage area mapped to the storage address is a permanently failed storage area. A permanently failed storage area may refer to a storage area where the stored data cannot be read normally and the stored data cannot be recovered. The flag of the storage address is 0, indicating that the storage area mapped to the storage address is not a permanently failed storage area. The flag of the storage address is 1, indicating that the storage area mapped to the storage address is a permanently failed storage area. A low fault address may refer to a failed fault address with a flag of 0. A high fault address may refer to a failed fault address with a flag of 1.

[0043] Optionally, MBIST control circuit 101 can be a hardware circuit for detecting whether the first data storage area fails according to test data. ECC generation circuit 103 can be a hardware circuit for generating an error correction code corresponding to the data. Fault address recording circuit 104 can be a hardware circuit for storing a storage address mapped to the first data storage area of ​​data that cannot be normally read for storage. MUX gating circuit 105 can be a two-choice selector. ECC detection circuit 107 can be a hardware circuit for detecting whether the first data storage area fails according to the error correction code, and processing the first data storage area that can correct the failure. MBIST result circuit 108 can be a hardware circuit for storing MBIST failure fault addresses. Remap circuit 109 can be a hardware circuit for managing the first data storage area and the second data storage area, and processing the first data storage area that permanently fails. The fault address comparison circuit 110 may be a hardware circuit for determining whether the failure address stored in DFLASH 102 is a permanent failure address by comparing the MBIST failure address stored in the MBIST result circuit 108 with the failure address stored in DFLASH 102, and marking the permanent failure address as a high failure address.

[0044] Optionally, after receiving the data to be written and the storage address of the data to be written sent by other modules in the chip, the ECC generation circuit 103 can generate an error correction code corresponding to the data to be written through an ECC algorithm, and then send the data to be written, the storage address of the data to be written and the error correction code corresponding to the data to be written to the MUX selection circuit 105.

[0045] Optionally, other modules in the chip can be software modules or hardware modules except SRAM, MBIST control circuit 101, DFLASH 102, ECC generation circuit 103, fault address recording circuit 104, MUX gating circuit 105, or gate 106, ECC detection circuit 107, MBIST result circuit 108, Remap circuit 109 and fault address comparison circuit 110 that are provided in the chip.Data to be written are the data that need to be written into the first data storage area in the SRAM.The storage address of data to be written is the storage address that needs to be written into the first data storage area mapping with data to be written.

[0046] Optionally, when the periodic enable signal output port and the ECC detection circuit 107 stop outputting a high level to the first input terminal of the OR gate 106, the output terminal of the OR gate 106 outputs a low level to the port of the control terminal of the MUX gating circuit 105. When the periodic enable signal output port or the ECC detection circuit 107 outputs a high level to the first input terminal of the OR gate 106, the output terminal of the OR gate 106 outputs a high level to the port of the control terminal of the MUX gating circuit 105.

[0047] Optionally, when the output end of the OR gate 106 outputs a low level to the control end of the MUX gating circuit 105, the MUX gating circuit 105 will send the data to be written, the storage address of the data to be written, and the error correction code corresponding to the data to be written sent by the ECC generation circuit 103 to the Remap circuit 109. When the output end of the OR gate 106 outputs a high level to the control end of the MUX gating circuit 105, the MUX gating circuit 105 will send the test data sent by the MBIST control circuit 101 and the storage address of the test data to the Remap circuit 109.

[0048] Optionally, after receiving the data to be written, the storage address of the data to be written and the error correction code corresponding to the data to be written, the Remap circuit 109 writes the data to be written and the error correction code corresponding to the data to be written into the first data storage area mapped to the storage address of the data to be written.

[0049] Optionally, after receiving the test data and the storage address of the test data, the Remap circuit 109 writes the test data into the first data storage area mapped to the storage address of the test data.

[0050] Optionally, after receiving a data read request corresponding to a first data storage area of ​​the SRAM storage area, the ECC detection circuit 107 detects whether the storage area mapped to the address to be read of the data read request is invalid based on the error correction code stored in the first data storage area; if so, the address to be read is defined as a failed fault address, the failed fault address is stored in the DFLASH 102 and marked as a low fault address, and the MBIST control circuit 101 is triggered to detect the failed fault address.

[0051] Optionally, the data read request corresponding to the first data storage area of ​​the SRAM storage area may be a request sent by the target module for requesting to read data stored in the specified first data storage area. The target module may be any other module in any chip. The specified first data storage area may be any first data storage area. The data read request carries an address to be read. The address to be read is the storage address of the specified first data storage area requested to be read by the data read request. The storage area mapped to the address to be read of the data read request is the specified first data storage area requested to be read by the data read request.

[0052] Optionally, the ECC detection circuit 107 detects whether the storage area mapped to the address to be read of the data read request is invalid based on the error correction code stored in the first data storage area, including: the ECC detection circuit 107 determines the storage area mapped to the address to be read of the data read request based on the address to be read of the data read request, and generates an error correction code corresponding to the data stored in the storage area mapped to the address to be read of the data read request through an ECC algorithm; the ECC detection circuit 107 compares the generated error correction code with the error correction code stored in the storage area mapped to the address to be read of the data read request to see if they are the same; if the generated error correction code is the same as the error correction code stored in the storage area mapped to the address to be read of the data read request, the ECC detection circuit 107 determines that the storage area mapped to the address to be read of the data read request is not invalid.

[0053] Optionally, if the generated error correction code is not the same as the error correction code stored in the storage area mapped to the address to be read of the data read request, the ECC detection circuit 107 decrypts the error correction code stored in the storage area mapped to the address to be read of the data read request through the ECC algorithm to obtain the restored data stored in the storage area mapped to the address to be read of the data read request. Then the ECC detection circuit 107 generates an error correction code corresponding to the data stored in the storage area mapped to the address to be read of the data read request through the ECC algorithm, and compares the error correction code corresponding to the data stored in the storage area mapped to the address to be read of the data read request and the error correction code stored in the storage area mapped to the address to be read of the data read request to see if they are the same. If so, it indicates that the recovered data stored in the storage area mapped with the address to be read of the data read request is the correct data that should be stored in the storage area mapped with the address to be read of the data read request, and the ECC detection circuit 107 recovers the correct data that should be stored in the storage area mapped with the address to be read of the data read request after failing to normally read the data stored in the storage area mapped with the address to be read of the data read request, and is able to correct errors in the data stored in the storage area mapped with the address to be read of the data read request and process the failed storage area. Then, the ECC detection circuit 107 replaces the data stored in the storage area mapped with the address to be read of the data read request with the recovered data stored in the storage area mapped with the address to be read of the data read request, thereby correcting errors in the data stored in the storage area mapped with the address to be read of the data read request and processing the failed storage area, and then sends the recovered data stored in the storage area mapped with the address to be read of the data read request to the target module, and stores the address to be read of the data read request in the fault address recording circuit 104. If not, it indicates that the ECC detection circuit 107 cannot normally read the data stored in the storage area mapped with the address to be read of the data read request, and cannot recover the data stored in the storage area mapped with the address to be read of the data read request. Then the ECC detection circuit 107 determines that the storage area mapped with the address to be read of the data read request is invalid.

[0054] Optionally, if the ECC detection circuit 107 determines that the storage area mapped to the address to be read of the data read request has not failed, it reads the data stored in the storage area mapped to the address to be read of the data read request, and then sends the data stored in the storage area mapped to the address to be read of the data read request to the target module.

[0055] Optionally, if the ECC detection circuit 107 determines that the storage area mapped with the address to be read of the data read request fails, the address to be read is defined as a failure fault address, the failure fault address is stored in the DFLASH 102 and marked as a low fault address, and the MBIST control circuit 101 is triggered to detect the failure fault address. The failure fault address can refer to the storage address mapped with the first data storage area that cannot read data normally and cannot recover data detected by the ECC detection circuit 107.

[0056] Optionally, storing the failed fault address in DFLASH 102 and marking it as a low fault address includes: determining that the mark bit of the failed fault address is 0, and storing the failed fault address and the flag bit of the failed fault address in DFLASH 102 .

[0057] Optionally, triggering MBIST control circuit 101 to detect the failure address comprises: sending the detection trigger information corresponding to the failure address to MBIST control circuit 101, outputting a high level to the second input terminal of OR gate 106, so that the output terminal of OR gate 106 outputs a high level to the control terminal of MUX gating circuit 105.

[0058] Optionally, after defining the address to be read as a failed fault address, the ECC detection circuit 107 feeds back the read failure prompt information to the target module, and stores the failed fault address in the fault address recording circuit 104. The read failure prompt information may be pre-set information used to indicate that the data stored in the storage area cannot be read. The ECC detection circuit 107 sends the read failure prompt information to the target module, thereby feeding back the read failure prompt information to the target module. The target module may determine that the data stored in the storage area mapped to the address to be read of the data read request cannot be read according to the read failure prompt information.

[0059] Optionally, the detection trigger information corresponding to the failure fault address can be information for triggering MBIST control circuit 101 to detect whether the failure fault address has an SRAM failure condition according to test data. The detection trigger information corresponding to the failure fault address includes the failure fault address.

[0060] Optionally, ECC detection circuit 107 can stop outputting high level to the second input of OR gate 106 after the duration of outputting high level to the second input of OR gate 106 reaches preset duration.Preset duration can be a preset duration.Usually, MBIST control circuit 101 can complete according to test data in preset duration, detects the process whether described failure fault address has SRAM failure condition.

[0061] Optionally, after receiving the detection trigger information corresponding to the failure fault address, the MBIST control circuit 101 writes the test data to the storage area mapped to the failure fault address through the MUX selection circuit 105 and the Remap circuit 109, and detects whether the failure fault address has an SRAM failure according to the data stored in the storage area mapped to the failure fault address. If so, the failure fault address is defined as the MBIST failure fault address and stored in the MBIST result circuit 108.

[0062] Optionally, test data is written to the storage area mapped to the failure fault address by MUX gating circuit 105 and Remap circuit 109, including: MBIST control circuit 101 determines the failure fault address as the storage address of test data after receiving the detection trigger information corresponding to the failure fault address, and sends the test data and the storage address of the test data to MUX gating circuit 105. Test data can be pre-set data. The storage address of the test data is the storage address mapped to the first data storage area to which the test data needs to be written. The output end of OR gate 106 outputs a high level to the control end of MUX gating circuit 105, and MUX gating circuit 105 sends the test data sent by MBIST control circuit 101 and the storage address of the test data to Remap circuit 109. Remap circuit 109, after receiving the test data and the storage address of the test data, writes the test data to the first data storage area mapped to the storage address of the test data. When the test data is written to the first data storage area mapped to the storage address of the test data, the data stored in the first data storage area will be overwritten.

[0063] Optionally, mbist control circuit 101 waits for the target duration after the storage address of test data, described test data is sent to MUX gating circuit 105, can determine that described test data is written to the storage area mapped with described failure fault address, then according to the data stored in the storage area mapped with described failure fault address, detect whether described failure fault address has SRAM failure condition.The target duration can be the duration set in advance.Usually, test data can be written to the first data storage area mapped with the storage address of test data in the target duration after mbist control circuit 101 test data, the storage address of test data is sent to MUX gating circuit 105.

[0064] Optionally, according to the data stored in the storage area mapped with the described failure fault address, detecting whether the described failure fault address has an SRAM failure condition, comprising: according to the described failure fault address, determining the first data storage area mapped with the described failure fault address, reading the data stored in the first data storage area mapped with the described failure fault address; Judging whether the data stored in the first data storage area mapped with the described failure fault address are identical with correct test data; If so, show that mbist control circuit 101 can normally read the data stored in the first data storage area mapped with the described failure fault address, and the first data storage area mapped with the described failure fault address does not fail, then determine that the described failure fault address does not have the SRAM failure condition; If not, show that mbist control circuit 101 can't normally read the data stored in the first data storage area mapped with the described failure fault address, and fail with the first data storage area mapped with the described failure fault address, then determine that the described failure fault address has the SRAM failure condition.

[0065] Optionally, if MBIST control circuit 101 determines that there is SRAM failure condition in the described failure fault address, then described failure fault address is defined as MBIST failure fault address, and is stored in the MBIST result circuit 108. MBIST failure fault address can refer to the storage address of the first data storage area mapping that can't normally read data detected by MBIST control circuit 101.

[0066] Optionally, a fault address comparison circuit 110 reads the MBIST failure fault address stored in the MBIST result circuit 108 and the failure fault address stored in the DFLASH 102, compares whether the MBIST failure fault address is the same as the failure fault address, and if so, determines that the failure fault address stored in the DFLASH 102 is a permanent failure fault address, and marks the failure fault address stored in the DFLASH 102 as a high fault address.

[0067] Optionally, fault address comparing circuit 110 can read the described MBIST failure fault address stored in the MBIST result circuit 108 and the described failure fault address stored in the DFLASH 102 after the MBIST control circuit 101 stores the MBIST failure fault address in the MBIST result circuit 108, and compare whether the described MBIST failure fault address is identical with the described failure fault address.If so, then fault address comparing circuit 110 determines that the described failure fault address stored in the DFLASH 102 is a permanent failure fault address, and the described failure fault address stored in the DFLASH 102 is marked as a high failure address. The permanent failure fault address can refer to the storage address mapped with the first data storage area of ​​permanent failure. The described failure fault address stored in the DFLASH 102 is marked as a high failure address, comprising: the flag bit of the described failure fault address stored in the DFLASH 102 is set to 1.If not, then fault address comparing circuit 110 determines that this comparison process ends.

[0068] Optionally, the Remap circuit 109 can read the DFLASH 102 after reset and at each power-on stage, and remap the failed fault address marked as a high fault address in the DFLASH 102 to the second data storage area of ​​the SRAM storage area to repair the permanent failed fault address.

[0069] Optionally, the Remap circuit 109 remaps the failed fault address marked as a high fault address in the DFLASH 102 to the second data storage area of ​​the SRAM storage area to repair the permanent failed fault address, including: performing the following operations for the failed fault address marked as a high fault address in the DFLASH 102: the Remap circuit 109 determines a new first data storage area mapped to the failed fault address in each second data storage area, establishes a mapping relationship between the failed fault address and the new first data storage area, thereby processing the permanently failed first data storage area mapped to the failed fault address, replacing the permanently failed first data storage area with the second data storage area, and repairing the permanently failed fault address. Determine a new first data storage area mapped to the failed fault address in each second data storage area, including: randomly select a second data storage area from each unused second data storage area as the new first data storage area mapped to the failed fault address. Each unused second data storage area is a second data storage area that has no mapping relationship established with the storage address and has not been used to replace the permanently failed first data storage area.

[0070] Optionally, if MBIST control circuit 101 determines that there is no SRAM failure condition in the described failure fault address, then determine that the first data storage area with the described failure fault address mapping is the first data storage area of ​​transient failure, the first data storage area with the described failure fault address mapping is reset.The first data storage area of ​​transient failure can be the first data storage area of ​​normal failure that has recovered.After new data are stored to the first data storage area of ​​transient failure, the data stored in the first data storage area of ​​transient failure can be normally read.The first data storage area with the described failure fault address mapping is reset, comprising: clearing all data stored in the first data storage area with the described failure fault address mapping.

[0071] Optionally, the periodic enable signal output port outputs a high level to the first input terminal of the OR gate 106 according to a preset period, so that the output terminal of the OR gate 106 outputs a high level to the control terminal of the MUX gating circuit 105 .

[0072] Optionally, the MBIST control circuit 101 detects whether there is an SRAM failure in the first data storage area of ​​the SRAM storage area according to a preset cycle, stores the storage address with the SRAM failure in the DFLASH 102 and marks it as a high fault address.

[0073] Optionally, the periodic enable signal output port can be a port for outputting a high level to the first input of the OR gate 106 according to a preset cycle, so that the output of the OR gate 106 outputs a high level to the control end of the MUX gating circuit 105. Outputting a high level to the first input of the OR gate 106 according to the preset cycle can be to start outputting a high level to the first input of the OR gate 106 at every preset time interval, and stop outputting a high level to the first input of the OR gate 106 after the duration of outputting a high level to the first input of the OR gate 106 reaches a specified duration. The preset time interval can be a preset time interval. The specified duration can be a preset duration. The preset time interval is greater than the specified duration. Normally, the MBIST control circuit 101 can complete the operation of detecting whether the first data storage area of ​​the SRAM storage area has a SRAM failure condition within the specified duration. The MBIST control circuit 101 detects whether the first data storage area of ​​the SRAM storage area has a SRAM failure condition according to the preset cycle, which can refer to the operation of the MBIST control circuit 101 performing a detection operation of the first data storage area of ​​the SRAM storage area once at every preset time interval to detect whether the first data storage area of ​​the SRAM storage area has a SRAM failure condition.

[0074] Optionally, detecting whether there is an SRAM failure in the first data storage area of ​​the SRAM storage area includes: performing the following operations for each first data storage area: backing up the data stored in the first data storage area; determining the storage address mapped to the first data storage area as the storage address of the test data, and sending the test data and the storage address of the test data to the MUX selection circuit 105; after determining that the test data is written to the first data storage area, detecting whether there is an SRAM failure in the first data storage area based on the test data and the data stored in the first data storage area.

[0075] Optionally, according to the test data and the data stored in the first data storage area, detecting whether the first data storage area has an SRAM failure condition comprises: reading the data stored in the first data storage area; judging whether the data stored in the first data storage area is identical with the correct test data; if so, indicating that the MBIST control circuit 101 can normally read the data stored in the first data storage area, and the first data storage area does not fail, then determining that the first data storage area does not have the SRAM failure condition; if not, indicating that the MBIST control circuit 101 cannot normally read the data stored in the first data storage area, and the first data storage area fails, then determining that the first data storage area has the SRAM failure condition.

[0076] Optionally, for each first data storage area, if MBIST control circuit 101 determines that there is no SRAM failure condition in the first data storage area, then replace the data stored in the first data storage area with the data of backup, thereby the data stored in the first data storage area are restored to before testing process begins.

[0077] Optionally, for each first data storage area, if MBIST control circuit 101 determines that there is SRAM failure condition in the first data storage area, then determine that the flag bit of the storage address mapped with the first data storage area is 1, the storage address mapped with the first data storage area, the flag bit of the storage address mapped with the first data storage area is stored in DFLASH 102. Thus, Remap circuit 109 can read DFLASH 102 after resetting and in each power-on stage, and remaps to the second data storage area of ​​the SRAM storage area with the storage address mapped with the first data storage area.

[0078] Optionally, in a specific example, Figure 2A schematic diagram of the structure of an SRAM provided in an embodiment of the present invention. The SRAM includes a plurality of first data storage areas and a plurality of second data storage areas. In each of the first data storage areas, there is a first data storage area that is permanently failed. The remap circuit is used to manage the first data storage area and the second data storage area in the SRAM, and to process the first data storage area that is permanently failed.

[0079] In the technical scheme of the embodiment of the present invention, an ECC detection circuit detects the failure mode of a first data storage area of ​​an SRAM storage area, stores the detected failure fault address in a DFLASH and marks it as a low failure address, and triggers an MBIST control circuit for detection; when the MBIST control circuit detects that the failure fault address has an SRAM failure situation, the failure fault address is defined as an MBIST failure fault address and stored in an MBIST result circuit; a failure address comparison circuit compares the MBIST failure fault address stored in the MBIST result circuit with the failure fault address stored in the DFLASH, and if the two are the same, determines that the failure fault address stored in the DFLASH is a permanent failure fault address, and marks the failure fault address as a low failure address. The address is marked as a high fault address; the Remap circuit reads the DFLASH after reset and at each power-on stage, and remaps the failed fault address marked as a high fault address in the DFLASH to the second data storage area of ​​the SRAM storage area, repairs the permanent failed fault address, solves the problem that the SRAM protection scheme in the related art cannot comprehensively and accurately detect whether the storage area in the SRAM is failed, and process the failed storage area. Based on the ECC detection circuit, the MBIST control circuit, the fault address comparison circuit and the Remap circuit, it is possible to comprehensively and accurately detect whether the storage area in the SRAM is failed, process the failed storage area, and replace the permanently failed storage area for storing data with a blank storage area.

[0080] Figure 3 Flow chart of a SRAM protection method provided by an embodiment of the present invention. The method can be executed by the SRAM protection circuit provided by an embodiment of the present invention. Figure 3 As shown, the method of this embodiment specifically includes:

[0081] Step 201, the ECC detection circuit detects the failure mode of the first data storage area of ​​the SRAM storage area, stores the detected failure fault address in the DFLASH and marks it as a low failure address, and triggers the MBIST control circuit to perform detection.

[0082] Optionally, the ECC detection circuit detects the failure mode of the first data storage area of ​​the SRAM storage area, stores the detected failure fault address in DFLASH and marks it as a low fault address, and triggers the MBIST control circuit to perform detection, including: after receiving a data read request corresponding to the first data storage area of ​​the SRAM storage area, the ECC detection circuit detects whether the storage area mapped to the address to be read of the data read request is failed according to the error correction code stored in the first data storage area; if so, the address to be read is defined as a failure fault address, the failure fault address is stored in DFLASH and marked as a low fault address, and the MBIST control circuit is triggered to detect the failure fault address.

[0083] Step 202: When the MBIST control circuit detects that the failure address has an SRAM failure, the MBIST control circuit defines the failure address as an MBIST failure address and stores the address in an MBIST result circuit.

[0084] Optionally, when detecting that the failure fault address has an SRAM failure condition, the MBIST control circuit defines the failure fault address as the MBIST failure fault address, and stores it in an MBIST result circuit, comprising: after receiving the detection trigger information corresponding to the failure fault address, the MBIST control circuit writes test data to the storage area mapped with the failure fault address through a MUX gating circuit and a Remap circuit, detects whether the failure fault address has an SRAM failure condition according to the data stored in the storage area mapped with the failure fault address, and if so, defines the failure fault address as the MBIST failure fault address, and stores it in an MBIST result circuit.

[0085] Step 203, the fault address comparison circuit compares the MBIST failure fault address stored in the MBIST result circuit with the failure fault address stored in the DFLASH. If the two are the same, it is determined that the failure fault address stored in the DFLASH is a permanent failure fault address, and the failure fault address is marked as a high fault address.

[0086] Optionally, a fault address comparison circuit compares the MBIST failure fault address stored in the MBIST result circuit with the failure fault address stored in the DFLASH, and if the two are the same, determines that the failure fault address stored in the DFLASH is a permanent failure fault address, and marks the failure fault address as a high fault address, including: a fault address comparison circuit reads the MBIST failure fault address stored in the MBIST result circuit and the failure fault address stored in the DFLASH, compares whether the MBIST failure fault address is the same as the failure fault address, and if so, determines that the failure fault address stored in the DFLASH is a permanent failure fault address, and marks the failure fault address stored in the DFLASH as a high fault address.

[0087] Step 204 , the remap circuit reads the DFLASH after reset and at each power-on stage, and remaps the failed fault address marked as a high fault address in the DFLASH to the second data storage area of ​​the SRAM storage area to repair the permanent failed fault address.

[0088] Optionally, it also includes: the MBIST control circuit detects whether there is an SRAM failure in the first data storage area of ​​the SRAM storage area according to a preset cycle, stores the storage address with the SRAM failure in the DFLASH and marks it as a high fault address.

[0089] In the technical scheme of the embodiment of the present invention, an ECC detection circuit detects the failure mode of a first data storage area of ​​an SRAM storage area, stores the detected failure fault address in a DFLASH and marks it as a low failure address, and triggers an MBIST control circuit for detection; when the MBIST control circuit detects that the failure fault address has an SRAM failure situation, the failure fault address is defined as an MBIST failure fault address and stored in an MBIST result circuit; a failure address comparison circuit compares the MBIST failure fault address stored in the MBIST result circuit with the failure fault address stored in the DFLASH, and if the two are the same, determines that the failure fault address stored in the DFLASH is a permanent failure fault address, and marks the failure fault address as a low failure address. The address is marked as a high fault address; the Remap circuit reads the DFLASH after reset and at each power-on stage, and remaps the failed fault address marked as a high fault address in the DFLASH to the second data storage area of ​​the SRAM storage area, repairs the permanent failed fault address, solves the problem that the SRAM protection scheme in the related art cannot comprehensively and accurately detect whether the storage area in the SRAM is failed, and process the failed storage area. Based on the ECC detection circuit, the MBIST control circuit, the fault address comparison circuit and the Remap circuit, it is possible to comprehensively and accurately detect whether the storage area in the SRAM is failed, process the failed storage area, and replace the permanently failed storage area for storing data with a blank storage area.

[0090] Figure 4 A schematic diagram of the structure of a chip provided by an embodiment of the present invention. Figure 4 As shown, the chip 301 includes an SRAM protection circuit 302. The SRAM protection circuit 302 is arranged in the chip 301. The chip 301 may be a vehicle-grade chip for vehicle control.

[0091] The SRAM protection circuit 302 includes an MBIST control circuit, a DFLASH, an ECC generation circuit, a fault address recording circuit, a MUX selection circuit and an OR gate, and also includes: an ECC detection circuit, an MBIST result circuit, a Remap circuit and a fault address comparison circuit.

[0092] The SRAM storage area includes a first data storage area and a second data storage area.

[0093] The ECC detection circuit detects the failure mode of the first data storage area of ​​the SRAM storage area, stores the detected failure fault address in the DFLASH and marks it as a low fault address, and triggers the MBIST control circuit to detect; when detecting that the failure fault address has an SRAM failure condition, the MBIST control circuit defines the failure fault address as an MBIST failure fault address, and stores it in the MBIST result circuit; the fault address comparison circuit compares the MBIST failure fault address stored in the MBIST result circuit with the failure fault address stored in the DFLASH, and if the two are the same, determines that the failure fault address stored in the DFLASH is a permanent failure fault address, and marks the failure fault address as a high fault address.

[0094] The remap circuit reads the DFLASH after reset and at each power-on stage, and remaps the failed fault address marked as a high fault address in the DFLASH to the second data storage area of ​​the SRAM storage area to repair the permanent failed fault address.

[0095] In the technical solution of the embodiment of the present invention, the SRAM protection circuit provided in the chip can comprehensively and accurately detect whether the storage area in the SRAM is invalid based on the ECC detection circuit, the MBIST control circuit, the fault address comparison circuit and the Remap circuit, process the invalid storage area, and replace the permanently invalid storage area for storing data with a blank storage area.

[0096] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0097] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A SRAM protection circuit, comprising an MBIST control circuit, a DFLASH, an ECC generation circuit, a fault address recording circuit, a MUX gating circuit and an OR gate, characterized in that, Also includes: ECC detection circuit, MBIST result circuit, Remap circuit and fault address comparison circuit; Wherein, the SRAM storage area includes a first data storage area and a second data storage area; Described ECC detection circuit detects the failure mode of the first data storage area of ​​the SRAM storage area, stores the detected failure fault address among the described DFLASH and is marked as low fault address, and triggers described MBIST control circuit to detect; Described MBIST control circuit defines described failure fault address as MBIST failure fault address when detecting that described failure fault address has SRAM failure condition, and is stored in described MBIST result circuit; Described fault address comparison circuit compares the described MBIST failure fault address of storing in the described MBIST result circuit with the described failure fault address of storing in the described DFLASH, if both are identical, then determine that the described failure fault address of storing in the described DFLASH is a permanent failure fault address, described failure fault address is marked as high fault address; The remap circuit reads the DFLASH after reset and at each power-on stage, and remaps the failed fault address marked as a high fault address in the DFLASH to the second data storage area of ​​the SRAM storage area to repair the permanent failed fault address.

2. The SRAM protection circuit according to claim 1, characterized in that: After receiving a data read request corresponding to the first data storage area of ​​the SRAM storage area, the ECC detection circuit detects whether the storage area mapped to the address to be read of the data read request is invalid according to the error correction code stored in the first data storage area; if so, the address to be read is defined as a failed fault address, the failed fault address is stored in the DFLASH and marked as a low fault address, and the MBIST control circuit is triggered to detect the failed fault address.

3. The SRAM protection circuit according to claim 1, characterized in that: After receiving the detection trigger information corresponding to the failure fault address, the MBIST control circuit writes the test data to the storage area mapped with the failure fault address through the MUX selection circuit and the Remap circuit, and detects whether the failure fault address has an SRAM failure condition according to the data stored in the storage area mapped with the failure fault address, and if so, defines the failure fault address as the MBIST failure fault address and stores it in the MBIST result circuit.

4. The SRAM protection circuit according to claim 1, characterized in that: The fault address comparison circuit reads the MBIST failure fault address stored in the MBIST result circuit and the failure fault address stored in the DFLASH, compares whether the MBIST failure fault address is the same as the failure fault address, and if so, determines that the failure fault address stored in the DFLASH is a permanent failure fault address, and marks the failure fault address stored in the DFLASH as a high fault address.

5. A SRAM protection method, applied to the SRAM protection circuit as claimed in claim 1, characterized in that: include: The ECC detection circuit detects the failure mode of the first data storage area of ​​the SRAM storage area, stores the detected failure fault address in the DFLASH and marks it as a low fault address, and triggers the MBIST control circuit to perform detection; When detecting that there is SRAM failure condition in the described failure fault address, the MBIST control circuit defines the described failure fault address as the MBIST failure fault address, and is stored in the MBIST result circuit; Fault address comparison circuit compares the described MBIST failure fault address stored in the described MBIST result circuit with the described failure fault address stored in the described DFLASH, if both are identical, then determines that the described failure fault address stored in the described DFLASH is a permanent failure fault address, and described failure fault address is marked as high fault address; The remap circuit reads the DFLASH after reset and at each power-on stage, and remaps the failed fault addresses marked as high fault addresses in the DFLASH to the second data storage area of ​​the SRAM storage area to repair the permanent failed fault addresses.

6. The SRAM protection method according to claim 5, characterized in that: The ECC detection circuit detects the failure mode of the first data storage area of ​​the SRAM storage area, stores the detected failure fault address in the DFLASH and marks it as a low failure address, and triggers the MBIST control circuit to perform detection, including: After receiving a data read request corresponding to a first data storage area of ​​the SRAM storage area, the ECC detection circuit detects whether the storage area mapped to the address to be read of the data read request is invalid according to the error correction code stored in the first data storage area. If so, the address to be read is defined as a failed fault address, the failed fault address is stored in DFLASH and marked as a low fault address, and the MBIST control circuit is triggered to detect the failed fault address.

7. The SRAM protection method according to claim 5, characterized in that: When the MBIST control circuit detects that the failure fault address has an SRAM failure condition, the failure fault address is defined as an MBIST failure fault address and stored in an MBIST result circuit, including: After receiving the detection trigger information corresponding to the failure fault address, the MBIST control circuit writes the test data to the storage area mapped to the failure fault address through the MUX selection circuit and the Remap circuit, and detects whether the failure fault address has an SRAM failure according to the data stored in the storage area mapped to the failure fault address. If so, the failure fault address is defined as the MBIST failure fault address and stored in the MBIST result circuit.

8. The SRAM protection method according to claim 5, characterized in that: The fault address comparison circuit compares the described MBIST failure fault address stored in the described MBIST result circuit with the described failure fault address stored in the described DFLASH, if both are identical, then determines that the described failure fault address stored in the described DFLASH is a permanent failure fault address, and the described failure fault address is marked as a high fault address, comprising: A fault address comparison circuit reads the MBIST failure fault address stored in the MBIST result circuit and the failure fault address stored in the DFLASH, compares whether the MBIST failure fault address is the same as the failure fault address, and if so, determines that the failure fault address stored in the DFLASH is a permanent failure fault address, and marks the failure fault address stored in the DFLASH as a high fault address.

9. The SRAM protection method according to claim 5, characterized in that: Also includes: The MBIST control circuit detects whether there is an SRAM failure in the first data storage area of ​​the SRAM storage area according to a preset cycle, stores the storage address with the SRAM failure in the DFLASH and marks it as a high fault address.

10. A chip, characterized in that: The invention comprises the SRAM protection circuit as claimed in claim 1.

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