Manufacturing method of zeroth metal layer of active region

Abstract

The invention discloses a method for manufacturing a zeroth metal layer of an active region. The method comprises the following steps of: 1, providing a semiconductor substrate on which an active region contact hole opening forming process is completed; 2, forming an inner side wall on the side surface of the opening of the active area contact hole; and step 3, forming a BARC layer. And 4, performing a photoetching process to form a photoresist pattern to open the first ion implantation region. And step 5, removing the BARC layer in the first ion implantation region and performing first ion implantation to form a contact region at the bottom of the active region contact hole opening. And step 6, removing the BARC layer by adopting an ashing process, wherein the ashing process does not contain oxygen so as to ensure that the inner side wall is not oxidized. And 7, pre-cleaning is conducted, and in the pre-cleaning process, the inner side wall is reserved due to the fact that the inner side wall is not oxidized. And 8, forming a zeroth metal layer of the active region. According to the invention, the contact region can be formed to reduce the contact resistance, meanwhile, the size of the M0A can be ensured not to be enlarged, the parasitic capacitance between the M0A and the grid can be reduced, and the short circuit between the M0A and the grid can be prevented.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a zeroth metal layer (M0A) in an active area. Background Art

[0002] Contact resistance is the excess resistance generated in the design of integrated circuit components. Its existence will reduce the performance of integrated circuit devices. The effect of contact resistance is cumulative, which means that the total effect of a string of resistors is much greater than that of a single resistor. As the integration level increases, the resistance will increase and the overall electrical performance will decrease. This also means that the effect of parasitic resistance on reducing the characteristic size of devices on the chip cannot be ignored. Therefore, reducing contact resistance has also become a major consideration in integrated circuit manufacturing.

[0003] In some processes, for N-type devices, PSD Post LRM, i.e., P-type source-drain injection (PSD) after liner removal (LRM), is used to reduce the contact resistance of the contact holes, thereby improving the performance of the device. WAT has verified that this method can reduce the parasitic resistance Rext by 200Ω to 500Ω, and improve the device DC performance (Perf.) by about 4%.

[0004] The existing PSD injection region is defined by a three-layer (Trilayer) photolithography layer. The three layers of photolithography are carbon coating (SOC), silicon-containing anti-reflective coating (SiARC) and photoresist. The existing PSD injection is completed before the metal zero layer is filled in the active area. The existing method for PSD injection includes the following steps:

[0005] First, after the contact hole is opened, an inner sidewall made of SiN material is formed on the side.

[0006] Afterwards, the SOC layer is used to fill the opening of the contact hole. After the SOC fills the opening, the top surface is flat inside and outside the opening.

[0007] Afterwards, SiARC and photoresist are formed in sequence, and then the photoresist is patterned by photolithography to define the ion implantation area, which needs to include the area between the openings of the contact holes at the top of the source and drain regions of each semiconductor device.

[0008] After that, SiARC and SOC in the ion implantation region are removed, so that the bottom surfaces of the openings of the contact holes at the tops of the source and drain regions in the ion implantation region are exposed.

[0009] Then, ion implantation, ie, PSD, is performed to form a contact region.

[0010] After that, the organic layer will be removed, that is, the remaining photoresist, SiARC and SOC will be removed. Since SiARC contains silicon, a wet process is required to remove SiARC. The wet process also uses HT SPM, that is, hot SPM. The SPM cleaning solution contains H2SO4, H2O2 and H2O, which has strong oxidizing properties. SPM will oxidize the silicon nitride on the inner wall, so that the protection of the inner wall to the interlayer film fails. In the subsequent pre-cleaning process before filling MOA, the inner wall will be removed, and the interlayer film will also be consumed to a certain thickness, so that the opening of the contact hole will be enlarged (enlarge), for example, by 3-4nm. This will cause the risk of short circuit between MOA and gate structures such as metal gate (MG) to increase sharply, and the parasitic capacitance between MOA and MG to increase, thereby deteriorating the device AC performance. Summary of the invention

[0011] The technical problem to be solved by the present invention is to provide a method for manufacturing a zero-layer metal layer in an active area, which can be injected into the bottom area of ​​the contact hole opening in the active area to form a contact area to reduce the contact resistance while ensuring that the contact hole opening in the active area will not expand during the process, thereby ensuring the spacing between the zero-layer metal layer in the active area and the gate structure and thereby reducing the parasitic capacitance between the two or preventing a short circuit between the two.

[0012] In order to solve the above technical problems, the present invention provides a method for manufacturing a zero-th metal layer in an active area, comprising the following steps:

[0013] Step 1: providing a semiconductor substrate after completing the process of forming an active area contact hole opening.

[0014] A gate structure of a semiconductor device is formed on the top surface of the semiconductor substrate, an active region and a drain region are self-alignedly formed in the semiconductor substrate on both sides of the gate structure, a zeroth layer of interlayer film is filled in the spacing area between the gate structures, and a first layer of interlayer film covers the top surface of the gate structure and the top surface of the zeroth layer of interlayer film.

[0015] The corresponding active region contact hole openings are formed on the tops of the source region and the drain region, and the active region contact hole openings pass through the first interlayer film and the zeroth interlayer film.

[0016] Step 2: forming inner sidewalls on the side surfaces of the openings of the contact holes in the active area, wherein the material of the inner sidewalls is different from the material of the first interlayer film and the zeroth interlayer film.

[0017] Step 3: forming a BARC layer, wherein the BARC layer covers the top surface of the first interlayer film and completely fills the active area contact hole opening, and the BARC layer has a flat top surface.

[0018] Step 4: Perform a photolithography process to form a photoresist pattern, wherein the photoresist pattern opens a first ion implantation region, wherein the first ion implantation region includes a region between the source region and the drain region of a plurality of the semiconductor devices.

[0019] Step 5: Remove the BARC layer in the first ion implantation area and perform a first ion implantation, wherein the first ion implantation forms a contact area at the bottom of the contact hole opening in the active area.

[0020] Step 6: Using the characteristic that the BARC layer does not contain silicon, an ashing process is used to remove the BARC layer. The ashing process does not contain oxygen to ensure that the inner sidewall is not oxidized.

[0021] Step seven: pre-cleaning. During the pre-cleaning, the inner sidewalls are not oxidized and remain on the side of the active area contact hole opening, thereby preventing the width of the active area contact hole opening from expanding.

[0022] Step eight, forming a zeroth metal layer in the active area, wherein the zeroth metal layer in the active area completely fills the contact hole opening in the active area, and the zeroth metal layer in the active area and the contact area form an ohmic contact to reduce contact resistance.

[0023] A further improvement is that the gate structure includes a gate dielectric layer and a gate conductive material layer stacked in sequence.

[0024] A further improvement is that the gate dielectric layer includes a high dielectric constant layer; and the gate conductive material layer includes a metal gate.

[0025] A further improvement is that a first silicon nitride layer is formed between the first interlayer film and the zeroth interlayer film.

[0026] A further improvement is that step 2 includes the following sub-steps:

[0027] An inner sidewall material layer is formed, and the inner sidewall material layer covers the inner surface of the contact hole opening in the active area.

[0028] An etching process is performed to remove the inner sidewall material layer on the bottom surface of the active area contact hole opening, and the inner sidewall is formed by the inner sidewall material layer retained on the side surface of the active area contact hole opening.

[0029] A further improvement is that the material of the inner sidewall includes silicon nitride.

[0030] A further improvement is that the semiconductor device is an N-type device, the source region and the drain region are both heavily N-type doped, and the impurity type of the first ion implantation is P-type.

[0031] Alternatively, the semiconductor device is a P-type device, the source region and the drain region are both heavily P-type doped, and the impurity type of the first ion implantation is N-type.

[0032] A further improvement is that when the impurity type of the first ion implantation is P type, the impurity of the first ion implantation includes boron.

[0033] A further improvement is that an embedded epitaxial layer is formed in the source region and the drain region.

[0034] A further improvement is that the thickness of the BARC layer is The thickness of the photoresist pattern is

[0035] A further improvement is that the thickness of the inner wall material layer is

[0036] A further improvement is that the process gas of the ashing process includes N2 and H2.

[0037] In the process of defining the first ion implantation area, the present invention uses a BARC layer to fill the contact hole opening of the active area. Before the first ion implantation, the BARC layer in the first ion implantation area is removed, and the BARC layer outside the first ion implantation area is retained. The first ion implantation can contact the area, thereby reducing the contact resistance, thereby improving the direct current (DC) performance of the device.

[0038] At the same time, after the first ion implantation, since the BARC layer does not contain silicon, there is no need to use a wet process to remove the BARC layer. The BARC layer can be directly removed by an ashing process that does not contain oxygen. In this way, while ensuring the removal of the BARC layer, the ashing process will not produce an oxidation effect on the inner sidewall, so that in the subsequent pre-cleaning, the inner sidewall will still remain on the side of the contact hole opening in the active area, so that the interlayer film on the two side walls of the contact hole opening in the active area, namely the zeroth interlayer film and the first interlayer film, can be protected, so that the width of the contact hole opening in the active area can be prevented from expanding. In this way, the spacing between the zeroth metal layer in the active area and the side of the gate structure is guaranteed, and the spacing between the zeroth metal layer in the active area and the side of the gate structure can be prevented from being reduced, thereby preventing the defect of the parasitic capacitance between the two being increased and reducing the alternating current (AC) performance of the device, and further preventing the zeroth metal layer in the active area and the gate structure from being short-circuited.

[0039] Therefore, the present invention can not only effectively reduce the contact resistance of the contact hole, i.e., the zeroth metal layer in the active area, thereby improving the DC performance of the device, but also ensure the spacing between the zeroth metal layer in the active area and the side of the gate structure, thereby improving the AC performance of the device and preventing the short circuit between the zeroth metal layer in the active area and the gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0041] Figure 1 is a flow chart of a method for manufacturing a zeroth metal layer in an active area according to an embodiment of the present invention;

[0042] Figure 2A-2F Schematic diagram of device structure in each step of the method for manufacturing the zeroth metal layer in the active area according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] like Figure 1 As shown, it is a flow chart of a method for manufacturing the zeroth metal layer in the active area according to an embodiment of the present invention; FIG. 2A to FIG. 2F As shown, a schematic diagram of the device structure in each step of the method for manufacturing the zeroth metal layer in the active area according to an embodiment of the present invention is shown; the method for manufacturing the zeroth metal layer in the active area according to an embodiment of the present invention comprises the following steps:

[0044] Step 1: Figure 2A As shown, a semiconductor substrate 101 is provided after the process of forming an active region contact hole opening 107 is completed.

[0045] A gate structure 102 of a semiconductor device is formed on the top surface of the semiconductor substrate 101, an active region 103 and a drain region 104 are self-alignedly formed in the semiconductor substrate 101 on both sides of the gate structure 102, a zeroth layer interlayer film 1050 is filled in the spacing region between the gate structures 102, and a first layer interlayer film 1051 covers the top surface of the gate structure 102 and the top surface of the zeroth layer interlayer film 1050.

[0046] The corresponding active region contact hole openings 107 are formed on the tops of the source region 103 and the drain region 104 . The active region contact hole openings 107 pass through the first interlayer film 1051 and the zeroth interlayer film 1050 .

[0047] In the embodiment of the present invention, the gate structure 102 includes a gate dielectric layer and a gate conductive material layer stacked in sequence.

[0048] In some embodiments, the gate dielectric layer includes a high dielectric constant layer; and the gate conductive material layer includes a metal gate.

[0049] A first silicon nitride layer 106 is formed between the first interlayer film 1051 and the zeroth interlayer film 1050 .

[0050] In the embodiment of the present invention, an embedded epitaxial layer 201 is further formed in the source region 103 and the drain region 104 .

[0051] Step 2: Figure 2B As shown, an inner sidewall 108 is formed on the side of the active area contact hole opening 107 , and the material of the inner sidewall 108 is different from the material of the first interlayer film 1051 and the zeroth interlayer film 1050 .

[0052] In the embodiment of the present invention, step 2 includes the following sub-steps:

[0053] An inner spacer material layer 108 a is formed, and the inner spacer material layer 108 a covers the inner surface of the active region contact hole opening 107 .

[0054] An etching process is performed to remove the inner sidewall material layer 108 a on the bottom surface of the active area contact hole opening 107 , and the inner sidewall material layer 108 a retained on the side surface of the active area contact hole opening 107 forms the inner sidewall 108 .

[0055] In some embodiments, the material of the inner sidewall spacer 108 includes silicon nitride.

[0056] The thickness of the inner wall material layer 108a is

[0057] Step 3: Figure 2C As shown, a BARC layer 109 is formed. The BARC layer 109 covers the top surface of the first interlayer film 1051 and completely fills the active region contact hole opening 107 . The BARC layer 109 has a flat top surface.

[0058] In some embodiments, the thickness of the BARC layer 109 is

[0059] Step 4: Figure 2C As shown, a photolithography process is performed to form a photoresist 110 pattern, and the photoresist 110 pattern opens a first ion implantation region, and the first ion implantation region includes a region between the source region 103 and the drain region 104 of a plurality of the semiconductor devices.

[0060] In some embodiments, the thickness of the photoresist 110 pattern is

[0061] Step 5: Figure 2D As shown, the BARC layer 109 in the first ion implantation area is removed and a first ion implantation is performed, and the first ion implantation forms a contact area at the bottom of the active area contact hole opening 107. The first ion implantation is shown by arrow line 111.

[0062] Step 6: Figure 2EAs shown, by utilizing the characteristic that the BARC layer 109 does not contain silicon, an ashing process is adopted to remove the BARC layer 109 , and the ashing process does not contain oxygen to ensure that the inner sidewall 108 is not oxidized.

[0063] That is, Figure 2E In the embodiment, the inner sidewall 108 is still made of silicon nitride.

[0064] In the embodiment of the present invention, the process gas of the ashing process includes N2 and H2.

[0065] Step 7: Figure 2F As shown, pre-cleaning is performed, during which the inner sidewall spacer 108 remains on the side of the active region contact hole opening 107 due to not being oxidized, thereby preventing the width of the active region contact hole opening 107 from expanding.

[0066] Since the inner sidewall 108 is still a silicon nitride layer, the inner sidewall 108 will not be removed during the pre-cleaning. Figure 2F The structure and Figure 2E same, Figure 2F Only the pre-cleaning is further performed.

[0067] Step eight, forming a zeroth metal layer (not shown) in the active area, wherein the zeroth metal layer in the active area completely fills the active area contact hole opening 107, and the zeroth metal layer in the active area and the contact area form an ohmic contact to reduce contact resistance.

[0068] Also refer to Figure 2F As shown, the distance between the zeroth metal layer in the active area and the gate structure 102 is the distance d101 between the inner side surface of the inner side wall 108 and the adjacent side surface of the gate structure 102. It can be seen that since the inner side wall 108 is retained during the pre-cleaning, the distance d101 can be maintained at the set value. In the existing method, the inner side wall will be removed during the pre-cleaning because it will be oxidized. After the inner side wall is removed, the corresponding interlayer film will also be consumed, and finally the distance between the zeroth metal layer in the active area and the gate structure is smaller than the distance d101 corresponding to the embodiment of the present invention. Keeping the distance d101 at a larger value can reduce the parasitic capacitance between the zeroth metal layer in the active area and the gate structure 102, thereby improving the AC performance of the device; at the same time, it can also prevent the short circuit between the zeroth metal layer in the active area and the gate structure 102.

[0069] In the embodiment of the present invention, the semiconductor device is an N-type device, the source region 103 and the drain region 104 are both heavily N-type doped, and the impurity type of the first ion implantation is P-type. When the impurity type of the first ion implantation is P-type, the impurity of the first ion implantation includes boron.

[0070] In other embodiments, the semiconductor device may be a P-type device, the source region 103 and the drain region 104 may be heavily P-type doped, and the impurity type of the first ion implantation may be N-type.

[0071] In the process of defining the first ion implantation area, the embodiment of the present invention uses a BARC layer 109 to fill the active area contact hole opening 107. Before the first ion implantation, the BARC layer 109 in the first ion implantation area is removed, and the BARC layer 109 outside the first ion implantation area is retained. The first ion implantation can contact the area, thereby reducing the contact resistance, thereby improving the direct current (DC) performance of the device.

[0072] At the same time, after the first ion implantation, since the BARC layer 109 does not contain silicon, it is not necessary to use a wet process to remove the BARC layer 109. The BARC layer 109 can be directly removed by an ashing process that does not contain oxygen. In this way, while ensuring the removal of the BARC layer 109, the ashing process will not produce an oxidation effect on the inner sidewall 108, so that in the subsequent pre-cleaning, the inner sidewall 108 will still remain on the side of the active area contact hole opening 107, so that the layer of the wall on both sides of the active area contact hole opening 107 can be cleaned. The interlayer film, i.e., the zero-layer interlayer film 1050 and the first-layer interlayer film 1051, is used for protection, so that the width of the contact hole opening 107 in the active area can be prevented from expanding. In this way, the spacing between the zero-layer metal layer in the active area and the side of the gate structure 102 is guaranteed, and the spacing between the zero-layer metal layer in the active area and the side of the gate structure 102 is prevented from being reduced, thereby increasing the parasitic capacitance between the two and reducing the alternating current (AC) performance of the device, and further preventing the zero-layer metal layer in the active area and the gate structure 102 from being short-circuited.

[0073] Therefore, the embodiments of the present invention can not only effectively reduce the contact resistance of the contact hole, i.e., the zeroth metal layer in the active area, thereby improving the DC performance of the device, but also ensure the spacing between the zeroth metal layer in the active area and the side of the gate structure 102, thereby improving the AC performance of the device and preventing the short circuit between the zeroth metal layer in the active area and the gate structure 102 at the same time.

[0074] The BARC used in the embodiment of the present invention not only has an anti-reflection function, but also has an excellent filling effect on trenches and contact holes with high aspect ratios, and can replace the functions of SOC and SiARC used in the existing method; and this BARC does not contain Si, so the ashing process can use N2 / H2 gas; by reducing the critical dimension (CD) of the contact hole, the risk of MOA and MG short circuit can be reduced, thereby improving the performance of the device. Therefore, the embodiment of the present invention can ensure DC Perf. without enlarge MOA CD, thereby ensuring the AC Perf. of the device.

[0075] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A method for manufacturing a zeroth metal layer in an active area, characterized in that: The steps include: Step 1, providing a semiconductor substrate having completed an active area contact hole opening formation process; A gate structure of a semiconductor device is formed on the top surface of the semiconductor substrate, an active region and a drain region are self-alignedly formed in the semiconductor substrate on both sides of the gate structure, a zeroth interlayer film is filled in the spacing region between the gate structures, and a first interlayer film covers the top surface of the gate structure and the top surface of the zeroth interlayer film; The source region and the drain region are both formed with corresponding active region contact hole openings, and the active region contact hole openings pass through the first interlayer film and the zeroth interlayer film; Step 2: forming an inner sidewall on the side of the opening of the contact hole in the active area, wherein the material of the inner sidewall is different from the material of the first interlayer film and the zeroth interlayer film; Step 3, forming a BARC layer, wherein the BARC layer covers the top surface of the first interlayer film and completely fills the active area contact hole opening, and the BARC layer has a flat top surface; Step 4: performing a photolithography process to form a photoresist pattern, wherein the photoresist pattern opens a first ion implantation region, wherein the first ion implantation region includes a region between the source region and the drain region of a plurality of the semiconductor devices; Step 5, removing the BARC layer in the first ion implantation area and performing a first ion implantation, wherein the first ion implantation forms a contact area at the bottom of the contact hole opening in the active area; Step 6: Using the characteristic that the BARC layer does not contain silicon, the BARC layer is removed by an ashing process, wherein the ashing process does not contain oxygen to ensure that the inner sidewall is not oxidized; Step 7, pre-cleaning, during which the inner sidewalls are not oxidized and remain on the side of the opening of the active area contact hole, thereby preventing the width of the opening of the active area contact hole from expanding; Step eight, forming a zeroth metal layer in the active area, wherein the zeroth metal layer in the active area completely fills the contact hole opening in the active area, and the zeroth metal layer in the active area and the contact area form an ohmic contact to reduce contact resistance.

2. The method for manufacturing the zeroth metal layer in the active area according to claim 1, characterized in that: The gate structure includes a gate dielectric layer and a gate conductive material layer stacked in sequence.

3. The method for manufacturing the zeroth metal layer in the active area according to claim 2, characterized in that: The gate dielectric layer includes a high dielectric constant layer; and the gate conductive material layer includes a metal gate.

4. The method for manufacturing the zeroth metal layer in the active area according to claim 1, characterized in that: A first silicon nitride layer is formed between the first interlayer film and the zeroth interlayer film.

5. The method for manufacturing the zeroth metal layer in the active area according to claim 1, characterized in that: Step 2 includes the following sub-steps: forming an inner sidewall material layer, wherein the inner sidewall material layer covers the inner surface of the opening of the contact hole in the active area; An etching process is performed to remove the inner sidewall material layer on the bottom surface of the active area contact hole opening, and the inner sidewall is formed by the inner sidewall material layer retained on the side surface of the active area contact hole opening.

6. The method for manufacturing the zeroth metal layer in the active area according to claim 1, characterized in that: The material of the inner sidewall includes silicon nitride.

7. The method for manufacturing the zeroth metal layer in the active area according to claim 1, characterized in that: The semiconductor device is an N-type device, the source region and the drain region are both heavily N-type doped, and the impurity type of the first ion implantation is P-type; Alternatively, the semiconductor device is a P-type device, the source region and the drain region are both heavily P-type doped, and the impurity type of the first ion implantation is N-type.

8. The method for manufacturing the zeroth metal layer in the active area according to claim 7, characterized in that: When the impurity type of the first ion implantation is P type, the impurity of the first ion implantation includes boron.

9. The method for manufacturing the zeroth metal layer in the active area according to claim 1, characterized in that: An embedded epitaxial layer is also formed in the source region and the drain region.

10. The method for manufacturing the zeroth metal layer in the active area according to claim 1, characterized in that: The thickness of the BARC layer is The thickness of the photoresist pattern is 11. The method for manufacturing the zeroth metal layer in the active area according to claim 5, characterized in that: The thickness of the inner wall material layer is 12. The method for manufacturing the zeroth metal layer in the active area according to claim 1, characterized in that: The process gas of the ashing process includes N2 and H2.

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