Paster type power hybrid integrated circuit module packaging method and packaging structure thereof

Abstract

The invention discloses a surface-mounted power hybrid integrated circuit module packaging method and a packaging structure thereof, and belongs to the technical field of microelectronic device packaging. The packaging structure is packaged by adopting a ceramic shell and a metal assembly; a high-power chip and a low-power chip are integrated in different areas in a packaging cavity of a ceramic shell, the integration areas of the high-power chip and the low-power chip are in a step type, the low-power chip and the high-power chip are sequentially integrated from an upper step to a lower step, and seamless isolation and staggered-layer integration are carried out; the high-power chip is sintered on the heat sink, and the heat sink penetrates through the ceramic shell to realize internal and external electric connection; a TU1 material is used in a key parasitic parameter generation area of the packaging structure and penetrates through the ceramic cavity and the outside, and penetrating type connection is achieved. The surface-mounted high-power chip module packaging structure solves the problems of high parasitic impedance, low heat dissipation efficiency, low product power density, low integration level and large packaging size in the conventional surface-mounted high-power chip module packaging structure. The packaging structure is widely applied to the packaging technology of the power hybrid integrated circuit module.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic device packaging, and further relates to the technical field of surface mount hybrid integrated circuit packaging, and specifically, to a surface mount power hybrid integrated circuit module packaging method and a packaging structure thereof. Background Art

[0002] With the development of microelectronic device packaging technology, the packaging requirements for integrated circuits are becoming increasingly higher. In the field of electronic packaging, traditional low-loss high-power control modules are PCB board-level discrete device packaging structures with large size and low power integration density. At present, the product technology is mature, but with the development needs of a new generation of power systems, avionics systems, and military control systems, especially in the defense and military fields such as aerospace and aviation, there is a clear demand for devices to develop in the direction of miniaturization, lightweight, low power consumption, and high power density. Although the package of a single device is small, when the functional system is assembled, it will still lead to a large system size, heavy mass, and low power density. Therefore, in order to meet the application needs of the industry, it is urgent to develop hybrid integrated microcircuit module products.

[0003] Compared with organic plastic packaging, ceramic packaging has higher mechanical strength, lower expansion coefficient and higher thermal conductivity. These characteristics can meet the requirements of high airtightness and high heat dissipation packaging of chips. Hybrid integrated circuit ceramic packaging is a packaging technology that fixes electronic components on a ceramic substrate through a specific process and seals them with a ceramic shell. This packaging technology can provide higher heat resistance, moisture resistance, corrosion resistance, and electromagnetic interference resistance. It can maintain stable performance in high temperature environment and will not cause performance degradation due to temperature increase. It has the following characteristics: 1. High moisture resistance: It has good waterproof and moisture-proof properties and is suitable for environments with high humidity; 2. High corrosion resistance: It has good corrosion resistance to chemicals such as acids, alkalis, salts and organic solvents; 3. High resistance to electromagnetic interference: It has good electromagnetic shielding ability and can be used at high frequencies without being affected by electromagnetic interference; 4. Excellent electrical properties: Ceramic materials have low resistivity and high insulation performance, which can effectively suppress electromagnetic interference and signal crosstalk; 5. Excellent mechanical properties and stability: Ceramic materials have high hardness and impact resistance, which can effectively protect the chip from external physical impact and damage; 6. Good airtightness: Ceramic packaging is an airtight packaging that can prevent moisture from entering the interior and contaminating the chip; 7. Small thermal expansion coefficient: The thermal expansion coefficient of ceramic materials is small, which is similar to the thermal expansion coefficient of chip materials, which is beneficial to improving the reliability of packaging.

[0004] Due to these remarkable characteristics, ceramic packages are widely used in various electronic fields with high performance requirements, including aerospace, military equipment, medical equipment, high-end communication equipment and functional electronics. For example, electronic equipment working in extreme temperature and radiation environments, communication and navigation systems that require high reliability and long-term stability.

[0005] The ceramic SMD package of high-power driver chips needs to meet the characteristics of high reliability and high conversion efficiency. The current package structure has large parasitic impedance, low heat dissipation efficiency, and low product power density. It cannot meet the requirements of high integration and miniaturized ceramic packaging.

[0006] In view of this, the present invention is proposed. Summary of the invention

[0007] The technical problem to be solved by the present invention is to solve the problems of large parasitic impedance, low heat dissipation efficiency, low product power density, low integration and large packaging volume in the existing surface-mount high-power chip module packaging structure.

[0008] To this end, in view of the high-power chip requirements, the packaging structure has the characteristics of high reliability, high conversion efficiency, etc., the present invention provides a surface mount power hybrid integrated circuit module packaging method, including the following method: The packaging structure is encapsulated by ceramic shell and metal components. The ceramic shell and metal components are precisely calculated and designed to put the entire product in an optimal state.

[0009] In the packaging cavity of the ceramic shell, high-power chips and low-power chips are integrated in different areas. The integration areas of high-power chips and low-power chips are stepped, and low-power chips and high-power chips are integrated in sequence from the upper step to the lower step. The use of steps for seamless isolation and staggered integration can not only ensure the isolation between chips and reduce parasitic effects, but also greatly improve the heat dissipation capacity and integration.

[0010] The high-power integrated circuit chip is directly sintered on a large heat sink made of tungsten copper. The heat sink material runs through the ceramic shell to achieve internal and external electrical connection, which greatly reduces the parasitic impedance of the product, while maximizing the heat dissipation efficiency of the product and increasing the power density of the product.

[0011] TU1 material (oxygen-free copper material) is used in the key parasitic parameter generation area of ​​the packaging structure, running through the ceramic cavity and the outside to achieve through-type connection, so as to reduce the parasitic impedance and inductive reactance of the product, thereby improving product reliability.

[0012] The packaging procedure is as follows: (1) The chip positioning mold is used to install the welding piece and high-power chip with high precision inside the shell base, and the chip and the package shell are welded by eutectic welding; (2) Nano silver paste is applied inside the shell base through a chip positioning mold and a low-power chip is installed with high precision, and the chip and the package shell are welded by sintering; (3) Interconnect the chip and the package shell through bonding technology; (4) Achieve airtight sealing between the metal cover and the packaging shell through parallel seam welding, energy storage welding or laser welding.

[0013] The packaging structure of the SMD power hybrid integrated circuit module packaging method is as follows: Figure 1 As shown. Includes: Ceramic base body 1, inner cavity 2, side cavity 3, sealing ring 4, cover plate 5, inner cavity bottom surface 6, inner cavity bottom surface metallization layer 7, inner cavity power area bottom surface 8, power area bottom surface metallization layer 9, high-power chip 10, copper-immersed heat sink 11, through-type inner electrode 12, buried inner electrode 13, side electrode 14, and external electrode 15.

[0014] The ceramic base body 1 is a multi-layer co-fired ceramic.

[0015] The inner cavity 2, side cavity 3, inner cavity bottom surface 6, inner cavity power zone bottom surface 8, mounting hole of copper-immersed heat sink 11 and filling hole of through-type inner electrode 12 are integrated into the ceramic base body 1. The inner cavity bottom surface 6 is located in the peripheral area of ​​the bottom of the inner cavity of the ceramic base, the inner cavity power zone bottom surface 8 is located in the central area of ​​the bottom of the inner cavity of the ceramic base, and the inner cavity bottom surface 6 is higher than the inner cavity power zone bottom surface 8.

[0016] The inner cavity bottom surface metallization layer 7 is made on the inner cavity bottom surface 6, and the power area bottom surface metallization layer 9 is made on the inner cavity power area bottom surface 8. The inner cavity bottom surface metallization layer 7 is used for the low-power chip assembly area, bonding area, internal electrode routing and connection with external electrodes, and the power area bottom surface metallization layer 9 is used for the high-power chip assembly area.

[0017] The copper-immersion heat sink 11 is located in the central area of ​​the high-power chip assembly area and penetrates the ceramic base body for rapid heat dissipation.

[0018] The through-type internal electrode 12 is located below the metallization layer 7 on the bottom surface of the inner cavity, penetrates the ceramic base body, and is used for via metal filling. The buried layer internal electrode 13 is located between the ceramic layers of the multilayer co-fired ceramic. The side electrode 14 is on the side wall of the ceramic base body. The external electrode 15 is located at the bottom of the ceramic base body. The upper end of the via metal is connected to the metallization layer 7 on the bottom surface of the inner cavity. The inside of the buried layer internal electrode 13 is connected to the metallization layer 7 on the bottom surface of the inner cavity, and the outside is connected to the side electrode 14. The external electrode 15 is connected to the lower end of the via metal and the lower end of the side electrode 14.

[0019] The present invention has the characteristics of high packaging power density, small parasitic inductance / impedance, high conversion efficiency, etc. (by reducing parasitic parameters, the power conversion efficiency of the product is as high as 99%).

[0020] The present invention has the characteristics of good insulation performance, ultra-small size, ultra-high integration, ultra-light weight, fast heat dissipation, high reliability, and wide coverage of product categories. It can be widely used in various products with high reliability requirements such as semiconductor devices, semiconductor power devices, hybrid integrated circuits, etc. Compared with the original plastic packaging appearance products, it has great advantages and promotion. It has very high promotion value for other products with similar appearance requirements. It can well meet the high reliability requirements and technical requirements of this type of appearance products in scientific research and production, and is widely used in aviation, aerospace and other fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of the ceramic packaging structure of a multi-channel driver chip.

[0022] Figure 2 This is a schematic diagram of the planar structure of the metallized area distribution in the inner cavity of the ceramic base packaging of the seven-channel driver chip.

[0023] Figure 3 This is a planar structural diagram of the connection relationship between the inner surface electrodes and the external electrodes of the ceramic base packaging of the seven-channel driver chip.

[0024] Figure 4 This is a top view structural diagram of the seven-channel driver chip packaging shell.

[0025] Figure 5 This is a schematic diagram of the side view structure of the seven-channel driver chip packaging shell.

[0026] In the figure: 1 is the ceramic base body, 2 is the inner cavity, 3 is the side cavity, 4 is the sealing ring, 5 is the cover plate, 6 is the bottom surface of the inner cavity, 7 is the metallization layer of the bottom surface of the inner cavity, 8 is the bottom surface of the inner cavity power area, 9 is the metallization layer of the bottom surface of the power area, 10 is the high-power chip, 11 is the copper-immersed heat sink, 12 is the through-type internal electrode, 13 is the buried internal electrode, 14 is the side electrode, and 15 is the external electrode.

[0027] 1B, 2B, 3B, 4B, 5B, 6B, 7B, 8E, 9M, 7C, 6C, 5C, 4C, 3C, 2C, 1C are the numbers of the electrodes distributed on the inner surface; B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18 are the numbers of the metallization layers distributed on the inner surface; P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16 are the numbers of the external lead electrodes. DETAILED DESCRIPTION

[0028] like Figure 1-5 As shown, taking the ceramic metal package of a seven-channel driver chip as an example, the specific implementation method of the SMD power hybrid integrated circuit module packaging method and its packaging structure is as follows: Embodiment 1: Encapsulation shell The base of the package shell is a square ceramic base. The ceramic body material is more than 95% Al2O3 ceramic (aluminum oxide) or AlN ceramic (aluminum nitride).

[0029] The cover of the package shell is a square metal cover, and the composition is 4J42 or 4J29.

[0030] The outer dimensions of the shell are 10.2mm long, 6mm wide, and 2.65mm high (length*width*height), and the volume of the internal closed cavity is 4.5mm 2 .

[0031] The sealing ring material is 4J42 / 4J29.

[0032] The through-type copper electrode material is TU1 (oxygen-free copper).

[0033] The layout of the base area is as follows: high-power chip area (referred to as P area), low-power device (including passive devices) area (referred to as K area), external lead electrode area (external electrode, referred to as B area), such as Figure 2 shown.

[0034] The surfaces of the high-power chip area, the low-power device area, and the external lead-out electrode (external electrode) area are provided with a metallization layer.

[0035] The inner surface metallization layer distribution is: B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, such as Figure 2 shown.

[0036] B17 is the main chip (high-power chip) welding area, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16 are the low-power chip welding areas and electrode leads or bonding areas, and B18 is the lead transition area that is electrically connected to the welding area.

[0037] The inner surface metallization layer is composed of multiple layers of metal materials. The surface material is gold, the second layer material is metal nickel, nickel cobalt or nickel phosphorus, and the third layer material is metal tungsten or molybdenum manganese. The surface and second layers are plated by electroplating. The third layer is the material of first printing the metal paste on the ceramic and then curing it. The thickness of the metal nickel is 1.3 to 8.9um.

[0038] The inner surface electrode distribution is: 1B, 2B, 3B, 4B, 5B, 6B, 7B, 8E, 9M, 7C, 6C, 5C, 4C, 3C, 2C, 1C, such as Figure 3 shown.

[0039] The external electrodes on the bottom outer surface are distributed as follows: P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, and P16. The structure of the external electrodes on the bottom outer surface is to first print metal tungsten or molybdenum manganese in a set area outside, and then weld a metal block on the metal tungsten or molybdenum manganese, such as Figure 1 shown.

[0040] P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, P16 are used as external lead terminals for user-side welding, and the length of each lead terminal is 0.5mm. The thickness range of each layer of metal in the metallization layer on the surface of the external electrode is: the thickness of the surface material gold is 1.3~5.7um, the purity is ≥99.9%, the thickness of the second layer material metal nickel, nickel cobalt or nickel phosphorus is 1.3~8.9um, and the thickness of the third layer material metal tungsten or molybdenum manganese is 5~30um.

[0041] The surface layer of the metal on the outer surface of the side electrode is nickel, nickel cobalt or nickel phosphorus, which is plated by electroplating. The thickness of the metal nickel is 1.3 to 8.9 um, and the bottom material is metal tungsten or molybdenum manganese, with a thickness of 5 to 30 um.

[0042] P1 is connected to 1B, P2 is connected to 2B, P3 is connected to 3B, P4 is connected to 4B, P5 is connected to 5B, P6 is connected to 6B, P7 is connected to 7B, P8 is connected to 8E, P9 is connected to 9M, P10 is connected to 7C, P11 is connected to 6C, P12 is connected to 5C, P13 is connected to 4C, P14 is connected to 3C, P15 is connected to 2C, and P16 is connected to 1C. Figure 3 shown.

[0043] The shell sealing ring and the cover plate are connected by parallel seam welding, such as Figure 1 shown.

[0044] Embodiment 2: Packaging method The specific steps are as follows: 1. Clean the outer shell: (1) First, wet clean the outer shell using vacuum or nitrogen baking; (2) Then, plasma clean the outer shell using Ar argon plasma as the cleaning gas.

[0045] For method (1): wet clean the shell first, and use vacuum or nitrogen baking: first soak the package shell in acetone for 10 minutes, then use ultrasonic low-frequency cleaning for 3 minutes, then rinse with regular water for 5 minutes, then rinse with deionized water for 10 minutes, and finally dehydrate with alcohol. Finish by baking in a 60°C nitrogen oven.

[0046] For method (2): the outer shell is cleaned with argon plasma before use; the specific scheme is as follows: the power of argon plasma cleaning is preferably set to 100W, the argon flow rate is ≯50SCCM, the cleaning time is preferably set to 180s, and each cleaning must be used up within 24 hours.

[0047] 2. Wet clean the mold and use vacuum or nitrogen baking. The method is the same as step 1 (1). If alcohol is used for dehydration, vacuum baking cannot be used.

[0048] 3. Prepare the power chips, subsystem control chips and peripheral auxiliary control chips to be packaged, passive devices, and select welding materials: high-temperature solder pads. The solder pads need to be plasma cleaned before use (the method is the same as step 1 (2)).

[0049] 4. Install the chip according to the settings. First, install the solder pads on each welding area line. Then place the chip on the solder pads in each welding area according to the position requirements. Then place the quartz press block on the chip. Finally, place the assembled mold as a whole in a vacuum sintering furnace for high-temperature sintering.

[0050] 5. Place the module in step 4 into a vacuum sintering furnace, and heat it to a preset temperature T1 at a set heating rate V1 under nitrogen conditions, and keep it at a temperature for t1 time; then, after evacuating for t2 time, fill in nitrogen, set the heating rate V2 to heat it to a preset temperature T2, and keep it at a temperature for t3 time; then, after evacuating again for t4 time, set the heating rate V3 to heat it to a preset maximum temperature T3, and keep it at a temperature for t5 time; then start cooling, set the cooling rate V4, and start filling in nitrogen when the temperature drops below the melting point of the solder piece, and finally cool it with the furnace to complete the device sintering; the relationship between the heating rates is: V1>V2>V3>V4.

[0051] 6. Place the sintered module on a bonding machine to perform wire bonding between each upper chip and the inner surface electrodes and patterns of the shell through interconnection materials to obtain a module with interconnected electrical properties.

[0052] 7. Place the device that has completed the electrical interconnection in step 6 into a parallel seam welding device, install a cover plate on the outer shell, and seal the outer shell sealing ring and the cover plate to complete the module packaging of the high power density hybrid integrated microcircuit module.

[0053] Specifically: All chips are silicon-based chips, the back metallization layer can be Ag, and the maximum chip size is 1mm×1.2mmX0.3mm. At the same time, through structural design, no less than 2 layers of staggered packaging are achieved, and the chip heat source is designed separately.

[0054] The bottom of the chip is connected to the inner cavity base with bottom solder, and the solder used for chip sintering is CT285 silver glue.

[0055] The chip mounting requirements are: installing the bottom solder, installing the bottom chip on the bottom solder, and placing a weight block on the bottom chip.

[0056] The shell sealing ring is connected to the cover plate by parallel seam welding. The shell material is a ceramic shell, and the cover plate is a metal cover plate (composition is 4J42 or 4J29). The shell and the cover plate are sealed for airtightness. After sealing, the internal water vapor content is ≤5000ppm, and the leakage rate after sealing is ≤1×10 -1 Pa cm 3 / s.

[0057] The power chip is connected to the inner surface electrode by metal wires. The metal wires are made of gold wires with a wire diameter of ≥25μm and a number of 16 wires.

[0058] The application of the method of the present invention realizes the packaging of high-power density hybrid integrated microcircuit modules. The power density, application scope and integration of low-loss high-power controllers are greatly improved. The nano silver paste and parallel seam welding multi-temperature gradient welding method can play an excellent role in heat dissipation and high-reliability airtight packaging, broadening the application scenarios of the module.

[0059] The packaging structure of the multi-channel driver chip of the present invention has the advantages of small size, light weight, high integration, high mechanical strength, stable chemical properties, excellent electrical properties, high reliability, good spatial applicability, etc. It can replace the traditional board-level discrete device packaging, solve the key problems of large size and low integrated power density, greatly save space, and simplify the system circuit layout. In addition, through stacking three-dimensional welding, the space of the volume cavity can be reduced, and the three-dimensional integrated rectifier array device packaging can be realized, which greatly improves the device production efficiency and saves the packaging shell.

[0060] Finally, it should be noted that the above embodiments are merely examples for the purpose of clear explanation. The present invention includes but is not limited to the above embodiments. It is not necessary and impossible to list all implementation methods exhaustively. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. All implementation methods that meet the requirements of the present invention belong to the protection scope of the present invention.

Claims

1. A method for packaging a surface mount power hybrid integrated circuit module, characterized in that: The following methods are included: The packaging structure is packaged with ceramic shell and metal components; The high-power chip and the low-power chip are integrated in different areas in the packaging cavity of the ceramic shell. The integration areas of the high-power chip and the low-power chip are stepped. The low-power chip and the high-power chip are integrated in sequence from the upper step to the lower step. The steps are used for seamless isolation and staggered integration. The high-power integrated circuit chip is directly sintered on the heat sink made of tungsten copper. The heat sink material runs through the ceramic shell to achieve internal and external electrical connection. TU1 material is used in the key parasitic parameter generation area of ​​the packaging structure, running through the ceramic cavity and the outside to achieve through-type connection.

2. A method for packaging a surface mount power hybrid integrated circuit module as claimed in claim 1, characterized in that: The packaging procedure is as follows: (1) The chip positioning mold is used to install the welding piece and high-power chip with high precision inside the shell base, and the chip and the package shell are welded by eutectic welding; (2) Nano silver paste is applied inside the shell base through a chip positioning mold and a low-power chip is installed with high precision, and the chip and the package shell are welded by sintering; (3) Interconnect the chip and the package shell through bonding technology; (4) Achieve airtight sealing between the metal cover and the packaging shell through parallel seam welding, energy storage welding or laser welding.

3. A method for packaging a surface mount power hybrid integrated circuit module as claimed in claim 2, characterized in that: The specific method is as follows:

1. Clean the shell: (1) Wet clean the shell first and bake it using vacuum or nitrogen; (2) The outer shell is then plasma cleaned, and the cleaning gas is Ar argon plasma; 2. Wet clean the mold and use vacuum or nitrogen baking. The method is the same as step 1 (1). If alcohol is used for dehydration, vacuum baking cannot be used.

3. Prepare the power chips, subsystem control chips and peripheral auxiliary control chips to be packaged, passive devices, and select welding materials: high-temperature solder pads. The solder pads need to be plasma cleaned before use. The method is the same as step 1 (2); 4. Install the chip according to the settings. First, install the solder pads on each soldering area. Then, place the chip on the solder pads in each soldering area according to the position requirements. Then, place the quartz block on the chip. Finally, place the assembled mold as a whole in a vacuum sintering furnace for high-temperature sintering.

5. Put the module in step 4 into a vacuum sintering furnace, and heat it to the preset temperature T1 at the set heating rate V1 under nitrogen conditions for t1 time; then fill nitrogen after vacuuming for t2 time, set the heating rate V2 to heat it to the preset temperature T2, and keep it for t3 time; then vacuum again for t4 time, set the heating rate V3 to heat it to the preset maximum temperature T3, and keep it for t5 time; then start cooling, set the cooling rate V4, start filling nitrogen when the temperature drops below the melting point of the solder sheet, and finally cool it with the furnace to complete the device sintering; the heating rate relationship is: V1>V2>V3>V4; 6. Place the sintered module on a bonding machine to perform wire bonding between each upper chip and the inner surface electrodes and patterns of the shell through interconnection materials to obtain a module with electrical interconnection; 7. Place the device that has completed the electrical interconnection in step 6 into a parallel seam welding device, install a cover plate on the outer shell, and seal the outer shell sealing ring and the cover plate to complete the module packaging of the high power density hybrid integrated microcircuit module.

4. A method for packaging a surface mount power hybrid integrated circuit module as claimed in claim 3, characterized in that: For method (1), the shell is first wet cleaned and then baked using vacuum or nitrogen: first, the package shell is soaked in acetone for 10 minutes, then cleaned with ultrasonic low-frequency for 3 minutes, then rinsed with conventional water for 5 minutes, then rinsed with deionized water for 10 minutes, and finally dehydrated with alcohol, and then baked in a nitrogen oven at 60°C.

5. A method for packaging a surface mount power hybrid integrated circuit module as claimed in claim 3, characterized in that: For method (2), the housing is cleaned with argon plasma before use. The specific scheme is as follows: the power of argon plasma cleaning is preferably set to 100 W, the argon flow rate is ≯50 SCCM, and the cleaning time is preferably set to 180 s.

6. The packaging structure of a surface mount power hybrid integrated circuit module packaging method according to claim 1, characterized in that: It comprises a ceramic base body (1), an inner cavity (2), a side cavity (3), a sealing ring (4), a cover plate (5), an inner cavity bottom surface (6), an inner cavity bottom surface metallization layer (7), an inner cavity power area bottom surface (8), a power area bottom surface metallization layer (9), a high-power chip (10), a copper-immersion heat sink (11), a through-type inner electrode (12), a buried inner electrode (13), a side electrode (14), and an external electrode (15); The ceramic base body (1) is a multi-layer co-fired ceramic; The inner cavity (2), the side cavity (3), the inner cavity bottom surface (6), the inner cavity power zone bottom surface (8), the copper-immersed heat sink (11) mounting hole and the through-type inner electrode (12) filling hole are integrally manufactured in the ceramic base body (1); the inner cavity bottom surface (6) is located in the peripheral area of ​​the inner cavity bottom of the ceramic base; the inner cavity power zone bottom surface (8) is located in the central area of ​​the inner cavity bottom of the ceramic base; and the inner cavity bottom surface (6) is higher than the inner cavity power zone bottom surface (8); The inner cavity bottom surface metallization layer (7) is manufactured on the inner cavity bottom surface (6), and the power area bottom surface metallization layer (9) is manufactured on the inner cavity power area bottom surface (8); the inner cavity bottom surface metallization layer (7) is used for the low-power chip assembly area, bonding area, internal electrode routing and connection with external electrodes, and the power area bottom surface metallization layer (9) is used for the high-power chip assembly area; The copper-immersion heat sink (11) is located in the central area of ​​the high-power chip assembly area and penetrates the ceramic base body; The through-type inner electrode (12) is located below the metallization layer (7) on the bottom surface of the inner cavity, penetrates the ceramic base body, and is used for via metal filling. The buried layer inner electrode (13) is located between the ceramic layers of the multilayer co-fired ceramic. The side electrode (14) is on the side wall of the ceramic base body. The external electrode (15) is located at the bottom of the ceramic base body. The upper end of the via metal is connected to the metallization layer (7) on the bottom surface of the inner cavity. The buried layer inner electrode (13) is connected to the metallization layer (7) on the bottom surface of the inner cavity and is connected to the side electrode (14) on the outside. The external electrode (15) is connected to the lower end of the via metal and the lower end of the side electrode (14).

7. The packaging structure of a surface mount power hybrid integrated circuit module packaging method according to claim 6, characterized in that: The layout of the base area is: high-power chip area, low-power device area, and external lead-out electrode area; The surfaces of the high-power chip region, the low-power device region, and the external lead-out electrode region are provided with a metallization layer.

8. The packaging structure of a surface mount power hybrid integrated circuit module packaging method according to claim 6, characterized in that: The inner surface metallization layer is composed of multiple layers of metal materials. The surface layer material is gold, the second layer material is metal nickel, nickel cobalt or nickel phosphorus, and the third layer material is metal tungsten or molybdenum manganese. The surface layer and the second layer material are plated by electroplating. The third layer is the material of first printing the metal slurry on the ceramic and then curing it. The thickness of the metal nickel is 1.3 to 8.9um.

9. The packaging structure of a surface mount power hybrid integrated circuit module packaging method according to claim 6, characterized in that: The structure of the external electrode on the outer surface of the bottom is to first print metal tungsten or molybdenum manganese in a set area outside, and then weld a metal block on the metal tungsten or molybdenum manganese.

10. The packaging structure of a surface mount power hybrid integrated circuit module packaging method according to claim 6, characterized in that: The length of each external electrode lead terminal is 0.5mm, and the thickness range of each metal layer in the external electrode surface metallization layer is: the thickness of the surface material gold is 1.3~5.7um, the purity is ≥99.9%, the thickness of the second layer material metal nickel, nickel cobalt or nickel phosphorus is 1.3~8.9um, and the thickness of the third layer material metal tungsten or molybdenum manganese is 5~30um.

11. The packaging structure of a surface mount power hybrid integrated circuit module packaging method according to claim 6, characterized in that: The surface layer of the metal on the outer surface of the side electrode is nickel, nickel cobalt or nickel phosphorus, which is plated by electroplating. The thickness of the metal nickel is 1.3 to 8.9 um, and the bottom material is metal tungsten or molybdenum manganese, with a thickness of 5 to 30 um.

12. The packaging structure of a surface mount power hybrid integrated circuit module packaging method according to claim 6, characterized in that: The outer shell sealing ring is connected to the cover plate by parallel seam welding; the outer shell and the cover plate are sealed in an airtight manner, and the internal water vapor content after sealing is ≤5000ppm, and the leakage rate after sealing is ≤1×10 -1 Pa cm 3 / s.

13. The packaging structure of a surface mount power hybrid integrated circuit module packaging method according to claim 6, characterized in that: The inner surface metallization layer is distributed as follows: B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18; B17 is a high-power chip welding area, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16 are low-power chip welding areas and electrode leads or bonding areas, and B18 is a lead transition area electrically connected to the welding area; The inner surface electrode distribution is: 1B, 2B, 3B, 4B, 5B, 6B, 7B, 8E, 9M, 7C, 6C, 5C, 4C, 3C, 2C, 1C; The external electrodes on the bottom outer surface are distributed as follows: P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14, P15, and P16.

14. The packaging structure of a surface mount power hybrid integrated circuit module packaging method according to claim 13, characterized in that: P1 is connected to 1B, P2 is connected to 2B, P3 is connected to 3B, P4 is connected to 4B, P5 is connected to 5B, P6 is connected to 6B, P7 is connected to 7B, P8 is connected to 8E, P9 is connected to 9M, P10 is connected to 7C, P11 is connected to 6C, P12 is connected to 5C, P13 is connected to 4C, P14 is connected to 3C, P15 is connected to 2C, and P16 is connected to 1C; The high-power chip is connected to the inner surface electrode by wire bonding.

15. The packaging structure of a surface mount power hybrid integrated circuit module packaging method according to claim 6, characterized in that: The package shell base is a square ceramic base, and the material of the ceramic base is more than 95% Al2O3 ceramic or AlN ceramic; The package shell cover is a square metal cover, and the material of the metal cover is 4J42 or 4J29; The material of the sealing ring is 4J42 / 4J29; The through-type copper electrode material is TU1; The dimensions of the package shell are: length 10.2mm, width 6mm, height 2.65mm, and the volume of the internal closed cavity is 4.5mm 2 .

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