Six-pulse rectification circuit

Abstract

The invention discloses a six-pulse rectification circuit, and relates to the technical field of power electronics. The six-pulse wave rectification circuit comprises an optical signal receiving and sending unit, a logic judgment unit and a trigger pulse output unit, and the optical signal receiving and sending unit is used for receiving an optical trigger signal and sending an optical return signal; the logical judgment unit is used for performing logical operation and judgment according to the processed signal; and the trigger pulse output unit is used for generating a trigger pulse according to a judgment result, and providing a stable control signal and efficient power management in a complex electrical environment. Through combination of different units, the system can safely and reliably control high-power equipment and timely respond to input signals.

Description

Technical Field

[0001] The invention relates to the technical field of power electronics, in particular to a six-pulse rectifier circuit. Background Art

[0002] In the field of power electronics, six-pulse rectification technology is widely used. However, traditional triggering methods often have problems such as poor stability, high harmonic content, and slow response speed. Multi-pulse rectification technology uses the electrical connection method of the transformer winding to achieve phase shift and increase the number of pulses of the rectifier. By using this technology, the number of pulses of the rectifier is increased to eliminate or suppress harmonic interference of a specific order in the input current, thereby reducing harmonic pollution in the power grid, thereby improving the power supply quality and meeting system requirements. However, in the multi-pulse rectification method, its optical triggering logic is an important component.

[0003] However, the existing six-pulse rectification technology has the problem of being difficult to provide stable control signals and efficient power management in complex electrical environments. Summary of the invention

[0004] In view of the deficiencies of the prior art, the present invention provides a six-pulse rectifier circuit, which solves the problem that the existing six-pulse rectifier technology is difficult to provide stable control signals and efficient power management in a complex electrical environment.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solutions: a six-pulse rectifier circuit, including an optical signal receiving and sending unit, a logic judgment unit and a trigger pulse output unit, wherein: the optical signal receiving and sending unit is used to receive an optical trigger signal and send an optical return signal; the logic judgment unit is used to perform logical operations and judgments based on the processed signal; and the trigger pulse output unit is used to generate a trigger pulse based on the judgment result.

[0006] Furthermore, the logic judgment unit is implemented based on a digital logic circuit.

[0007] Furthermore, the optical signal receiving and sending unit includes an optical fiber transmitter PH1, an optical fiber receiver PH2 and a driver chip U1, the optical fiber transmitter PH1 is connected to the driver chip U1, and the optical fiber receiver PH2 is connected to a resistor R9 and a capacitor C4 and then to a transistor N1.

[0008] Furthermore, the second pin of the driving chip U1 is connected in parallel with resistors R1 - R4 , and the resistors R1 - R4 are all grounded.

[0009] Furthermore, the models of the optical fiber transmitter PH1 and the optical fiber receiver PH2 are FT05MVNR respectively, the model of the driver chip U1 is SCT52240STDR, and the model of the transistor N1 is 2N5551G.

[0010] Furthermore, the logic judgment unit includes a valve voltage sampling and feedback voltage state circuit and a BOD undervoltage detection circuit, and the valve voltage sampling and feedback voltage state circuit is connected to the BOD undervoltage detection circuit.

[0011] Furthermore, the logic judgment unit also includes a chip U5B, and the chip U5B is connected to the chip U4B and the chip U4A respectively. The chip U4B and the chip U4A are both dual D flip-flops CD4013, and the chip U5B is a monostable multivibrator CD4538SA16.

[0012] Furthermore, the valve voltage sampling and feedback voltage state circuit includes inverters U2D-U2F, and the inverters U2D-U2F are connected in sequence; the BOD undervoltage detection circuit includes a chip U3B, and the chip U3B is connected to the chip U4B, the chip U3B is a monostable multivibrator CD4538SA16, and the chip U4B is a dual D flip-flop CD4013.

[0013] Furthermore, the trigger output unit includes a chip U3A, an inverter U2A and an inverter U2B, the inverter U2B is connected to the inverter U2A, the inverter U2A is connected to the monostable multivibrator U3A; the monostable multivibrator U3A is connected to the transistor N5.

[0014] Furthermore, the chip U3A is a monostable multivibrator CD4538SA16, and the inverter U2A and the inverter U2B are both CD40106BM96.

[0015] The present invention has the following beneficial effects: The six-pulse rectifier circuit method achieves precise control of the six-pulse rectifier light trigger logic through hardware construction and coordination with the controller, reduces the risk of failure, and increases the flexibility of component use. The circuit design of the present invention is used to provide stable control signals and efficient power management in complex electrical environments. Through the combination of different units, the system can safely and reliably control high-power devices and respond to input signals in a timely manner.

[0016] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a circuit diagram of an optical signal receiving and sending unit of a six-pulse rectifier circuit of the present invention; Figure 2 This is a circuit diagram of a logic operation judgment unit of a six-pulse rectifier circuit of the present invention; Figure 3This is a circuit diagram of a trigger pulse output unit of a six-pulse rectifier circuit of the present invention; Figure 4 It is a six-pulse rectification logic timing diagram of the six-pulse rectification circuit of the present invention. DETAILED DESCRIPTION

[0018] The present invention discloses a six-pulse rectifier optical trigger logic, which relates to the field of power electronics technology. The trigger logic realizes precise control of the six-pulse rectifier process through a unique optical signal detection and processing mechanism. It includes an optical signal receiving and sending module, a signal conditioning module, a logic judgment module and a trigger pulse output module. The optical signal receiving module is used to receive the optical trigger signal, the signal conditioning module performs filtering and other processing on the received signal, the logic judgment module performs logical operations and judgments based on the processed signal, and finally the trigger pulse output module generates a precise trigger pulse to control the operation of the six-pulse rectifier. The present invention can effectively improve the stability and reliability of the six-pulse rectifier, reduce the harmonic content, and improve the quality of electric energy.

[0019] The optical signal receiving and sending unit of the present invention is as follows Figure 1 PH1 is the fiber optic transmitter FT05MVNR; PH2 is the fiber optic receiver FR05MVIR; U1 is the driver chip SCT52240STDR; the pull-down resistors R1, R2, R3, and R4 are 200Ω, and R11 is 10kΩ; the RC absorption circuit is composed of R9=1.5kΩ and C4=100pF in parallel; C2, C3, C5, and C6 are power supply filter capacitors; and transistor N1 is 2N5551G.

[0020] In this unit, the feedback pulse signal is finally output to the PH1 fiber optic transmitter through the U1 driver chip, and then converted into an optical signal by the PH1 fiber optic transmitter and sent to the main controller for reading back. The feedback trigger output circuit provides a safe signal transmission path, using optical isolation signals to ensure the safe connection between the control circuit and the high-voltage equipment. The PH2 fiber optic receiver receives the PWM signal sent by the main controller. The PWM signal is filtered by resistors R8, R9, and C4 and input to the base of the NPN transistor 2N5551G. This signal controls the conduction and shutdown of the transistor, thereby amplifying or switching the PWM signal. When the transistor is turned on, the current flows from the collector to the emitter, and the PWM signal is output through the PH2 port. The reported valve voltage state is used as a blocking signal to block / unblock the U1 driver chip. When the reported valve voltage state is normal, U1 is blocked, and the U1 output is always low (the fiber optic transmitter is in the light state). When the reported valve voltage signal is abnormal, U1 is unblocked, and the U1 output depends on the reported pulse signal.

[0021] The logic operation judgment unit in the present invention is as follows Figure 2. U3 and U5 are monostable multivibrators CD4538SA16. U4 is a dual D flip-flop CD4013. U2 is an inverter CD40106BM96. C9, C10, C11, and C12 are power supply filter capacitors. U5 RC circuit R17=330kΩ, C8=100pF; R19=100kΩ, C13=220pF. U3 RC circuit R13=56kΩ, C7=220pF. U2 RC circuit R5=200kΩ, C1=30pF. The main function of this part of the circuit is to control the inversion of the PWM signal and generate a monostable pulse signal through a logic circuit, and finally realize the trigger control and state feedback of the system.

[0022] In this unit, CD4538 is a dual precision monostable multivibrator used to generate precise pulse signals. Two CD4538s (U5A and U5B) in the figure are used to generate trigger pulses. When the input terminals (such as 1A and 2A) receive PWM signals, the output terminals (1Q and 2Q) will generate a pulse signal with a fixed width. The pulse width is determined by external resistors and capacitors (in the circuit, these are resistors R19, R17 and capacitors C7, C8 associated with U5A and U5B). When the controller's PWM inverted signal reaches the 1A pin of U5A, the 1Q pin of U5A outputs a monostable pulse signal, which can be used to control the operation of subsequent circuits. This module is mainly used for pulse delay or pulse shaping. Ensure that a pulse signal with a clear width is output after the trigger event occurs. CD4013 is a dual D flip-flop, and U4A and U4B are used to latch the signal. Among them, pins 13 and 3 of U5, pin 4 of U4, and pin 13 of U3 are reset signal input terminals. Reset is independent of the clock and is completed by the high level on the reset line. When the pulse signal generated by CD4538 is input to the D or CLK pin of CD4013, the trigger latches its current state according to this input signal and outputs it to the Q port. This state will not change until the next clock pulse or reset signal arrives. In the figure, the trigger pulses of U4A and U4B are provided by the output of CD4538, and the latched output Q is used as one of the signals for trigger pulse output logic judgment in the subsequent trigger output unit.

[0023] This unit also includes a valve voltage sampling and feedback voltage state module, as well as a BOD undervoltage detection reset module. It is converted into a clear digital signal through multiple Schmitt trigger inverters CD40106BM96 to ensure that the output signal has a clear high and low level state for further control and feedback. This part of the circuit is used to sample and judge the valve voltage state. The input signal enters the inverter U2D through the diode D2 and the resistor R11, and the inverter outputs the signal to the subsequent inverters U2E and U2F, forming a multi-stage signal shaping process. Capacitor C1 and resistor R17 form an RC circuit, which defines the time constant of the signal to ensure smooth conversion and stable sampling of the signal. The final shaped signal is output by the diode D10 as a feedback signal of "returning the valve voltage state" for Figure 1 The U1 gate driver chip mentioned above implements blocking / unblocking. When a BOD (undervoltage detection) condition is detected, an undervoltage signal is generated. This signal is input to the monostable trigger U5B through diode D11. The output signal of U5B is used to trigger the latch U4B, latch the undervoltage fault state and output it as a "return valve voltage state" signal. Indicates the BOD fault state. When the system returns to normal, the reset signal will be triggered by the monostable trigger U5B, reset the latch U4B, and restore the system to normal. At this time, in the second single pulse, the BOD fault is reset and the valve voltage is read back again. If there is light (low level) output, the valve voltage is normal and the power supply is normal. If there is no light (high level) output, the valve voltage is abnormal, or the power supply is abnormal. These two modules work together to ensure that the entire system can operate stably under voltage changes and potential faults, and timely feedback the system status for necessary protection measures.

[0024] The trigger output unit of the present invention is as follows Figure 3 . U3 is a monostable multivibrator CD4538SA16. U2 is an inverter CD40106BM96. U6 is a logic NAND gate CD4023BM. C15~C20 are power supply filter capacitors. U3RC circuit R31=56kΩ, C14=220pF. HL2 and HL3 are voltage regulators ZM4735A. N4 is a trigger pulse output transistor BU406.

[0025] In this unit, the VCC power supply detection signal enters the input of U2A (CD40106BM96 inverter). The Schmitt trigger inverter converts the input analog signal into a stable digital signal. The shaped signal is further processed by U2B and then enters the input of U6B (three-input NAND gate). U6B performs a logical "NAND" operation on multiple input signals. The logic signal output from U6B enters U3A (CD4538BM), which is used as a monostable trigger to generate a fixed width trigger pulse signal. This pulse signal is set by the external resistor R31 and capacitor C14 to set the time constant. The generated trigger signal is amplified by transistor N5 to drive the subsequent control circuit. The monostable signal output by the U6 logic NAND gate controls the conduction and shutdown of the transistor after passing through the U3 monostable multivibrator CD4538SA16. The ZM4735A voltage regulator diode is used to stabilize the voltage to ensure that the transistor works at a stable voltage to avoid misoperation or damage due to voltage fluctuations. Diodes D6 and D7 (LL4148) are used to protect transistors from reverse current or high voltage spikes. Finally, the trigger pulse signal is output through N4 transistor BU406.

[0026] Figure 4 The timing diagram of the six-pulse rectification logic of the present invention is shown in Figure 1. Through tests under different load conditions, the results show that compared with the traditional triggering method, the light-triggered logic of the present invention can significantly improve the stability and reliability of rectification, and has a faster response speed.

[0027] The trigger pulse comes from the controller, and the pulse signal sent by the controller is triggered in the form of single, double, and single pulses. Compared with the single pulse trigger, the pulse form of "single, double, and single" provides higher reliability. The existence of double pulses can be used as a redundancy mechanism to ensure that the trigger signal is correctly received and recognized. Even in the presence of noise or interference, the repetitive nature of the double pulse increases the reliability of the trigger. The pulse form of "single, double, and single" can also be used to detect the trigger state. If the receiving end does not receive the double pulse correctly, an error occurs and a trigger failure signal is reported.

[0028] The pulse signal of the application scenario of the present invention adopts single, double, and single pulse forms, and the pulse modulation time should be reasonably determined according to factors such as AC power frequency, load characteristics, and thyristor characteristics. Generally, the pulse modulation time needs to be between a few microseconds and tens of microseconds, which is 5 microseconds in the present invention. According to the pulse modulation time, the clock frequency of the controller needs to be at least 2MHz.

[0029] During the whole process of triggering and reading back, a single pulse only reads back the status, while a double pulse triggers. At the end of the first single pulse, that is, the falling edge, the status before the trigger is read back. If there is valve voltage, the output is no light (high level), and if there is no valve voltage, the output is light (low level). At this time, while U5-9 and U5-4 perform feedback triggering (falling edge), the reported status is D latched and input into U5-10 and U4-5. The double pulse generates a trigger pulse and reads back the valve voltage status after the trigger. Under normal circumstances, there is light (low level) output. When a BOD fault occurs or the trigger fails, there is no light (high level) output. The second single pulse resets the BOD fault and reads back the valve voltage again. If there is light (low level) output, the valve voltage is normal and the power supply is normal. If there is no light (high level) output, the valve voltage is abnormal or the power supply is abnormal.

[0030] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0031] The present invention is described with reference to flowcharts and / or block diagrams of systems, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0032] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0033] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0034] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0035] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A six-pulse rectifier circuit, characterized in that: It includes an optical signal receiving and sending unit, a logic judgment unit and a trigger pulse output unit, wherein: The optical signal receiving and sending unit is used to receive an optical trigger signal and send an optical return signal; The logic judgment unit is used to perform logic operations and judgments according to the processed signals; The trigger pulse output unit is used to generate a trigger pulse according to the judgment result.

2. A six-pulse rectifier circuit according to claim 1, characterized in that: The logic judgment unit is implemented based on a digital logic circuit.

3. A six-pulse rectifier circuit according to claim 1, characterized in that: The optical signal receiving and sending unit includes an optical fiber transmitter PH1, an optical fiber receiver PH2 and a driver chip U1. The optical fiber transmitter PH1 is connected to the driver chip U1. The optical fiber receiver PH2 is connected to a resistor R9 and a capacitor C4 and then to a transistor N1.

4. A six-pulse rectifier circuit according to claim 3, characterized in that: The second pin of the driving chip U1 is connected in parallel with resistors R1 - R4 , and the resistors R1 - R4 are all grounded.

5. A six-pulse rectifier circuit according to claim 3, characterized in that: The models of the optical fiber transmitter PH1 and the optical fiber receiver PH2 are FT05MVNR respectively, the model of the driver chip U1 is SCT52240STDR, and the model of the transistor N1 is 2N5551G.

6. A six-pulse rectifier circuit according to claim 1, characterized in that: The logic judgment unit includes a valve voltage sampling and feedback voltage state circuit and a BOD undervoltage detection circuit, and the valve voltage sampling and feedback voltage state circuit is connected to the BOD undervoltage detection circuit.

7. A six-pulse rectifier circuit according to claim 6, characterized in that: The logic judgment unit also includes a chip U5B, which is connected to the chip U4B and the chip U4A respectively. The chip U4B and the chip U4A are both dual D flip-flops CD4013, and the chip U5B is a monostable multivibrator CD4538SA16.

8. The six-pulse rectifier circuit according to claim 6, characterized in that: The valve voltage sampling and feedback voltage state circuit includes inverters U2D-U2F, which are connected in sequence; the BOD undervoltage detection circuit includes chip U3B, which is connected to chip U4B, the chip U3B is a monostable multivibrator CD4538SA16, and the chip U4B is a dual D flip-flop CD4013.

9. The six-pulse rectifier circuit according to claim 1, characterized in that: The trigger output unit includes a chip U3A, an inverter U2A and an inverter U2B, wherein the inverter U2B is connected to the inverter U2A, and the inverter U2A is connected to the monostable multivibrator U3A; The monostable multivibrator U3A is connected to the transistor N5.

10. A six-pulse rectifier circuit according to claim 9, characterized in that: The chip U3A is a monostable multivibrator CD4538SA16, and the inverter U2A and the inverter U2B are both CD40106BM96.

Images