Power supply identification grading circuit and radio frequency switch system

Abstract

The invention discloses a power supply identification grading circuit which comprises a VDD gear identification module, a step-down circuit switch and a step-down module. The step-down circuit switch is a PMOS tube; the step-down module comprises a step-down diode; the VDD gear identification module comprises a peak-shaped current source, a constant current source and a current comparator. The invention also discloses a radio frequency switch system which comprises a decoder module, a driver module, a charge pump module, a radio frequency switch and a power supply identification grading circuit. In the case that the input voltage VDD is mainly a fixed voltage (2.8 V / 1.8 V / 1.2 V), the on / off of the PMOS transistor is controlled through the identification circuit in the chip, so that the function of replacing a voltage regulator module is achieved, the gear compatibility of the input voltage VDD is realized, and the area of the chip is saved at the same time.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency front-end chips, and in particular to a power supply identification and grading circuit and a radio frequency switch system. Background Art

[0002] With the continuous development of technology, people's demand for RF front-end equipment (such as power amplifiers, active antenna tuners, low noise amplifiers and antenna switches, etc.) continues to increase, and the integration of RF chip modules on the whole system board continues to increase. For equipment manufacturers, the routing resources of chip interfaces including working voltage are becoming increasingly tight. At the same time, the requirement of low power consumption of the system promotes the optimization of working voltage in the direction of low voltage. The digital control voltage on the system board is generally 1.2V. Taking the RF switch as an example, the working voltage is generally 2.8V. The working voltage needs to be compatible with 1.8V or even 1.2V to work normally, so as to achieve intensive use of the routing resources of the working voltage.

[0003] The design of the RF switch has been reused by calling the underlying modules to shorten the product development cycle. In response to the change of the external input voltage VDD, the following solution is generally adopted in the prior art, calling the reused voltage regulator module to convert the external input voltage VDD, especially the high voltage, to the internal voltage Vint of the appropriate level. The voltage regulator module is suitable for wide range voltage conversion, but this circuit module occupies a large area and does not meet the trend of continuous chip shrinking.

[0004] Therefore, how to design an input power identification and grading circuit with a small footprint, which is compatible with several fixed-level (2.8V / 1.8V / 1.2V) input voltages VDD and can be used in a radio frequency switch system, is an urgent problem to be solved. Summary of the invention

[0005] In view of this, the purpose of the present invention is to solve the problem that the voltage regulator module includes a bandgap module and an LDO module as mentioned above, and occupies a large chip area. For the case where the input voltage VDD is mainly a fixed voltage (2.8V / 1.8V / 1.2V), the gear recognition circuit is used to control the conduction or shutdown of the PMOS tube, and when the input voltage VDD is a higher gear, the buck module with a fixed voltage reduction amplitude is enabled to reduce the voltage to the range corresponding to the lower gear, thereby achieving the function of replacing the voltage regulator module, realizing the input voltage VDD gear compatibility and saving chip area.

[0006] To achieve the above object, the present invention provides a power supply identification and grading circuit, including a VDD gear position identification module, a step-down circuit switch and a step-down module;

[0007] The step-down circuit switch is a PMOS tube; the step-down module includes a step-down diode or a plurality of step-down diodes arranged in series; the step-down circuit switch and the step-down module are connected in parallel and bridged between the input end and the output end of the power identification and grading circuit;

[0008] The input end of the VDD gear position identification module is electrically connected to the input end of the power supply identification and grading circuit, and the output end of the VDD gear position identification module 110 is electrically connected to the control end of the step-down circuit switch;

[0009] The VDD gear identification module includes a peak current source, a constant current source and a current comparator, and the peak current source and the constant current source are electrically connected to the current comparator respectively; the VDD gear identification module is used to output a low voltage signal and turn off the buck circuit switch when the input voltage VDD is a voltage corresponding to a preset first VDD gear, and output a high voltage signal and turn on the buck circuit switch when the input voltage VDD is a voltage corresponding to a preset second VDD gear, and the voltage corresponding to the first VDD gear is less than the voltage corresponding to the second VDD gear.

[0010] Preferably, the peak current source comprises a first resistor and a Nagata current mirror, and two ends of the first resistor are electrically connected to an input end of the VDD gear position identification module and an input end of the Nagata current mirror, respectively.

[0011] Preferably, the Nagata current mirror includes a first NMOS tube, a second NMOS tube and a second resistor; the source of the first NMOS tube and the source of the second NMOS tube are grounded; the two ends of the second resistor are electrically connected to the drain of the first NMOS tube and the gate of the first NMOS tube respectively; the gate of the second NMOS tube is electrically connected to the drain of the first NMOS tube; the threshold voltage of the first NMOS tube is the same as the threshold voltage of the second NMOS tube.

[0012] Preferably, the constant current source comprises a Widlar current mirror; the constant current source further comprises a third PMOS tube and a fourth PMOS tube in a cascode arrangement, and the third PMOS tube and the fourth PMOS tube are used to maintain the reference current and the output current of the Widlar current mirror equal.

[0013] Preferably, the Widlar current mirror includes a fifth NMOS tube, a sixth NMOS tube and a third resistor R3; the source of the third PMOS tube and the source of the fourth PMOS tube are electrically connected to the input end of the VDD gear position identification module; the gate of the third PMOS tube and the gate of the fourth PMOS tube are electrically connected to the drain of the fourth PMOS tube; the drain of the fifth NMOS tube is electrically connected to the drain of the third PMOS tube; the drain of the sixth NMOS tube is electrically connected to the drain of the fourth PMOS tube; the gate of the fifth NMOS tube and the gate of the sixth NMOS tube are electrically connected to the drain of the fifth NMOS tube; the source of the fifth NMOS tube is grounded; the two ends of the third resistor R3 are electrically connected to the source and the ground of the sixth NMOS tube respectively; the third PMOS tube MP3 and the fourth PMOS tube have the same device parameters; the threshold voltage of the fifth NMOS tube is the same as the threshold voltage of the sixth NMOS tube; the channel width-to-length ratio of the sixth NMOS tube is K times the channel width-to-length ratio of the fifth NMOS tube, K>1.

[0014] Preferably, the VDD grading identification circuit includes a first parallel branch, a second parallel branch, a third parallel branch, a fourth parallel branch, a fifth parallel branch and a sixth parallel branch; the first to sixth parallel branches are respectively connected between the input terminal and the ground terminal of the VDD grading identification circuit; the first parallel branch includes a first resistor R1, a second resistor R2 and a first NMOS tube connected in series in sequence; the second parallel branch includes a first PMOS tube and a second NMOS tube connected in series and having a common drain; the third parallel branch includes a second PMOS tube and a third NMOS tube connected in series and having a common drain; the fourth parallel branch includes a third PMOS tube and a fifth NMOS tube connected in series and having a common drain; the fifth parallel branch includes a fourth PMOS tube, a sixth NMOS tube and a third resistor R3 connected in series in sequence; the sixth parallel branch includes a fifth PMOS tube and a fourth NMOS tube connected in series and having a common drain; the source electrodes of the first to fifth PMOS tubes are electrically connected to the input terminal of the VDD grading identification circuit. connection; the sources of the first to fifth NMOS tubes are grounded; the sixth NMOS tube and the fourth PMOS tube are electrically connected to the common drain, and the source of the sixth NMOS tube is electrically connected to the third resistor R3; the drain of the fifth PMOS tube is electrically connected to the output end of the VDD gear position identification module; the gate of the first NMOS tube is electrically connected to the circuit node between the first resistor R1 and the second resistor R2; the gate of the second NMOS tube is electrically connected to the drain of the first NMOS tube; the gate of the third NMOS tube and the gate of the fourth NMOS tube are electrically connected to the drain of the third NMOS tube; the gate of the fifth NMOS tube and the gate of the sixth NMOS tube are electrically connected to the drain of the fifth NMOS tube; the gate of the first PMOS tube and the gate of the second PMOS tube are electrically connected to the drain of the first PMOS tube; the gate of the third PMOS tube, the gate of the fourth PMOS tube and the gate of the fifth PMOS tube are electrically connected to the drain of the fourth PMOS tube.

[0015] Preferably, the step-down module specifically includes a step-down diode, the first VDD gear is 1.2V gear, and the second VDD gear is 1.8V gear.

[0016] Preferably, the step-down module specifically includes two step-down diodes connected in series, the first VDD gear is a 1.8V gear, and the second VDD gear is a 2.8V gear.

[0017] On the other hand, the present invention provides a radio frequency switch system, including a decoder module, a driver module, a charge pump module, a radio frequency switch and the aforementioned power identification and grading circuit; the power identification and grading circuit is electrically connected to the input end, the decoder module and the driver module of the radio frequency switch system, respectively, and the power identification and grading circuit is used to convert the input voltage of the radio frequency switch system into an internal voltage; the decoder module is used to decode the control coding signal and provide a control signal to the driver module; the decoder module and the driver module are electrically connected to the charge pump module, respectively, and the charge pump module is electrically connected to the radio frequency switch.

[0018] The beneficial effects of the present invention are:

[0019] When the input voltage VDD is mainly a fixed voltage (2.8V / 1.8V / 1.2V), the on or off of the PMOS tube is controlled by the identification circuit inside the chip, thereby achieving the function of replacing the voltage regulator module, realizing input voltage VDD gear compatibility while saving chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 The circuit structure block diagram of the radio frequency switch system;

[0022] Figure 2 The circuit structure block diagram of the power source identification and grading circuit of the first embodiment;

[0023] Figure 3 1 is a circuit structure block diagram of a VDD gear position identification module according to an embodiment of the present invention;

[0024] Figure 4 The circuit diagram of the Nagata current mirror based on NMOS tube;

[0025] Figure 5 is the I of the Nagata current mirror out —I in Schematic diagram of the relationship curve;

[0026] Figure 6 is a circuit diagram of a peak current source according to an embodiment of the present invention;

[0027] Figure 7 is a circuit diagram of a constant current source according to an embodiment of the present invention;

[0028] Figure 8 is a circuit diagram of a VDD gear position identification module according to an embodiment of the present invention;

[0029] Fig. 9 This is a circuit simulation result diagram of Example 1;

[0030] Fig.10 This is a circuit structure block diagram of the power supply identification and grading circuit of the second embodiment. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] Figure 1 The circuit structure block diagram of a radio frequency switch system in the prior art is shown. The function of the radio frequency switch system is to connect any one or several of the multiple radio frequency signals through control logic to realize the switching of different signal paths, including the switching of receiving and transmitting, the switching between different frequency bands, etc. The radio frequency switch system includes a voltage regulator module 100a, a decoder module 200, a driver module 300, a charge pump module 400 and a plurality of radio frequency switches 500. The voltage regulator module 100a is electrically connected to the VDD terminal, and is used to convert the input voltage VDD into the working voltage Vint inside the system, and to supply power to the decoder module 200 and the driver module 300 and other modules; the decoder module 200 receives the control coding signal from the control coding terminal CTL0~CTL2, and controls the driver module 300 to generate a corresponding driving signal after decoding, and drives the radio frequency switch 500 to be turned on or off; the decoder module 200 and the driver module 300 are respectively electrically connected to the charge pump module 400; the charge pump module 400 and the radio frequency switch 500 are electrically connected to provide a bias voltage to the radio frequency switch 500. The voltage regulator module 100a usually includes a bandgap module (Bandgap) and a low voltage linear regulator module (LDO), and the chip occupies a large area, which does not meet the trend of continuous chip shrinking. Considering that the voltage regulator module 100a is suitable for wide-range voltage conversion in terms of function, and the input voltage VDD of the RF switch system usually has only a few fixed gears (2.8V / 1.8V / 1.2V), the function of the voltage regulator module 100a is redundant, so a circuit module dedicated to compatible conversion between the fixed gears of the above-mentioned input voltage VDD is customized to replace the voltage regulator module 100a in the prior art, which can further save chip area and improve chip performance while achieving the same function.

[0033] Embodiment 1

[0034] Figure 2 The structural block diagram of the power supply identification and grading circuit 100b of this embodiment is shown, including a VDD gear position identification module 110 (VDD detect), a buck circuit switch 120 and a buck module. The buck circuit switch 120 is a PMOS tube, and the buck module includes a diode 131. The input end of the power supply identification and grading circuit 100b is used to connect the input voltage VDD, and the output end of the power supply identification and grading circuit 100b is used to output the internal voltage Vint used by the radio frequency switch system. The buck circuit switch 120 and the buck module are connected in parallel and bridged between the input end and the output end of the power supply identification and grading circuit 100b. The input end of the VDD gear position identification module 110 is electrically connected to the input end of the power supply identification and grading circuit 100b (that is, connected to the input voltage VDD), and the output end of the VDD gear position identification module 110 is electrically connected to the control end of the buck circuit switch 120 (that is, the gate of the PMOS tube). The power supply identification and grading circuit 100b is used for applications where the input voltage VDD is compatible with 1.8V and 1.2V. Since the conduction voltage drop of a single diode is 0.6V, it can be directly used as a step-down module to save chip area. During operation, when the VDD gear recognition module 110 detects that the input voltage VDD is 1.8V, the output voltage is high, that is, VOUT=VDD, and the PMOS tube is turned off. At this time, the output voltage of the power supply identification and grading circuit 100b, that is, the internal voltage Vint=1.8-0.6V=1.2V; when the VDD gear recognition module 110 detects that the input voltage VDD is 1.2V, the output voltage is low, that is, VOUT=0, and the PMOS tube is turned on. At this time, the output voltage of the power supply identification and grading circuit 100b, that is, the internal voltage Vint=VDD=1.2V.

[0035] Figure 3 The circuit structure block diagram of the VDD gear position identification module 110 is shown. The VDD gear position identification module includes a peak current source 111, a constant current source 112 and a current comparator 113. The peak current source 111 includes a Nagata current mirror, and the constant current source 112 includes a Widlar current mirror. The input ends of both are electrically connected to the input end of the VDD gear position identification module 110 (that is, connected to the input voltage VDD), and the output ends of both are electrically connected to the current comparator 113 respectively. The current comparator 113 is used to compare the output current magnitudes of the peak current source 111 and the constant current source 112 and output the corresponding output voltage VOUT of the VDD gear position identification module 110 according to the comparison result.

[0036] Figure 4The circuit structure of a Nagata current mirror is shown, including a first NMOS transistor MN1, a second NMOS transistor MN2, and a second resistor R2. The source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 are grounded; the second resistor R2 is connected between the drain and the gate of the first NMOS transistor MN1; the gate of the second NMOS transistor MN2 is electrically connected to the drain of the first NMOS transistor MN1; the gate of the first NMOS transistor serves as the input end of the Nagata current mirror, and its input current is I in The drain of the second NMOS tube MN2 serves as the output end of the Nagata current mirror, and its output current is I out The first NMOS transistor MN1 and the second NMOS transistor MN2 are manufactured on the chip by the same batch of manufacturing processes, and their threshold voltage V t1 and V t2 The same. During operation, both the first NMOS transistor MN1 and the second NMOS transistor MN2 operate in the saturation region. The principle of the Nagata current mirror is as follows:

[0037] According to Kirchhoff's voltage law of the circuit, we can get formula (1):

[0038] V gs1 -I in R2=V gs2 (1);

[0039] Since V t1 =V t2 , and further get formula (2):

[0040] V gs1 -V t1 -I in R2=V gs2 -V t2 (2);

[0041] Substituting the MOS tube saturation region output characteristics into formula (3):

[0042]

[0043] You can get I in and I out The relationship between (Nagata) is formula (4):

[0044]

[0045] Where: R2 is the resistance of the second resistor; V gs1 and V gs2 The gate-source voltage difference (V gsvoltage); I is the leakage current of the NMOS tube, the leakage current of the first NMOS tube MN1 is the input current I in , the leakage current of the second NMOS tube MN2 is the output current I out (Nagata); V t is the threshold voltage of the NMOS tube; k n is the transconductance parameter of the NMOS tube, k n =μ n ·c ox , that is, the carrier mobility μ n and the gate oxide capacitance per unit area c ox The product of; (W / L) is the channel width-to-length ratio of the MOS device, and its subscripts 1 and 2 correspond to the first NMOS transistor MN1 and the second NMOS transistor MN2 respectively.

[0046] like Figure 5 As shown, the I out —I in The curve is a peak curve, I out (Nagata) in I in The first input current I in1 When the peak value is reached, the deviation is smaller. Figure 6 As shown, a first resistor R1 is connected between the input terminal of the Nagata current mirror and the input voltage VDD to form the peak current source 111 of this embodiment, which can output a current related to the input voltage VDD, and its relationship curve is also a peak-shaped curve.

[0047] Figure 7The constant current source 112 of this embodiment is shown, which includes a pair of PMOS tubes (third PMOS tube MP3 and fourth PMOS tube MP4) with common source and common gate and a Widlar current mirror, and the Widlar current mirror includes a fifth NMOS tube MN5, a sixth NMOS tube MN6 and a third resistor R3. The source of the third PMOS tube MP3 and the source of the fourth PMOS tube MP4 are electrically connected to the input end of the constant current source 112 (i.e., connected to the input voltage VDD), the gate of the third PMOS tube MP3 and the gate of the fourth PMOS tube MP4 are electrically connected to the drain of the fourth PMOS tube MP4; the drain of the fifth NMOS tube MN5 is electrically connected to the drain of the third PMOS tube MP3; the drain of the sixth NMOS tube MN6 is electrically connected to the drain of the fourth PMOS tube MP4; the gate of the fifth NMOS tube MN5 and the gate of the sixth NMOS tube MN6 are electrically connected to the drain of the fifth NMOS tube; the source of the fifth NMOS tube MN5 is grounded; and the third resistor R3 is connected between the source of the sixth NMOS tube MN6 and the grounding terminal. The third PMOS transistor MP3 and the fourth PMOS transistor have the same device parameters, including threshold voltage, transconductance parameter and channel width-to-length ratio; the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 have the same threshold voltage and transconductance parameter, and the channel width-to-length ratio of the sixth NMOS transistor MN6 is K times the channel width-to-length ratio of the fifth NMOS transistor, K> 1. Each MOS transistor operates in the saturation region.

[0048] Since the third PMOS tube MP3 and the fourth PMOS tube MP4 have the same device parameters and common source and common gate, the output current I out (Widlar) mirror feedback to the reference current I ref , so that the two are the same size, so similarly, I can be calculated based on Kirchhoff's voltage law and the saturation region output characteristics of the MOS tube out The relationship between (Widlar) and the device parameters of each component is as follows:

[0049]

[0050] Where: R3 is the resistance of the third resistor; k n is the transconductance parameter of the NMOS transistor, (W / L) is the channel width-to-length ratio of the MOS device, the subscript 5 corresponds to the fifth NMOS transistor MN5, and correspondingly the channel width-to-length ratio of the sixth NMOS transistor MN6 is (W / L)6=K·(W / L)5;

[0051] It can be seen that when working in the saturation region, the output current I of the Widlar current mirror is out (Widlar) has nothing to do with the input voltage VDD and can be determined by the device parameters of the circuit components. By setting appropriate device parameters, the output current Iout (Nagata) is greater than the output current I of the Widlar current mirror within a preset range of about 1.2V for the input voltage VDD. out (Widlar), the current comparator 113 can output a low voltage signal VOUT=0 within the preset range (e.g., VDD<1.4V); and when the input voltage VDD is about 1.8V, the output current I out (Nagata) decays to a value significantly smaller than the output current I of the Widlar current mirror out (Widlar), the current comparator 113 can output a high voltage signal VOUT=VDD.

[0052] Figure 8The specific device circuit diagram of the VDD gear position identification module 110 of the present embodiment is further shown, including the first to sixth parallel branches, the first to sixth parallel branches are connected across the input terminal and the ground terminal; the first parallel branch includes a first resistor R1, a second resistor R2 and a first NMOS tube MN1 connected in series in sequence; the second parallel branch includes a first PMOS tube MP1 and a second NMOS tube MN2 connected in series and with a common drain; the third parallel branch includes a second PMOS tube MP2 and a third NMOS tube MN3 connected in series and with a common drain; the fourth parallel branch includes a third PMOS tube MP3 and a fifth NMOS tube MN5 connected in series and with a common drain; the fifth parallel branch includes a fourth PMOS tube MP4, a sixth NMOS tube MN6 and a third resistor R3 connected in series in sequence; the sixth parallel branch includes a fifth PMOS tube MP5 and a fourth NMOS tube MN4 connected in series and with a common drain; the source of the first to fifth PMOS tubes MP1 / 2 / 3 / 4 / 5 is electrically connected to the input terminal; the source of the first to fifth NMOS tubes MP1 / 2 / 3 / 4 / 5 is electrically connected to the input terminal; The sixth NMOS tube MN6 and the fourth PMOS tube MP4 are electrically connected to the drain, and the source of the sixth NMOS tube MN6 is electrically connected to the third resistor R3; the drain of the fifth PMOS tube MP5 is electrically connected to the output end of the VDD gear position identification module 110; the gate of the first NMOS tube MN1 is electrically connected to the circuit node between the first resistor R1 and the second resistor R2; the gate of the second NMOS tube MN2 is electrically connected to the drain of the first NMOS tube MN1; the gate of the third NMOS tube MN3 and the gate of the fourth NMOS tube MN4 are electrically connected to the drain of the third NMOS tube MN3; the gate of the fifth NMOS tube MN5 and the gate of the sixth NMOS tube MN6 are electrically connected to the drain of the fifth NMOS tube MN5; the gate of the first PMOS tube MP1 and the gate of the second PMOS tube MP2 are electrically connected to the drain of the first PMOS tube MP1; the gate of the third PMOS tube MP3, the gate of the fourth PMOS tube MP4 and the gate of the fifth PMOS tube MP5 are electrically connected to the drain of the fourth PMOS tube MP4. The circuit parts of the peak current source 111 and the constant current source 112 are shown in dashed boxes, and the remaining PMOS tubes and NMOS tubes are used to mirror the current and realize the function of the current comparator 113.

[0053] Fig. 9 The simulation result of the circuit is shown in FIG. The horizontal axis in the figure is the input voltage VDD, and the peak curve (blue) above corresponds to I out (Nagata), constant current curve (red) corresponds to I out (Widlar), the voltage curve (green) below corresponds to the output voltage VOUT of the VDD gear position identification module 110. As can be seen from the figure, the output voltage VOUT is 0 between 0.7V and 1.4V, and is the input voltage VDD above 1.5V.

[0054] exist Figure 1 On the basis of the above, the voltage regulator module 100a in the prior art is replaced by the power identification grading circuit 100b of the present embodiment to obtain the structure of the RF antenna system of the present embodiment. That is, the RF switch system of the present embodiment includes a power identification grading circuit 100b, a decoder module 200, a driver module 300, a charge pump module 400 and a plurality of RF switches 500. The power identification grading circuit 100b is electrically connected to the VDD terminal, and is used to convert the input voltage VDD into the working voltage Vint inside the system, and to supply power to the decoder module 200 and the driver module 300 and other modules; the decoder module 200 receives the control coding signal from the control coding terminal CTL0~CTL2, and after decoding, provides the control signal to the driver module 300, and the driver module 300 further drives the conduction or shutdown of the RF switch 500; the decoder module 200 and the driver module 300 are respectively electrically connected to the charge pump module 400; the charge pump module 400 and the RF switch 500 are electrically connected to provide a bias voltage to the RF switch 500.

[0055] Embodiment 2

[0056] The difference between this embodiment and the first embodiment is that Fig.10 The power identification and grading circuit 100c shown replaces the power identification and grading circuit 100b in the first embodiment.

[0057] Fig.10The structural block diagram of the power identification and grading circuit 100c of this embodiment is shown, including a VDD gear position identification module 110 (VDD detect), a buck circuit switch 120 and a buck module. The buck circuit switch 120 is a PMOS tube, and the buck module includes two diodes 131 / 132 connected in series. The input end of the power identification and grading circuit 100c is used to connect the input voltage VDD, and the output end of the power identification and grading circuit 100c is used to output the internal voltage Vint used by the radio frequency switch system. The buck circuit switch 120 and the buck module are connected in parallel and are connected across the input and output ends of the power identification and grading circuit 100c. The input end of the VDD gear position identification module 110 is electrically connected to the input end of the power identification and grading circuit 100c (that is, connected to the input voltage VDD), and the output end of the VDD gear position identification module 110 is electrically connected to the control end of the buck circuit switch 120 (that is, the gate of the PMOS tube). The power identification and grading circuit 100c is used for applications where the input voltage VDD is compatible with 2.8V and 1.8V. During operation, when the VDD gear position identification module 110 detects that the input voltage VDD is 2.8V, the output voltage is high, that is, VOUT=VDD, and the PMOS tube is turned off. At this time, the output voltage of the power identification and grading circuit 100c, that is, the internal voltage Vint=2.8-2×0.6V=1.6V; when the VDD gear position identification module 110 detects that the input voltage VDD is 1.8V, the output voltage is low, that is, VOUT=0, and the PMOS tube is turned on. At this time, the output voltage of the power identification and grading circuit 100c, that is, the internal voltage Vint=VDD=1.8V. Since the internal voltage Vint of the RF switch system can still operate normally when it deviates from the rated value by 0.2V, the gear compatibility achieved by the power identification and grading circuit 100c can meet the application requirements while greatly saving the chip area occupied by the circuit.

[0058] Compared with the first embodiment, the circuit topology of the VDD gear position identification module 110 in this embodiment remains unchanged, but the device parameters are different. Those skilled in the art can adjust the relevant device parameters (for example, adjust the channel width-to-length ratio W / L and the resistance values ​​of each resistor) according to the aforementioned formulas (1) to (5) and simulation methods, so that the module meets the identification function requirements during operation of this embodiment.

[0059] In some preferred embodiments, the power identification and grading circuit 100c and the power identification and grading circuit 100b can be multiplexed in series to be compatible with three fixed voltage levels.

[0060] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A power identification and grading circuit, characterized in that: It includes a VDD gear position identification module, a step-down circuit switch and a step-down module; The step-down circuit switch is a PMOS tube; the step-down module includes a step-down diode or a plurality of step-down diodes arranged in series; the step-down circuit switch and the step-down module are connected in parallel and bridged between the input end and the output end of the power identification and grading circuit; The input end of the VDD gear position identification module is electrically connected to the input end of the power supply identification and grading circuit, and the output end of the VDD gear position identification module 110 is electrically connected to the control end of the step-down circuit switch; The VDD gear identification module includes a peak current source, a constant current source and a current comparator, and the peak current source and the constant current source are electrically connected to the current comparator respectively; the VDD gear identification module is used to output a low voltage signal and turn off the buck circuit switch when the input voltage VDD is a voltage corresponding to a preset first VDD gear, and output a high voltage signal and turn on the buck circuit switch when the input voltage VDD is a voltage corresponding to a preset second VDD gear, and the voltage corresponding to the first VDD gear is less than the voltage corresponding to the second VDD gear.

2. The power identification and grading circuit according to claim 1, characterized in that: The peak current source includes a first resistor and a Nagata current mirror, and two ends of the first resistor are electrically connected to an input end of the VDD gear position identification module and an input end of the Nagata current mirror respectively.

3. The power identification and grading circuit according to claim 2, characterized in that: The Nagata current mirror includes a first NMOS tube, a second NMOS tube and a second resistor; the source of the first NMOS tube and the source of the second NMOS tube are grounded; the two ends of the second resistor are electrically connected to the drain of the first NMOS tube and the gate of the first NMOS tube respectively; the gate of the second NMOS tube is electrically connected to the drain of the first NMOS tube; the threshold voltage of the first NMOS tube is the same as the threshold voltage of the second NMOS tube.

4. The power identification and grading circuit according to claim 1, characterized in that: The constant current source includes a Widlar current mirror; the constant current source also includes a third PMOS tube and a fourth PMOS tube in a cascode arrangement, and the third PMOS tube and the fourth PMOS tube are used to maintain the reference current and the output current of the Widlar current mirror equal.

5. The power identification and grading circuit according to claim 4, characterized in that: The Widlar current mirror includes a fifth NMOS tube, a sixth NMOS tube and a third resistor R3; the source of the third PMOS tube and the source of the fourth PMOS tube are electrically connected to the input end of the VDD gear position identification module; the gate of the third PMOS tube and the gate of the fourth PMOS tube are electrically connected to the drain of the fourth PMOS tube; the drain of the fifth NMOS tube is electrically connected to the drain of the third PMOS tube; the drain of the sixth NMOS tube is electrically connected to the drain of the fourth PMOS tube; the gate of the fifth NMOS tube and the gate of the sixth NMOS tube are electrically connected to the drain of the fifth NMOS tube; the source of the fifth NMOS tube is grounded; the two ends of the third resistor R3 are electrically connected to the source and the ground of the sixth NMOS tube respectively; the third PMOS tube MP3 and the fourth PMOS tube have the same device parameters; the threshold voltage of the fifth NMOS tube is the same as the threshold voltage of the sixth NMOS tube; the channel width-to-length ratio of the sixth NMOS tube is K times the channel width-to-length ratio of the fifth NMOS tube, K>1.

6. The power identification and grading circuit according to claim 1, characterized in that: The VDD grading identification circuit includes a first parallel branch, a second parallel branch, a third parallel branch, a fourth parallel branch, a fifth parallel branch and a sixth parallel branch; the first to sixth parallel branches are respectively connected between the input end and the ground end of the VDD grading identification circuit; the first parallel branch includes a first resistor R1, a second resistor R2 and a first NMOS tube connected in series in sequence; the second parallel branch includes a first PMOS tube and a second NMOS tube connected in series and with a common drain; the third parallel branch includes a second PMOS tube and a third NMOS tube connected in series and with a common drain; the fourth parallel branch includes a third PMOS tube and a fifth NMOS tube connected in series and with a common drain; the fifth parallel branch includes a fourth PMOS tube, a sixth NMOS tube and a third resistor R3 connected in series in sequence; the sixth parallel branch includes a fifth PMOS tube and a fourth NMOS tube connected in series and with a common drain; the source electrodes of the first to fifth PMOS tubes are electrically connected to the input end of the VDD grading identification circuit ; The sources of the first to fifth NMOS tubes are grounded; the sixth NMOS tube and the fourth PMOS tube are electrically connected to a common drain, and the source of the sixth NMOS tube is electrically connected to the third resistor R3; the drain of the fifth PMOS tube is electrically connected to the output end of the VDD gear position identification module; the gate of the first NMOS tube is electrically connected to a circuit node between the first resistor R1 and the second resistor R2; the gate of the second NMOS tube is electrically connected to the drain of the first NMOS tube; the gate of the third NMOS tube and the gate of the fourth NMOS tube are electrically connected to the drain of the third NMOS tube; the gate of the fifth NMOS tube and the gate of the sixth NMOS tube are electrically connected to the drain of the fifth NMOS tube; the gate of the first PMOS tube and the gate of the second PMOS tube are electrically connected to the drain of the first PMOS tube; the gate of the third PMOS tube, the gate of the fourth PMOS tube and the gate of the fifth PMOS tube are electrically connected to the drain of the fourth PMOS tube.

7. The power identification and grading circuit according to claim 1, characterized in that: The step-down module specifically includes a step-down diode, the first VDD gear is 1.2V gear, and the second VDD gear is 1.8V gear.

8. The power identification and grading circuit according to claim 1, characterized in that: The step-down module specifically includes two step-down diodes arranged in series, the first VDD gear is a 1.8V gear, and the second VDD gear is a 2.8V gear.

9. A radio frequency switch system, characterized in that: It comprises a decoder module, a driver module, a charge pump module, a radio frequency switch and a power identification grading circuit as described in any one of claims 1 to 8; the power identification grading circuit is electrically connected to the input end of the radio frequency switch system, the decoder module and the driver module respectively, and the power identification grading circuit is used to convert the input voltage of the radio frequency switch system into an internal voltage; the decoder module is used to decode the control coding signal and provide a control signal to the driver module; the decoder module and the driver module are electrically connected to the charge pump module respectively, and the charge pump module is electrically connected to the radio frequency switch.

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