Network data message processing method and device, equipment and storage medium

Abstract

The invention discloses a network data message processing method and device, equipment and a storage medium. The method provided by the embodiment of the invention is applied to an FPGA (Field Programmable Gate Array), a network data message in an Ethernet switch can be acquired firstly, and the network data message is converted into a digital signal through a PHY (Physical Layer); and then carrying out CRC verification on the network data message. And if the CRC verification is passed, filtering the network data message based on preset configuration information to obtain a target message. And matching the preset configuration information with the target message to obtain a matching result. According to the invention, the FPGA is used for processing the network data message, and high-speed parallel processing can be realized, so that dependence on a CPU and resource occupation are reduced. CRC and data filtering tasks can be efficiently executed through the hardware acceleration capacity of the FPGA, and compared with traditional firewall serial check, the mode has the advantages that the performance is remarkably improved, delay is reduced, and high-bandwidth services are more powerfully supported.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a method, device, equipment and storage medium for processing network data messages. Background Art

[0002] With the rapid development of Internet technology, network communication has become an indispensable part of modern life. As one of the most important LAN communication standards, the widespread popularity and application of Ethernet has greatly improved the efficiency of information transmission. However, with the rise of high-bandwidth services such as video and voice, higher requirements are placed on network transmission speed and central processing unit (CPU) processing power. At the same time, problems such as malicious attacks and virus propagation are becoming increasingly serious, making network security protection an important task.

[0003] The related technology is to identify and intercept useless data packets (such as unnecessary data transmission, repeated data transmission, etc.) and virus messages transmitted in Ethernet by analyzing Ethernet network traffic, checking Ethernet data packet header information, and filtering content through firewalls. However, network filtering solutions based on firewall functions rely on complex rule sets and precise data packet inspection. When processing high-speed data streams, this serial inspection process will result in a large number of CPU operations, thereby occupying higher CPU resources.

[0004] Therefore, how to reduce the high demand for CPU resources while maintaining efficient network data processing capabilities is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0005] Based on the above problems, the present application provides a method, device, equipment and storage medium for processing network data packets, which can reduce the high demand for CPU resources while maintaining efficient network data processing capabilities.

[0006] The embodiments of the present application disclose the following technical solutions:

[0007] A method for processing network data messages, applied to a field programmable gate array (FPGA), comprises:

[0008] Obtaining a network data message in an Ethernet switch; the network data message has been converted into a digital signal through a physical layer PHY;

[0009] Performing a cyclic redundancy check (CRC) on the network data message;

[0010] If the CRC check passes, the network data message is filtered based on the preset configuration information to obtain the target message;

[0011] Matching the preset configuration information with the target message to obtain a matching result;

[0012] Wherein, the preset configuration information is configured through the target central processing unit CPU.

[0013] In a possible implementation, the preset configuration information includes:

[0014] Media Access Control MAC address configuration information, Internet Protocol IP address configuration information, network packet type configuration information, and port number configuration information.

[0015] In a possible implementation, the matching result includes:

[0016] The MAC address of the target message is consistent with or inconsistent with the MAC address configuration information;

[0017] The IP address of the target message is consistent with or inconsistent with the IP address configuration information;

[0018] The network packet type of the target message is consistent with or inconsistent with the network packet type configuration information;

[0019] The port number of the target message is consistent with or inconsistent with the port number configuration information.

[0020] In a possible implementation, the method further includes:

[0021] Feedback the MAC address of the target message consistent with the MAC address configuration information to the target CPU;

[0022] Feedback the IP address of the target message consistent with the IP address configuration information to the target CPU;

[0023] Feedback the network packet type of the target message consistent with the network packet type configuration information to the target CPU;

[0024] The port number of the target message that is consistent with the port number configuration information is fed back to the target CPU.

[0025] In a possible implementation, the method further includes:

[0026] If the MAC address of the target message is inconsistent with the MAC address configuration information, feeding back a MAC address inconsistency result to the target CPU;

[0027] If the IP address of the target message is inconsistent with the IP address configuration information, the IP address inconsistency result is fed back to the target CPU;

[0028] If the network packet type of the target message is inconsistent with the network packet type configuration information, feeding back the network packet type inconsistency result to the target CPU;

[0029] If the port number of the target message is inconsistent with the port number configuration information, the result of the inconsistent port number is fed back to the target CPU.

[0030] An FPGA, comprising:

[0031] The MAC module is used to obtain the network data message in the Ethernet switch and perform CRC check on the network data message; the network data message has been converted into a digital signal through PHY;

[0032] A filtering module, for filtering the network data message to obtain a target message based on preset configuration information if the CRC check passes;

[0033] A matching module, used for matching the preset configuration information with the target message to obtain a matching result;

[0034] Wherein, the preset configuration information is configured through the target central processing unit CPU.

[0035] In a possible implementation, the preset configuration information includes:

[0036] MAC address configuration information, IP address configuration information, network packet type configuration information, and port number configuration information.

[0037] In a possible implementation, the matching result includes:

[0038] The MAC address of the target message is consistent with or inconsistent with the MAC address configuration information;

[0039] The IP address of the target message is consistent with or inconsistent with the IP address configuration information;

[0040] The network packet type of the target message is consistent with or inconsistent with the network packet type configuration information;

[0041] The port number of the target message is consistent with or inconsistent with the port number configuration information.

[0042] A network data message processing device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the network data message processing method as described above is implemented.

[0043] A computer-readable storage medium, wherein instructions are stored in the computer-readable storage medium, and when the instructions are executed on a terminal device, the terminal device executes the method for processing network data packets as described above

[0044] Compared with the prior art, this application has the following beneficial effects:

[0045] The present application provides a method, device, equipment and storage medium for processing network data messages. Specifically, the method is applied to a field programmable gate array (FPGA). When executing the method for processing network data messages provided in the embodiment of the present application, the network data message in the Ethernet switch converted into a digital signal by the physical layer (PHY) can be first obtained, and a cyclic redundancy check (CRC) is performed on it. If the CRC check passes, the target message is filtered out based on the preset configuration information, and the configuration information is matched with the target message to obtain a matching result. The preset configuration information is configured by the CPU. When the present application uses FPGA to process network data, the occupancy of the CPU can be significantly reduced. Traditionally, the firewall function relies on the CPU to execute complex software logic, which may cause the CPU to be overloaded, especially in a high-bandwidth environment. FPGA provides a dedicated hardware logic that can independently handle the inspection and filtering tasks of part or all of the network traffic, reducing the pressure on the CPU. At the same time, FPGA can provide hardware-level accelerated processing capabilities, especially for tasks with high repetitiveness and high parallelism, such as CRC verification and packet filtering. FPGA can complete them at a higher speed and lower latency without waiting for operating system scheduling, thereby greatly improving processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in this embodiment or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 A method flow chart of a method for processing a network data message provided in an embodiment of the present application;

[0048] Figure 2 A schematic diagram of the structure of a network data message processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] To facilitate understanding of the technical solutions provided by the embodiments of the present application, the background technology involved in the embodiments of the present application will be described below.

[0050] With the rapid advancement of Internet technology, network communication has become a basic element of modern life. As the leading LAN communication standard, Ethernet has been widely used to significantly improve the efficiency of information transmission. However, with the rise of multimedia applications such as video and voice services, more stringent requirements have been put forward for network transmission speed and CPU computing power. At the same time, network security issues have become increasingly prominent, and the threats of malicious attacks and virus transmission have become increasingly serious. Ensuring network security has become a top priority.

[0051] At present, firewall technology is a common means of implementing network filtering. It aims to identify and block useless data transmission, repeated data transmission and other unnecessary operations, as well as suspicious virus messages by monitoring and analyzing traffic in Ethernet, checking packet header information and performing content filtering. Although such functional solutions based on firewalls play a key role in protecting network security, the complex rule sets and precise packet inspection mechanisms they rely on are prone to cause a large number of CPU operations when processing high-speed data streams, resulting in high CPU resource consumption.

[0052] In order to solve this problem, a method, device, equipment and storage medium for processing network data packets are provided in an embodiment of the present application. The method is applied to FPGA, and the network data packets of the Ethernet switch converted by PHY are first obtained, and the network data packets are digital signals. Then, CRC check is performed on these digital signals to ensure the integrity of data transmission. If the CRC check is successful, the data packets are screened using specific rules pre-configured in the target CPU to extract the required target packets. Finally, these configuration rules are compared with the screened target packets to obtain matching results. The present application uses FPGA to process network data, which significantly reduces the resource occupation of the CPU. Compared with the traditional firewall function that relies on the CPU to execute complex software logic, this hardware acceleration solution can effectively reduce the load pressure of the CPU in a high-bandwidth environment. The dedicated hardware logic provided by FPGA can not only independently handle the inspection and filtering of network traffic, but also can perform tasks with high repetitiveness and parallelism such as CRC and data packet filtering at a faster speed and lower latency, without waiting for the operating system to schedule, thereby greatly improving the processing efficiency and overall performance.

[0053] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0054] See also Figure 1 , which is a flow chart of a method for processing a network data message provided by an embodiment of the present application, such as Figure 1 As shown, the method for processing network data packets is applied to FPGA, and the method for processing network data packets may include steps S101-S104:

[0055] S101: Acquire a network data message in an Ethernet switch.

[0056] The process of FPGA acquiring network data packets in the Ethernet switch refers to the FPGA as a hardware accelerator that is directly connected to the network interface of the Ethernet switch. In this process, first, the PHY is responsible for converting the electrical or optical signals output by the actual Ethernet switch into digital signals. Then, the FPGA is connected to the interface of the Ethernet switch and can receive the network data packets in the form of digital signals converted by the PHY in real time.

[0057] It should be noted that the output signal of an Ethernet switch can be either electrical or optical, depending on the type of interface used:

[0058] Electrical signal: For standard Ethernet interfaces (such as RJ45 connectors), the switch outputs electrical signals. This signal is transmitted through twisted pair cables (such as Cat5e (Category 5Enhanced), Cat6 (Category6Enhanced), etc.);

[0059] Optical signal: For fiber optic interfaces (such as Small Form-factor Pluggable (SFP) and Enhanced Small Form-factor Pluggable (SFP+)), the switch outputs optical signals, which are transmitted through optical fibers.

[0060] FPGA does not obtain data through traditional software programs, but is directly connected to the network as a hardware device. This means that it can process network traffic at high speed and low latency without processing by the host CPU, thereby achieving efficient management and accelerated processing of network data. This method of obtaining data directly from network devices allows FPGAs to focus on specific tasks, such as packet filtering, content inspection, or network security analysis, while reducing the demand for CPU resources.

[0061] S102: Perform CRC check on the network data message.

[0062] FPGA performs CRC check on network data messages, which means using the parallel processing capability and highly customized features of FPGA at the hardware level to quickly and efficiently perform CRC calculations to ensure the integrity of data transmission.

[0063] Specifically, FPGA directly executes the CRC algorithm on the input network data message through its internal logic circuit. Unlike software implementation, the hardware architecture of FPGA allows it to process data in a pipeline or parallel manner, that is, it can perform CRC check operations on multiple data streams at the same time, greatly improving the check speed and efficiency.

[0064] FPGA mainly implements CRC check of network data messages through the following steps:

[0065] Data reception: First, the FPGA receives the network data message that needs to be CRC checked from the network interface or other external source;

[0066] Checksum generation: Next, based on the CRC algorithm, the FPGA calculates the checksum of the message. This usually involves operations such as XOR operations on binary bits and circular shifts;

[0067] Comparison verification: Then, the FPGA compares the generated checksum with the checksum originally contained in the message to determine whether the two are consistent;

[0068] Result feedback: If the verification is successful, it means that no error occurred during the data transmission process; otherwise, there may be an error, and the data may need to be retransmitted or other measures may need to be taken.

[0069] Compared with software-implemented CRC checks, this hardware implementation can greatly reduce delays and improve the overall data processing capability and reliability of the system.

[0070] S103: If the CRC check passes, the network data message is filtered based on preset configuration information to obtain a target message.

[0071] When the CRC check performed by the FPGA is successful, the FPGA will then filter the network data packets based on the configuration information pre-set in the target CPU to obtain the specific required packets, i.e., the target packets. This series of operations is usually used in the fields of network data processing, traffic management, or data analysis.

[0072] Specifically, "preset configuration information is configured through the target central processing unit CPU" means that these policies, rules or standards are set in advance by the CPU according to application requirements and passed to the FPGA in some way (such as configuration files, instruction sets, etc.). The CPU is responsible for defining which data packets should be filtered out, received or discarded, or how to modify the packet structure and other logic.

[0073] Based on this configuration information, the FPGA can efficiently perform the following steps to obtain the target message:

[0074] Identify match conditions: The FPGA reads and understands the information configured by the CPU, which may include specific packet types, source addresses, destination addresses, protocol types, or other identifiers;

[0075] Data screening: FPGA screens the input network data packets according to the rules in the configuration information. This means that FPGA can quickly determine whether each packet meets the screening conditions, and then retain or remove the corresponding packets;

[0076] Output target message: After screening, the FPGA outputs the target message that meets the requirements of the preset configuration information. These messages may be data that need further processing, data streams for specific business processes, or data packets with specific value.

[0077] This process utilizes the parallel computing power and high-speed data processing capabilities of FPGA at the hardware level, which can significantly improve the efficiency and accuracy of network data processing and reduce the CPU load.

[0078] In a possible implementation, the preset configuration information includes:

[0079] Media Access Control (MAC) address configuration information, Internet Protocol (IP) address configuration information, network packet type configuration information, and port number configuration information.

[0080] Preset configuration information refers to a set of rules, parameters or limiting conditions that are pre-set in a data processing or communication system. This information is set by the system administrator or user according to actual needs to guide the system on how to screen, identify, filter or process specific types of network data packets. When it comes to network communication and data processing, the following four types of configuration information are particularly important:

[0081] MAC address configuration information: The MAC address is a unique identifier for a physical network device, usually located on a network interface card (NIC). Through this configuration information, you can specify which devices or network segments should receive data packets and which should be ignored or discarded.

[0082] IP address configuration information: The IP address indicates the destination or source of the datagram. The configuration information can define how to handle data packets with the same or different IP addresses, such as only receiving data packets from a specific IP range, or specifically receiving communications from a specific IP.

[0083] Network packet type configuration information: This can include message type, packet size, timestamp, etc. For example, the system may need to filter out messages of a specific format (such as Transmission Control Protocol (TCP), User Datagram Protocol (UDP), etc.), or decide whether to receive or process a data packet based on the message length or specific field content.

[0084] Port number configuration information: Port is another key element of network connection, which is used to distinguish multiple applications on the same device. Configuration information can allow or deny communication requests of specific application layer protocols (such as Hypertext Transfer Protocol (HTTP), File Transfer Protocol (FTP), etc.), or specify that only packets from or to specific ports are received.

[0085] S104: Match the preset configuration information with the target message to obtain a matching result.

[0086] Matching the preset configuration information with the target message to obtain a matching result means that during the operation of the system, the set rules, parameters or specific standards (i.e., the preset configuration information) are compared and analyzed with the received data message (target message) to determine whether the data message meets these preset conditions.

[0087] In a possible implementation, the matching result includes:

[0088] The MAC address of the target message is consistent with or inconsistent with the MAC address configuration information;

[0089] The IP address of the target message is consistent with or inconsistent with the IP address configuration information;

[0090] The network packet type of the target message is consistent with or inconsistent with the network packet type configuration information;

[0091] The port number of the target message is consistent with or inconsistent with the port number configuration information.

[0092] In a possible implementation, the method further includes:

[0093] Feedback the MAC address of the target message consistent with the MAC address configuration information to the target CPU;

[0094] Feedback the IP address of the target message consistent with the IP address configuration information to the target CPU;

[0095] Feedback the network packet type of the target message consistent with the network packet type configuration information to the target CPU;

[0096] The port number of the target message that is consistent with the port number configuration information is fed back to the target CPU.

[0097] In a possible implementation, the method further includes:

[0098] If the MAC address of the target message is inconsistent with the MAC address configuration information, feeding back a MAC address inconsistency result to the target CPU;

[0099] If the IP address of the target message is inconsistent with the IP address configuration information, the IP address inconsistency result is fed back to the target CPU;

[0100] If the network packet type of the target message is inconsistent with the network packet type configuration information, feeding back the network packet type inconsistency result to the target CPU;

[0101] If the port number of the target message is inconsistent with the port number configuration information, the result of the inconsistent port number is fed back to the target CPU.

[0102] Based on the contents of S101-S104, it can be known that the method is applied to FPGA, and first obtains the network data message in the Ethernet switch, and the network data message has been converted into a digital signal through PHY. Then, a CRC check is performed on the data message. If the check passes, the target message is filtered out according to the preset configuration information, and the configuration information is matched with the target message to obtain a matching result, wherein the configuration information is configured by the target CPU. This application significantly reduces the CPU occupancy and reduces the CPU burden by using FPGA to process network data, especially in a high-bandwidth environment. FPGA uses dedicated hardware logic to independently perform network traffic inspection and filtering tasks, while providing hardware-level acceleration, which is particularly suitable for tasks with high repetitiveness and parallelism, such as CRC check and data packet filtering, and can complete processing at a higher speed and lower latency, greatly improving efficiency.

[0103] See also Figure 2 , Figure 2 A schematic diagram of the structure of a network data message processing device provided in an embodiment of the present application. Figure 2 As shown, the network data message processing device includes:

[0104] The MAC module 201 is used to obtain the network data message in the Ethernet switch and perform CRC check on the network data message; the network data message has been converted into a digital signal through PHY;

[0105] The filtering module 202 is used to filter the network data message based on the preset configuration information to obtain the target message if the CRC check passes;

[0106] A matching module 203, used to match the preset configuration information with the target message to obtain a matching result;

[0107] Wherein, the preset configuration information is configured through the target central processing unit CPU.

[0108] In a possible implementation, the preset configuration information includes:

[0109] MAC address configuration information, IP address configuration information, network packet type configuration information, and port number configuration information.

[0110] In a possible implementation, the matching result includes:

[0111] The MAC address of the target message is consistent with or inconsistent with the MAC address configuration information;

[0112] The IP address of the target message is consistent with or inconsistent with the IP address configuration information;

[0113] The network packet type of the target message is consistent with or inconsistent with the network packet type configuration information;

[0114] The port number of the target message is consistent with or inconsistent with the port number configuration information.

[0115] In a possible implementation, the FPGA further includes: a first feedback unit, wherein the first feedback unit is configured to:

[0116] Feedback the MAC address of the target message consistent with the MAC address configuration information to the target CPU;

[0117] Feedback the IP address of the target message consistent with the IP address configuration information to the target CPU;

[0118] Feedback the network packet type of the target message consistent with the network packet type configuration information to the target CPU;

[0119] The port number of the target message that is consistent with the port number configuration information is fed back to the target CPU.

[0120] In a possible implementation, the FPGA further includes: a second feedback unit, wherein the second feedback unit is configured to:

[0121] If the MAC address of the target message is inconsistent with the MAC address configuration information, feeding back a MAC address inconsistency result to the target CPU;

[0122] If the IP address of the target message is inconsistent with the IP address configuration information, the IP address inconsistency result is fed back to the target CPU;

[0123] If the network packet type of the target message is inconsistent with the network packet type configuration information, feeding back the network packet type inconsistency result to the target CPU;

[0124] If the port number of the target message is inconsistent with the port number configuration information, the result of the inconsistent port number is fed back to the target CPU.

[0125] In addition, an embodiment of the present application also provides a network data packet processing device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the network data packet processing method described above is implemented.

[0126] In addition, an embodiment of the present application further provides a computer-readable storage medium, in which instructions are stored. When the instructions are executed on a terminal device, the terminal device executes the method for processing network data packets as described above.

[0127] The embodiment of the present application provides a processing device for network data packets, first using the MAC module 201 to obtain the network data packets in the Ethernet switch, and performing CRC check on the network data packets, wherein the network data packets have been converted into digital signals by PHY. If the CRC check passes the filtering module 202, the network data packets are filtered based on the preset configuration information to obtain the target message, wherein the preset configuration information is configured by the target central processing unit CPU. Then the preset configuration information is matched with the target message by the matching module 203 to obtain the matching result. The present application uses FPGA to process network data, which can significantly reduce the burden on the CPU. Traditional firewalls rely on the CPU to execute complex logic, which is prone to cause excessive load in a high-bandwidth environment. FPGA independently performs network traffic inspection and filtering through dedicated hardware, providing hardware acceleration, which is particularly suitable for repeated and parallel tasks, such as CRC check and data packet filtering, thereby improving processing efficiency with higher speed and lower latency.

[0128] The above is a detailed introduction to a method, device, equipment and storage medium for processing network data packets provided by the present application. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

[0129] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0130] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

Claims

1. A method for processing network data messages, characterized in that: Applied to a field programmable gate array (FPGA), the method comprises: Obtaining a network data message in an Ethernet switch; the network data message has been converted into a digital signal through a physical layer PHY; Performing a cyclic redundancy check (CRC) on the network data message; If the CRC check passes, the network data message is filtered based on the preset configuration information to obtain the target message; Matching the preset configuration information with the target message to obtain a matching result; Wherein, the preset configuration information is configured through the target central processing unit CPU.

2. The method according to claim 1, characterized in that The preset configuration information includes: Media Access Control MAC address configuration information, Internet Protocol IP address configuration information, network packet type configuration information, and port number configuration information.

3. The method according to claim 2, characterized in that The matching results include: The MAC address of the target message is consistent with or inconsistent with the MAC address configuration information; The IP address of the target message is consistent with or inconsistent with the IP address configuration information; The network packet type of the target message is consistent with or inconsistent with the network packet type configuration information; The port number of the target message is consistent with or inconsistent with the port number configuration information.

4. The method according to claim 3, characterized in that The method further comprises: Feedback the MAC address of the target message consistent with the MAC address configuration information to the target CPU; Feedback the IP address of the target message consistent with the IP address configuration information to the target CPU; Feedback the network packet type of the target message consistent with the network packet type configuration information to the target CPU; The port number of the target message that is consistent with the port number configuration information is fed back to the target CPU.

5. The method according to claim 3, characterized in that: The method further comprises: If the MAC address of the target message is inconsistent with the MAC address configuration information, feeding back a MAC address inconsistency result to the target CPU; If the IP address of the target message is inconsistent with the IP address configuration information, the IP address inconsistency result is fed back to the target CPU; If the network packet type of the target message is inconsistent with the network packet type configuration information, feeding back the network packet type inconsistency result to the target CPU; If the port number of the target message is inconsistent with the port number configuration information, the result of the inconsistent port number is fed back to the target CPU.

6. An FPGA, characterized in that: The FPGA comprises: The MAC module is used to obtain the network data message in the Ethernet switch and perform CRC check on the network data message; the network data message has been converted into a digital signal through PHY; A filtering module, for filtering the network data message to obtain a target message based on preset configuration information if the CRC check passes; A matching module, used for matching the preset configuration information with the target message to obtain a matching result; Wherein, the preset configuration information is configured through the target central processing unit CPU.

7. The FPGA according to claim 6, characterized in that: The preset configuration information includes: MAC address configuration information, IP address configuration information, network packet type configuration information, and port number configuration information.

8. The FPGA according to claim 6, characterized in that: The matching results include: The MAC address of the target message is consistent with or inconsistent with the MAC address configuration information; The IP address of the target message is consistent with or inconsistent with the IP address configuration information; The network packet type of the target message is consistent with or inconsistent with the network packet type configuration information; The port number of the target message is consistent with or inconsistent with the port number configuration information.

9. A network data message processing device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the method for processing network data messages according to any one of claims 1 to 6 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores instructions, and when the instructions are executed on the terminal device, the terminal device executes the method for processing network data packets according to any one of claims 1 to 6.

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