RapidIO message receiving packet serial number error correction method, device, medium and system

Abstract

The invention discloses a RapidIO message receiving packet serial number error correction method, device, medium and system, and belongs to the field of aviation integrated communication, and the method comprises the following steps: a sending node 1 to a sending node N are connected with a RapidIO exchange chip through a RapidIO bus; and the FPGA receiving node is connected with the RapidIO exchange chip through the RapidIO bus. An FPGA receiving node receives data from a RapidIO exchange chip through a RapidIO bus, and through a two-stage packet level FIFO receiving processing mode, the problem that after-stage processing enters cyclic deadlock due to the fact that RapidIO information receives continuous error packet serial numbers is solved. The invention provides a solution which is simple in software implementation and can improve the fault tolerance of a receiving end to a message receiving error packet sequence number.

Description

Technical Field

[0001] The present invention relates to the field of aviation integrated communications, and more specifically, to a RapidIO message receiving packet sequence number error correction method, device, medium and system. Background Art

[0002] With the rapid development of aviation integrated technology, the bandwidth requirements of both parties in communication are getting higher and higher. The traditional parallel bus that increases bandwidth by increasing the working clock is no longer applicable. The high-speed serial RapidIO bus based on the packet switching architecture has gradually become the mainstream bus for communication between multiple heterogeneous chips in the aviation integrated system with its high bandwidth, low latency, and high reliability. It provides a good high-speed interconnection for the mainstream hardware configuration of the FPGA+DSP+PPC multi-heterogeneous chip architecture combination.

[0003] Based on the high reliability of RapidIO protocol message communication, short data transmission and instruction transmission in existing aviation integrated systems mostly adopt message data communication. The length of RapidIO message data packets sent and received is between 8 bytes and 4096 bytes, supporting up to 16 RapidIO data packets at a time. For the receiving end of FPGA node type, due to the limited length of RapidIO message data packets, it is generally received first, the data is stored in the FPGA local cache RAM or FIFO, and the current received message data packet length is given, and then the subsequent stage is notified for processing; and when the subsequent stage reads the previous stage cache RAM or FIFO, it determines how much data to read based on the length of the currently received message data packet. Therefore, the current received message data packet length calculated by the previous stage is very important for the subsequent stage processing. When the receiving end receives the wrong packet sequence number, a small number of packet sequence number errors will result in an incorrect length, and the subsequent stage cannot correctly parse the current message packet; a large number of packet sequence number errors is likely to cause a cache RAM or FIFO overflow. Once a cache overflow occurs, errors will occur continuously during the subsequent stage processing, and the cycle will be deadlocked. For an aviation integrated system, reliability is crucial, and the above-mentioned cycle deadlock cannot be tolerated. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a RapidIO message receiving packet sequence number correction method, device, medium and system. Without increasing the system hardware cost, the present invention solves the problem of continuous error packet sequence numbers appearing at the receiving end, causing the receiving data buffer to overflow, and cyclic deadlock in the post-processing by software error correction, thereby effectively improving the fault tolerance and reliability of the system.

[0005] The object of the present invention is achieved through the following solutions:

[0006] A RapidIO message receiving packet sequence number error correction system, comprising:

[0007] Transmitting nodes 1 to N, a RapidIO switching chip and an FPGA receiving node; the transmitting nodes 1 to N are interconnected with the RapidIO switching chip through a RapidIO bus; the FPGA receiving node is interconnected with the RapidIO switching chip through a RapidIO bus.

[0008] A RapidIO message receiving packet sequence number error correction method, based on the RapidIO message receiving packet sequence number error correction system as described above, comprises the following steps:

[0009] The FPGA receiving node receives data from the RapidIO switching chip through the RapidIO bus, and under the control of the RapidIO message receiving processing module, separates the RapidIO message packets, writes the RapidIO message data into the first-level data Data_FIFO, and writes the calculated data length and message receiving error flag into the first-level length Len_FIFO at the same time;

[0010] Also, under the control of the RapidIO message receiving processing module, when the first-level length Len_FIFO is not empty, data of the corresponding length of the first-level Data_FIFO is read according to the read first-level Len_FIFO value. If the message receiving error flag is invalid, all data of the current message packet from the first-level Data_FIFO is written into the second-level data Data_FIFO, and then the data packet length is written into the second-level length Len_FIFO. If the message packet receiving error flag is valid, all data of the current message packet is read out from the first-level Data_FIFO and discarded.

[0011] Furthermore, the message reception error flag being invalid specifically means that the flag value is 0.

[0012] Furthermore, the message packet reception error flag is valid when the flag value is 1.

[0013] A RapidIO message receiving packet sequence number error correction method, based on the RapidIO message receiving packet sequence number error correction system as described above, comprises the following steps:

[0014] The first-level processing flow of RapidIO message packet reception enters the initial state after the power-on reset is completed; monitor whether the received RapidIO data packet is the first packet of the message, otherwise continue to monitor, and if so, enter the process of judging whether the total number of current message packets is only one packet;

[0015] In the judgment process of whether the total number of current message packets is only one, if yes, the message packet length and message reception error flag are written into the first-level length FIFO state, and then the message reception error flag is cleared. After the message reception error flag is cleared, the initial state is returned;

[0016] In the current message total packet number judgment process, whether there is only one packet, otherwise, it is transferred to the current message packet sequence number whether it has been repeated. In the current message packet sequence number whether it has been repeated, if it is, it is transferred to the message reception error flag setting state, and then transferred to the message packet length and the message reception error flag writing first-level length FIFO state, and then transferred to the message reception error flag clearing state. After the message reception error flag is cleared, it returns to the initial state;

[0017] In the process of determining whether the sequence number of the current message packet has been repeated, if not, it is transferred to the process of determining whether the current message packet is the last packet; in the process of determining whether the current message packet is the last packet, if yes, it is transferred to the state of writing the message packet length and the message receiving error flag into the first-level length FIFO, and then enters the state of clearing the message receiving error flag, and after executing the clearing of the message receiving error flag, it returns to the initial state;

[0018] In the process of determining whether the current message packet is the last packet, if not, it is transferred to the process of determining whether the total length of the received message is greater than or equal to 4096 bytes; in the process of determining whether the total length of the received message is greater than or equal to 4096 bytes, if it is, it enters the state of setting the message packet reception error flag, and then enters the state of writing the message packet length and the message reception error flag into the first-level length FIFO, and then enters the state of clearing the message reception error flag, and after executing the clearing of the message reception error flag, it returns to the initial state;

[0019] In the process of determining whether the total length of the received message is greater than or equal to 4096 bytes, if not, the process of determining whether the current message packet sequence number has appeared repeatedly is entered.

[0020] Furthermore, the RapidIO message packet receiving second-level processing flow enters the initial state after the power-on reset is completed. Monitor whether there is data in the first-level length FIFO. If so, enter the state of reading the value of the first-level length FIFO. After reading the value of the first-level length FIFO, enter the process of determining whether the message error flag taken out of the length FIFO is valid. In the process of determining whether the message error flag taken out of the length FIFO is valid, if yes, enter the process of reading the first-level data FIFO according to the length of the data taken out of the length FIFO, and perform the discard processing state. Then enter the process of determining whether the current message packet in the first-level data FIFO has been read. If yes, return to the initial state.

[0021] In the process of determining whether the error mark of the message taken out of the length FIFO is valid, if not, the process proceeds to read the first-level data FIFO according to the length of the data taken out of the length FIFO and writes it into the second-level data FIFO state. Then, the process proceeds to determine whether the current message packet in the first-level data FIFO has been read and written into the second-level data FIFO. If yes, the process proceeds to write the length of the data taken out of the first-level length FIFO into the second-level length FIFO state. After writing the length of the data taken out of the first-level length FIFO into the second-level length FIFO state, the process returns to the initial state.

[0022] A RapidIO message receiving packet sequence number error correction method, based on the RapidIO message receiving packet sequence number error correction system as described above, comprises the following steps:

[0023] The second-level processing flow of RapidIO message packet reception enters the initial state after the power-on reset is completed; monitor whether there is data in the first-level length FIFO, otherwise continue to monitor; if yes, enter the state of reading the value of the first-level length FIFO; after reading the value of the first-level length FIFO, enter the process of determining whether the error mark of the message taken out of the length FIFO is valid; in the process of determining whether the error mark of the message taken out of the length FIFO is valid, if yes, enter the process of reading the first-level data FIFO according to the length of the data taken out of the length FIFO, and perform the discard processing state; then enter the process of determining whether the current message packet in the first-level data FIFO has been read, if yes, return to the initial state;

[0024] In the process of determining whether the error flag of the message taken out of the length FIFO is valid, if not, proceed to read the first-level data FIFO according to the data length taken out of the length FIFO and write it into the second-level data FIFO state; then proceed to determine whether the current message packet in the first-level data FIFO has been read and written into the second-level data FIFO. If so, proceed to write the data length taken out of the first-level length FIFO into the second-level length FIFO state. After completing writing the data length taken out of the first-level length FIFO into the second-level length FIFO state, return to the initial state.

[0025] A RapidIO message receiving packet sequence number error correction device comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, any of the above methods is executed.

[0026] A computer-readable storage medium stores a computer program, wherein the computer program executes any of the above methods when loaded by a processor.

[0027] The beneficial effects of the present invention include:

[0028] (1) The scheme of the present invention can improve the fault tolerance of the message receiving and processing at the receiving end and improve the reliability of the system. By adopting a two-level packet-level FIFO receiving and processing method, the packet sequence numbers of the continuously received message data are detected. When the packet sequence numbers of the same message data are received repeatedly, the message packet reception error flag is set to be valid; in the subsequent processing, the current erroneous message data packet will be taken out from the first-level data FIFO and discarded, and will not be written into the second-level FIFO. In the case of continuous reception of erroneous packet sequence numbers, it is ensured that the first-level data FIFO will not overflow, and the subsequent processing will not enter a loop deadlock.

[0029] (2) The present invention can improve the data processing capability of the subsequent stage and improve the performance of the system. By adopting a two-level packet-level FIFO receiving and processing method, when a message data packet sequence number error occurs at the receiving end, on the one hand, the data can be discarded before being written into the second-level packet-level FIFO; on the other hand, it does not affect the continuous reception of the message data packet at the first stage. The two-level FIFO adopts a pipeline operation to improve the overall data processing capability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0031] Figure 1 A schematic diagram of a RapidIO message receiving packet sequence number correction method of the present invention;

[0032] Figure 2 for Figure 1 Implement the schematic diagram;

[0033] Figure 3 for Figure 2 RapidIO message packet receiving first level processing flow chart;

[0034] Figure 4 for Figure 2 RapidIO message packet receiving second-level processing flow chart. DETAILED DESCRIPTION

[0035] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or expanded or replaced in any manner.

[0036] The specific implementation process of the present invention is as follows:

[0037] like Figure 1 As shown, the present invention provides a RapidIO message receiving packet sequence number correction method, comprising: sending node 1 to sending node N + RapidIO switching chip + FPGA receiving node. Sending node 1 to sending node N are interconnected with the RapidIO switching chip through a RapidIO bus; the FPGA receiving node is interconnected with the RapidIO switching chip through a RapidIO bus.

[0038] like Figure 2 As shown, the FPGA receiving node receives data from the RapidIO switching chip through the RapidIO bus. Under the control of the RapidIO message receiving processing module, on the one hand, the RapidIO message packet is separated, the data in the RapidIO message packet is written into the first-level data Data_FIFO, and the calculated data packet length msg_data_len_in and the message receiving error flag msg_packet_err_in are written into the first-level length Len_FIFO together; on the other hand, when the first-level length Len_FIFO is not empty, the data of the corresponding length of the first-level Data_FIFO is read according to the read first-level Len_FIFO value. If the message receiving error flag msg_packet_err_out output by the first-level Len_FIFO is invalid (the value is 0), all the data of the current message packet from the first-level Data_FIFO is written into the second-level data Data_FIFO, and then the data packet length is written into the second-level length Len_FIFO. If the message receiving error flag msg_packet_err_out output by the first-level Len_FIFO is valid (the value is 1), all the data of the current message packet are discarded.

[0039] like Figure 3 As shown, the first-level processing flow of RapidIO message packet reception enters the initial state after power-on reset is completed. It monitors whether the received RapidIO data packet is the first message packet, and if so, it enters the process of judging whether the total number of current message packets is only one packet.

[0040] In the judgment process of whether the total number of current message packets is only one, if yes, the message packet length and message reception error flag are written into the first-level length FIFO state, and then the message reception error flag is cleared. After the message reception error flag is cleared, the state is returned to the initial state.

[0041] Figure 3In the process of judging whether the total number of current message packets is only one, otherwise, it will enter the process of judging whether the current message packet sequence number has been repeated. In the process of judging whether the current message packet sequence number has been repeated, if it is, it will enter the state of setting the message reception error flag, and then enter the state of writing the message packet length and the message reception error flag into the first-level length FIFO, and then enter the state of clearing the message reception error flag. After clearing the message reception error flag, it will return to the initial state.

[0042] Figure 3 In the determination process of whether the current message packet sequence number has been repeated, if not, it will enter the determination process of whether the current message packet is the last packet. In the determination process of whether the current message packet is the last packet, if yes, it will enter the state of writing the message packet length and the message reception error flag into the first-level length FIFO, and then enter the state of clearing the message reception error flag. After clearing the message reception error flag, it will return to the initial state.

[0043] Figure 3 In the process of determining whether the current message packet is the last packet, if not, it will enter the process of determining whether the total length of the received message is greater than or equal to 4096 bytes. In the process of determining whether the total length of the received message is greater than or equal to 4096 bytes, if it is, it will enter the state of setting the message packet reception error flag, and then enter the state of writing the message packet length and the message reception error flag into the first-level length FIFO, and then enter the state of clearing the message reception error flag. After executing the clearing of the message reception error flag, it will return to the initial state.

[0044] Figure 3 In the process of determining whether the total length of the received message is greater than or equal to 4096 bytes, if not, the process of determining whether the current message packet sequence number has appeared repeatedly is entered, and the above process is repeated.

[0045] like Figure 4 As shown, the RapidIO message packet receiving second-level processing flow enters the initial state after the power-on reset is completed. Monitor whether there is data in the first-level length FIFO. If yes, enter the state of reading the value of the first-level length FIFO. After reading the value of the first-level length FIFO, enter the process of determining whether the message error mark taken out of the length FIFO is valid. In the process of determining whether the message error mark taken out of the length FIFO is valid, if yes, enter the process of reading the first-level data FIFO according to the length of the data taken out of the length FIFO, and perform the discard processing state. Then enter the process of determining whether the current message packet in the first-level data FIFO has been read. If yes, return to the initial state.

[0046] Figure 4In the process of determining whether the error mark of the message taken out of the length FIFO is valid, otherwise, it is transferred to the state of reading the first-level data FIFO according to the length of the data taken out of the length FIFO and writing it into the second-level data FIFO. Then, it is transferred to the process of determining whether the current message packet in the first-level data FIFO has been read and written into the second-level data FIFO. If it is, it is transferred to the state of writing the length of the data taken out of the first-level length FIFO into the state of the second-level length FIFO. After the execution of writing the length of the data taken out of the first-level length FIFO into the state of the second-level length FIFO, it returns to the initial state.

[0047] It should be noted that within the scope of protection defined in the claims of the present invention, the following embodiments can be combined and / or expanded or replaced in any logical way from the above specific implementation methods, such as disclosed technical principles, disclosed technical features or implicitly disclosed technical features.

[0048] Example 1

[0049] A RapidIO message receiving packet sequence number error correction system, comprising:

[0050] Transmitting nodes 1 to N, a RapidIO switching chip and an FPGA receiving node; the transmitting nodes 1 to N are interconnected with the RapidIO switching chip through a RapidIO bus; the FPGA receiving node is interconnected with the RapidIO switching chip through a RapidIO bus.

[0051] Example 2

[0052] A RapidIO message receiving packet sequence number error correction method, based on the RapidIO message receiving packet sequence number error correction system described in Example 1, comprises the following steps:

[0053] The FPGA receiving node receives data from the RapidIO switching chip through the RapidIO bus, and under the control of the RapidIO message receiving processing module, separates the RapidIO message packets, writes the RapidIO message data into the first-level data Data_FIFO, and writes the calculated data length and message receiving error flag into the first-level length Len_FIFO at the same time;

[0054] Also, under the control of the RapidIO message receiving processing module, when the first-level length Len_FIFO is not empty, data of the corresponding length of the first-level Data_FIFO is read according to the read first-level Len_FIFO value. If the message receiving error flag is invalid, all data of the current message packet from the first-level Data_FIFO is written into the second-level data Data_FIFO, and then the data packet length is written into the second-level length Len_FIFO. If the message packet receiving error flag is valid, all data of the current message packet is read out from the first-level Data_FIFO and discarded.

[0055] Example 3

[0056] Based on Example 2, the message reception error flag is invalid, specifically the flag value is 0.

[0057] Example 4

[0058] Based on Example 2, the message packet reception error flag is valid when the flag value is 1.

[0059] Example 5

[0060] A RapidIO message receiving packet sequence number error correction method, based on the RapidIO message receiving packet sequence number error correction system described in Example 1, comprises the following steps:

[0061] The first-level processing flow of RapidIO message packet reception enters the initial state after the power-on reset is completed; monitor whether the received RapidIO data packet is the first packet of the message, otherwise continue to monitor, and if so, enter the process of judging whether the total number of current message packets is only one packet;

[0062] In the judgment process of whether the total number of current message packets is only one, if yes, the message packet length and message reception error flag are written into the first-level length FIFO state, and then the message reception error flag is cleared. After the message reception error flag is cleared, the initial state is returned;

[0063] In the current message total packet number judgment process, whether there is only one packet, otherwise, it is transferred to the current message packet sequence number whether it has been repeated. In the current message packet sequence number whether it has been repeated, if it is, it is transferred to the message reception error flag setting state, and then transferred to the message packet length and the message reception error flag writing first-level length FIFO state, and then transferred to the message reception error flag clearing state. After the message reception error flag is cleared, it returns to the initial state;

[0064] In the process of determining whether the sequence number of the current message packet has been repeated, if not, it is transferred to the process of determining whether the current message packet is the last packet; in the process of determining whether the current message packet is the last packet, if yes, it is transferred to the state of writing the message packet length and the message receiving error flag into the first-level length FIFO, and then enters the state of clearing the message receiving error flag, and after executing the clearing of the message receiving error flag, it returns to the initial state;

[0065] In the process of determining whether the current message packet is the last packet, if not, it is transferred to the process of determining whether the total length of the received message is greater than or equal to 4096 bytes; in the process of determining whether the total length of the received message is greater than or equal to 4096 bytes, if it is, it enters the state of setting the message packet reception error flag, and then enters the state of writing the message packet length and the message reception error flag into the first-level length FIFO, and then enters the state of clearing the message reception error flag, and after executing the clearing of the message reception error flag, it returns to the initial state;

[0066] In the process of determining whether the total length of the received message is greater than or equal to 4096 bytes, if not, the process of determining whether the current message packet sequence number has appeared repeatedly is entered.

[0067] Example 6

[0068] On the basis of Example 2, the RapidIO message packet receiving second-level processing flow enters the initial state after the power-on reset is completed. Monitor whether there is data in the first-level length FIFO, and if so, enter the state of reading the value of the first-level length FIFO. After reading the value of the first-level length FIFO, enter the process of determining whether the message error identifier taken out of the length FIFO is valid. In the process of determining whether the message error identifier taken out of the length FIFO is valid, if yes, enter the process of reading the first-level data FIFO according to the length of the data taken out of the length FIFO, and perform the discard processing state. Then enter the process of determining whether the current message packet in the first-level data FIFO has been read, and if yes, return to the initial state.

[0069] In the process of determining whether the error mark of the message taken out of the length FIFO is valid, if not, the process proceeds to read the first-level data FIFO according to the length of the data taken out of the length FIFO and writes it into the second-level data FIFO state. Then, the process proceeds to determine whether the current message packet in the first-level data FIFO has been read and written into the second-level data FIFO. If yes, the process proceeds to write the length of the data taken out of the first-level length FIFO into the second-level length FIFO state. After writing the length of the data taken out of the first-level length FIFO into the second-level length FIFO state, the process returns to the initial state.

[0070] Example 7

[0071] A RapidIO message receiving packet sequence number error correction method, based on the RapidIO message receiving packet sequence number error correction system described in Example 1, comprises the following steps:

[0072] The second-level processing flow of RapidIO message packet reception enters the initial state after the power-on reset is completed; monitor whether there is data in the first-level length FIFO, otherwise continue to monitor; if yes, enter the state of reading the value of the first-level length FIFO; after reading the value of the first-level length FIFO, enter the process of determining whether the error mark of the message taken out of the length FIFO is valid; in the process of determining whether the error mark of the message taken out of the length FIFO is valid, if yes, enter the process of reading the first-level data FIFO according to the length of the data taken out of the length FIFO, and perform the discard processing state; then enter the process of determining whether the current message packet in the first-level data FIFO has been read, if yes, return to the initial state;

[0073] In the process of determining whether the error flag of the message taken out of the length FIFO is valid, if not, proceed to read the first-level data FIFO according to the data length taken out of the length FIFO and write it into the second-level data FIFO state; then proceed to determine whether the current message packet in the first-level data FIFO has been read and written into the second-level data FIFO. If so, proceed to write the data length taken out of the first-level length FIFO into the second-level length FIFO state. After completing writing the data length taken out of the first-level length FIFO into the second-level length FIFO state, return to the initial state.

[0074] Example 8

[0075] A RapidIO message receiving packet sequence number error correction device comprises a processor and a memory, wherein the memory stores a computer program, and when the computer program is loaded by the processor, the method described in any one of Embodiments 1 to 7 is executed.

[0076] Example 9

[0077] A computer-readable storage medium stores a computer program, and when the computer program is loaded by a processor, the method described in any one of Embodiments 1 to 7 is executed.

[0078] The units involved in the embodiments of the present invention may be implemented by software or hardware, and the units described may also be arranged in a processor. The names of these units do not, in some cases, limit the units themselves.

[0079] According to one aspect of an embodiment of the present invention, a computer program product or a computer program is provided, the computer program product or the computer program includes a computer instruction, and the computer instruction is stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the method provided in the above various optional implementations.

[0080] As another aspect, an embodiment of the present invention further provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements the method described in the above embodiment.

Claims

1. A RapidIO message receiving packet sequence number error correction system, characterized in that: include: Transmitting nodes 1 to N, a RapidIO switching chip and an FPGA receiving node; the transmitting nodes 1 to N are interconnected with the RapidIO switching chip through a RapidIO bus; the FPGA receiving node is interconnected with the RapidIO switching chip through a RapidIO bus.

2. A RapidIO message receiving packet sequence number correction method, characterized in that: The RapidIO message receiving packet sequence number correction system according to claim 1 comprises the following steps: The FPGA receiving node receives data from the RapidIO switching chip through the RapidIO bus, and under the control of the RapidIO message receiving processing module, separates the RapidIO message packets, writes the RapidIO message data into the first-level data Data_FIFO, and writes the calculated data length and message receiving error flag into the first-level length Len_FIFO at the same time; Also, under the control of the RapidIO message receiving processing module, when the first-level length Len_FIFO is not empty, data of the corresponding length of the first-level Data_FIFO is read according to the read first-level Len_FIFO value. If the message receiving error flag is invalid, all data of the current message packet from the first-level Data_FIFO is written into the second-level data Data_FIFO, and then the data packet length is written into the second-level length Len_FIFO. If the message packet receiving error flag is valid, all data of the current message packet is read out from the first-level Data_FIFO and discarded.

3. The RapidIO message receiving packet sequence number correction method according to claim 2, characterized in that: The message reception error flag is invalid when the flag value is 0.

4. The RapidIO message receiving packet sequence number correction method according to claim 2, characterized in that: The message packet reception error flag is valid when the flag value is 1.

5. A RapidIO message receiving packet sequence number correction method, characterized in that: The RapidIO message receiving packet sequence number correction system according to claim 1 comprises the following steps: The first-level processing flow of RapidIO message packet reception enters the initial state after the power-on reset is completed; monitor whether the received RapidIO data packet is the first packet of the message, otherwise continue to monitor, and if so, enter the process of judging whether the total number of current message packets is only one packet; In the judgment process of whether the total number of current message packets is only one, if yes, the message packet length and message reception error flag are written into the first-level length FIFO state, and then the message reception error flag is cleared. After the message reception error flag is cleared, the initial state is returned; In the process of judging whether the total number of current message packets is only one, otherwise, it goes to the process of judging whether the sequence number of the current message packet has appeared repeatedly; In the process of determining whether the current message packet sequence number has been repeated, if yes, it will enter the state of setting the message reception error flag, then enter the state of writing the message packet length and the message reception error flag into the first-level length FIFO, and then enter the state of clearing the message reception error flag. After clearing the message reception error flag, it will return to the initial state; In the process of determining whether the sequence number of the current message packet has been repeated, if not, it is transferred to the process of determining whether the current message packet is the last packet; in the process of determining whether the current message packet is the last packet, if yes, it is transferred to the state of writing the message packet length and the message receiving error flag into the first-level length FIFO, and then enters the state of clearing the message receiving error flag, and after executing the clearing of the message receiving error flag, it returns to the initial state; In the process of determining whether the current message packet is the last packet, if not, it proceeds to the process of determining whether the total length of the received message is greater than or equal to 4096 bytes; In the process of determining whether the total length of the received message is greater than or equal to 4096 bytes, if yes, the state of setting the message packet reception error flag is entered, and then the state of writing the message packet length and the message reception error flag into the first-level length FIFO is entered, and then the state of clearing the message reception error flag is entered. After the clearing of the message reception error flag is executed, the initial state is returned; In the process of determining whether the total length of the received message is greater than or equal to 4096 bytes, if not, the process of determining whether the current message packet sequence number has appeared repeatedly is entered.

6. The RapidIO message receiving packet sequence number error correction method according to claim 2, characterized in that: The second-level processing flow of RapidIO message packet reception enters the initial state after the power-on reset is completed; monitors whether there is data in the first-level length FIFO, and if so, enters the state of reading the value of the first-level length FIFO; after reading the value of the first-level length FIFO, enters the process of determining whether the error mark of the message taken out of the length FIFO is valid; In the process of determining whether the message error flag taken out by the length FIFO is valid, if it is, it is transferred to the first-level data FIFO for reading according to the data length taken out by the length FIFO, and the discard processing state is performed; Then, the process of judging whether the current message packet in the first-level data FIFO has been read is entered, and if so, the process returns to the initial state; In the process of determining whether the message error flag taken out from the length FIFO is valid, if not, the process proceeds to read the first-level data FIFO according to the data length taken out from the length FIFO, and write the second-level data FIFO status; Then, the process starts to determine whether the current message packet in the first-level data FIFO has been read and written into the second-level data FIFO. If so, the process starts to write the data length taken out of the first-level length FIFO into the second-level length FIFO state. After completing the process of writing the data length taken out of the first-level length FIFO into the second-level length FIFO state, the process returns to the initial state.

7. A RapidIO message receiving packet sequence number error correction method, characterized in that: The RapidIO message receiving packet sequence number correction system according to claim 1 comprises the following steps: The second-level processing flow of RapidIO message packet reception enters the initial state after the power-on reset is completed; monitors whether there is data in the first-level length FIFO, otherwise continues to monitor; if yes, enters the state of reading the value of the first-level length FIFO; after reading the value of the first-level length FIFO, enters the process of determining whether the message error flag taken out of the length FIFO is valid; In the process of determining whether the message error flag taken out by the length FIFO is valid, if it is, it is transferred to the first-level data FIFO for reading according to the data length taken out by the length FIFO, and the discard processing state is performed; Then, the process of judging whether the current message packet in the first-level data FIFO has been read is entered, and if so, the process returns to the initial state; In the process of determining whether the message error flag taken out from the length FIFO is valid, if not, the process proceeds to read the first-level data FIFO according to the data length taken out from the length FIFO, and write the second-level data FIFO status; Then, the process starts to determine whether the current message packet in the first-level data FIFO has been read and written into the second-level data FIFO. If so, the process starts to write the data length taken out of the first-level length FIFO into the second-level length FIFO state. After completing the process of writing the data length taken out of the first-level length FIFO into the second-level length FIFO state, the process returns to the initial state.

8. A RapidIO message receiving packet sequence number error correction device, characterized in that: The method comprises a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is loaded by the processor, the method according to any one of claims 1 to 7 is executed.

9. A computer-readable storage medium, characterized in that: A computer program is stored in a readable storage medium, and when the computer program is loaded by a processor, the method according to any one of claims 1 to 7 is executed.

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