Transistor preparation method, transistor array and electronic equipment
By using a combination of low-dielectric materials and air gaps in a vertical gate all-around transistor array, the problem of capacitance effects between word lines was solved, transistor performance was improved, and the fabrication process was simplified.
Patent Information
- Application Number
- CN202310827613.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-06
- Publication Date
- 2025-01-10
AI Technical Summary
In a vertical gate all-around transistor array, the isolation medium between word lines affects the capacitance, leading to an increase in the resistance-capacitance delay of the transistor array circuit.
By using a combination of low-dielectric materials and air gaps during the transistor fabrication process, the parasitic capacitance between word lines is reduced. The specific steps include stacking multiple layers on a silicon substrate, etching to form bit lines and word lines, and depositing low-dielectric materials and forming air gaps between word lines to isolate gate materials.
This reduces parasitic capacitance between word lines, improves transistor device performance, and reduces fabrication complexity.
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Figure CN119300383A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a method for manufacturing a transistor, a transistor array, and an electronic device. Background Art
[0002] The vertical gate-all-around (VGAA) transistor is a new type of semiconductor device. Compared with the planar GAA transistor, the vertical GAA transistor (VGAA) has a small projected area and an unlimited channel length.
[0003] In the related art, in a VGAA transistor array, the isolation medium between word lines affects the capacitance between word lines. Generally, the higher the dielectric constant k value of the insulating medium, the higher the parasitic capacitance C between word lines, which leads to a greater resistance and capacitance delay (RC delay) of the transistor array circuit. Summary of the invention
[0004] The embodiments of the present application provide a method for manufacturing a transistor, a transistor array, and an electronic device, which can reduce the influence of capacitance between word lines. The technical solution is as follows:
[0005] In one aspect, a method for preparing a transistor is provided, the method comprising:
[0006] stacking a first silicon film layer, a germanium silicon film layer, and a second silicon film layer in sequence on a silicon substrate, wherein the first silicon film layer is adjacent to the silicon substrate;
[0007] Etching a first etched groove along the bit line direction on the silicon substrate, the first silicon film layer, the germanium silicon film layer and the second silicon film layer, filling the first etched groove with metal material and annealing to generate a bit line;
[0008] Etching a second etched groove along the word line direction on the second silicon film layer and the silicon germanium film layer, and after generating a channel based on the silicon germanium film layer, filling a gate material in the second etched groove along the word line direction to generate a word line;
[0009] A low dielectric material is deposited in the first etching groove, the second etching groove and on the second silicon film layer, and an air gap is formed by etching and depositing a silicon dielectric material on the top to isolate the gate material and obtain a vertical gate all-around transistor.
[0010] In an optional embodiment, a low dielectric material is deposited in the first etched groove and the second etched groove and on the second silicon film layer, and an air gap is formed by etching and depositing a silicon dielectric material on the top to isolate the gate material and the second silicon film layer to obtain a vertical gate all-around transistor, comprising:
[0011] Depositing the low dielectric material in the first etching groove and the second etching groove and on the second silicon film layer;
[0012] Etching the low dielectric material on the surfaces of the first silicon film layer and the second silicon film layer, and etching a portion of the low dielectric material between the gate materials;
[0013] A silicon dielectric material is deposited on the second silicon film layer to obtain the vertical gate all-around transistor.
[0014] In an optional embodiment, depositing a silicon dielectric material on the second silicon film layer to obtain the vertical gate all-around transistor includes:
[0015] Depositing a metal material on the second silicon film layer so as to contact the second silicon film layer;
[0016] The silicon dielectric material is deposited in the first etching groove and the second etching groove to obtain the vertical gate all-around transistor.
[0017] In an optional embodiment, etching the silicon substrate, the first silicon film layer, the silicon germanium film layer and the second silicon film layer along the bit line direction to form a first etched groove includes:
[0018] forming a plurality of columns of first mask material on the second silicon film layer along the bit line direction;
[0019] Regions of the silicon substrate, the first silicon film layer, the silicon germanium film layer, and the second silicon film layer that are not covered by the first mask material are etched to form first etching grooves along the direction of the bit lines.
[0020] In an optional embodiment, the step of filling the first etched groove with a metal material and annealing to generate a bit line includes:
[0021] Filling the first etching groove with the silicon dielectric material to obtain a first height, wherein the first height is less than a depth of the first etching groove in the silicon substrate;
[0022] The metal material is filled on the silicon dielectric material and annealed to generate a bit line, wherein adjacent bit lines are isolated by the silicon dielectric material.
[0023] In an optional embodiment, etching the second silicon film layer and the silicon germanium film layer along the word line direction to form a second etched groove includes:
[0024] forming a plurality of columns of second mask material on the second silicon film layer along the word line direction;
[0025] The regions of the second silicon film layer and the silicon germanium film layer that are not covered by the second mask material are etched to form second etching grooves along the direction of the word lines.
[0026] In an optional embodiment, forming a plurality of columns of second mask material on the second silicon film layer along the word line direction includes:
[0027] Filling the first etching groove with the silicon dielectric material to obtain a second height, wherein an upper plane of the silicon dielectric material at the second height and an upper plane of the first silicon film layer meet a plane distance requirement;
[0028] The first etching groove is filled with an oxide material, and a plurality of columns of a second mask material are formed along the word line direction on the second silicon film layer filled with the oxide material.
[0029] In an optional embodiment, the second mask material includes a mandrel material and a sidewall material distributed on both sides of the mandrel material;
[0030] The step of generating a channel based on the germanium silicon film layer comprises:
[0031] On the silicon pillars obtained by etching the first etching grooves and the second etching grooves, performing lateral etching of a first thickness on the surface of the germanium silicon film layer;
[0032] generating an epitaxial silicon material with a second thickness on the etched surface of the germanium silicon film layer, wherein the second thickness is less than the first thickness;
[0033] Etching the portion covered by the mandrel material in the second silicon film layer and the silicon germanium film layer to split the silicon column into at least two sub-silicon columns;
[0034] The silicon germanium film layer in the at least two silicon sub-pillars is removed and filled with oxide material to obtain the oxide material surrounding the epitaxial silicon material, and the epitaxial silicon material forms the channel of the transistor.
[0035] On the other hand, a transistor array is provided, wherein the transistor array includes a plurality of transistor units arranged in an array;
[0036] The transistor unit comprises a first source / drain, a channel, a second source / drain, and a normally closed contact which are vertically distributed in sequence, and the channel of the transistor unit is surrounded by a gate material;
[0037] The first sources / drains of the plurality of first transistor cells in the first queue are connected by coupling to a buried bit line;
[0038] The gate materials of the plurality of second transistor units in the second queue are connected, so that the word line is coupled to the plurality of second transistor units, wherein the first queue is a queue along the first array direction, and the second queue is a queue along the second array direction;
[0039] The surfaces of the transistor units between the plurality of the second queues are covered with a low dielectric material, the tops of the plurality of the second queues are covered with a silicon dielectric material, and air gaps are formed between the low dielectric materials.
[0040] On the other hand, an electronic device is provided, wherein the electronic device comprises a logic device, and the logic device comprises the transistor array as described in the above embodiment.
[0041] In an optional embodiment, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.
[0042] The beneficial effects brought by the technical solution provided in the embodiments of the present application include at least:
[0043] After laying out the transistor's bit line, word line, source / drain and ring gate, a layer of protective material is deposited between the ring gate and the top source / drain to prevent oxidation. Finally, a high deposition rate, low step coverage dielectric is used to form an air gap between the word lines. This reduces the parasitic capacitance between the word lines, improves the device performance of the VGAA transistor, and reduces the complexity of preparation. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0045] Figure 1 is a schematic diagram of a vertical gate all-around transistor structure provided by one or more exemplary embodiments of the present application;
[0046] Figure 2 is a flow chart of a method for preparing a VGAA transistor provided by an exemplary embodiment of the present application;
[0047] Figure 3 is based on Figure 2 A schematic diagram of a process preparation flow on a silicon substrate provided by the illustrated embodiment;
[0048] Figure 4 is based on Figure 2 A schematic diagram of a process flow for forming a first mask material provided in the illustrated embodiment;
[0049] Figure 5 is based on Figure 2 A schematic diagram of a process flow for preparing a first etching groove provided in the illustrated embodiment;
[0050] Figure 6 is based on Figure 2 A schematic diagram of a process flow for preparing a bit line provided by an embodiment is shown;
[0051] Figure 7 is based on Figure 2 A schematic diagram of a process flow for forming a second mask material provided in the illustrated embodiment;
[0052] Figure 8 is based on Figure 2 A schematic diagram of a process flow for forming a second mask material provided in the illustrated embodiment;
[0053] Fig. 9 is a flow chart of a method for preparing a VGAA transistor provided by another exemplary embodiment of the present application;
[0054] Fig.10 is based on Fig. 9 The illustrated embodiment provides a schematic diagram of a process flow for lateral etching of a germanium silicon film layer;
[0055] Fig.11 is based on Fig. 9 A schematic diagram of a process flow for selectively epitaxially growing epitaxial silicon material provided by the illustrated embodiment;
[0056] Fig.12 is based on Fig. 9 A schematic diagram of a process flow for preparing mandrel etching provided by the illustrated embodiment;
[0057] Fig.13 is based on Fig. 9 A schematic diagram of the process flow of oxide filling provided by the illustrated embodiment;
[0058] Fig.14 is based on Fig. 9 A schematic diagram of a process flow for preparing a word line provided by an embodiment is shown;
[0059] Fig.15 is based on Fig. 9 The schematic diagram of the process flow of low dielectric material deposition provided by the illustrated embodiment;
[0060] Fig.16 is a schematic diagram of a stacking structure provided by one or more exemplary embodiments of the present application;
[0061] Fig.17is a schematic diagram of a stacking structure provided by one or more exemplary embodiments of the present application;
[0062] Fig.18 is a schematic diagram of a process for forming a stacked structure provided by one or more exemplary embodiments of the present application;
[0063] Fig.19 is a schematic diagram of a formation process of a stacking structure provided by one or more exemplary embodiments of the present application;
[0064] Fig. 20 is a schematic diagram of a formation process of a stacking structure provided by one or more exemplary embodiments of the present application;
[0065] Fig.21 It is a schematic diagram of a forming process of a stacking structure provided by one or more other exemplary embodiments of the present application.
[0066] Silicon substrate-00;
[0067] A first silicon film layer-11, a germanium silicon film layer-12, and a second silicon film layer-13;
[0068] Metal material - 20, gate material - 30, low dielectric material - 40;
[0069] Silicon dielectric material-50, first mask material-60, second mask material-70;
[0070] Oxide materials - 80, epitaxial silicon materials - 90;
[0071] Mandrel material-71, side wall material-72. DETAILED DESCRIPTION
[0072] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.
[0073] A gate-all-around FET is a transistor structure in which the gate material wraps around the periphery of the channel. Compared with planar GAA transistors, vertical GAA transistors have a small projected area, unlimited channel length, no contacted gate pitch (CGP) restrictions, good parasitic capacitance control, and are suitable for 3D integration.
[0074] In the related art, when manufacturing a VGAA transistor, the following processes are usually included:
[0075] First, a silicon film layer is provided as a source, and a silicon nanocolumn perpendicular to the silicon film layer is formed on the silicon film layer. After an isolation layer is deposited on the silicon film layer, a gate dielectric is deposited on the silicon nanocolumn and the silicon film layer, and a gate material is deposited on the surface of the gate dielectric. The coverage of the gate material on the upper surface of the silicon nanocolumn is etched, and the height of the silicon nanocolumn exceeds the coverage height of the gate material, and then an isolation layer is deposited to a height lower than the silicon nanocolumn. After silicon is deposited on the silicon nanocolumn as a drain, the source is set to contact with the lower source silicon film layer, the drain is set to contact with the drain silicon deposited on the upper layer, and the ring gate material is set to contact along the word line.
[0076] However, in the above-mentioned method, when materials such as bit lines and word lines are arranged, it is impossible to ensure accurate alignment of positions of the bit lines, source and drain regions, gate regions, channels, etc.
[0077] In an embodiment of the present application, a method for preparing a transistor is provided. Optionally, the method for preparing the transistor is mainly applied in a process for preparing a VGAA transistor.
[0078] First, the structure of the VGAA transistor in the embodiment of the present application is introduced.
[0079] In an embodiment of the present application, a transistor array is provided. The transistor array includes a plurality of transistor units arranged in an array; the transistor unit includes a first source / drain, a channel, a second source / drain, and a normally closed contact that are vertically distributed in sequence, and a gate material is wrapped around the channel of the transistor unit; the first source / drain of a plurality of first transistor units in a first queue is connected by coupling to a buried bit line; the gate materials of a plurality of second transistor units in a second queue are connected, so that a word line is coupled to a plurality of second transistor units, wherein the first queue is a queue along the first array direction, and the second queue is a queue along the second array direction; the surfaces of the transistor units between the plurality of second queues are covered with a low dielectric material, and the tops of the plurality of second queues are covered with a silicon dielectric material, and air gaps are formed between the low dielectric materials.
[0080] like Figure 1 As shown, the transistor array 100 includes a plurality of transistor cells 110 .
[0081] Each transistor unit 110 is connected to a bit line (BL) 111 through a source / drain 113 and a word line (WL) 112 through a gate 114. The gate 114 surrounds a channel 115, and a normally closed contact (NC) 116 contacts the source / drain 113. The source / drain 113 is a heavily doped material, and the channel is a lightly doped material or an undoped material.
[0082] Among them, multiple transistor units 110 in the same column of the transistor array 100 are connected by coupling with the extended bit line 111; multiple transistor units 110 in the same row of the transistor array 100 are connected by coupling with the extended word line 112.
[0083] The word line WL112 is connected to the gate 114 as a gate line to turn on the transistor unit 110 ; the bit line BL111 is connected to the source / drain 113 as a data signal writing line. The gate 114 surrounds the channel 115 .
[0084] The normally open contact or normally closed contact 116 refers to the natural state without any external effect (such as power on), at which time the normally open contact is disconnected and the normally closed contact 116 is connected. In the embodiment of the present application, the source / drain 113 of the transistor unit 110 is connected to the normally closed contact as an example for explanation. If the source is connected to the bit line 111, the drain is connected to the normally closed contact 116; if the drain is connected to the bit line 111, the source is connected to the normally closed contact 116.
[0085] In the embodiment of the present application, the surfaces of the gate 114 and the source / drain 113 are covered with a low-dielectric (Low-K) material 40 to form an air layer for isolation.
[0086] Combined with the above introduction to VGAA transistors, Figure 2 is a flow chart of a method for preparing a VGAA transistor provided by an exemplary embodiment of the present application, such as Figure 2 As shown, the method includes the following steps.
[0087] Step 201 : stacking a first silicon film layer, a germanium silicon film layer, and a second silicon film layer in sequence on a silicon substrate.
[0088] The first silicon film layer 11 is adjacent to the silicon substrate 00. Optionally, the silicon substrate may be properly doped to form a well.
[0089] That is, the stacking sequence is to first deposit the first silicon film layer 11 on the silicon substrate 00 , deposit the silicon germanium film layer 12 on the first silicon film layer 11 , and then deposit the second silicon film layer 13 on the silicon germanium film layer 12 .
[0090] The first silicon film layer 11 and the second silicon film layer 13 are used as the source / drain in the transistor, and doping is performed during the in-situ growth process of the first silicon film layer 11 and the second silicon film layer 13. The first silicon film layer 11, the silicon germanium film layer 12 and the second silicon film layer 13 are deposited by in-situ growth, and the duration of the in-situ growth is controlled to control the thickness of the first silicon film layer 11, the silicon germanium film layer 12 and the second silicon film layer 13; and during the doping process, the ion implantation concentration of the first silicon film layer 11 and the second silicon film layer 13 is controlled.
[0091] Indicatively, Figure 3 As shown, a first silicon film layer 11 , a germanium silicon film layer 12 , and a second silicon film layer 13 are sequentially deposited on a silicon substrate 00 from bottom to top.
[0092] Step 202, etching along the bit line direction to form a first etched groove on the silicon substrate, the first silicon film layer, the germanium silicon film layer and the second silicon film layer, filling the first etched groove with metal material and annealing to generate a bit line.
[0093] In some embodiments, multiple columns of first mask material 60 are formed on the second silicon film layer 13 along the bit line direction, and areas of the silicon substrate 00, the first silicon film layer 11, the germanium silicon film layer 12, and the second silicon film layer 13 that are not covered by the first mask material 60 are etched to form a first etching groove along the bit line direction.
[0094] In some embodiments, photoresist (PR) is used as the first mask material 60, or other materials can be selected as the first mask material 60, and there is a certain etching selectivity between the first mask material 60 and silicon and silicon germanium. Optionally, a self-aligned double patterning technology (SADP) or a self-aligned quadruple patterning technology (SAQP) or other self-aligned multiple patterning (SAMP) technology is used to form multiple columns of the first mask material 60 on the first silicon film layer 11.
[0095] Among them, SADP is used as an example for explanation in this embodiment. SADP refers to the process of using non-photolithography process steps (thin film deposition, etching, etc.) to achieve spatial frequency doubling of the photolithography pattern after one photolithography is completed. Finally, another photolithography and etching are used to remove the redundant pattern, thereby realizing the process of forming a patterned mask material. In some embodiments, the SADP process includes: providing a material layer to be etched; forming a sacrificial photoresist layer on the material layer to be etched; curing the photoresist on the top and side walls of the sacrificial photoresist layer to form a cured photoresist shell; etching back the cured photoresist shell on the top of the sacrificial photoresist layer until the uncured internal sacrificial photoresist layer is exposed, and the cured photoresist shell located on the side walls of the internal sacrificial photoresist layer forms the pattern of the first mask material 60; removing the uncured internal sacrificial photoresist layer to obtain a plurality of columns of first mask materials 60 formed on the first silicon film layer 11.
[0096] Indicatively, Figure 4 As shown, a plurality of columns of first mask material 60 are formed on the second silicon film layer 13 along the bit line direction.
[0097] In some embodiments, when etching the area of the silicon substrate 00, the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 that is not covered by the first mask material 60, the etching rate of the silicon substrate 00, the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 is greater than the etching rate of the first mask material 60, so that the silicon substrate 00, the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 are etched while maintaining a small amount of sacrifice of the first mask material 60. The first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 are penetrated during the etching process, and the silicon substrate 00 with a partial thickness is etched by controlling the etching time, without penetrating the silicon substrate 00.
[0098] In some embodiments, in order to prevent the first silicon film layer 11, the silicon germanium film layer 12 and the second silicon film layer 13 from being affected by the metal material 20 during the process of generating the bit line, the first silicon film layer 11, the silicon germanium film layer 12 and the second silicon film layer 13 are isolated by oxide.
[0099] Optionally, first, the areas in the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13 that are not covered by the first mask material 60 are etched to form candidate etching grooves along the bit line direction; oxide material 80 is deposited to cover the inner and outer surfaces of the candidate etching grooves with the oxide material 80, and the oxide material 80 is used to isolate the reaction between the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13 and the metal material 20; on the basis of the candidate etching grooves, the areas in the silicon substrate 00 that are not covered by the first mask material 60 are etched to form a first etching groove along the bit line direction.
[0100] Indicatively, Figure 5 As shown, first, the areas in the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13 that are not covered by the first mask material 60 are etched by controlling the etching time to obtain candidate etching grooves, and then an oxide material 80, such as silicon dioxide (SiO2), is deposited by atomic layer deposition (ALD). The oxide material 80 covers the inner and outer surfaces of the candidate etching grooves, and the oxide and silicon substrate 00 are continuously etched. By controlling the etching time, the silicon substrate 00 with a preset thickness requirement is etched to obtain a first etching groove.
[0101] In some embodiments, a metal material 20, such as tungsten (W) material, is deposited at the bottom of the first etched groove, and the silicon substrate 00 is annealed to form a metal silicide as a bit line through annealing. Annealing refers to the process of diffusing metal into the silicon substrate 00 through ohmic contact to form a metal silicide.
[0102] In some embodiments, a silicon dielectric material 50 with a first height is firstly filled in the first etched groove. In some embodiments, the silicon dielectric material 50 can be implemented as a nitride material or an oxide material, which is not limited in this embodiment. Taking the nitride material as an example, the silicon dielectric material 50 can be implemented as silicon nitride (SiN), and the first height is less than the depth of the first etched groove in the silicon substrate 00. The metal material 20 is filled on the silicon dielectric material 50 and annealed to generate a bit line, wherein adjacent bit lines are isolated by the silicon dielectric material 50.
[0103] Optionally, a silicon dielectric material 50 is deposited in the first etching groove by atomic layer deposition ALD or chemical vapor deposition (CVD) and then polished, and then the silicon dielectric material 50 is etched to a first height by controlling the etching time. The etching rate of the silicon dielectric material 50 is greater than the etching rate of the first mask material 60.
[0104] Indicatively, Figure 6 As shown, first, the silicon dielectric material 50 is filled in the first etched groove and ground flat, and then the silicon dielectric material 50 of a first height in the first etched groove is retained by etching, and the first height is less than the depth of the first etched groove of the silicon substrate 00, that is, the upper plane of the silicon dielectric material 50 after etching is below the upper plane of the silicon substrate 00. After the metal material 20 is deposited on the silicon dielectric material 50, a metal silicide is generated by annealing as a bit line.
[0105] Optionally, excess metal material 20 is removed by wet etching.
[0106] Step 203, etching the second silicon film layer and the silicon germanium film layer along the word line direction to form a second etched groove, and after generating a channel based on the silicon germanium film layer, filling the second etched groove along the word line direction with a gate material to generate a word line.
[0107] A plurality of columns of second mask material 70 are formed on the second silicon film layer 13 along the word line direction, and the areas of the second silicon film layer 13 and the silicon germanium film layer 12 not covered by the second mask material 70 are etched to form second etching grooves along the word line direction.
[0108] In some embodiments, the first mask material 60 is first etched away, and then the second mask material 70 is formed on the second silicon film layer 13 .
[0109] Optionally, the second mask material 70 is used to control the direction of word line generation. After the second mask material 70 is formed along the word line direction, the second silicon film layer 13 and the germanium silicon film layer 12 are etched. In some embodiments, the etching time is controlled so that the germanium silicon film layer 12 is etched, while the first silicon film layer 11 is not etched or is less etched.
[0110] In some embodiments, the silicon dielectric material 50 of the second height is filled in the first etching groove, wherein the upper plane of the silicon dielectric material 50 of the second height meets the plane distance requirement with the upper plane of the first silicon film layer 11, such as: the upper plane of the silicon dielectric material 50 and the upper plane of the first silicon film layer 11 are in the same plane or the distance is less than the distance threshold. The oxide material 80 is filled in the first etching groove, and a plurality of columns of the second mask material 70 are formed on the first silicon film layer 11 after the oxide material 80 is filled along the word line direction.
[0111] In some embodiments, when the silicon dielectric material 50 of the second height is filled in the first etching groove, the silicon dielectric material 50 exceeding the height of the second silicon film layer 13 is first filled and polished, and then the silicon dielectric material 50 is etched to the second height by controlling the etching time.
[0112] In some embodiments, since oxide is deposited on the surfaces of the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13 in the above step 202, optionally, the silicon dielectric material 50 can be filled after etching away the oxide, or the silicon dielectric material 50 can be directly filled without removing the oxide, which is not limited in this embodiment.
[0113] Among them, the silicon dielectric material 50 is used as an etching stop line when etching along the word line direction, that is, when the second silicon film layer 13 and the germanium silicon film layer 12 are etched along the word line direction, the etching time is controlled until the upper surface of the silicon dielectric material 50 is etched and the etching is stopped.
[0114] In some embodiments, after depositing the silicon dielectric material 50 of the second height, the oxide material 80 is continuously deposited on the silicon dielectric material 50 to a height exceeding the second silicon film layer 13 and then ground flat. A plurality of columns of the second mask material 70 are formed on the oxide and the second silicon film layer 13, and the areas of the second silicon film layer 13, the silicon germanium film layer 12, and the oxide material 80 that are not covered by the second mask material 70 are etched to form a second etched groove along the word line direction.
[0115] Indicatively, Figure 7 As shown, after the word line is generated, the silicon dielectric material 50 is filled in the first etching groove to a level higher than the second silicon film layer 13 and then ground by ALD / CVD / furnace method, and the ground silicon dielectric material 50 is etched until the upper plane corresponding to the silicon dielectric material 50 is flush with the contact surface of the first silicon film layer 11 and the germanium silicon film layer 12.
[0116] like Figure 8 As shown, the oxide material 80 is continuously deposited on the silicon dielectric material 50 to a level higher than the second silicon film layer 13 and then ground flat, and multiple rows of the second mask material 70 are formed on the oxide material 80 and the second silicon film layer 13 by SADP or SAQP. Based on the second mask material 70, the second silicon film layer 13, the silicon germanium film layer 12, and the area of the oxide material 80 not covered by the second mask material 70 are etched to form a second etched groove, wherein the etching rate of the second silicon film layer 13, the silicon germanium film layer 12, and the oxide material 80 is greater than the etching rate of the second mask material 70.
[0117] In some embodiments, the second silicon film layer 13 , the germanium silicon film layer 12 , and the oxide material 80 are etched by dry etching or wet etching.
[0118] In some embodiments, after a channel is generated in the germanium silicon film layer 12 based on the second mask material 70, a gate material 30 (Metal Gate) is filled in the second etched groove to obtain a gate surrounding the channel and generate a word line to obtain a vertical all-around gate transistor.
[0119] Step 204, depositing low dielectric material in the first etching groove, the second etching groove and on the first silicon film layer, and forming an air gap by etching and depositing silicon dielectric material on the top to isolate the gate material and obtain a vertical gate all-around transistor.
[0120] In some embodiments, after removing the high-K dielectric around the word line, a low dielectric material is deposited to isolate the gate material to protect the word line and S / D. Optionally, the gate material includes dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, or includes conductive materials such as polysilicon, tantalum, aluminum, and tungsten.
[0121] In order to reduce the RC delay (proportional to R×C) and energy consumption (C×V×2f) of the circuit under high-speed reading and writing conditions, an air gap with a dielectric constant of approximately 1 is used as the dielectric layer of the word line to reduce the parasitic capacitance between the word lines and improve the performance of the transistor in high-speed application scenarios. Wherein, R represents resistance, C represents capacitance, V represents voltage, and f represents current frequency. However, since metal is easily oxidized when in contact with air, which affects the performance of the word line, in an embodiment of the present application, after a low dielectric material is deposited between the gate materials, a portion of the low dielectric material is etched, and a silicon dielectric material is deposited on top, thereby forming an air gap between the gate materials, and the gate material is isolated by the low dielectric material and the air gap.
[0122] In an embodiment of the present application, after setting the bit line, word line, ring gate, source / drain, a low dielectric (Low-K) material is deposited on the surface of the ring gate and the upper source / drain to isolate the word line and reduce the K value between the word lines, that is, reduce the capacitance between the word lines, thereby improving the performance of the transistor.
[0123] Optionally, a low dielectric material 40 is deposited in the first etching groove, the second etching groove and on the first silicon film layer 11; the low dielectric material 40 on the surface of the first silicon film layer 11 and the second silicon film layer 13 is etched, and part of the low dielectric material 40 between the gate material 30 is etched; and a silicon dielectric material 50 is deposited on the second silicon film layer 13 to obtain a vertical gate full-surround transistor.
[0124] Optionally, a metal material 20 is deposited on the second silicon film layer 13 to contact the second silicon film layer 13 ; and a silicon dielectric material 50 is deposited in the first etching groove and the second etching groove to obtain a vertical gate all-around transistor.
[0125] In summary, the method provided in this embodiment, after laying out the bit line, word line, source / drain and ring gate of the transistor, removes the high dielectric constant dielectric between the word lines, and deposits a layer of protective material between the ring gate and the top source / drain to avoid oxidation, and finally forms an air gap between the word lines through a high deposition rate and low step coverage dielectric, thereby reducing the parasitic capacitance between the word lines, improving the device performance of the VGAA transistor, and reducing the preparation complexity.
[0126] The method provided in this embodiment, through the sequential stacking of a silicon substrate, a first silicon film layer, a germanium silicon film layer, and a second silicon film layer, based on the first silicon film layer and the second silicon film layer as the source / drain, on the basis of forming a bit line on the silicon substrate through a first mask material, and forming a channel and a word line and a ring gate through a second mask material, thereby improving the alignment between the bit line, the channel, the source / drain, the word line and the ring gate, improving the preparation accuracy and success rate of the VGAA transistor, improving the device performance of the VGAA transistor, and reducing the preparation complexity.
[0127] In some embodiments, the second mask material 70 includes a mandrel material 71 and spacer materials 72 distributed on both sides of the mandrel material 71 , and a channel of the transistor is generated based on the mandrel material 71 and the spacer materials 72 distributed on both sides of the mandrel material 71 . Fig. 9 is a flow chart of a method for preparing a transistor provided by another exemplary embodiment of the present application, such as Fig. 9 As shown, the above steps 203 to 204 can also be implemented as the following steps 901 to 908.
[0128] Step 901 , performing lateral etching of a first thickness on the surface of the silicon germanium film layer on the silicon pillars obtained by etching the first etching groove and the second etching groove.
[0129] In some embodiments, the surface of the germanium silicon film layer 12 is laterally etched to a first thickness on the silicon pillar by a lateral atomic layer etching (ALE) process or a lateral wet etching or a lateral dry etching.
[0130] In some embodiments, the germanium silicon film layer 12 is firstly etched separately by lateral ALE, wherein in the etching process, there is a certain selectivity between the etching of the second silicon film layer 13 and the germanium silicon film layer 12, so that the etching rate of the germanium silicon film layer 12 is greater than the etching rate of the second silicon film layer 13. Then, the second silicon film layer 13 and the germanium silicon film layer 12 are etched by silicon etching to achieve etching of the first thickness on the surface of the germanium silicon film layer 12.
[0131] Indicatively, Fig.10 As shown, the surface of the silicon germanium film layer 12 in the silicon pillar is initially etched by lateral etching, and then the second silicon film layer 13 and the silicon germanium film layer 12 are etched by silicon etching to achieve a first thickness of etching on the surface of the silicon germanium film layer 12 .
[0132] Step 902 , generating an epitaxial silicon material of a second thickness on the etched surface of the silicon germanium film layer.
[0133] The second thickness is smaller than the first thickness.
[0134] Epitaxial silicon material 90 is generated on the silicon pillar and silicon dielectric material 50 by epitaxy; the epitaxial silicon material 90 on the surface of the second silicon film layer 13 and the silicon dielectric material 50 is annealed to obtain epitaxial silicon material 90 of a second thickness generated on the surface of the silicon germanium film layer 12. The process growth rate of the epitaxial silicon material is selective, that is, the epitaxial silicon rate on the surface of the silicon pillar and the silicon germanium material is faster, and the rate on the dielectric material is very low, so the main epitaxial silicon exists on the silicon pillar and the silicon germanium material.
[0135] In some embodiments, intrinsic silicon, i.e., epitaxial silicon material 90, is generated on the surface of the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 by selective epitaxy. The selective epitaxy is to generate epitaxial silicon material 90 by reacting the precursor adsorbed on the silicon / silicon germanium material after depositing the precursor, while other materials will not adsorb the precursor, so epitaxial silicon material 90 will not be generated. The epitaxial silicon material 90 is generated on the surface of the first silicon film layer 11, the silicon germanium film layer 12, and the second silicon film layer 13 by controlling the adsorption amount of the precursor or the duration of epitaxial growth, wherein the epitaxial silicon material 90 of the second thickness is generated on the surface of the silicon germanium film layer 12, and the epitaxial silicon material 90 on the surface of the first silicon film layer 11 and the second silicon film layer 13 is diffused into the silicon material by annealing treatment, and is integrated with the source / drain, and the epitaxial silicon material 90 generated on the surface of the silicon germanium film layer 12 is retained.
[0136] Indicatively, Fig.11 As shown, epitaxial silicon material 90 is generated on the surfaces of the first silicon film layer 11, the silicon germanium film layer 12 and the second silicon film layer 13 by selective epitaxy, and the epitaxial silicon material 90 on the surfaces of the first silicon film layer 11 and the second silicon film layer 13 is diffused by annealing, and the epitaxial silicon material 90 on the surface of the silicon germanium film layer 12 is retained, so as to obtain the epitaxial silicon material 90 of the second thickness on the surface of the silicon germanium film layer 12. Fig.11 It can be seen that the second thickness is smaller than the first thickness.
[0137] The epitaxial silicon material 90 forms a channel of the transistor.
[0138] Step 903 , etching the portions of the second silicon film layer and the silicon germanium film layer covered by the mandrel material to split the silicon column into at least two sub-silicon columns.
[0139] In some embodiments, the mandrel material 71 and the spacer material 72 correspond to a certain etching selectivity ratio, so that during the etching process of the mandrel material 71 , only a small amount of sacrificial etching occurs on the spacer material 72 .
[0140] Optionally, the oxide material 80 is first filled between the silicon pillars, and the oxide material 80 not covered by the second mask material 70 is etched, and then the silicon dielectric material 50 is filled between the silicon pillars. It is worth noting that the silicon dielectric material 50 can be filled on the basis of etching the oxide material 80, or can be filled directly, or can be directly filled with the silicon dielectric material 50 without filling the oxide material 80, which is not limited in this embodiment.
[0141] After filling the silicon dielectric material 50, the portions of the second silicon film layer 13 and the silicon germanium film layer 12 covered by the mandrel material 71 are etched to expose the second silicon film layer 13 and the silicon germanium film layer 12 on the etched side surfaces of the sub-silicon pillars.
[0142] Indicatively, Fig.12As shown, firstly, oxide material 80 is filled between silicon pillars, and the oxide material 80 not covered by the second mask material 70 is etched, then silicon dielectric material 50 is filled, and the second silicon film layer 13 and silicon germanium film layer 12 covered by the mandrel material 71 are etched.
[0143] Step 904 , removing the silicon germanium film layer in at least two sub-silicon pillars, and filling with oxide material to obtain oxide material surrounding the epitaxial silicon material.
[0144] After the core shaft material 71 is etched, the germanium silicon film layer 12 on one side of the channel is exposed, and the other side of the channel is the oxide material 80. Therefore, the germanium silicon film layer 12 is etched and filled with the oxide material 80, so that the oxide material 80 can surround the epitaxial silicon material 90 and use the epitaxial silicon material 90 as a channel.
[0145] Indicatively, Fig.13 As shown, after etching the second silicon film layer 13 and the germanium silicon film layer 12 covered by the core shaft material 71, the germanium silicon film layer 12 in the sub-silicon pillars is removed by lateral etching, and the etched areas between the sub-silicon pillars are filled with oxide material 80, and the oxide material 80 not covered by the side wall material 72 is etched, thereby obtaining the oxide material 80 surrounding the epitaxial silicon material 90.
[0146] Step 905: Fill the second etched groove with a silicon dielectric material.
[0147] In some embodiments, after etching the spacer material 72 , the area between the sub-silicon pillars that is not filled with the silicon dielectric material 50 is filled with the silicon dielectric material 50 to a level higher than the second silicon film layer 13 and then ground flat.
[0148] Step 906 , etching the oxide material and filling the gate material along the direction of the second etched groove.
[0149] In some embodiments, the oxide material 80 retained in the structure is etched by wet etching, and the oxide is replaced by the gate material 30 by utilizing the selectivity between oxide and nitride.
[0150] Step 907, etching the gate material within the first height range, and retaining the gate material within the second height range.
[0151] The first height range corresponds to the height range of the second silicon film layer 13 , that is, the gate material 30 on the surface of the source / drain is removed by etching, and the gate material 30 on the surface of the channel is retained.
[0152] Indicatively, Fig.14As shown, after etching the sidewall material 72 and the silicon dielectric material 50 in the same height range as the sidewall material 72, the silicon dielectric material 50 is filled between each sub-silicon pillar, and after etching the oxide material 80 on the sub-silicon pillar, the gate material 30 is generated along the word line direction, and the gate material 30 in the height range corresponding to the second silicon film layer 13 is etched, and the gate material 30 in the height range corresponding to the channel is retained.
[0153] Step 908, deposit low dielectric material in the first etching groove, the second etching groove and on the second silicon film layer, etch part of the low dielectric material between the gate materials, and deposit silicon dielectric material on the top to form an air gap to isolate the gate material, thereby obtaining a vertical gate full-surround transistor.
[0154] In some embodiments, silicon dielectric material 50 is filled between each silicon sub-pillar, so the silicon dielectric material 50 between each silicon sub-pillar is first etched, and then low dielectric material 40 is deposited on the surface of the silicon sub-pillar. Optionally, after the low dielectric material 40 is deposited, since the upper source / drain still needs to contact with the metal material 20, the metal material 20 is used as a normally closed contact, so the low dielectric material 40 on the upper surface is etched and removed to expose the upper surface of the source / drain, and the metal material 20 is deposited on the silicon pillar to contact the second silicon film layer 13, and the silicon dielectric material 50 is filled to form an air gap, and a vertical surrounding gate transistor is obtained.
[0155] like Fig.15 As shown, the silicon dielectric material 50 between each sub-silicon pillar is first etched, and then the low dielectric material 40 is deposited on the surface of the sub-silicon pillar. The upper layer of the low dielectric material 40 is etched to expose the upper source / drain. Then, the metal material 20 is deposited on the silicon pillar to contact the second silicon film layer 13. After filling the silicon dielectric material 50, a vertical surrounding gate transistor is obtained.
[0156] In summary, the method provided in this embodiment, after laying out the bit line, word line, source / drain and ring gate of the transistor, removes the high dielectric constant dielectric between the word lines, and deposits a layer of protective material between the ring gate and the top source / drain to avoid oxidation, and finally forms an air gap between the word lines through a high deposition rate and low step coverage dielectric, thereby reducing the parasitic capacitance between the word lines, improving the device performance of the VGAA transistor, and reducing the preparation complexity.
[0157] The method provided in this embodiment, through the sequential stacking of a silicon substrate, a first silicon film layer, a germanium silicon film layer, and a second silicon film layer, based on the first silicon film layer and the second silicon film layer as the source / drain, on the basis of forming a bit line on the silicon substrate through a first mask material, and forming a channel and a word line and a ring gate through a second mask material, thereby improving the alignment between the bit line, the channel, the source / drain, the word line and the ring gate, improving the preparation accuracy and success rate of the VGAA transistor, improving the device performance of the VGAA transistor, and reducing the preparation complexity.
[0158] The method provided in this embodiment is based on the epitaxial VGAA transistor process flow, generates epitaxial silicon material as a channel and fills the gate material to surround it, thereby improving the alignment between the channel and the word line and the gate and improving the process accuracy.
[0159] The method provided in this embodiment utilizes oxide to perform a self-aligned replacement metal gate process, thereby improving the accuracy of generating gate materials.
[0160] based on Figure 2 In the method embodiment shown, when executing step 201 , well isolation is also formed in the stack structure.
[0161] In one embodiment, in conjunction with reference Fig.16 , Fig.16 Part (A1) shows the stack structure after well isolation is formed. Fig.16 Part (A2) shows a two-dimensional plan view of the stacked structure. Considering the stacked structure after well isolation, it includes a silicon substrate 00, a first silicon film layer 11, a germanium silicon film layer 12 and a second silicon film layer 13. Further, the silicon substrate 00 includes an upper silicon substrate 00-1 and a lower silicon substrate 00-2. Optionally, the lower silicon substrate 00-2 is doped to N type, the upper silicon substrate 00-1 is doped to P type, and the first silicon film layer 11 is doped to P type. Optionally, the lower silicon substrate 00-2 is doped to P type, the upper silicon substrate 00-1 is doped to N type, and the first silicon film layer 11 is doped to N type.
[0162] It can be noted that Fig.16 Part (B1) shows the three-dimensional structure of multiple first silicon pillars 1601 obtained after considering well isolation. Fig.16 Part (B2) shows a plan view corresponding to the three-dimensional structure. At this time, the longitudinal etching depth of the first silicon pillar 1601 only reaches the upper part of the silicon substrate 00-1, and multiple first silicon pillars 1601 (i.e., bit lines) are isolated from each other by the PN junction structure to prevent leakage between the first silicon pillars 1601.
[0163] In one embodiment, in conjunction with reference Fig.17 , Fig.17Part (A1) shows the stack structure after well isolation is formed. Fig.17 Part (A2) shows a two-dimensional plan view of the stacked structure. Considering the stacked structure after well isolation, it includes a silicon substrate 00, a first silicon film layer 11, a germanium silicon film layer 12, a second silicon film layer 13, and a third silicon film layer 14 located between the silicon substrate 00 and the first silicon film layer. Optionally, the silicon substrate 00 is doped to P type, and the first silicon film layer 11 and the third silicon film layer 14 are doped to N type.
[0164] It can be noted that Fig.17 Part (B1) shows the three-dimensional structure of multiple first silicon pillars 1601 obtained after considering well isolation. Fig.17 At this time, the longitudinal etching depth of the first silicon pillar 1601 only reaches the third silicon film layer 14, and the plurality of first silicon pillars 1601 (i.e., bit lines) are isolated from each other by the PN junction structure to prevent leakage between the first silicon pillars 1601.
[0165] Illustratively, the following four possible implementations are provided for the above step 201.
[0166] A first possible implementation method is to obtain a silicon substrate; dope the lower part of the silicon substrate into N-type, and dope the upper part of the silicon substrate into P-type; sequentially stack a first silicon film layer, a germanium silicon film layer, and a second silicon film layer on the silicon substrate; and dope the first silicon film layer into P-type. Optionally, after doping the silicon substrate, an annealing operation is performed to restore the silicon substrate lattice.
[0167] Combined with reference Fig.18 , Fig.18 Part (A) shows a silicon substrate 00; Fig.18 Part (B) of FIG. 1 shows a lower portion of the silicon substrate 00 - 1 doped with N type and an upper portion of the silicon substrate 00 - 2 doped with P type. Fig.18 Part (C) shows the stacked first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13, and the first silicon film layer 11 is doped to P type.
[0168] A second possible implementation method is to obtain a silicon substrate; dope the lower part of the silicon substrate into P type, and dope the upper part of the silicon substrate into N type; sequentially stack a first silicon film layer, a germanium silicon film layer, and a second silicon film layer on the silicon substrate; and dope the first silicon film layer into N type. Optionally, after doping the silicon substrate, an annealing operation is performed to restore the silicon substrate lattice.
[0169] Combined with reference Fig.19 , Fig.19 Part (A) shows a silicon substrate 00; Fig.19Part (B) of FIG. 1 shows a lower portion of the silicon substrate 00 - 1 doped with a P type and an upper portion of the silicon substrate 00 - 2 doped with an N type. Fig.19 Part (C) shows the stacked first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13, and the first silicon film layer 11 is doped to N type.
[0170] A third possible implementation method is to obtain a silicon substrate; dope the silicon substrate to N-type; sequentially stack a third silicon layer, a first silicon film layer, a germanium silicon film layer, and a second silicon film layer on the silicon substrate; and dope the third silicon layer and the first silicon film layer to P-type.
[0171] Combined with reference Fig. 20 , Fig. 20 Part (A) shows a silicon substrate 00; Fig. 20 Part (B) shows a silicon substrate 00 doped to N type. Fig. 20 Part (C) shows the stacked third silicon film layer 14, the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13. The third silicon film layer 14 is doped to P type, and the first silicon film layer 11 is doped to P type.
[0172] A fourth possible implementation method is to obtain a silicon substrate; dope the silicon substrate into P type; sequentially stack a third silicon film layer, a first silicon film layer, a germanium silicon film layer, and a second silicon film layer on the silicon substrate; and dope the third silicon film layer and the first silicon film layer into N type.
[0173] Combined with reference Fig.21 , Fig.21 Part (A) shows a silicon substrate 00; Fig.21 Part (B) shows a silicon substrate 00 doped to a P type. Fig.21 Part (C) shows the stacked third silicon film layer 14, the first silicon film layer 11, the germanium silicon film layer 12 and the second silicon film layer 13. The third silicon film layer 14 is doped to N type, and the first silicon film layer 11 is doped to N type.
[0174] The embodiment of the present application provides an electronic device, which includes a logic device, and the logic device includes a transistor array as provided in the above embodiment. The logic device can be applied to a logic operator and a memory, etc. The transistor array is prepared by the process preparation method of the transistor provided in the above embodiment.
[0175] Optionally, the electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.
[0176] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "at least one" means one or more, and the term "plurality" means two or more, unless otherwise clearly defined.
[0177] The term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.
[0178] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.
Claims
1. A method for preparing a transistor, characterized in that: The method comprises: A first silicon film layer (11), a germanium silicon film layer (12), and a second silicon film layer (13) are sequentially stacked on a silicon substrate (00), wherein the first silicon film layer (11) is adjacent to the silicon substrate (00); Etching a first etching groove along the direction of the bit line on the silicon substrate (00), the first silicon film layer (11), the germanium silicon film layer (12) and the second silicon film layer (13), filling the first etching groove with a metal material (20) and annealing to generate a bit line; Etching a second etched groove along the word line direction on the second silicon film layer (13) and the silicon germanium film layer (12), generating a channel based on the silicon germanium film layer (12), and then filling a gate material (30) in the second etched groove along the word line direction to form a word line; A low dielectric material (40) is deposited in the first etching groove, the second etching groove and on the second silicon film layer (13), and an air gap is formed by etching and depositing a silicon dielectric material (50) on the top to isolate the gate material (30) and obtain a vertical gate all-around transistor.
2. The method according to claim 1, characterized in that: The method comprises depositing a low dielectric material (40) in the first etching groove and the second etching groove and on the second silicon film layer (13), and forming an air gap by etching and depositing a silicon dielectric material (50) on the top, isolating the gate material (30) and the second silicon film layer (13), and obtaining a vertical gate all-around transistor, comprising: Depositing the low dielectric material (40) in the first etching groove and the second etching groove and on the second silicon film layer (13); Etching the low dielectric material (40) on the surface of the first silicon film layer (11) and the second silicon film layer (13), and etching a portion of the low dielectric material (40) between the gate materials (30); A silicon dielectric material (50) is deposited on the second silicon film layer (13) to obtain the vertical gate all-around transistor.
3. The method according to claim 2, characterized in that The step of depositing a silicon dielectric material (50) on the second silicon film layer (13) to obtain the vertical gate all-around transistor comprises: Depositing a metal material (20) on the second silicon film layer (13) so as to be in contact with the second silicon film layer (13); The silicon dielectric material (50) is deposited in the first etching groove and the second etching groove to obtain the vertical gate all-around transistor.
4. The method according to claim 1, characterized in that The step of etching the silicon substrate (00), the first silicon film layer (11), the silicon germanium film layer (12) and the second silicon film layer (13) along the bit line direction to form a first etching groove comprises: forming a plurality of columns of first mask material (60) on the second silicon film layer (13) along the bit line direction; Areas not covered by the first mask material (60) in the silicon substrate (00), the first silicon film layer (11), the silicon germanium film layer (12) and the second silicon film layer (13) are etched to form a first etching groove along the bit line direction.
5. The method according to claim 4, characterized in that The step of filling the first etching groove with a metal material (20) and annealing to generate a bit line comprises: forming the silicon dielectric material (50) with a first height in the first etching groove, wherein the first height is less than the depth of the first etching groove in the silicon substrate (00); The metal material (20) is filled on the silicon dielectric material (50) and annealed to generate a bit line, wherein adjacent bit lines are isolated by the silicon dielectric material (50).
6. The method according to claim 1, characterized in that The step of etching the second silicon film layer (13) and the germanium silicon film layer (12) along the word line direction to form a second etching groove comprises: forming a plurality of columns of second mask material (70) on the second silicon film layer (13) along the word line direction; Areas in the second silicon film layer (13) and the germanium silicon film layer (12) that are not covered by the second mask material (70) are etched to form a second etching groove along the word line direction.
7. The method according to claim 6, characterized in that The step of forming a plurality of columns of second mask material (70) on the second silicon film layer (13) along the word line direction comprises: Filling the first etching groove with the silicon dielectric material (50) of a second height, wherein an upper plane of the silicon dielectric material (50) of the second height and an upper plane of the first silicon film layer (11) meet a plane distance requirement; An oxide material (80) is filled in the first etching groove, and a plurality of columns of second mask material (70) are formed along the word line direction on the second silicon film layer (13) filled with the oxide material (80).
8. The method according to claim 7, characterized in that The second mask material (70) comprises a mandrel material (71) and sidewall materials (72) distributed on both sides of the mandrel material (71); The step of generating a channel based on the germanium silicon film layer (12) comprises: On the silicon pillars obtained by etching the first etching grooves and the second etching grooves, performing lateral etching of a first thickness on the surface of the germanium silicon film layer (12); generating an epitaxial silicon material (90) of a second thickness on the etched surface of the germanium silicon film layer (12), wherein the second thickness is less than the first thickness; Etching the second silicon film layer (13) and the germanium silicon film layer (12) at the portion covered by the mandrel material (71) to split the silicon column into at least two sub-silicon columns; The germanium silicon film layer (12) in the at least two sub-silicon pillars is removed and filled with an oxide material (80) to obtain the oxide material (80) surrounding the epitaxial silicon material (90), and the epitaxial silicon material (90) forms a channel of the transistor.
9. A transistor array, characterized in that: The transistor array includes a plurality of transistor units arranged in an array; The transistor unit comprises a first source / drain, a channel, a second source / drain, and a normally closed contact which are vertically distributed in sequence, and the channel of the transistor unit is surrounded by a gate material; The first sources / drains of the plurality of first transistor cells in the first queue are connected by coupling to a buried bit line; The gate materials of the plurality of second transistor units in the second queue are connected, so that the word line is coupled to the plurality of second transistor units, wherein the first queue is a queue along the first array direction, and the second queue is a queue along the second array direction; The surfaces of the transistor units between the plurality of the second queues are covered with a low dielectric material, the tops of the plurality of the second queues are covered with a silicon dielectric material, and air gaps are formed between the low dielectric materials.
10. An electronic device, characterized in that: The electronic device comprises a logic device, and the logic device comprises the transistor array as claimed in claim 9.
11. The electronic device according to claim 10, characterized in that: The electronic device includes a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device or a smart mobile terminal.