Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a semiconductor substrate, an epitaxial layer is formed on the surface of the semiconductor substrate, and a contact doping region is formed in the epitaxial layer; the shielding doped regions are located in the epitaxial layer on the two sides of the contact doped region, and the doping type of the shielding doped regions is opposite to that of the contact doped region; the well region is located in the epitaxial layer at the bottom of the contact doped region, the doping type of the well region is opposite to that of the contact doped region, and the depth of the shielding doped region is larger than that of the well region and larger than that of the contact doped region; the trench gate structures are located on the two sides of the shielding doped region and penetrate through part of the shielding doped region to be connected with the well region and the contact doped region, and the depth of the trench gate structures is larger than that of the well region and smaller than that of the shielding doped region. The MOSFET unit structure can solve the problems that an existing MOSFET unit structure is not high in reliability and low in integration level.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] A basic power MOSFET cell structure consists of the following key parts: the gate, which is the electrode that controls the conductive state of the device. In a power MOSFET, the gate is isolated from the trench by an insulating layer (usually silicon dioxide); the gate dielectric layer (Gate Oxide), which is an insulating layer under the gate, which serves to isolate the gate and the channel and store charge when the gate voltage is applied; channel, located on the sidewalls and the semiconductor region below the gate dielectric layer, is the path for current flow; source, which is the source current end of the device, usually coincides with the channel region and has doping; drain, which is the drain current end of the device, located at the other end of the channel region, before the conductive channel is formed, the drain and the source are isolated by a high-resistance P-type semiconductor; body, in some MOSFET designs, especially in situations where isolation is required, the body region may be introduced as another terminal, electrically isolated from the source to provide better noise suppression and stability; contact doping region, usually a heavily doped N-type region is formed under the source and drain to reduce contact resistance and provide better current collection; metallization layer, a metal layer formed on the top and / or back of the device, used to connect the gate, source and drain, and connect the device to an external circuit. In actual power MOSFET design, more complex structures may be included, such as a multi-finger design, which includes multiple parallel trench and source structures to improve the current carrying capacity of the device.

[0003] The main deficiencies or directions for optimization of existing power MOSFET units are mainly in the following aspects: the P-type shielding doping area of ​​the gate dielectric layer leads to low efficiency and unstable reliability. It is necessary to further improve the P-type shielding doping area to increase the channel density to reduce the on-resistance. At the same time, it is necessary to further improve the electric field shielding efficiency of the gate dielectric layer to improve the gate reliability of the device. The mesa (the area between adjacent trench gate structures) of the semiconductor region with a specific shape on the device structure defines the conductive channel of the device. This area is the active part when the device is working. The physical size of this area in the existing power MOSFET unit structure is relatively large. At the same time, the characteristics of the device structure unit make it impossible to achieve carrier enrichment effect by reducing the mesa size, which will affect its current carrying capacity. It is necessary to further optimize the MOSFET unit structure and reduce the Mesa size to increase the carrier density to achieve low on-resistance R on and low diode conduction voltage drop Vsd In addition, another important goal of reducing the size of the power MOSFET unit Mesa is to increase the cell density of the device structure unit. Summary of the invention

[0004] The invention purpose of this application is to solve the problem of low reliability and low integration of the existing MOSFET unit structure, as well as the problem of low body diode integration. The technical solution of this application provides a MOSFET unit structure to achieve the purpose of optimizing the MOSFET unit structure and improving its reliability and integration.

[0005] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, wherein an epitaxial layer is formed on the surface of the semiconductor substrate; forming a contact doping region in the epitaxial layer; forming a shielding doping region in the epitaxial layer on both sides of the contact doping region, wherein the shielding doping region has an opposite doping type to the contact doping region; forming a well region in the epitaxial layer, wherein the well region has an opposite doping type to the contact doping region, wherein the depth of the shielding doping region is greater than the depth of the well region, which is greater than the depth of the contact doping region, the well region surrounds the bottom and side walls of the contact doping region, and the well region is also located on the side walls of the shielding doping region; and forming trench gate structures penetrating part of the shielding doping region, the well region and the contact doping region on both sides of the shielding doping region, wherein the depth of the trench gate structure is greater than the depth of the well region and less than the depth of the shielding doping region.

[0006] In some embodiments of the present application, the distance between the two trench gate structures on both sides of the contact doping region is 0.01 to 1 micron.

[0007] In some embodiments of the present application, the method for forming the semiconductor structure also includes: forming a dielectric layer covering the trench gate structure, the shielding doping region and the contact doping region on the surface of the epitaxial layer; forming a plurality of contact through holes that penetrate the dielectric layer and extend to a position between two adjacent trench gate structures; and filling the plurality of contact through holes with conductive material to form a plurality of contact structures.

[0008] In some embodiments of the present application, the depths of the plurality of contact structures are greater than the depth of the contact doping region and less than the depth of the well region.

[0009] In some embodiments of the present application, the method for forming the semiconductor structure also includes: forming a front metal layer covering the dielectric layer and electrically connecting the plurality of contact structures on the surface of the dielectric layer; and forming a back metal layer on the surface of the semiconductor substrate facing away from the epitaxial layer.

[0010] Another aspect of the present application also provides a semiconductor structure, including: a semiconductor substrate, an epitaxial layer is formed on the surface of the semiconductor substrate, and a contact doping region is formed in the epitaxial layer; a shielding doping region, located in the epitaxial layer on both sides of the contact doping region, the shielding doping region and the contact doping region have opposite doping types; a well region, located in the epitaxial layer at the bottom of the contact doping region, the well region and the contact doping region have opposite doping types, wherein the depth of the shielding doping region is greater than the depth of the well region and is greater than the depth of the contact doping region; a trench gate structure, located on both sides of the shielding doping region, penetrating part of the shielding doping region and connected to the well region and the contact doping region, the depth of the trench gate structure is greater than the depth of the well region and is less than the depth of the shielding doping region.

[0011] In some embodiments of the present application, the distance between the two trench gate structures on both sides of the contact doping region is 0.01 to 1 micron.

[0012] In some embodiments of the present application, the semiconductor structure also includes: a dielectric layer located on the surface of the epitaxial layer and covering the trench gate structure, the shielding doping region and the contact doping region; a plurality of contact through holes that penetrate the dielectric layer and extend to a position between two adjacent trench gate structures; and a plurality of contact structures located in the plurality of contact through holes.

[0013] In some embodiments of the present application, the depths of the plurality of contact structures are greater than the depth of the contact doping region and less than the depth of the well region.

[0014] In some embodiments of the present application, the semiconductor structure further includes: a front metal layer located on the surface of the dielectric layer, covering the dielectric layer and electrically connecting the plurality of contact structures; and a back metal layer located on the surface of the semiconductor substrate facing away from the epitaxial layer.

[0015] The beneficial effects of this application include but are not limited to the following:

[0016] By surrounding part of the trench gate structure with the shielding doping region, the area of ​​the gate dielectric layer in the trench gate structure exposed to the high electric field region is reduced. At the same time, there is no gate dielectric layer structure at the high electric field position in the center of the JFET region formed by the two adjacent shielding doping regions in the present application, which reduces the electric field stress in the gate dielectric layer. These two aspects achieve higher device gate reliability.

[0017] In the present invention, since a shielding doping region simultaneously shields two trench gate structures, a repeated power MOSFET unit has two channels, which improves the channel integration of the device, reduces the channel resistance, and thus reduces the on-resistance R of the device. on .

[0018] Due to the structural characteristics of the present invention, the carrier enrichment effect can be achieved by processing a narrow mesa structure. When the gate bias voltage is positive, the P-well and JFET regions in the MOSFET source region have a higher electron concentration, thereby having a smaller channel resistance and JFET region resistance; when the gate bias voltage is negative, the diode source region has a higher hole concentration, so that the diode region has a lower conduction voltage drop V sd , so the MOSFET structure of the present application has a low on-resistance R on and low diode V sd Advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The following figures describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale.

[0020] in:

[0021] Figures 1 to 12 It is a structural schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0023] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

[0024] Figures 1 to 12 The following is a schematic diagram of the structure of each step in the method for forming a semiconductor structure according to an embodiment of the present application. The method for forming a semiconductor structure according to an embodiment of the present application is described in detail in conjunction with the accompanying drawings.

[0025] refer to Figure 1 As shown, a semiconductor substrate 100 is provided, and an epitaxial layer 110 is formed on the surface of the semiconductor substrate 100 .

[0026] The semiconductor structure described in the embodiment of the present application is, for example, a power MOSFET device. In some embodiments, the material of the semiconductor substrate 100 is silicon carbide material, and the material of the epitaxial layer 110 is also silicon carbide material.

[0027] In some embodiments of the present application, the semiconductor substrate 100 may be made of other semiconductor materials other than silicon carbide, such as silicon. The second epitaxial layer 110 may also be made of other semiconductor materials other than silicon carbide, such as silicon.

[0028] In some embodiments of the present application, the epitaxial layer 110 may have doping ions, such as N-type doping ions. The doping concentration of the epitaxial layer 110 is, for example, 5E13 to 1E17 cm -3 The thickness of the epitaxial layer 110 is, for example, 2-200 microns.

[0029] refer to Figure 2 As shown, a contact doping region 120 is formed in the epitaxial layer 110. The doping concentration of the contact doping region 120 is greater than the doping concentration of the epitaxial layer 110. The doping type of the contact doping region 120 is the same as the doping type of the epitaxial layer 110, for example, N-type. The method of forming the contact doping region 120 is, for example, an ion implantation process.

[0030] In some embodiments of the present application, the doping concentration of the contact doping region 120 is 1E18 to 1E21 cm -3 The depth of the contact doping region 120 is 0.1-2 microns.

[0031] refer to Figure 3 As shown, shielding doping regions 130 are formed in the epitaxial layer 110 on both sides of the contact doping region 120. The shielding doping region 130 has a doping type opposite to that of the contact doping region 120, for example, P type. The shielding doping region 130 is formed by, for example, an ion implantation process.

[0032] In some embodiments of the present application, the doping concentration of the shielding doping region 130 is 1E16 to 3E19 cm -3 The depth of the shielding doping region 130 is 1-200 microns.

[0033] refer to Figure 4As shown, a well region 140 is formed in the epitaxial layer 110, and the doping type of the well region 140 is opposite to that of the contact doping region 120, for example, P type. The depth of the shielding doping region 130 is greater than the depth of the well region 140, and the depth of the contact doping region 120 is greater than the depth of the well region 140. The well region 140 surrounds the bottom and sidewalls of the contact doping region 120, and the well region 140 is also located on the sidewalls of the shielding doping region 130. The method of forming the well region 140 is, for example, an ion implantation process.

[0034] In some embodiments of the present application, the doping concentration of the well region 140 is 1E16 to 3E19 cm -3 The depth of the well region 140 is 0.2-4 microns.

[0035] The well region 140 is one of the key processes for realizing specific functions of the device in the manufacture of semiconductor devices, and it has an important influence on the performance and characteristics of the final device. The well region 140 and the contact doping region 120 form a MOSFET source region 141 (this MOSFET structure will be described later); the well region 140 forms a diode source region 142 in the shielding doping region 130 (a PN junction diode formed by the shielding doping region 130 and the epitaxial layer 110).

[0036] In some embodiments of the present application, the method for forming the semiconductor structure further comprises: performing a high temperature annealing process on the surface of the epitaxial layer 110. The temperature of the high temperature annealing process is 1600-1800 degrees Celsius, and the annealing time is 5-40 minutes. The high temperature annealing process can activate the ion-implanted impurities.

[0037] refer to Figures 5 to 7 As shown, a trench gate structure 150 penetrating part of the shielding doping region 130 , the well region 140 and the contact doping region 120 is formed on both sides of the shielding doping region 130 , and the depth of the trench gate structure 150 is greater than the depth of the well region 140 and less than the depth of the shielding doping region 130 .

[0038] refer to Figure 5 As shown, an etching process is performed to form a gate trench 153 on both sides of the shielding doping region 130 that penetrates part of the shielding doping region 130, the well region 140 and the contact doping region 120, respectively. The depth of the gate trench 153 is greater than the depth of the well region 140 and less than the depth of the shielding doping region 130.

[0039] refer to Figure 6 As shown, a gate dielectric layer 151 is formed at the bottom and sidewall of the gate trench 153. The material of the gate dielectric layer 151 includes a low-k or high-k insulating dielectric material such as silicon oxide or silicon nitride.

[0040] refer to Figure 7 As shown, a gate layer 152 filling the gate trench 153 is formed on the surface of the gate dielectric layer 151 , and the gate dielectric layer 151 and the gate layer 152 constitute the trench gate structure 150 .

[0041] In some embodiments of the present application, the material of the gate layer 152 is, for example, polysilicon. The method of forming the gate layer 152 includes a chemical vapor deposition process, etc.

[0042] In some embodiments of the present application, after the gate layer 152 is deposited, the polysilicon material needs to be annealed. This is a high-temperature heat treatment process to reduce lattice defects, increase grain size, and thus improve the electrical properties of the material. The annealing process helps to repair lattice damage that may occur during the deposition process and can promote the diffusion of doping elements.

[0043] refer to Figure 7 As shown, the MOSFET source region 141 formed by the well region 140 and the contact doping region 120 , and the two adjacent trench gate structures 150 are all part of a repeatable basic power MOSFET unit 160 .

[0044] refer to Figure 7 As shown, in the technical solution of the present application, the shielding doping region 130 surrounds part of the trench gate structure 150 (surrounding a side wall and part of the bottom surface of each trench gate structure 150), thereby reducing the area of ​​the gate dielectric layer 151 in the trench gate structure 150 exposed to the high electric field region; at the same time, there is no gate dielectric layer structure at the high electric field position in the center of the JFET region formed by two adjacent shielding doping regions 130 in the present application, thereby reducing the electric field stress in the gate dielectric layer. These two aspects achieve higher device gate reliability.

[0045] refer to Figure 7 As shown, in the technical solution of the present application, a shielding doping region 130 simultaneously shields two adjacent trench gate structures 150, so that a repeated power MOSFET unit 160 has two channels, which improves the channel integration of the device, reduces the channel resistance and thus reduces the on-resistance R of the device. on .

[0046] refer to Figure 7As shown, in some embodiments of the present application, the spacing between the two trench gate structures 150 on both sides of the contact doping region 120 is 0.01 to 1 micron, for example, 0.02 to 0.9 micron, 0.05 to 0.7 micron, 0.1 to 0.5 micron, 0.2 to 0.4 micron. The area between the two trench gate structures 150 on both sides of the contact doping region 120 is a semiconductor region mesa (Mesa). In the technical solution of the present application, this area only includes the contact doping region 120 and the well region 140, and the structure is single and simple, so the size of this area can be reduced.

[0047] That is to say, due to the structural characteristics of the present application, the carrier enrichment effect can be achieved by processing a narrow mesa structure. When the gate bias voltage is positive, the P-well and JFET regions of the MOSFET source region have a higher electron concentration, thereby having a smaller channel resistance and JFET region resistance; when the gate bias voltage is negative, the diode source region has a higher hole concentration, so that the diode region has a lower conduction voltage drop V sd , so the MOSFET structure of the present application has a low on-resistance R on and low diode V sd Advantages.

[0048] In some embodiments of the present application, the method for forming a semiconductor structure further includes: referring to Figure 8 As shown, a dielectric layer 170 covering the trench gate structure 150, the shielding doping region 130 and the contact doping region 120 is formed on the surface of the epitaxial layer 110; Fig. 9 As shown, a plurality of contact through holes 171 are formed which penetrate the dielectric layer 170 and extend to the position between two adjacent trench gate structures 150; Fig.10 As shown, a conductive material is filled in the plurality of contact through holes 171 to form a plurality of contact structures 180 .

[0049] In some embodiments of the present application, the depth of the plurality of contact structures 180 is greater than the depth of the contact doping region 120 and less than the depth of the well region 140 so as to short-circuit the contact doping region 120 and the well region 140 .

[0050] In some embodiments of the present application, the material of the dielectric layer 170 includes insulating dielectric materials such as silicon oxide or silicon nitride. The material of the contact structure 180 includes metal conductive materials such as tungsten or copper.

[0051] The contact structure 180 forms an ohmic contact with the MOSFET source region 141 and the diode source region 142. Ohmic contact refers to a low-resistance electrical contact formed between a semiconductor and other conductive materials (usually metals). Ideally, the resistance of the ohmic contact is negligible compared to the resistance inside the semiconductor material. This contact mode follows Ohm's law, that is, the current is proportional to the voltage, and the proportionality constant is the resistance. In semiconductor devices, ohmic contacts are often used in gates, sources, drains and other parts to achieve good current collection and transmission.

[0052] In some embodiments of the present application, the method for forming a semiconductor structure further includes: referring to Fig.11 As shown, a front metal layer 191 is formed on the surface of the dielectric layer 170 to cover the dielectric layer 170 and electrically connect the plurality of contact structures 180; Fig.12 As shown, a back metal layer 192 is formed on the surface of the semiconductor substrate 100 facing away from the epitaxial layer 110 .

[0053] In some embodiments of the present application, the material of the front metal layer 191 and the back metal layer 192 includes copper, aluminum, tungsten, etc.

[0054] The front metal layer refers to the metal interconnection located on the surface of the wafer or the front of the device. The front metal layer is used to form electrical connections inside the device, such as connecting the source, drain, gate, etc. of the transistor. In traditional IC design, most of the interconnection work is completed on the front side, including multi-layer interconnection technology, and these levels are connected through contact holes (vias). The back metal layer refers to the metal interconnection located on the back side of the wafer or the back side of the device. In some high-power or high-frequency applications, the back metal layer is used to provide additional electrical connections or as a heat dissipation path. For example, the back metal layer 192 in this embodiment can be used as a transistor drain. The back metal layer can also be used to form a substrate for the device to provide mechanical support and electrical connections.

[0055] The embodiment of the present application also provides a semiconductor structure, referring to Figure 7As shown, it includes: a semiconductor substrate 100, an epitaxial layer 110 is formed on the surface of the semiconductor substrate 100, and a contact doping region 120 is formed in the epitaxial layer 110; a shielding doping region 130 is located in the epitaxial layer 110 on both sides of the contact doping region 120, and the doping type of the shielding doping region 130 is opposite to that of the contact doping region 120; a well region 140 is located in the epitaxial layer 110 at the bottom of the contact doping region 120, and the doping type of the well region 140 is opposite to that of the contact doping region 120, wherein the depth of the shielding doping region 130 is greater than the depth of the well region 140 is greater than the depth of the contact doping region 120; a trench gate structure 150 is located on both sides of the shielding doping region 130, penetrates part of the shielding doping region 130, and is connected to the sidewalls of the well region 140 and the contact doping region 120, and the depth of the trench gate structure 150 is greater than the depth of the well region 140 and less than the depth of the shielding doping region 130.

[0056] The semiconductor structure described in the embodiment of the present application is, for example, a power MOSFET device. In some embodiments, the material of the semiconductor substrate 100 is silicon carbide material, and the material of the epitaxial layer 110 is also silicon carbide material.

[0057] In some embodiments of the present application, the semiconductor substrate 100 may be made of other semiconductor materials other than silicon carbide, such as silicon. The second epitaxial layer 110 may also be made of other semiconductor materials other than silicon carbide, such as silicon.

[0058] In some embodiments of the present application, the epitaxial layer 110 may have doping ions, such as N-type doping ions. The doping concentration of the epitaxial layer 110 is, for example, 5E13 to 1E17 cm -3 The thickness of the epitaxial layer 110 is, for example, 2-200 microns.

[0059] In some embodiments of the present application, the doping concentration of the contact doping region 120 is greater than the doping concentration of the epitaxial layer 110. The doping type of the contact doping region 120 is the same as the doping type of the epitaxial layer 110, for example, N-type.

[0060] In some embodiments of the present application, the doping concentration of the contact doping region 120 is 1E18 to 1E21 cm -3 The depth of the contact doping region 120 is 0.1-2 microns.

[0061] In some embodiments of the present application, the shielding doping region 130 and the contact doping region 120 have a doping type opposite to that of the contact doping region 120 , for example, a P-type.

[0062] In some embodiments of the present application, the doping concentration of the shielding doping region 130 is 1E16 to 3E19 cm -3 The depth of the shielding doping region 130 is 1-200 microns.

[0063] In some embodiments of the present application, the well region 140 has an opposite doping type to the contact doping region 120, for example, a P-type. The depth of the shielding doping region 130 is greater than the depth of the well region 140, which is greater than the depth of the contact doping region 120. The well region 140 surrounds the bottom and sidewalls of the contact doping region 120, and the well region 140 is also located on the sidewalls of the shielding doping region 130.

[0064] In some embodiments of the present application, the doping concentration of the well region 140 is 1E16-3E19 cm -3 The depth of the well region 140 is 0.2-4 microns.

[0065] The well region 140 is one of the key processes for realizing specific functions of a semiconductor device in manufacturing, and it has a significant impact on the performance and characteristics of the final device. Figure 4 As shown, the well region 140 and the contact doping region 120 form a MOSFET source region 141 ; the well region 140 forms a diode source region 142 in the shielding doping region 130 (a PN junction diode formed by the shielding doping region 130 and the epitaxial layer 110 ).

[0066] In some embodiments of the present application, the trench gate structure 150 includes a gate layer 152 and a gate dielectric layer 151 covering the bottom and sidewalls of the gate layer 150. The material of the gate dielectric layer 151 includes a low-k or high-k insulating dielectric material such as silicon oxide or silicon nitride. The material of the gate layer 152 is, for example, polysilicon.

[0067] refer to Figure 7 As shown, the MOSFET source region 141 formed by the well region 140 and the contact doping region 120 , and the two adjacent trench gate structures 150 are all part of a repeatable basic power MOSFET unit 160 .

[0068] refer to Figure 7 As shown, in the technical solution of the present application, the shielding doping region 130 surrounds part of the trench gate structure 150 (surrounding a side wall and part of the bottom surface of each trench gate structure 150), thereby reducing the area of ​​the gate dielectric layer 151 in the trench gate structure 150 exposed to the high electric field region; at the same time, there is no gate dielectric layer structure at the high electric field position in the center of the JFET region formed by two adjacent shielding doping regions 130 in the present application, thereby reducing the electric field stress in the gate dielectric layer. These two aspects achieve higher device gate reliability.

[0069] refer to Figure 7 As shown, in the technical solution of the present application, a shielding doping region 130 simultaneously shields two adjacent trench gate structures 150, so that a repeated power MOSFET unit 160 has two channels, which improves the channel integration of the device, reduces the channel resistance and thus reduces the on-resistance R of the device. on .

[0070] refer to Figure 7 As shown, in some embodiments of the present application, the spacing between the two trench gate structures 150 on both sides of the contact doping region 120 is 0.01 to 1 micron, for example, 0.02 to 0.9 micron, 0.05 to 0.7 micron, 0.1 to 0.5 micron, 0.2 to 0.4 micron. The area between the two trench gate structures 150 on both sides of the contact doping region 120 is a semiconductor region mesa (Mesa). In the technical solution of the present application, this area only includes the contact doping region 120 and the well region 140, and the structure is single and simple, so the size of this area can be reduced.

[0071] That is to say, due to the structural characteristics of the present application, the carrier enrichment effect can be achieved by processing a narrow mesa structure. When the gate bias voltage is positive, the P-well and JFET regions of the MOSFET source region have a higher electron concentration, thereby having a smaller channel resistance and JFET region resistance; when the gate bias voltage is negative, the diode source region has a higher hole concentration, so that the diode region has a lower conduction voltage drop V sd , so the MOSFET structure of the present application has a low on-resistance R on and low diode V sd Advantages.

[0072] refer to Fig.12 As shown, in some embodiments of the present application, the semiconductor structure also includes: a dielectric layer 170 covering the trench gate structure 150, the shielding doping region 130 and the contact doping region 120; a plurality of contact through holes 171 penetrating the dielectric layer 170 and extending to a position between two adjacent trench gate structures 150; and a plurality of contact structures 180 located in the plurality of contact through holes 171.

[0073] In some embodiments of the present application, the depth of the plurality of contact structures 180 is greater than the depth of the contact doping region 120 and less than the depth of the well region 140 so as to short-circuit the contact doping region 120 and the well region 140 .

[0074] In some embodiments of the present application, the material of the dielectric layer 170 includes insulating dielectric materials such as silicon oxide or silicon nitride. The material of the contact structure 180 includes metal conductive materials such as tungsten or copper.

[0075] The contact structure 180 forms an ohmic contact with the MOSFET source region 141 and the diode source region 142 .

[0076] refer to Fig.12 As shown, in some embodiments of the present application, the semiconductor structure also includes: a front metal layer 191 covering the dielectric layer 170 and electrically connecting the plurality of contact structures 180 ; and a back metal layer 192 located on the surface of the semiconductor substrate 100 facing away from the epitaxial layer 110 .

[0077] In some embodiments of the present application, the material of the front metal layer 191 and the back metal layer 192 includes copper, aluminum, tungsten, etc.

[0078] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0079] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can also be intermediate elements.

[0080] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or there can be intervening elements. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recited features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0081] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.

[0082] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, wherein an epitaxial layer is formed on the surface of the semiconductor substrate; forming a contact doped region in the epitaxial layer; forming a shielding doping region in the epitaxial layer on both sides of the contact doping region, wherein the shielding doping region has a doping type opposite to that of the contact doping region; forming a well region in the epitaxial layer, the well region having a doping type opposite to that of the contact doping region, wherein the depth of the shielding doping region is greater than the depth of the well region and greater than the depth of the contact doping region, the well region surrounds the bottom and sidewalls of the contact doping region, and the well region is also located on the sidewalls of the shielding doping region; A trench gate structure penetrating part of the shielding doping region, the well region and the contact doping region is formed on both sides of the shielding doping region, wherein the depth of the trench gate structure is greater than the depth of the well region and less than the depth of the shielding doping region.

2. The method for forming a semiconductor structure according to claim 1, wherein: The distance between the two trench gate structures on both sides of the contact doping region is 0.01 to 1 micron.

3. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: Forming a dielectric layer covering the trench gate structure, the shielding doping region and the contact doping region on the surface of the epitaxial layer; forming a plurality of contact through holes penetrating the dielectric layer and extending to a position between two adjacent trench gate structures; A conductive material is filled in the plurality of contact through holes to form a plurality of contact structures.

4. The method for forming a semiconductor structure according to claim 3, wherein: The depths of the plurality of contact structures are greater than the depth of the contact doping region and less than the depth of the well region.

5. The method for forming a semiconductor structure according to claim 3, wherein: Also includes: forming a front metal layer on the surface of the dielectric layer, covering the dielectric layer and electrically connecting the plurality of contact structures; A back metal layer is formed on a surface of the semiconductor substrate facing away from the epitaxial layer.

6. A semiconductor structure, characterized in that: include: A semiconductor substrate, wherein an epitaxial layer is formed on a surface of the semiconductor substrate, and a contact doping region is formed in the epitaxial layer; a shielding doping region, located in the epitaxial layer on both sides of the contact doping region, the shielding doping region and the contact doping region having a doping type opposite to that of the contact doping region; A well region is located in the epitaxial layer at the bottom of the contact doping region, the well region and the contact doping region have opposite doping types, wherein the depth of the shielding doping region is greater than the depth of the well region and greater than the depth of the contact doping region; A trench gate structure is located on both sides of the shielding doping region, penetrates part of the shielding doping region and is connected to the well region and the contact doping region. The depth of the trench gate structure is greater than the depth of the well region and less than the depth of the shielding doping region.

7. The semiconductor structure according to claim 6, wherein: The distance between the two trench gate structures on both sides of the contact doping region is 0.01 to 1 micron.

8. The semiconductor structure according to claim 6, wherein: Also includes: A dielectric layer, located on the surface of the epitaxial layer and covering the trench gate structure, the shielding doping region and the contact doping region; A plurality of contact through holes, penetrating the dielectric layer and extending to a position between two adjacent trench gate structures; A plurality of contact structures are located in the plurality of contact through holes.

9. The semiconductor structure according to claim 8, characterized in that The depths of the plurality of contact structures are greater than the depth of the contact doping region and less than the depth of the well region.

10. The semiconductor structure according to claim 8, wherein: Also includes: A front metal layer, located on the surface of the dielectric layer, covers the dielectric layer and is electrically connected to the plurality of contact structures; The back metal layer is located on the surface of the semiconductor substrate facing away from the epitaxial layer.

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