Semiconductor element and manufacturing method thereof
By using a gate oxide extension as a self-aligned silicide barrier layer in the self-aligned silicide fabrication process, a silicide layer can be formed directly on the heavily doped region, solving the complexity and cost problems of additional self-aligned silicide barrier layer deposition in the prior art, and achieving the effect of simplifying the process and reducing costs.
Patent Information
- Application Number
- CN202310895399.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-06
- Filing Date
- 2023-07-20
- Publication Date
- 2025-01-10
AI Technical Summary
Existing self-aligned silicide fabrication processes require additional deposition and patterning of self-aligned silicide barrier layers, increasing process complexity and cost.
By using the gate oxide extension as a self-aligned silicide barrier layer, and forming a silicide layer on the heavily doped region, additional deposition steps and photomask costs are reduced, and nickel silicide or cobalt silicide layers are formed directly on the heavily doped region.
It simplifies the process, reduces costs, improves production efficiency, and enables the formation of highly efficient silicide materials in the source/drain regions.
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Figure CN119300402A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a structure and a manufacturing method of a semiconductor element. Background Art
[0002] The self-aligned silicide manufacturing process has been used to form a silicide material that can reduce the sheet resistance of the source / drain region. The steps basically include: forming the source / drain region, then forming a metal layer such as cobalt, titanium or nickel on the source / drain region, and then performing rapid thermal processing (RTP) to make the metal layer react with the silicon of the gate structure and the source / drain region to form a metal silicide.
[0003] Typically, in the salicide manufacturing process, a self-aligned silicide barrier (SAB) is used to define the area where silicide is to be formed. For example, before forming a metal layer, a self-aligned silicide barrier composed of nitride is deposited on a semiconductor substrate, and then a portion of the self-aligned silicide barrier is etched away to expose the source / drain region on the semiconductor substrate. Summary of the invention
[0004] The main purpose of the present invention is to provide an improved semiconductor device and a method for manufacturing the same to solve the deficiencies or shortcomings of the prior art.
[0005] The present invention provides a semiconductor element on one hand, comprising a substrate; a channel region (channel region) disposed in the substrate; a diffusion region disposed in the substrate on one side of the channel region, the diffusion region comprising a lightly doped drain region and a heavily doped region located in the lightly doped drain region. A gate is disposed above the channel region, wherein the gate partially overlaps with the lightly doped drain region; a spacer is disposed on the sidewall of the gate; a gate oxide layer is disposed between the gate and the channel region, between the gate and the lightly doped drain region, and between the spacer and the lightly doped drain region; a gate oxide extension protrudes from the edge of the spacer and partially overlaps with the heavily doped region; and a silicide layer is disposed on the heavily doped region not covered by the gate oxide extension, and the silicide layer is spaced apart from the edge of the spacer.
[0006] According to an embodiment of the present invention, the spacer comprises silicon nitride.
[0007] According to an embodiment of the present invention, the gate oxide extension is thinner than the gate oxide layer.
[0008] According to an embodiment of the present invention, the gate oxide extension has a thickness of at least 30 angstroms.
[0009] According to an embodiment of the present invention, the thickness of the gate oxide layer is at least 80 angstroms.
[0010] According to an embodiment of the present invention, the silicide layer includes nickel silicide or cobalt silicide.
[0011] According to an embodiment of the present invention, the gate comprises metal.
[0012] According to an embodiment of the present invention, the silicide layer is adjacent to the gate oxide extension.
[0013] According to an embodiment of the present invention, the substrate is a silicon substrate having a first conductivity type, the channel region and the diffusion region are arranged in an ion well having the first conductivity type, wherein the heavily doped region and the lightly doped drain region have a second conductivity type opposite to the first conductivity type.
[0014] According to an embodiment of the present invention, the first conductivity type is P type, and the second conductivity type is N type.
[0015] Another aspect of the present invention provides a method for forming a semiconductor element, comprising: providing a substrate; forming a channel region in the substrate; forming a diffusion region in the substrate on one side of the channel region, the diffusion region comprising a lightly doped drain region and a heavily doped region located in the lightly doped drain region; forming a gate above the channel region, wherein the gate partially overlaps with the lightly doped drain region; forming a spacer on the sidewall of the gate; forming a gate oxide layer between the gate and the channel region, between the gate and the lightly doped drain region, and between the spacer and the lightly doped drain region; forming a gate oxide extension, the gate oxide extension protruding from the edge of the spacer and partially overlapping with the heavily doped region; and forming a silicide layer on the heavily doped region not covered by the gate oxide extension, and the silicide layer is spaced apart from the edge of the spacer.
[0016] According to an embodiment of the present invention, the gate oxide extension is thinner than the gate oxide layer.
[0017] According to an embodiment of the present invention, the gate oxide extension has a thickness of at least 30 angstroms.
[0018] According to an embodiment of the present invention, the thickness of the gate oxide layer is at least 80 angstroms.
[0019] According to an embodiment of the present invention, the silicide layer includes nickel silicide or cobalt silicide.
[0020] According to an embodiment of the present invention, the gate comprises metal.
[0021] According to an embodiment of the present invention, the silicide layer is adjacent to the gate oxide extension.
[0022] According to an embodiment of the present invention, according to an embodiment of the present invention, the substrate is a silicon substrate having a first conductivity type, the channel region and the diffusion region are arranged in an ion well having the first conductivity type, wherein the heavily doped region and the lightly doped drain region have a second conductivity type opposite to the first conductivity type.
[0023] According to an embodiment of the present invention, the first conductivity type is P type, and the second conductivity type is N type.
[0024] On the other hand, the present invention provides a semiconductor element, comprising: a substrate; a channel region, arranged in the substrate; a diffusion region, arranged in the substrate on one side of the channel region, the diffusion region comprising a lightly doped drain region and a heavily doped region located in the lightly doped drain region; a gate, arranged above the channel region, wherein the gate partially overlaps with the lightly doped drain region; a spacer, arranged on the side wall of the gate; a gate oxide layer, arranged between the gate and the channel region, between the gate and the lightly doped drain region, and between the spacer and the lightly doped drain region; and a silicide layer, arranged on the heavily doped region and spaced apart from the edge of the spacer. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 A schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention;
[0026] Figures 2 to 4 For a formation Figure 1 A schematic diagram of a method for a semiconductor element in the embodiment of the present invention;
[0027] Figure 5 is a schematic diagram showing that gate oxide extensions on both sides of a gate of a semiconductor device are removed after forming a silicide layer;
[0028] Figure 6 A schematic diagram of a semiconductor device having an asymmetric diffusion region;
[0029] Figure 7 Schematic diagram of a semiconductor device with an asymmetric gate oxide extension.
[0030] Explanation of symbols
[0031] 1 Semiconductor components
[0032] 100 Base
[0033] 110 Shallow Trench Insulation Structure
[0034] 120 Ion Trap
[0035] 130 Lightly doped drain region
[0036] 131 Lightly doped drain region
[0037] 140 Heavily doped region
[0038] 210 Gate
[0039] 220 Spacer
[0040] 220e Edge
[0041] 230 Gate Oxide
[0042] 230a Gate oxide extension
[0043] 250 Silicide layer
[0044] AA active area
[0045] CH Channel Area
[0046] F Diffusion zone
[0047] PR patterning photoresist pattern DETAILED DESCRIPTION
[0048] In the following, the details will be described with reference to the accompanying drawings, which also constitute part of the detailed description of the specification and are illustrated in a specific way that the embodiment can be implemented. The following embodiments have been described in sufficient detail to enable a person skilled in the art to implement them.
[0049] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered as limiting, but rather, the embodiments included therein will be defined by the appended claims.
[0050] See also Figure 1 , which is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, a semiconductor element 1, such as a medium voltage or high voltage transistor element, includes a substrate 100, such as a semiconductor substrate. According to an embodiment of the present invention, a shallow trench insulation structure 110 is provided in the substrate 100 to define an active area AA. According to an embodiment of the present invention, a channel region CH is provided in the substrate 100. According to an embodiment of the present invention, a diffusion region F is provided in the substrate 100 on one side of the channel region CH. The diffusion region F includes a lightly doped drain (LDD) region 130 and a heavily doped region 140 located in the lightly doped drain region 130. In other embodiments, the semiconductor element 1 may be a low voltage transistor element.
[0051] According to an embodiment of the present invention, for example, the substrate 100 is a silicon substrate with a first conductivity type. For example, the first conductivity type is P type. For example, the substrate 100 is a P type silicon substrate. According to an embodiment of the present invention, for example, an ion well 120 with a first conductivity type is further provided in the substrate 100, for example, a P type well, and the channel region CH and the diffusion region F are both provided in the ion well 120, wherein the heavily doped region 140 and the lightly doped drain region 130 have a second conductivity type opposite to the first conductivity type. According to an embodiment of the present invention, for example, the second conductivity type is N type. The above electrical properties are merely illustrative, and those familiar with the technical field should understand that the semiconductor element 1 of the present invention can be an NMOS element or a PMOS element.
[0052] According to an embodiment of the present invention, a gate 210 is disposed above the channel region CH, wherein the gate 210 partially overlaps with the lightly doped drain region 130. According to an embodiment of the present invention, the gate 210 may include a metal, such as copper, aluminum, tungsten, titanium, titanium nitride, or any combination thereof. According to an embodiment of the present invention, the gate 210 may include polysilicon.
[0053] According to an embodiment of the present invention, a spacer 220 is disposed on the sidewall of the gate 210. According to an embodiment of the present invention, for example, the spacer 220 may include silicon nitride.
[0054] According to an embodiment of the present invention, the semiconductor device 1 further includes a gate oxide layer 230 disposed between the gate 210 and the channel region CH, between the gate 210 and the lightly doped drain region 130, and between the spacer 220 and the lightly doped drain region 130. According to an embodiment of the present invention, the thickness of the gate oxide layer 230 is at least 80 angstroms. According to an embodiment of the present invention, the thickness of the spacer 220 is at least 15 nm.
[0055] According to an embodiment of the present invention, the semiconductor device 1 further includes a gate oxide extension 230a, which protrudes from the edge 220e of the spacer 220 and partially overlaps with the heavily doped region 140. According to an embodiment of the present invention, the gate oxide extension 230a is thinner than the gate oxide layer 230. According to an embodiment of the present invention, the thickness of the gate oxide extension 230a is at least 30 angstroms. According to an embodiment of the present invention, the gate oxide extension 230a protrudes from the edge 220e of the spacer 220 by at least 30 nm.
[0056] According to an embodiment of the present invention, the semiconductor device 1 further includes a silicide layer 250, which is disposed on the heavily doped region 140 not covered by the gate oxide extension 230a, and the silicide layer 250 is spaced apart from the edge 220e of the spacer 220. According to an embodiment of the present invention, the silicide layer 250 may include nickel silicide or cobalt silicide, but is not limited thereto. According to an embodiment of the present invention, the silicide layer 250 is adjacent to the gate oxide extension 230a.
[0057] Figures 2 to 4 Example of a formation Figure 1 First, as Figure 2 As shown, a substrate 100 is provided, for example, a semiconductor substrate. According to an embodiment of the present invention, a shallow trench isolation structure 110 is formed in the substrate 100 to define an active area AA. According to an embodiment of the present invention, a channel region CH is formed in the substrate 100. According to an embodiment of the present invention, a diffusion region F is formed in the substrate 100 on one side of the channel region CH by using an ion implantation process. According to an embodiment of the present invention, for example, the diffusion region F includes a lightly doped drain region 130 and a heavily doped region 140 located in the lightly doped drain region 130.
[0058] According to an embodiment of the present invention, for example, the substrate 100 is a silicon substrate with a first conductivity type. For example, the first conductivity type is P type. For example, the substrate 100 is a P type silicon substrate. According to an embodiment of the present invention, for example, an ion well 120 with a first conductivity type is formed in the substrate 100, for example, a P type well, and the channel region CH and the diffusion region F are both formed in the ion well 120, wherein the heavily doped region 140 and the lightly doped drain region 130 have a second conductivity type opposite to the first conductivity type. According to an embodiment of the present invention, for example, the second conductivity type is N type.
[0059] According to an embodiment of the present invention, a gate oxide layer 230 is then formed above the channel region CH, and is disposed on the channel region CH, the lightly doped drain region 130, and the heavily doped region 140. According to an embodiment of the present invention, the thickness of the gate oxide layer 230 is at least 80 angstroms. According to an embodiment of the present invention, for example, the gate oxide layer 230 can be formed by a thermal oxidation method or a chemical vapor deposition method.
[0060] According to an embodiment of the present invention, a gate 210 is then formed above the channel region CH, wherein the gate 210 partially overlaps with the lightly doped drain region 130. According to an embodiment of the present invention, the gate 210 may include a metal, such as copper, aluminum, tungsten, titanium, titanium nitride, or any combination thereof. According to an embodiment of the present invention, the gate 210 may include polysilicon. A spacer 220 is then formed on the sidewall of the gate 210. According to an embodiment of the present invention, for example, the spacer 220 may include silicon nitride.
[0061] The anisotropic dry etching performed during the formation of the spacer 220 slightly etches away a portion of the gate oxide layer 230 that is not covered by the gate 210 and the spacer 220, forming a gate oxide extension 230a protruding from the edge 220e of the spacer 220. According to an embodiment of the present invention, the gate oxide extension 230a is thinner than the gate oxide layer 230. According to an embodiment of the present invention, the thickness of the gate oxide extension 230a is at least 30 angstroms.
[0062] like Figure 3 As shown, then, a photolithography process is performed to form a patterned photoresist pattern PR on the substrate 100, covering the gate 210, the spacer 220 and a portion of the gate oxide extension 230a. Then, an etching process is performed, for example, a dry etching process, to etch away the gate oxide extension 230a not covered by the patterned photoresist pattern PR, revealing a portion of the heavily doped region 140. Subsequently, the patterned photoresist pattern PR is removed.
[0063] like Figure 4 As shown, a self-aligned silicide manufacturing process is then performed to form a silicide layer 250 on the heavily doped region 140, and the silicide layer 250 is spaced apart from the edge 220e of the spacer 220. In the aforementioned self-aligned silicide manufacturing process, the gate oxide extension 230a is used as a self-aligned silicide blocking layer, so the advantage of using the present invention is that there is no need to deposit a self-aligned silicide blocking layer and pattern the self-aligned silicide blocking layer and the cost of a photomask. For example, the aforementioned self-aligned silicide manufacturing process includes: firstly depositing a metal layer, such as cobalt, titanium or nickel, on the substrate 100, and then performing a rapid thermal treatment to react the metal layer with the silicon of the gate structure and the source / drain region to form a metal silicide, and then removing the incompletely reacted metal layer.
[0064] The semiconductor element 1 provided by the present invention comprises: a substrate 100; a channel region CH, which is arranged in the substrate 100; a diffusion region F, which is arranged in the substrate 100 on one side of the channel region CH, and the diffusion region F comprises a lightly doped drain region 130 and a heavily doped region 140 located in the lightly doped drain region; a gate 210, which is arranged above the channel region CH, wherein the gate 210 partially overlaps with the lightly doped drain region 130; a spacer 220, which is arranged on the sidewall of the gate 210; a gate oxide layer 230, which is arranged between the gate 210 and the channel region CH, between the gate 210 and the lightly doped drain region 130, and between the spacer 220 and the lightly doped drain region 130; and a silicide layer 250, which is arranged on the heavily doped region 140 and is spaced apart from an edge 220e of the spacer 220. According to some embodiments of the present invention, the semiconductor element 1 may further comprise a gate oxide extension 230a, which protrudes from the edge 220e of the spacer 220 and partially overlaps with the heavily doped region 140. In some embodiments, as Figure 5 As shown, the gate oxide extensions 230 a on both sides of the gate 210 may be removed after forming the silicide layer 250 .
[0065] Figure 1 The diffusion region F of the semiconductor element 1 is a left-right symmetrical structure. However, in other embodiments, the diffusion region F may also be a left-right asymmetrical structure, such as Figure 6 As shown. Figure 6For example, the diffusion region F on the right further includes a lightly doped drain region 131 , and the lightly doped drain region 130 is formed in the lightly doped drain region 131 .
[0066] Figure 1 The gate oxide extension portion 230a of the semiconductor device 1 is a left-right symmetrical structure. However, in other embodiments, the gate oxide extension portion 230a may also be a left-right asymmetrical structure, such as Figure 7 As shown. Figure 7 For example, the gate oxide extension 230 a on the left side of the gate 210 is removed, so that when a self-aligned silicide manufacturing process is subsequently performed, the silicide layer 250 on the left side will extend to the bottom of the sidewall 220 e of the spacer 220 .
[0067] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.
Claims
1. A semiconductor device comprising: substrate; a channel region disposed in the substrate; A diffusion region is disposed in the substrate at one side of the channel region, the diffusion region comprising a lightly doped drain region and a heavily doped region located in the lightly doped drain region; A gate is disposed above the channel region, wherein the gate partially overlaps with the lightly doped drain region; A spacer is disposed on the side wall of the gate; A gate oxide layer is disposed between the gate and the channel region, between the gate and the lightly doped drain region, and between the spacer and the lightly doped drain region; A gate oxide extension protrudes from an edge of the spacer and partially overlaps the heavily doped region; and The silicide layer is disposed on the heavily doped region not covered by the gate oxide extension, and the silicide layer is spaced apart from the edge of the spacer.
2. The semiconductor device according to claim 1, wherein The spacer comprises silicon nitride.
3. The semiconductor device according to claim 1, wherein: The gate oxide extension is thinner than the gate oxide layer.
4. The semiconductor device according to claim 3, wherein: The gate oxide extension has a thickness of at least 30 angstroms.
5. The semiconductor device according to claim 3, wherein: The gate oxide layer has a thickness of at least 80 angstroms.
6. The semiconductor device according to claim 1, wherein The silicide layer includes nickel silicide or cobalt silicide.
7. The semiconductor device according to claim 1, wherein: The gate includes metal.
8. The semiconductor device according to claim 1, wherein: The silicide layer is adjacent to the gate oxide extension.
9. The semiconductor device according to claim 1, wherein: The substrate is a silicon substrate with a first conductivity type. The channel region and the diffusion region are arranged in an ion well with the first conductivity type. The heavily doped region and the lightly doped drain region have a second conductivity type opposite to the first conductivity type.
10. The semiconductor device according to claim 9, wherein The first conductivity type is P type, and the second conductivity type is N type.
11. A method for forming a semiconductor device, comprising: providing a substrate; forming a channel region in the substrate; forming a diffusion region in the substrate at one side of the channel region, the diffusion region comprising a lightly doped drain region and a heavily doped region located in the lightly doped drain region; A gate is formed above the channel region, wherein The gate partially overlaps with the lightly doped drain region; forming a spacer on a sidewall of the gate; forming a gate oxide layer between the gate and the channel region, between the gate and the lightly doped drain region, and between the spacer and the lightly doped drain region; forming a gate oxide extension, the gate oxide extension protruding from an edge of the spacer and overlapping the heavily doped region; as well as A silicide layer is formed on the heavily doped region not covered by the gate oxide extension, and the silicide layer is spaced apart from an edge of the spacer.
12. The method of claim 11, wherein: The gate oxide extension is thinner than the gate oxide layer.
13. The method of claim 12, wherein: The gate oxide extension has a thickness of at least 30 angstroms.
14. The method of claim 13, wherein: The gate oxide layer has a thickness of at least 80 angstroms.
15. The method of claim 11, wherein: The silicide layer includes nickel silicide or cobalt silicide.
16. The method of claim 11, wherein: The gate includes metal.
17. The method of claim 11, wherein: The silicide layer is adjacent to the gate oxide extension.
18. The method of claim 11, wherein: The substrate is a silicon substrate with a first conductivity type. The channel region and the diffusion region are arranged in an ion well with the first conductivity type. The heavily doped region and the lightly doped drain region have a second conductivity type opposite to the first conductivity type.
19. The method of claim 18, wherein: The first conductivity type is P type, and the second conductivity type is N type.
20. A semiconductor device comprising: substrate; a channel region disposed in the substrate; A diffusion region is disposed in the substrate at one side of the channel region, the diffusion region comprising a lightly doped drain region and a heavily doped region located in the lightly doped drain region; A gate is disposed above the channel region, wherein the gate partially overlaps with the lightly doped drain region; A spacer is disposed on the side wall of the gate; A gate oxide layer is disposed between the gate and the channel region, between the gate and the lightly doped drain region, and between the spacer and the lightly doped drain region; and The silicide layer is disposed on the heavily doped region and is spaced apart from the edge of the spacer.