Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a substrate, sub-pixels and a plurality of data lines, wherein the substrate comprises a display area and a first frame area; a plurality of data lines are located in the display area and extend to the first frame area from the display area, any data line comprises a fan-out line located in the first frame area, the resistance of the fan-out line is set to be R1, the preset resistance is set to be R0, R1 is smaller than or equal to R0, and R0 is larger than or equal to 2.5 k omega and smaller than or equal to 10 k omega.

Description

Technical Field

[0001] The present invention relates to display technology, and more particularly to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility and low cost. At present, the display substrate has a problem of turning red on the entire surface under heavy load. Summary of the invention

[0003] The present application provides a display substrate, including:

[0004] A substrate, comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a first frame area located at one side of the display area;

[0005] A plurality of sub-pixels are located in the display area;

[0006] A plurality of data lines are located in the display area and extend from the display area to the first border area, the plurality of data lines are electrically connected to the plurality of sub-pixels, each of the plurality of data lines includes a fan-out line located in the first border area, the resistance of the fan-out line is set to R1, the preset resistance is set to R0, R1≤R0, 2.5kΩ≤R0≤10kΩ.

[0007] In some exemplary embodiments, the first border area includes a first fan-out area, and the fan-out line includes a first fan-out line located in the first fan-out area;

[0008] The first fan-out line includes a first connection line and a second connection line, one end of the first connection line extends toward the display area, the other end of the first connection line is connected to the second connection line, and a cross-sectional area of ​​the first connection line is greater than a cross-sectional area of ​​the second connection line.

[0009] In some exemplary embodiments, the first fan-out region includes a first corner region and a second corner region, and a position where the first connection line and the second connection line meet is located at one of the first corner region and the second corner region;

[0010] The line width of the first connection line is greater than the line width of the second connection line.

[0011] In some exemplary embodiments, the line width of the first connection line is set to be consistent along an extension direction of the first connection line.

[0012] In some exemplary embodiments, the line width of the first connection line is configured to gradually decrease in a direction away from the display area.

[0013] In some exemplary embodiments, the first connection line includes a plurality of sub-connection lines arranged sequentially along an extension direction of the first connection line, and the line widths of the plurality of sub-connection lines are configured to decrease sequentially from one end close to the display area to one end connected to the second connection line.

[0014] In some exemplary embodiments, the first fan-out line is configured as a zigzag line, the first connection line and the second connection line both extend along a straight line, and an angle between the first connection line and the second connection line is configured as α, 100°≤α≤175°.

[0015] In some exemplary embodiments, a plurality of first fan-out lines are provided, and the plurality of first fan-out lines are spaced apart in a direction parallel to the substrate, a distance between first connection lines of adjacent first fan-out lines is a first distance, a distance between second connection lines of adjacent first fan-out lines is a second distance, and the first distance is greater than the second distance;

[0016] The line width of the first connecting line is equal to the line width of the second connecting line;

[0017] The first connection line includes a first routing layer and a second routing layer stacked in a direction perpendicular to the substrate, and the second connection line includes a third routing layer, which is arranged in the same layer as the first routing layer or the second routing layer.

[0018] In some exemplary embodiments, a plurality of first fan-out lines are provided, and the plurality of first fan-out lines are arranged at equal intervals in a direction parallel to the substrate;

[0019] A distance between adjacent first connection lines of the first fan-out lines is a first distance, a distance between adjacent second connection lines of the first fan-out lines is a second distance, and the first distance is equal to the second distance.

[0020] In some exemplary embodiments, the line width of the first fan-out line is set to be greater than 2 microns;

[0021] The line width of the first fan-out line is set to L0, 2μm≤L0≤5μm.

[0022] In some exemplary embodiments, R1 ≤ 2.5 kΩ.

[0023] In some exemplary embodiments, the display substrate also includes a plurality of parallel driving circuit lines located in the first border area, the plurality of driving circuit lines are configured to be electrically connected to a plurality of gate driving circuits, the plurality of driving circuit lines include AC signal lines and DC signal lines, and the line width of the DC signal line is greater than the line width of the AC signal line.

[0024] In some exemplary embodiments, the first border area includes a circuit routing area, and the circuit routing area is located on a side of the first fan-out area away from the display area;

[0025] The circuit routing area includes a first area and a second area, the first area and the second area are sequentially arranged along the circumference of the display area, the minimum distance between an edge of the first area close to the display area and an edge far from the display area is set to a third distance, the minimum distance between an edge of the second area close to the display area and an edge far from the display area is set to a fourth distance, and the third distance is smaller than the fourth distance;

[0026] At least one driving circuit routing line among the plurality of driving circuit routing lines comprises a first routing line and a second routing line, the first routing line is located in the first area, the second routing line is located in the second area, and a line width of the first routing line is smaller than a line width of the second routing line.

[0027] In some exemplary embodiments, the first border area further includes a second fan-out area, and the second fan-out area is located on a side of the first fan-out area away from the display area;

[0028] The fan-out line also includes a second fan-out line located in the second fan-out area, and a plurality of second fan-out lines are provided. The plurality of second fan-out lines include a third routing line and a fourth routing line. The line length of the third routing line is greater than the line length of the fourth routing line, and the line width of the third routing line is greater than the line width of the fourth routing line.

[0029] In some exemplary embodiments, at least one of the second fan-out lines includes a fourth routing layer and a fifth routing layer stacked in a direction perpendicular to the substrate.

[0030] In some exemplary embodiments, the display substrate includes a plurality of first power lines and a first power pin, the plurality of first power lines are located in the display area and are electrically connected to the plurality of sub-pixels, the first power pin is located in the first frame area, and the plurality of first power lines are electrically connected to the first power pin;

[0031] A portion of at least one second fan-out line is located on a side of the first power pin close to an edge of the display substrate, and an orthographic projection of at least one second fan-out line on the substrate overlaps with an orthographic projection of the first power pin on the substrate.

[0032] In some exemplary embodiments, the display substrate includes a second power line and a second power pin, the second power line is located in the peripheral area and at least partially surrounds the display area, the second power pin is located in the first frame area, and the second power line is connected to the second power pin;

[0033] A portion of at least one second fan-out line is located on a side of the second power pin away from the first power pin, and an orthographic projection of at least one second fan-out line on the substrate overlaps with both orthographic projections of the first power pin and the second power pin on the substrate.

[0034] In some exemplary embodiments, the device further comprises a plurality of driving circuit lines located in the peripheral region, and at least a portion of the line segments of the at least one second fan-out line is located between the second power pin and the plurality of driving circuit lines.

[0035] An embodiment of the present application provides a display device, including the above-mentioned display substrate.

[0036] The display substrate of the embodiment of the present application can reduce the impedance of the wiring and reduce crosstalk, thereby solving the problem of the screen turning red when overloaded. The display substrate of this exemplary embodiment can reduce the space occupied by the AC signal line without reducing the DC signal line, ensuring that the drive circuit wiring is not burned, and making room for widening the data line. The display substrate of this exemplary embodiment can take advantage of the large free space in the second fan-out area to reduce the wiring resistance in the second fan-out area, and further reduce the impedance of the data line.

[0037] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0039] Figure 1 is a structural schematic diagram of a display device;

[0040] Figure 2 It is a schematic diagram of a planar structure of a display substrate;

[0041] Figure 3 is a schematic diagram of a display substrate of this exemplary embodiment;

[0042] Figure 4 for Figure 3 A local enlarged schematic diagram of the A in FIG.

[0043] Figure 5 for Figure 3 A schematic diagram of a partial cross section of aa in FIG.

[0044] Figure 6 for Figure 4 A local enlarged schematic diagram of point C in FIG.

[0045] Figure 7 for Figure 3 A local enlarged schematic diagram of point B in FIG.

[0046] Figure 8 for Figure 6 A local enlarged schematic diagram of point D in FIG.

[0047] Fig. 9 is a schematic diagram of a first fan-out line of this exemplary embodiment;

[0048] Fig.10 is a partial schematic diagram of a first border area of ​​this exemplary embodiment;

[0049] Fig.11 is a partial schematic diagram of another first border area of ​​this exemplary embodiment;

[0050] Fig.12 is a partial schematic diagram of another first border area of ​​this exemplary embodiment;

[0051] Fig.13 for Fig.12 Schematic diagram of the GG section;

[0052] Fig.14 for Fig.12 Schematic diagram of the JJ section;

[0053] Fig.15 is a partial schematic diagram of another first border area of ​​this exemplary embodiment;

[0054] Fig.16 is a partial schematic diagram of another first border area of ​​this exemplary embodiment;

[0055] Fig.17 for Figure 6 A local enlarged schematic diagram of point E in FIG.

[0056] Fig.18 for Figure 7 FF cross-sectional diagram;

[0057] Fig.19 for Figure 7 Schematic diagram of the HH section;

[0058] Fig. 20 for Figure 7 Schematic diagram of the KK section. DETAILED DESCRIPTION

[0059] The present application describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present application. Although many possible feature combinations are shown in the drawings and discussed in the specific embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0060] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements disclosed in the present application may also be combined with any conventional features or elements to form a unique invention scheme. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme. Therefore, it should be understood that any feature shown and / or discussed in the present application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0061] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps of the specific order described. As will be understood by those of ordinary skill in the art, other sequences of steps are also possible. Therefore, the specific sequence of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these sequences can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0062] In some exemplary embodiments, a display substrate includes:

[0063] A substrate, comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a first frame area located at one side of the display area;

[0064] A plurality of sub-pixels are located in the display area;

[0065] A plurality of data lines are located in the display area and extend from the display area to the first border area, the plurality of data lines are electrically connected to the plurality of sub-pixels, each of the plurality of data lines includes a fan-out line located in the first border area, the resistance of the fan-out line is set to R1, the preset resistance is set to R0, R1≤R0, 2.5kΩ≤R0≤10kΩ.

[0066] In some exemplary embodiments, the first border area includes a first fan-out area, and the fan-out line includes a first fan-out line located in the first fan-out area;

[0067] The first fan-out line includes a first connection line and a second connection line, one end of the first connection line extends toward the display area, the other end of the first connection line is connected to the second connection line, and a cross-sectional area of ​​the first connection line is greater than a cross-sectional area of ​​the second connection line.

[0068] In some exemplary embodiments, the first fan-out region includes a first corner region and a second corner region, and a position where the first connection line and the second connection line meet is located at one of the first corner region and the second corner region;

[0069] The line width of the first connection line is greater than the line width of the second connection line.

[0070] In some exemplary embodiments, the line width of the first connection line is configured to gradually decrease in a direction away from the display area.

[0071] In some exemplary embodiments, the first fan-out line is configured as a zigzag line, the first connection line and the second connection line both extend along a straight line, and an angle between the first connection line and the second connection line is configured as α, 100°≤α≤175°.

[0072] In some exemplary embodiments, a plurality of first fan-out lines are provided, and the plurality of first fan-out lines are spaced apart in a direction parallel to the substrate, a distance between first connection lines of adjacent first fan-out lines is a first distance, a distance between second connection lines of adjacent first fan-out lines is a second distance, and the first distance is greater than the second distance;

[0073] The line width of the first connecting line is equal to the line width of the second connecting line;

[0074] The first connection line includes a first routing layer and a second routing layer stacked in a direction perpendicular to the substrate, and the second connection line includes a third routing layer, which is arranged in the same layer as the first routing layer or the second routing layer.

[0075] In some exemplary embodiments, R1 ≤ 2.5 kΩ.

[0076] In some exemplary embodiments, the display substrate also includes a plurality of parallel driving circuit lines located in the first border area, the plurality of driving circuit lines are configured to be electrically connected to a plurality of gate driving circuits, the plurality of driving circuit lines include AC signal lines and DC signal lines, and the line width of the DC signal line is greater than the line width of the AC signal line.

[0077] In some exemplary embodiments, the first border area includes a circuit routing area, and the circuit routing area is located on a side of the first fan-out area away from the display area;

[0078] The circuit routing area includes a first area and a second area, the first area and the second area are sequentially arranged along the circumference of the display area, the minimum distance between an edge of the first area close to the display area and an edge far from the display area is set to a third distance, the minimum distance between an edge of the second area close to the display area and an edge far from the display area is set to a fourth distance, and the third distance is smaller than the fourth distance;

[0079] At least one driving circuit routing line among the plurality of driving circuit routing lines comprises a first routing line and a second routing line, the first routing line is located in the first area, the second routing line is located in the second area, and a line width of the first routing line is smaller than a line width of the second routing line.

[0080] In some exemplary embodiments, the first border area further includes a second fan-out area, and the second fan-out area is located on a side of the first fan-out area away from the display area;

[0081] The fan-out line also includes a second fan-out line located in the second fan-out area, and a plurality of second fan-out lines are provided. The plurality of second fan-out lines include a third routing line and a fourth routing line. The line length of the third routing line is greater than the line length of the fourth routing line, and the line width of the third routing line is greater than the line width of the fourth routing line.

[0082] In some exemplary embodiments, at least one of the second fan-out lines includes a fourth routing layer and a fifth routing layer stacked in a direction perpendicular to the substrate.

[0083] In some exemplary embodiments, the display substrate includes a plurality of first power lines and a first power pin, the plurality of first power lines are located in the display area and are electrically connected to the plurality of sub-pixels, the first power pin is located in the first frame area, and the plurality of first power lines are electrically connected to the first power pin;

[0084] At least one of the second fan-out lines is located on a side of the first power pin close to an edge of the display substrate, and an orthographic projection of at least one of the second fan-out lines on the substrate overlaps with an orthographic projection of the first power pin on the substrate.

[0085] In some exemplary embodiments, the display substrate includes a second power line and a second power pin, the second power line is located in the peripheral area and at least partially surrounds the display area, the second power pin is located in the first frame area, and the second power line is connected to the second power pin;

[0086] A portion of at least one second fan-out line is located on a side of the second power pin away from the first power pin, and an orthographic projection of at least one second fan-out line on the substrate overlaps with both orthographic projections of the first power pin and the second power pin on the substrate.

[0087] In some exemplary embodiments, the device further comprises a plurality of driving circuit lines located in the peripheral region, and at least a portion of the line segments of the at least one second fan-out line is located between the second power pin and the plurality of driving circuit lines.

[0088] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include a pixel driving circuit, and the pixel driving circuit is connected to the scan signal line, the light emitting signal line and the data signal line. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specifications of the data driver to the data driver, may provide a clock signal suitable for the specifications of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specifications of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values ​​and control signals received from the timing controller. For example, the data driver can sample grayscale values ​​using a clock signal, and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn in units of unit lines, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm. For example, the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number. The light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0089] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting device, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to the scanning signal line, the light-emitting signal line, and the data signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0090] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 may be a green sub-pixel (G) emitting green light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged in a horizontal parallel, vertical parallel or triangular manner, which is not limited in the present disclosure.

[0091] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0092] Figure 3 is a schematic diagram of a display substrate of this exemplary embodiment, Figure 4 for Figure 3 A local enlarged schematic diagram, Figure 5 for Figure 3 A partial cross-sectional diagram of aa in FIG. Figure 6 for Figure 4 A local enlarged schematic diagram of point C in the figure. Figure 5 The structure of a sub-pixel in the display area is taken as an example for illustration. Figure 5 In the figure, a pixel circuit of each sub-pixel includes a transistor 21 and a capacitor 22 as an example for illustration. The transistor 21 may be a low temperature polysilicon thin film transistor.

[0093] In some exemplary embodiments, Figure 5As shown, in the direction perpendicular to the display substrate, the display area of ​​the display substrate may include at least: a substrate 10, and a circuit structure layer 12, a light emitting structure layer 13 and a packaging structure layer 14 sequentially arranged on the substrate 10. The circuit structure layer 12 may include at least: a pixel circuit of a plurality of sub-pixels, and the pixel circuit of each sub-pixel may include a plurality of transistors and at least one capacitor. The light emitting structure layer 13 may include at least: a light emitting element of a plurality of sub-pixels. In other examples, a touch structure layer may be provided on the side of the packaging structure layer 14 away from the substrate 10 to integrate a touch function.

[0094] In some exemplary embodiments, Figure 5 As shown, the circuit structure layer 12 of the display area may include: a shielding layer 200 arranged on the substrate 10, a semiconductor layer, a first conductive layer (also referred to as a first gate metal layer), a second conductive layer (also referred to as a second gate metal layer), a third conductive layer (also referred to as a first source-drain metal layer) and a fourth conductive layer (also referred to as a second source-drain metal layer). A first insulating layer (also called a buffer layer) 101 may be provided between the blocking layer 200 and the semiconductor layer; a second insulating layer (also called a first gate insulating layer) 102 may be provided between the semiconductor layer and the first conductive layer; a third insulating layer (also called a second gate insulating layer) 103 may be provided between the first conductive layer and the second conductive layer; a fourth insulating layer (also called an interlayer insulating layer) 104 may be provided between the second conductive layer and the third conductive layer; a fifth insulating layer (also called a passivation layer) 105 and a sixth insulating layer (also called a first flat layer) 106 may be provided between the third conductive layer and the fourth conductive layer, and the sixth insulating layer 106 may be located on the side of the fifth insulating layer 105 away from the substrate 10; a seventh insulating layer (also called a second flat layer) 107 may be provided on the side of the fourth conductive layer away from the substrate 10. The first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104 and the fifth insulating layer 105 may be inorganic insulating layers, and the sixth insulating layer 106 and the seventh insulating layer 107 may be organic insulating layers. However, this embodiment is not limited to this. In other examples, the fifth insulating layer may be omitted between the third conductive layer and the fourth conductive layer, and only the sixth insulating layer may be provided between the third conductive layer and the fourth conductive layer.

[0095] In some exemplary embodiments, Figure 5As shown, the semiconductor layer of the display area may include: an active layer 210 of a transistor 21 of a pixel circuit. The active layer 210 of the transistor 21 may include: a first area 2101, a second area 2102, and a channel area 2100 located between the first area 2101 and the second area 2102. The first conductive layer may include: a first gate 213 of the transistor 21, and a first electrode 221 of the capacitor 22. The orthographic projection of the first gate 213 of the transistor 21 on the substrate 10 may cover the orthographic projection of the channel area 2100 of the active layer 210 on the substrate 10. The second conductive layer may include: a second electrode 222 of the capacitor 22. The orthographic projections of the second electrode 222 and the first electrode 221 of the capacitor 22 on the substrate 10 may at least partially overlap, for example, the two may coincide.

[0096] In some exemplary embodiments, Figure 5 As shown, the third conductive layer of the display area may include: a first source 211 and a first drain 212 of the transistor 21. The first source 211 of the transistor 21 may be electrically connected to the first area 2101 of the active layer 210, and the first drain 212 may be electrically connected to the second area 2102 of the first active layer 210. The fourth conductive layer may include at least: a first anode transition electrode 241. The first anode transition electrode 241 may be electrically connected to the first drain 212 of the transistor 21 of the pixel circuit through a via hole provided in the fifth insulating layer 105 and the sixth insulating layer 106. In this example, the electrical connection between the pixel circuit and the light-emitting element may be realized through the first anode transition electrode 241.

[0097] In some exemplary embodiments, Figure 5 As shown, the light emitting structure layer 13 may include: a pixel definition layer 134 and a plurality of light emitting elements. For example, each light emitting element may include: a stacked first electrode 131, an organic light emitting layer 132 and a second electrode 133. The first electrode 131 of the light emitting element may be an anode, and the first electrode 131 may be disposed on the seventh insulating layer 107, and electrically connected to the first anode switching electrode 241 through a via hole provided in the seventh insulating layer 107. The pixel definition layer 134 is disposed on the first electrode 131 and the seventh insulating layer 107, and the pixel definition layer 134 may be provided with a plurality of pixel openings, and one pixel opening may expose at least part of the surface of a corresponding first electrode 131. At least part of the organic light emitting layer 132 may be disposed in one pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on the organic light emitting layer 132 and connected to the organic light emitting layer 132. The organic light emitting layer 132 may emit light of corresponding colors under the drive of the first electrode 131 and the second electrode 133.

[0098] In some exemplary embodiments, the organic light-emitting layer 132 of the light-emitting element may include at least one light-emitting layer (EML), and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 131 and the second electrode 133, the light-emitting characteristics of the organic material can be used to emit light according to the required grayscale.

[0099] In some exemplary embodiments, the light-emitting layers of light-emitting elements of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. In order to reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may use a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may use a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer can be made by a single process (a single evaporation process or a single inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM, Fine Metal Mask) or an open mask (Open Mask), or by inkjet technology.

[0100] In some exemplary embodiments, Figure 5As shown, the encapsulation structure layer 14 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 stacked. Among them, the first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, silicon oxynitride, etc. The inorganic material has high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 142 may be arranged between the first encapsulation layer 141 and the third encapsulation layer 143 to ensure that external water vapor cannot enter the light-emitting element. The second encapsulation layer 142 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block water vapor, or it may be a polymer resin, etc. to flatten the surface of the display substrate, and it may relieve the stress of the first encapsulation layer 141 and the third encapsulation layer 143, and it may also include a desiccant and other water-absorbing materials to absorb water, oxygen, and other substances that invade the interior. However, this embodiment is not limited to this. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0101] In some exemplary embodiments, Figures 3 to 6 As shown, the display substrate may include a display area AA and a peripheral area BB surrounding the periphery of the display area AA. In some exemplary embodiments, the display area AA may include a plurality of sub-pixels PX arranged in a matrix manner, and the sub-pixels PX may include a pixel driving circuit and a light-emitting device. The peripheral area BB may have isolation dams (Dam1 and Dam2), a gate driver circuit (Gate Driver on Array, GOA for short), and a power line for transmitting voltage signals to the plurality of sub-pixels PX, and the isolation dam of the peripheral area BB forms a ring structure surrounding the display area AA. For example, the peripheral area BB may include: a first frame area C1 located on one side of the display area AA in the first direction, a second frame area C2 on the other side of the first direction, a third frame area C3 located on one side of the display area AA in the second direction, and a fourth frame area C4 on the other side of the second direction. Both the first direction and the second direction are parallel to the substrate 10, and the first direction is perpendicular to the second direction. The first frame area C1 may be the lower frame of the display substrate, the second frame area C2 may be the upper frame of the display substrate, the third frame area C3 may be the left frame of the display substrate, and the fourth frame area C4 may be the right frame of the display substrate.

[0102] In some exemplary embodiments, Figures 3 to 6As shown, the display area AA may include at least a plurality of sub-pixels PX, a plurality of gate lines GL and a plurality of data lines DL. The plurality of gate lines GL may extend along the second direction, and the plurality of data lines DL may extend along the first direction. The positive projections of the plurality of gate lines GL and the plurality of data lines DL on the substrate intersect to form a plurality of sub-pixel regions, and a sub-pixel PX is arranged in each sub-pixel region. The plurality of data lines DL are electrically connected to the plurality of sub-pixels PX, for example, a data line DL is electrically connected to a column of sub-pixels PX. The plurality of data lines DL may be configured to provide data signals to the plurality of sub-pixels PX. The plurality of data lines DL may extend to the binding area. The plurality of gate lines GL are electrically connected to the plurality of sub-pixels PX, for example, a gate line GL is electrically connected to a row of sub-pixels PX. The plurality of gate lines GL may be configured to provide gate control signals to the plurality of sub-pixels PX. In some examples, the gate control signal may include a scan signal and a light emitting control signal.

[0103] In some exemplary embodiments, Figures 3 to 6As shown, the first frame area C1 includes a first fan-out area B11, a bending area B12, a second fan-out area B13, a first circuit area B14, a third fan-out area B15, a chip binding area B16 and a circuit board binding area B17 arranged in sequence along a direction away from the display area AA. The first fan-out area B11 can be connected to the display area AA, and a plurality of data lines DL of the display area AA can be extended to the first fan-out area B11 in a fan-out routing manner. The first power bus of the first fan-out area B11 can be configured to connect the first power line (VDD) of the display area AA, and the second power line (VSS) can be located in the peripheral area BB. The first power line (VDD) is a high-level power line or a positive-level power line, and the second power line (VSS) is a low-level power line or a negative-level power line. The bending area B12 is connected between the first fan-out area B11 and the second fan-out area B13, and can be configured to bend to the back of the display area AA. The plurality of data lines DL of the display area AA can extend to the first circuit area B14 through the second fan-out area B13. The first circuit area B14 may include at least one first circuit group, the first circuit group may include multiple test circuits, the test circuit may be configured to be electrically connected to multiple data lines DL, and provide test data signals to multiple data lines DL of the display area AA during the test phase. The first circuit group may also include an electrostatic discharge circuit. The chip binding area B16 may include at least one driver chip area, each driver chip area may include multiple conductive bumps (Bump) (also known as contact pads), and the multiple conductive bumps may be configured to be bound to at least one driver chip (IC, Integrated Circuit). The driver chip may be configured to generate a driving signal required to drive the sub-pixel, for example, including a data driving signal. The data driving signal is provided to multiple sub-pixels PX in the display area through multiple data lines DL. The circuit board binding area B17 may include at least one binding pin area, each binding pin area may include multiple binding pins, and the multiple binding pins may be configured to be bound and connected to at least one corresponding circuit board, such as a flexible printed circuit (FPC).

[0104] like Figure 3 As shown, the gate drive circuit of the display panel includes a plurality of shift register units GOA0, GOA1 ... and GOAn, a plurality of gate drive signal lines (i.e., drive circuit wiring 600) GSTV, GCK, GCB are electrically connected to the gate drive circuit, and each GOA unit is electrically connected to a gate line GL. The plurality of gate drive signal lines GSTV, GCK, GCB extend to the chip binding area B16 and are connected to pads corresponding to the chip binding area B16.

[0105] The applicant found that the display substrate turned red on the entire surface under heavy-loaded images, and there was no way to solve this problem through timing. At present, the sum of the resistances of the data lines in the first fan-out area and the second fan-out area is usually not less than 5KΩ. Through multiple experiments, the applicant found that reducing the resistance of the data line can effectively alleviate the situation of the entire surface turning red, and the smaller the resistance of the data line, the less obvious the red phenomenon of the heavy-loaded image. Therefore, it can be confirmed that the excessive resistance of the data line is the main reason for the redness of the heavy-loaded image.

[0106] The technical solution of the embodiment of the present invention is described in detail below through specific embodiments.

[0107] In some exemplary embodiments, a display substrate, such as Figures 3 to 6 As shown, the display substrate may include a substrate 10, a sub-pixel PX and a plurality of data lines DL. The substrate 10 may include a display area AA and a peripheral area surrounding the display area AA. The peripheral area includes a first frame area C1 located on one side of the display area AA. The plurality of data lines DL are located in the display area AA and extend from the display area AA to the first frame area C1. At least one of the plurality of data lines DL includes a fan-out line 300 located in the first frame area C1. The resistance of the fan-out line 300 is set to R1, and the preset resistance is set to R0, R1≤R0, 2.5kΩ≤R0≤10kΩ. Therefore, the display substrate of this embodiment can reduce the impedance of the wiring and reduce the crosstalk, thereby solving the problem of the red screen under heavy load.

[0108] Figure 7 for Figure 3 In the locally enlarged schematic diagram of B in FIG. 1 , in some exemplary embodiments, as shown in FIG. Figures 3 to 7 As shown, the fan-out line 300 led out from the display area AA may include a first fan-out line 301 located in the first fan-out area B11, and a second fan-out line 302 located in the second fan-out area B13. One end of the first fan-out line 301 away from the display area AA may be electrically connected to one end of the second fan-out line 302. In some exemplary embodiments, the sum of the resistances of the first fan-out line 301 and the second fan-out line 302 may be R1, and R1 may be less than or equal to 2.5 kΩ. In this example, the value of R1 may be 1.5 kΩ, but is not limited thereto, for example, R1=1 kΩ, or R1=2 kΩ, or R1=2.3 kΩ.

[0109] In some exemplary embodiments, Figures 3 to 6As shown, the first border area C1 also includes a circuit routing area B18 where driving circuit routing is arranged, and a dam area B19. The circuit routing area B18 is located on the side of the first fan-out area B11 away from the display area AA, and the dam area B19 is located on the side of the circuit routing area B18 away from the display area AA. The dam area B19 is away from the edge of the circuit routing area B18, i.e., the cutting path. The distance between the edge of the first fan-out area B11 close to the display area and the edge close to the circuit wiring area B18 can be a first width M1, the distance between the edge of the circuit wiring area B18 close to the first fan-out area B11 and the edge close to the dam area B19 can be a second width M2, and the distance between the edge of the dam area B19 close to the first fan-out area B11 and the edge away from the first fan-out area B11 can be a third width M3, wherein M1:M2:M3=5:(3~3.5):(1.5~2), which can not only satisfy that the first fan-out area B11 has sufficient width to arrange the widened first fan-out line 301, but also meet the wiring requirements of the driving circuit wiring, ensuring that there will be no reliability problems from the boundary to the driving circuit wiring.

[0110] In some exemplary embodiments, Figures 3 to 6 As shown, the peripheral area BB surrounds the display area AA, and the area of ​​the first border area C1 corresponding to the corner position of the display area AA can form a first corner area B20 and a second corner area B21. The first corner area B20 and the second corner area B21 are symmetrically arranged in the second direction, and the minimum distance between the edge of the first corner area B20 and the second corner area B21 close to the display area AA and the edge away from the display area AA can be set to be smaller than the minimum distance between the edge of other areas of the first border area C1 close to the display area AA and the edge away from the display area AA, so that the width of the first corner area B20 and the second corner area B21 is narrower than that of other areas of the first border area C1.

[0111] In some exemplary embodiments, Figures 3 to 6 As shown, a plurality of first fan-out lines 301 may be provided, and the plurality of first fan-out lines 301 may be arranged at equal intervals in a direction parallel to the substrate. The line width of each first fan-out line 301 may be the dimension of the first fan-out line 301 in a direction parallel to the substrate 10 and perpendicular to the extension direction of the first fan-out line 301, and the line width of other lines as follows may be the dimension of the line in a direction parallel to the substrate 10 and perpendicular to the extension direction of the line. The line width of the first fan-out line 301 may be greater than 2 microns, which increases the line width of the data line DL, and the resistance of the first fan-out line 301 may be reduced on the basis of unchanged thickness. In some exemplary embodiments, the line width of the first fan-out line 301 is L0, 2μm≤L0≤5μm, in this exemplary embodiment, L0=2.3μm, but not limited thereto, for example, L0=3μm, L0=3.3μm, L0=2.5μm, or L0=2.8μm.

[0112] In some exemplary embodiments, Figures 3 to 6 As shown, the first fan-out line 301 may include a first connection line 301' and a second connection line 301", and the first connection line 301' and the second connection line 301" may be an integral part, and the first connection line 301' and the second connection line 301" may be completed by a single patterning process. One end of the first connection line 301' extends toward the display area AA, and the other end is connected to the second connection line 301", and the connection position of the first connection line 301' and the second connection line 301" is located in the first corner area B20 or the second corner area B21. The cross-sectional area of ​​the first connection line 301' is greater than the cross-sectional area of ​​the second connection line 301".

[0113] Figure 8 for Figure 6 In the partial enlarged schematic diagram of D in FIG. 1 , in some exemplary embodiments, as shown in FIG. Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 8 As shown, the line width of the first connection line 301' may be greater than the line width of the second connection line 301", that is, L1>L2. The line width (L1) of the first connection line 301' may be consistent along the extension direction of the first connection line 301', so that the width of the first fan-out line 301 suddenly changes at the connecting position of the first connection line 301' and the second connection line 301". In this example, L1=3.3μm, L2=2.3μm, so that the resistance of a single first fan-out line 301 is reduced by about 40%, but is not limited to this, for example, L1=2.8μm, L2=2.3μm; for another example, L1=2.5μm, L2=2.3μm; for another example, L1=3μm, L2=2.5μm.

[0114] In some exemplary embodiments, Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 8 As shown, the edge of the connecting position of the first connecting line 301' and the second connecting line 301" is stepped. For example, the edge of the first fan-out line 301 on one side of the line width direction is the first edge 303. The positive projection of the first edge 303 on the substrate at the connecting position of the first connecting line 301' and the second connecting line 301" can be extended like the auxiliary line T1 to form a step shape. The auxiliary line T1 can be a fold line with a "Z" shape. The first fan-out line 301 can be perpendicular to the extension direction of the first fan-out line 301 and parallel to the substrate in the line width direction.

[0115] In some exemplary embodiments, Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 8As shown, the minimum distance between the edges of the first connection lines 301' of adjacent first fan-out lines 301 is the first distance S', and the distance between the edges of the first connection lines 301' of adjacent first fan-out lines 301 remains unchanged along the extension direction of the first fan-out line 301, that is, the distance between the edges of the first connection lines 301' of adjacent first fan-out lines 301 is the first distance S' along the extension direction of the first fan-out line 301. The minimum distance between the edges of the second connection lines 301" of adjacent first fan-out lines 301 is the second distance S", and the distance between the edges of the adjacent second connection lines 301" remains unchanged along the extension direction of the first fan-out line 301, that is, the distance between the edges of the adjacent second connection lines 301" is the second distance S" along the extension direction of the first fan-out line 301. In some exemplary embodiments, the spacing between the line centers of the plurality of first fan-out lines 301 is equal, so that the spacing between the line centers of the adjacent first fan-out lines 301 remains unchanged, and the line width of the first connection line 301' is greater than the line width of the second connection line 301", so that the first distance S' is smaller than the second distance S".

[0116] Fig. 9 is a schematic diagram of a first fan-out line of this exemplary embodiment. In some exemplary embodiments, as Figure 3 , Figure 4 , Figure 5 , Figure 6 and Fig. 9 As shown, the second connection lines 301" of adjacent first fan-out lines 301 are gathered at one end away from the first connection line 301', the minimum distance between the edges of the first connection lines 301' of adjacent first fan-out lines 301 is the first distance S', the minimum distance between the edges of the second connection lines 301" of adjacent first fan-out lines 301 is the second distance S", and the first distance S' is equal to the second distance S".

[0117] Fig.10 is a partial schematic diagram of a first border area of ​​the present exemplary embodiment. In some exemplary embodiments, as Figure 3 , Figure 4 , Figure 5 , Figure 6 and Fig.10As shown, the line width of the first connection line 301' may gradually decrease in the direction away from the display area AA. In some exemplary embodiments, the first connection line 301' includes a plurality of sub-connection lines 400 arranged in sequence along the extension direction of the first connection line 301', and the line width of the plurality of sub-connection lines 400 may decrease in sequence from the end close to the display area AA to the end connected to the second connection line 301". The number of sub-connection lines 400 may be N, N>2, and the difference between the line widths of adjacent sub-connection lines 400 may be a fixed value, so that the line width of the first connection line 301' gradually changes along the extension direction, which is beneficial to the smooth design of the first fan-out line 301. In this exemplary embodiment, the plurality of sub-connection lines 400 may include a first sub-connection line 401, a second sub-connection line 402, a third sub-connection line 403 and a fourth sub-connection line 404, and the first sub-connection line 401, the second sub-connection line 402, the third sub-connection line 403 and the fourth sub-connection line 404 may be arranged in sequence in the direction away from the second connection line 301". One end of the first sub-connection line 401 is connected to the second connection line 301″, and the other end is connected to the second sub-connection line 402. The line width of the first sub-connection line 401 is L3, the line width of the second sub-connection line 402 is L4, the line width of the third sub-connection line 403 is L5, and the line width of the fourth sub-connection line 404 is L6, wherein L6>L5>L4>L3. In this example, L3=2.6μm, L4=2.7μm, L5=2.8 μm, L6=2.9μm, the difference in line widths of adjacent sub-connection lines 400 is 0.1μm, but is not limited thereto. For example, the difference in line widths of adjacent sub-connection lines 400 may be a fixed value and be 0.2μm, 0.05μm or 0.5μm, etc. For another example, the difference in line widths of adjacent sub-connection lines 400 may be a non-fixed value, L3=2.6μm, L4=2.7μm, L5=2.9μm, L6=3.3μm.

[0118] Fig.11 FIG. 1 is a partial schematic diagram of another first border area of ​​the exemplary embodiment. In some exemplary embodiments, as shown in FIG. Fig.11 As shown, among the plurality of first fan-out lines 301, the first connection lines 301' of some first fan-out lines 301 may have a constant line width, and the first connection lines 301' of other first fan-out lines 301 may have a structure with a gradually varying line width, ie, include a plurality of sub-connection lines 400 with different line widths.

[0119] Fig.12 is a partial schematic diagram of another first border area of ​​this exemplary embodiment, Fig.13 for Fig.12 The GG cross-sectional diagram in the figure is as follows: Fig.14 for Fig.12 In the JJ-direction cross-sectional diagram, in some exemplary embodiments, as Figure 12 to Figure 14As shown, the distance between adjacent first fan-out lines 301 gradually expands from one end of the first connection line 301' connected to the second connection line 301" toward one end away from the second connection line 301", so that the distance between adjacent first connection lines 301' is greater than the distance between adjacent second connection lines 301", that is, the minimum distance between the edges of the first connection lines 301' of adjacent first fan-out lines 301 is the first distance S', and the minimum distance between the edges of the second connection lines 301" of adjacent first fan-out lines 301 is the second distance S", and the first distance S' is greater than the second distance S". In some exemplary embodiments, the line width of the first connection line 301' may be L1, and the line width of the second connection line 301" may be L2, wherein L1=L2, that is, the line width of the first connection line 301' is equal to the line width of the second connection line 301".

[0120] In some exemplary embodiments, Figure 12 to Figure 14 As shown, the first connection line 301' includes a first routing layer 501 and a second routing layer 502 stacked in a direction perpendicular to the substrate (third direction), and the first routing layer 501 can be located on the side of the second routing layer 502 close to the substrate 10. The materials of the first routing layer 501 and the second routing layer 502 can be the same or different. The first routing layer 501 can be a first gate metal layer, and the second routing layer 502 can be a second gate metal layer. The first connection line 301' forms a double-layer structure, so that the thickness of the first connection line 301' is increased, and the resistance of the first fan-out line 301 can also be reduced. The third direction is perpendicular to the above-mentioned first direction and second direction. The second connection line 301" may include a third routing layer 503, and the third routing layer 503 can be arranged in the same layer as the first routing layer 501 or the second routing layer 502. The second connection line 301" can be a one-layer structure. On the basis that the line widths of the first connecting line 301' and the second connecting line 301" are the same, the thickness of the first connecting line 301' is greater than the thickness of the second connecting line 301", and the thicknesses of both refer to the dimensions in the third direction, so that the cross-sectional area of ​​the first connecting line 301' is greater than the cross-sectional area of ​​the second connecting line 301".

[0121] Fig.15 FIG. 1 is a partial schematic diagram of another first fan-out region of the exemplary embodiment. In some exemplary embodiments, as shown in FIG. Fig.15As shown, the first fan-out line 301 may be in the shape of a broken line, and the first fan-out line 301 may include a first connection line 301' and a second connection line 301", and the first connection line 301' and the second connection line 301" are arranged at an angle. The first connection line 301' and the second connection line 301" both extend along a straight line, and the angle between the first connection line 301' and the second connection line 301" is α, wherein the value of α may be 100° to 175°. In this example, α=150°, but is not limited thereto, for example, α=130°, α=160°, or α=170°. The line width of the first connection line 301' may be greater than the line width of the second connection line 301", that is, L1>L2, so that the line width of the first fan-out line 301 suddenly changes at the junction of the first connection line 301' and the second connection line 301". In some exemplary embodiments, the spacing between the line centers of the plurality of first fan-out lines 301 is equal, so that the spacing between the line centers of adjacent first fan-out lines 301 remains unchanged, and the line width of the first connecting line 301' is greater than the line width of the second connecting line 301", so that the first distance S' is less than the second distance S".

[0122] Fig.16 FIG. 1 is a partial schematic diagram of another first fan-out region of the exemplary embodiment. In some exemplary embodiments, as shown in FIG. Fig.16 As shown, the first fan-out line 301 may be in the shape of a broken line, and the first fan-out line 301 may include a first connection line 301' and a second connection line 301", and the first connection line 301' and the second connection line 301" are set at an angle. The line width of the first connection line 301' may be greater than the line width of the second connection line 301", that is, L1>L2. The line width of the first fan-out line 301 at the junction of the first connection line 301' and the second connection line 301" increases linearly in the direction away from the second connection line 301", and the first fan-out line 301 at the junction of the first connection line 301' and the second connection line 301" is trumpet-shaped, so that the line shape of the first fan-out line 301 can smoothly transition at the junction of the first connection line 301' and the second connection line 301".

[0123] Fig.17 for Figure 6 In the locally enlarged schematic diagram at E in some exemplary embodiments, as Figure 3 , Figure 6 and Fig.17As shown, the display substrate may include a plurality of driving circuit lines 600, and the plurality of driving circuit lines 600 may be located in the circuit line area B18, and the plurality of driving circuit lines 600 may be arranged in parallel and at intervals. The plurality of driving circuit lines 600 may include an AC signal line 602 and a DC signal line 601, and the line width of the DC signal line 601 may be L7, and the line width of the AC signal line 602 may be L8, and the line width of the DC signal line 601 is greater than the line width of the AC signal line 602, that is, L7>L8. The AC signal line 602 may be an AC signal line such as a clock signal (CK) line, a vertical synchronization start signal (STV) line, or a multiplexer (Mux) line. The risk of burns from the AC signal line 602 is low, and the line width of the AC signal line 602 may be appropriately reduced, and the area of ​​the circuit line area B18 may be compressed to provide more space for widening the data line DL. The DC signal line 601 needs to have a wider line width to avoid worsening of the burning phenomenon.

[0124] In some exemplary embodiments, Figure 3 , Figure 6 and Fig.17As shown, the circuit routing area B18 includes a first area B18' and a second area B18", and the first area B18' and the second area B18" are arranged in sequence along the circumference of the display area AA. The circumference of the display area AA can be the extension direction of the outer edge of the display area AA (i.e., the direction surrounding the display area AA), the edge of the circuit routing area B18 close to the display area AA is the second edge 605, and the edge of the circuit routing area B18 away from the display area AA is the third edge 606. The minimum distance between the edge of the first area B18' close to the display area AA and the edge away from the display area AA may be the third distance L13, that is, the minimum distance between the second edge 605 and the third edge 606 in the first area B18' is the third distance L13; the minimum distance between the edge of the second area B18" close to the display area AA and the edge away from the display area AA may be the fourth distance L14, that is, the minimum distance between the second edge 605 and the third edge 606 in the second area B18" is the fourth distance L14; wherein the third distance L13 is smaller than the fourth distance L14, so that the width of the first area B18' is narrower than that of the second area B18". At least one driving circuit wiring 600 includes a first wiring 603 and a second wiring 604, one end of the first wiring 603 is connected to the second wiring 604, the first wiring 603 is located in the first area B18', and the second wiring 604 is located in the second area B18". In some exemplary embodiments, the line width of the first routing line 603 may be L9, and the line width of the second routing line 604 may be L10. The line width of the first routing line 603 is smaller than the line width of the second routing line 604, that is, L9<L10, so that the second routing line 604 with a larger line width is arranged in the wider second area B18", thereby reducing the resistance of the driving circuit routing line 600 and alleviating the phenomenon of the screen turning red when overloaded.

[0125] Fig.18 for Figure 7 FF cross-sectional diagram, Fig.19 for Figure 7 The HH cross-sectional diagram in Fig. Fig. 20 for Figure 7 A schematic cross-sectional view of the middle KK direction, in some exemplary embodiments, as Figure 3 , Figure 7 , Fig.18 , Fig.19 and Fig. 20As shown, a plurality of second fan-out lines 302 are provided, and the plurality of second fan-out lines 302 include a third line 302' and a fourth line 302", and the third line 102' and the fourth line 302" both extend from the bending area B12 to the first circuit area B14. The bending area B12 has a plurality of routing groups 700, and each routing group 700 may include a plurality of routings, and the plurality of routings may be in a straight line shape, a folded line shape, a twisted shape, a curved shape, etc. One end of the second fan-out line 302 may be connected to the routing group 700 of the bending area B12. The routing distance of the third routing line 302' is greater than that of other second fan-out lines 302, that is, the length of the third routing line 302' in its extension direction is greater than the length of the fourth routing line 302" in its extension direction. Moreover, the line width of the third routing line 302' may be L11, and the line width of the fourth routing line 302" may be L12, wherein the line width of the third routing line 302' is greater than the line width of the fourth routing line 302", that is, L11>L12, so that the resistance of the second fan-out line 302 is reduced. The display substrate of this example can take advantage of the large free space of the second fan-out area B13 to widen the line width of the second fan-out line 302, reduce the routing resistance in the second fan-out area B13, and further reduce the impedance of the data line DL.

[0126] In some exemplary embodiments, Figure 3 , Figure 7 , Fig.18 , Fig.19 and Fig. 20 As shown, at least one second fan-out line 302 may be a two-layer structure stacked in a direction perpendicular to the substrate 10 (i.e., the third direction). The thickness of the second fan-out line 302 increases, and the resistance of the second fan-out line 302 may also be reduced. In this example, part of the routing of the second fan-out line 302 may include a fourth routing layer 504 and a fifth routing layer 505 stacked in the third direction, and the materials of the fourth routing layer 504 and the fifth routing layer 505 may be the same or different. The fourth routing layer 504 may be arranged in the same layer as the first routing layer 501 described above, and the fifth routing layer 505 may be arranged in the same layer as the second routing layer 502 described above.

[0127] In some exemplary embodiments, Figure 3 and Figure 7As shown, the display substrate may include a plurality of first power lines F1 and a first power pin J1, the plurality of first power lines F1 may be located in the display area AA and electrically connected to a plurality of sub-pixels PX, the first power pin J1 may be located in the first frame area C1, one end of the first power pin J1 is electrically connected to the wiring group 700 of the bending area B12 and is led upward through the wiring group 700, the other end of the first power pin J1 is arranged in the circuit board binding area B17, and the plurality of first power lines F1 may be electrically connected to the first power pin J1. At least one second fan-out line 302 is located on one side of the first power pin J1 close to the edge of the display substrate, and the orthographic projection of at least one second fan-out line 302 on the substrate 10 overlaps with the orthographic projection of the first power pin J1 on the substrate 10. In this example, portions of the plurality of third traces 302' may be located on a side of the first power pin J1 close to an edge of the display substrate (fourth edge 800), wherein each third trace 302' includes a first segment 304, and the first segment 304 may be located on a side of the first power pin J1 close to an edge of the display substrate (fourth edge 800). The orthographic projection of at least one third trace 302' on the substrate 10 overlaps with the orthographic projection of the first power pin J1 on the substrate 10.

[0128] In some exemplary embodiments, Figure 3 and Figure 7 As shown, the display substrate may include a second power line F2 and a second power pin J2, the second power line F2 may be located in the peripheral area and at least partially surround the display area AA, the second power pin J2 is located in the first frame area C1, one end of the second power pin J2 is electrically connected to the routing group 700 of the bending area B12 and is led up through the routing group 700, the other end of the second power pin J2 is arranged in the circuit board binding area B17, and the second power line F2 may be electrically connected to the second power pin J2. At least one second fan-out line 302 is located on the side of the second power pin J2 away from the first power pin J1, and the orthographic projection of at least one second fan-out line 302 on the substrate 10 overlaps with the orthographic projections of the first power pin J1 and the second power pin J2 on the substrate 10. In this example, a portion of the third routing line 302' is located on the side of the second power pin J2 away from the first power pin J1, and the orthographic projection of the third routing line 302' on the substrate 10 overlaps with the orthographic projections of the first power pin J1 and the second power pin J2 on the substrate 10. The third trace 302 ′ includes a first line segment 304 . The first line segment 304 is located at a side of the second power pin J2 away from the first power pin J1 .

[0129] In some exemplary embodiments, Figure 3 and Figure 7As shown, at least part of the line segments of at least one second fan-out line 302 are located between the second power pin J2 and the plurality of drive circuit traces 600. In this example, the first line segment of the second fan-out line 302 is located between the second power pin J2 and the plurality of drive circuit traces 600, and the plurality of drive circuit traces 600 may be a plurality of gate drive signal lines (GSTV, GCK, GCB, etc.).

[0130] In some exemplary embodiments, a display device includes the above-mentioned display substrate. The display device provided by the embodiments of the present disclosure can be applied to electronic devices, which can be mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigators, car displays, wearable devices, and any products or components with display functions, such as smart watches, smart bracelets, smart glasses, smart headphones, smart clothing, head-mounted displays, etc.

[0131] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0132] In addition, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include at least one of the features.

[0133] In the description of the present application, “plurality” means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined.

[0134] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0135] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, and “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0136] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0137] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display substrate, characterized in that: include: A substrate, comprising a display area and a peripheral area surrounding the display area, wherein the peripheral area comprises a first frame area located at one side of the display area; A plurality of sub-pixels are located in the display area; A plurality of data lines are located in the display area and extend from the display area to the first border area, the plurality of data lines are electrically connected to the plurality of sub-pixels, each of the plurality of data lines includes a fan-out line located in the first border area, the resistance of the fan-out line is set to R1, the preset resistance is set to R0, R1≤R0, 2.5kΩ≤R0≤10kΩ.

2. The display substrate according to claim 1, characterized in that: The first border area includes a first fan-out area, and the fan-out line includes a first fan-out line located in the first fan-out area; The first fan-out line includes a first connection line and a second connection line, one end of the first connection line extends toward the display area, the other end of the first connection line is connected to the second connection line, and a cross-sectional area of ​​the first connection line is greater than a cross-sectional area of ​​the second connection line.

3. The display substrate according to claim 2, characterized in that: The first fan-out area includes a first corner area and a second corner area, and the connecting position of the first connection line and the second connection line is located at one of the first corner area and the second corner area; The line width of the first connection line is greater than the line width of the second connection line.

4. The display substrate according to claim 3, characterized in that: The line width of the first connecting line is set to be consistent along the extension direction of the first connecting line.

5. The display substrate according to claim 3, characterized in that: The line width of the first connection line is configured to gradually decrease in a direction away from the display area.

6. The display substrate according to claim 5, characterized in that: The first connection line includes a plurality of sub-connection lines arranged in sequence along an extension direction of the first connection line, and the line widths of the plurality of sub-connection lines are configured to decrease in sequence from one end close to the display area to one end connected to the second connection line.

7. The display substrate according to claim 2, characterized in that: The first fan-out line is configured as a folded line, the first connection line and the second connection line both extend along a straight line, and an angle between the first connection line and the second connection line is configured as α, 100°≤α≤175°.

8. The display substrate according to claim 2, characterized in that: There are a plurality of first fan-out lines, and the plurality of first fan-out lines are arranged at intervals in a direction parallel to the substrate, a distance between first connection lines of adjacent first fan-out lines is a first distance, a distance between second connection lines of adjacent first fan-out lines is a second distance, and the first distance is greater than the second distance; The line width of the first connecting line is equal to the line width of the second connecting line; The first connection line includes a first routing layer and a second routing layer stacked in a direction perpendicular to the substrate, and the second connection line includes a third routing layer, which is arranged in the same layer as the first routing layer or the second routing layer.

9. The display substrate according to any one of claims 3 to 7, characterized in that: There are a plurality of first fan-out lines, and the plurality of first fan-out lines are arranged at equal intervals in a direction parallel to the substrate; A distance between adjacent first connection lines of the first fan-out lines is a first distance, a distance between adjacent second connection lines of the first fan-out lines is a second distance, and the first distance is equal to the second distance.

10. The display substrate according to any one of claims 2 to 8, characterized in that: The line width of the first fan-out line is set to be greater than 2 microns; The line width of the first fan-out line is set to L0, 2μm≤L0≤5μm.

11. The display substrate according to any one of claims 2 to 8, characterized in that: R1≤2.5kΩ.

12. The display substrate according to claim 2, characterized in that: The display substrate also includes a plurality of parallel drive circuit lines located in the first border area, the plurality of drive circuit lines are configured to be electrically connected to a plurality of gate drive circuits, the plurality of drive circuit lines include AC signal lines and DC signal lines, and the line width of the DC signal line is greater than the line width of the AC signal line.

13. The display substrate according to claim 12, characterized in that: The first border area includes a circuit routing area, and the circuit routing area is located on a side of the first fan-out area away from the display area; The circuit routing area includes a first area and a second area, the first area and the second area are sequentially arranged along the circumference of the display area, the minimum distance between an edge of the first area close to the display area and an edge far from the display area is set to a third distance, the minimum distance between an edge of the second area close to the display area and an edge far from the display area is set to a fourth distance, and the third distance is smaller than the fourth distance; At least one driving circuit routing line among the plurality of driving circuit routing lines comprises a first routing line and a second routing line, the first routing line is located in the first area, the second routing line is located in the second area, and a line width of the first routing line is smaller than a line width of the second routing line.

14. The display substrate according to claim 2, characterized in that: The first frame area further includes a second fan-out area, and the second fan-out area is located at a side of the first fan-out area away from the display area; The fan-out line also includes a second fan-out line located in the second fan-out area, and a plurality of second fan-out lines are provided. The plurality of second fan-out lines include a third routing line and a fourth routing line. The line length of the third routing line is greater than the line length of the fourth routing line, and the line width of the third routing line is greater than the line width of the fourth routing line.

15. The display substrate according to claim 14, characterized in that: At least one of the second fan-out lines includes a fourth routing layer and a fifth routing layer stacked in a direction perpendicular to the substrate.

16. The display substrate according to claim 14, characterized in that: The display substrate comprises a plurality of first power lines and a first power pin, wherein the plurality of first power lines are located in the display area and are electrically connected to the plurality of sub-pixels, and the first power pin is located in the first frame area, and the plurality of first power lines are electrically connected to the first power pin; A portion of at least one second fan-out line is located on a side of the first power pin close to an edge of the display substrate, and an orthographic projection of at least one second fan-out line on the substrate overlaps with an orthographic projection of the first power pin on the substrate.

17. The display substrate according to claim 16, characterized in that: The display substrate comprises a second power line and a second power pin, the second power line is located in the peripheral area and at least partially surrounds the display area, the second power pin is located in the first frame area, and the second power line is connected to the second power pin; A portion of at least one second fan-out line is located on a side of the second power pin away from the first power pin, and an orthographic projection of at least one second fan-out line on the substrate overlaps with both orthographic projections of the first power pin and the second power pin on the substrate.

18. The display substrate according to claim 17, characterized in that: It also includes a plurality of drive circuit lines located in the peripheral area, and at least part of the line segments of at least one of the second fan-out lines are located between the second power pin and the plurality of drive circuit lines.

19. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 18.

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