Semiconductor device and method for manufacturing semiconductor device

Abstract

The front surface electrode (14) is in ohmic contact with the semiconductor substrate (8) via a contact structure comprising the TiSix film (11), the TiN film (12), and the metal plug (13). The TiSix film (11) is directly deposited by sputtering, and is provided along the inner wall of the source contact trench (8a) from the side wall (side surface of the interlayer insulating film (9)) of the contact hole (9a). An end portion of the TiSix film (11) terminates on a side surface of the interlayer insulating film (9). The thickness of the TiSix film (11) is the same from the side wall of the contact hole (9a) to the side wall of the source contact trench (8a). The TiN film (12) is provided along the surface of the TiSix film (11). A metal plug (13) is embedded in the TiN film (12) inside the contact hole (9a) and the source contact trench (8a). As a result, the reliability of the semiconductor device (10) is improved.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] In the past, a semiconductor device has been proposed, which has a bonding layer composed of titanium (Ti) and / or a barrier layer composed of titanium silicon nitride (Ti-Si-N) between a front electrode and a semiconductor substrate, or has a contact structure including a titanium silicide (TiSi) film formed by silicidation of a Ti film or a TiSi film formed by plasma enhanced chemical vapor deposition (PECVD) (for example, see Patent Documents 1 to 5 below). In addition, a semiconductor device having a gate electrode including a TiSi film deposited by sputtering has been proposed (for example, see Patent Document 6 below).

[0003] Prior art literature Patent Literature Patent Document 1: Japanese Patent Application Laid-Open No. 10-321812 Patent Document 2: Japanese Patent Application Laid-Open No. 10-79431 Patent Document 3: Japanese Patent Application Laid-Open No. 10-79481 Patent Document 4: Japanese Patent Application Laid-Open No. 7-297136 Patent Document 5: Japanese Patent Application Publication No. 2015-124397 Patent Document 6: Patent Publication No. 3988342 Summary of the invention

[0004] Technical issues However, in the above-mentioned patent documents 1 to 4, the effect of hydrogen annealing for recovering crystal damage of the semiconductor substrate is hindered by the Ti film included in the stacked structure of the front electrode. In addition, in the above-mentioned patent document 4, the stress generated locally in the semiconductor substrate increases due to the volume expansion of the TiSi film caused by silicidation. In the above-mentioned patent document 5, chlorine (Cl) included in the introduction gas composition of PECVD for forming the TiSi film becomes the cause of corrosion of the semiconductor substrate.

[0005] The present disclosure aims to solve the above-mentioned problems of the prior art and to provide a semiconductor device with high reliability and a method for manufacturing the semiconductor device.

[0006] Technical Solution A semiconductor device according to one embodiment of the present disclosure is as follows. A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate. A second semiconductor region of a second conductivity type is provided between the front surface of the semiconductor substrate and the first semiconductor region. An element structure including a pn junction between the second semiconductor region and the first semiconductor region is provided on the front surface side of the semiconductor substrate. An interlayer insulating film is provided on the front surface of the semiconductor substrate. The interlayer insulating film covers the element structure. A contact hole penetrates the interlayer insulating film in a depth direction and reaches the semiconductor substrate. The contact structure contacts the semiconductor substrate in the contact hole.

[0007] The first electrode is electrically connected to the second semiconductor region via the contact structure. The second electrode is arranged on the back side of the semiconductor substrate. The contact structure is composed of a titanium silicide film, a titanium nitride film and a metal plug. The titanium silicide film contacts the semiconductor substrate in the contact hole and extends on the surface of the interlayer insulating film along the side wall of the contact hole. The titanium nitride film is arranged along the surface of the titanium silicide film. The metal plug is buried on the titanium nitride film inside the contact hole.

[0008] In addition, a method for manufacturing a semiconductor device according to one embodiment of the present disclosure is as follows. A first process is performed, in which a second semiconductor region of a second conductivity type in contact with a first semiconductor region of a first conductivity type inside the semiconductor substrate is formed in a surface area on the front surface of a semiconductor substrate, and an element structure including a pn junction between the second semiconductor region and the first semiconductor region is formed. A second process is performed, in which an interlayer insulating film covering the element structure is formed on the front surface of the semiconductor substrate. A third process is performed, in which a contact hole is formed that penetrates the interlayer insulating film in a depth direction and reaches the semiconductor substrate. A fourth process is performed, in which a contact structure that contacts the semiconductor substrate in the contact hole is formed. A fifth process is performed, in which a first electrode electrically connected to the second semiconductor region via the contact structure is formed.

[0009] After the fifth step, a first annealing step is performed, in which the crystal damage of the semiconductor substrate is restored by heat treatment in a hydrogen atmosphere. The fourth step includes first to third deposition steps. In the first deposition step, a titanium silicide film is deposited by sputtering, the titanium silicide film covers the entire surface of the interlayer insulating film and contacts the semiconductor substrate in the contact hole. In the second deposition step, a titanium nitride film is deposited on the surface of the titanium silicide film by sputtering. In the third deposition step, a metal plug is buried on the titanium nitride film inside the contact hole. The contact structure consisting of the titanium silicide film, the titanium nitride film and the metal plug is formed.

[0010] Technical Effects According to the semiconductor device and the method for manufacturing the semiconductor device of the present invention, it is possible to improve reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0012] Figure 2 This is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment.

[0013] Figure 3 This is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment.

[0014] Figure 4 This is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment.

[0015] Figure 5 This is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment.

[0016] Figure 6 This is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment.

[0017] Figure 7 This is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment.

[0018] Figure 8 This is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the second embodiment.

[0019] Fig. 9 This is a diagram showing the relationship between the crystal damage recovery degree of a semiconductor substrate by hydrogen annealing and the barrier metal.

[0020] Fig.10 3 is a cross-sectional view showing the structure of Comparative Example 1.

[0021] Fig.11 3 is a cross-sectional view showing the structure of Comparative Example 2.

[0022] Fig.12 This is a cross-sectional view showing a state in the middle of manufacturing of Comparative Example 2.

[0023] Fig.13 This is a cross-sectional view showing a state in the middle of manufacturing of Comparative Example 2.

[0024] Fig.14 This is a cross-sectional view showing a state in the middle of manufacturing of Comparative Example 2.

[0025] Fig.15 This is a cross-sectional view showing a state in the middle of manufacturing of Comparative Example 2.

[0026] Fig.16 This is a cross-sectional view showing a state in the middle of manufacturing of Comparative Example 2.

[0027] Fig.17 This is a cross-sectional view showing a state in the middle of manufacturing of Comparative Example 2.

[0028] Fig.18 This is a cross-sectional view showing a state in the middle of manufacturing of Comparative Example 2.

[0029] Explanation of symbols 1 n - Drift zone 2 p-type base region 3 n + Type source region 4p + Type contact area 5 Grooves 6 Gate insulation film 7. Gate electrode 8 Semiconductor substrate 8a Source contact trench 9 Interlayer insulation film 9-1 HTO film 9-2 BPSG membrane 9a Contact hole 10, 20 Semiconductor devices 11.21 TiSix membrane 12, 22 TiN film 13, 23 Metal plug 13a W film 14. Front electrode 15n + Type Drain 16 Back electrode d The distance that the side surface of the interlayer insulating film retreats away from the source contact trench w1 Width of contact hole w2 Width of source contact trench DETAILED DESCRIPTION

[0030] <Overview of Embodiments of the Invention> (1) A semiconductor device according to one embodiment of the present disclosure is as follows. A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate. A second semiconductor region of a second conductivity type is provided between the front surface of the semiconductor substrate and the first semiconductor region. An element structure including a pn junction between the second semiconductor region and the first semiconductor region is provided on the front surface side of the semiconductor substrate. An interlayer insulating film is provided on the front surface of the semiconductor substrate. The interlayer insulating film covers the element structure. A contact hole penetrates the interlayer insulating film in a depth direction and reaches the semiconductor substrate. The contact structure contacts the semiconductor substrate in the contact hole.

[0031] The first electrode is electrically connected to the second semiconductor region via the contact structure. The second electrode is arranged on the back side of the semiconductor substrate. The contact structure is composed of a titanium silicide film, a titanium nitride film and a metal plug. The titanium silicide film contacts the semiconductor substrate in the contact hole and extends on the surface of the interlayer insulating film along the side wall of the contact hole. The titanium nitride film is arranged along the surface of the titanium silicide film. The metal plug is buried on the titanium nitride film inside the contact hole.

[0032] According to the above disclosure, the first electrode is electrically connected to the semiconductor substrate via a TiSix film (titanium silicide film), thereby reducing the contact resistance between the first electrode and the semiconductor substrate. In addition, according to the above disclosure, special high-temperature heat treatment such as silicidation is not required when forming the TiSix film. Therefore, the stress generated locally on the semiconductor substrate can be suppressed. In addition, since a Ti film that absorbs hydrogen is not formed on the surface of the interlayer insulating film, it becomes easy to recover the crystal damage of the semiconductor substrate by hydrogen annealing. In addition, since a Ti film is not formed on the surface of the interlayer insulating film, it is possible to prevent the adhesion with the interlayer insulating film from being reduced due to the reaction between the material gas and the Ti film when forming the metal plug.

[0033] (2) In the semiconductor device of the present disclosure, in the above (1), a contact trench having a predetermined depth is provided on the front surface of the semiconductor substrate so as to be continuous with the contact hole. The titanium silicide film may be provided along the sidewall of the contact hole and the inner wall of the contact trench.

[0034] According to the above disclosure, the stress applied to the interlayer insulating film and the semiconductor substrate is the same at the sidewall of the contact hole and the sidewall of the contact trench.

[0035] (3) In the semiconductor device of the present disclosure in the above (2), the thickness of the titanium silicide film may be the same from the sidewall of the contact hole to the sidewall of the contact trench.

[0036] According to the above disclosure, the stress applied to the interlayer insulating film and the semiconductor substrate is the same at the sidewall of the contact hole and the sidewall of the contact trench.

[0037] (4) In the semiconductor device of the present disclosure in the above (2), the interlayer insulating film may be located at a distance of 10 nm or less from the contact trench in a direction parallel to the front surface of the semiconductor substrate.

[0038] According to the above disclosure, the step coverage of the metal plug is improved.

[0039] (5) In the semiconductor device of the present disclosure, in any one of (1) to (4) above, the titanium silicide film terminates at a side surface of the interlayer insulating film. The first electrode may be provided on an upper surface of the interlayer insulating film in contact with the interlayer insulating film.

[0040] According to the above disclosure, the adhesion of the first electrode is improved, and it is possible to suppress the first electrode from being peeled off from the interlayer insulating film.

[0041] (6) In the semiconductor device of the present disclosure, in any one of (1) to (4) above, the titanium silicide film covers the entire surface of the interlayer insulating film. The first electrode is provided on the upper surface of the interlayer insulating film via the titanium silicide film and the titanium nitride film.

[0042] According to the above disclosure, it is possible to suppress damage to the interlayer insulating film caused by ultrasonic vibration when wire bonding is performed on the first electrode.

[0043] (7) A method for manufacturing a semiconductor device according to one embodiment of the present disclosure is as follows. A first step is performed, in which a second semiconductor region of a second conductivity type is formed in a surface area on the front surface of a semiconductor substrate, which is in contact with a first semiconductor region of a first conductivity type inside the semiconductor substrate, and an element structure including a pn junction between the second semiconductor region and the first semiconductor region is formed. A second step is performed, in which an interlayer insulating film covering the element structure is formed on the front surface of the semiconductor substrate. A third step is performed, in which a contact hole is formed that penetrates the interlayer insulating film in a depth direction and reaches the semiconductor substrate. A fourth step is performed, in which a contact structure that contacts the semiconductor substrate is formed in the contact hole.

[0044] A fifth step is performed, in which a first electrode electrically connected to the second semiconductor region via the contact structure is formed. A first annealing step is performed, which, after the fifth step, recovers the crystal damage of the semiconductor substrate by heat treatment in a hydrogen atmosphere. The fourth step includes first to third deposition steps. In the first deposition step, a titanium silicide film is deposited by sputtering, the titanium silicide film covers the entire surface of the interlayer insulating film and contacts the semiconductor substrate in the contact hole. In the second deposition step, a titanium nitride film is deposited on the surface of the titanium silicide film by sputtering. In the third deposition step, a metal plug is buried on the titanium nitride film inside the contact hole. The contact structure composed of the titanium silicide film, the titanium nitride film and the metal plug is formed.

[0045] According to the above disclosure, the first electrode is electrically connected to the semiconductor substrate via a TiSix film (titanium silicide film), thereby reducing the contact resistance between the first electrode and the semiconductor substrate. In addition, according to the above disclosure, when forming the TiSix film, a particularly high-temperature heat treatment such as silicidation is not required. Therefore, the stress generated locally on the semiconductor substrate can be suppressed. In addition, since a Ti film that absorbs hydrogen is not formed on the surface of the interlayer insulating film, it becomes easy to recover the crystal damage of the semiconductor substrate by hydrogen annealing. In addition, since a Ti film is not formed on the surface of the interlayer insulating film, it is possible to prevent the adhesion with the interlayer insulating film from being reduced due to the reaction between the material gas and the Ti film when forming the metal plug.

[0046] (8) In addition, the method for manufacturing a semiconductor device of the present disclosure includes, in the above (7), a sixth step after the third step and before the fourth step, in which a contact groove of a predetermined depth continuous with the contact hole is formed on the front surface of the semiconductor substrate. In the first deposition step, the titanium silicide film may be formed along the surface of the interlayer insulating film and the inner wall of the contact groove.

[0047] According to the above disclosure, since the contact area between the TiSix film and the semiconductor substrate is increased, it is possible to suppress an increase in the contact resistance between the first electrode and the semiconductor substrate.

[0048] (9) In the method for manufacturing a semiconductor device according to the present disclosure, in the above (8), the method may include a seventh step after the sixth step and before the fourth step, wherein the interlayer insulating film is flattened in the seventh step.

[0049] According to the above disclosure, it is possible to improve the embedding property of the metal plug into the contact trench.

[0050] (10) In the method for manufacturing a semiconductor device according to the present disclosure, in any one of (7) to (9) above, the first deposition step and the second deposition step may be performed continuously using the same sputtering device.

[0051] According to the above disclosure, the process can be simplified and the cost can be reduced.

[0052] (11) In addition, in any one of the above (7) to (10), the fourth step further includes a removal step, in which the titanium nitride film and the titanium silicide film are etched back using the metal plug as a mask to expose the upper surface of the interlayer insulating film. In the fifth step, the first electrode may be formed on the upper surface of the interlayer insulating film in contact with the interlayer insulating film.

[0053] According to the above disclosure, the adhesion of the first electrode is improved, and it is possible to suppress the first electrode from being peeled off from the interlayer insulating film.

[0054] (12) In the method for manufacturing a semiconductor device of the present disclosure, in any one of (7) to (11) above, the first deposition step may be performed in a temperature environment of 300° C. or less.

[0055] According to the above disclosure, it is possible to suppress stress generated locally in the semiconductor substrate.

[0056] (13) In addition, in any one of the above (7) to (12), the method for manufacturing a semiconductor device of the present disclosure includes performing an irradiation step, irradiating the semiconductor substrate with radiation after the first annealing step. A second annealing step may also be performed, and after the irradiation step, a parasitic diode formed at the pn junction is adjusted to a predetermined reverse recovery characteristic by heat treatment in a hydrogen atmosphere.

[0057] According to the above disclosure, the crystal damage that causes the gate threshold voltage to decrease can be recovered.

[0058] <Foundation underlying the present invention> As the subject of this embodiment, it is possible to reduce the contact (electrical contact) resistance between the front electrode and the semiconductor substrate, and to recover the crystal damage caused to the semiconductor substrate by irradiation with radiation such as electron beams, implantation of impurity ions, etc. by hydrogen annealing (heat treatment in a hydrogen atmosphere). Conventionally, since titanium (Ti) and n-type silicon (Si) have low contact resistance, a method of forming a titanium silicide (TiSix) film between the front electrode and the semiconductor substrate by silicidation reaction of the Ti film and the semiconductor substrate (Si substrate) is known, but due to the volume expansion of the TiSix film caused by silicidation, the stress generated locally on the semiconductor substrate becomes larger.

[0059] The higher the heat treatment temperature for silicidation, the lower the contact resistance between the TiSix film and the semiconductor substrate. However, due to the volume expansion of the TiSix film caused by silicidation, the stress generated locally on the semiconductor substrate further increases. For example, in the case where the contact area between the front electrode and the semiconductor substrate is increased by burying the contact structure of the front electrode in a contact groove provided on the front side of the semiconductor substrate, thereby reducing the contact resistance between the front electrode and the semiconductor substrate, the TiSix film is formed along the inner wall of the contact groove. Since the width of the contact groove is narrow and the depth is shallow, there is a concern that the stress generated locally on the semiconductor substrate will further increase due to the volume expansion of the TiSix film caused by silicidation.

[0060] In addition, when a TiSix film is formed by a silicidation reaction with a semiconductor substrate, a Ti film as a material film of the TiSix film is formed so as to cover the entire surface of the interlayer insulating film. However, the Ti film easily absorbs hydrogen, which hinders the effect of hydrogen annealing for recovering crystal damage of the semiconductor substrate. Therefore, even if hydrogen annealing is performed, it is difficult to recover characteristics such as gate threshold voltage. In particular, in order to improve the gate voltage between the p-type base region and the n-type base region, the gate voltage between the p-type base region and the n-type base region is increased. - In products (semiconductor devices) that have been irradiated with radiation such as electron beams to improve switching characteristics such as the reverse recovery time trr of the parasitic diode (body diode) formed by the pn junction (main junction) of the type drift region, crystal damage caused in the semiconductor substrate by the radiation irradiation is not fully recovered.

[0061] It is also possible to imagine that the crystal damage of the semiconductor substrate is not fully recovered, and the reduction caused by the crystal damage of the semiconductor substrate is estimated by excessively increasing the impurity dose of the predetermined diffusion region in the semiconductor substrate, and the predetermined characteristics as a product are matched with the predetermined value by presetting the predetermined characteristics high. However, in this case, the crystal damage of the semiconductor substrate is recovered by hydrogen annealing, so that the predetermined characteristics sometimes become higher than the predetermined value, which is easy to cause characteristic changes in reliability tests such as high temperature application tests. Therefore, it is necessary to allow the product specifications to predict the characteristic changes caused by the crystal damage of the semiconductor substrate to a certain extent, and the reliability of the product (the reliability of each characteristic evaluated in reliability tests such as high temperature application tests) is poor. This embodiment eliminates such a problem.

[0062] Hereinafter, preferred embodiments of the semiconductor device and the method for manufacturing the semiconductor device disclosed in the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, in the layers and / or regions marked with n or p, it means that electrons or holes are the majority carriers, respectively. In addition, + and - marked on n and p refer to high impurity concentration and low impurity concentration, respectively, compared with the layers and / or regions not marked with + and -. It should be noted that in the following descriptions of the embodiments and the accompanying drawings, the same symbols are marked for the same configurations, and repeated descriptions are omitted.

[0063] (Details of Implementation Method 1) Hereinafter, a semiconductor device according to the first embodiment that solves the above-mentioned problems will be described by taking a MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS field effect transistor having an insulated gate having a three-layer structure of metal-oxide film-semiconductor) as an example. Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment. Figure 1 The semiconductor device 10 of the first embodiment shown is a vertical MOSFET having a trench gate structure (element structure) having a contact structure composed of a titanium silicide (TiSix) film 11 (where x is a positive number), a titanium nitride (TiN) film 12, and a metal plug (lead electrode portion) 13 between a front electrode (first electrode) 14 and a semiconductor substrate (semiconductor chip) 8.

[0064] The semiconductor substrate 8 is, for example, n - n type drift region (first semiconductor region) 1 - Type Si bulk substrate, or in the form of n + The n-type drain region 15 + The n-type starting substrate (Si bulk substrate) is stacked on top of the - Type drift region 1 n - The semiconductor substrate 8 is a Si substrate formed by an n-type epitaxial layer. - Type drift region 1 n - In the case of bulk Si substrate, n + The drain region 15 is a diffusion region formed in the surface region of the back side of the semiconductor substrate 8 by ion implantation. + The drain region 15 is connected to n - The back side of the semiconductor substrate 8 is provided in contact with the n type drift region 1. - The entire back side of the semiconductor substrate 8 is connected to the n + A back surface electrode (second electrode) 16 serving as a drain electrode is provided in contact with the drain region 15 .

[0065] The trench gate structure consists of a p-type base region (second semiconductor region) 2, n + Type source region 3, p + The p-type base region 2, n-type contact region 4, trench 5, gate insulating film 6 and gate electrode 7 are provided on the front side of semiconductor substrate 8. + Type 3 source region and p + The p-type contact region 4 is a diffusion region formed by ion implantation in the surface region of the front side of the semiconductor substrate 8. - The type drift region 1 is arranged on the front side of the semiconductor substrate 8 in contact with the n - Type drift region 1. + Type 3 source region and p + The p-type contact regions 4 are selectively provided between the front surface of the semiconductor substrate 8 and the p-type base region 2 in a manner to be in contact with the p-type base region 2 .

[0066] n + Type 3 source region and p + The type contact region 4 is in ohmic contact with the TiSix film 11. + The type contact region 4 is arranged in a manner separated from the trench 5. + The contact region 4 extends from the front surface of the semiconductor substrate 8 to a depth of about 100 m. + Type source region 3 is closer to n + The p-type drain region 15 is located at a deep position on the back side of the semiconductor substrate 8. + In this case, the p-type base region 2 replaces the p + The semiconductor substrate 8 has a p-type base region 2, an n-type contact region 4 and a contact region 5 with the TiSix film 11. + Type source region 3, p + Type contact area 4 and n + The portion outside the drain region 15 is n - Type drift region 1.

[0067] The trench 5 penetrates the semiconductor substrate 8 from the front surface in the depth direction. + type source region 3 and p-type base region 2 while in n - The inner part of the type drift region 1 is terminated. A gate insulating film 6 is provided along the inner wall (side wall and bottom surface) of the trench 5. In the inner part of the trench 5, a gate electrode 7 is buried on the gate insulating film 6. + Type source region 3, p-type base region 2 and n - The type drift region 1 may be opposed to the gate electrode 7 via the gate insulating film 6 on the side wall of the trench 5, and the upper ends of the gate electrode 7 and the gate insulating film 6 (the ends on the opening side of the trench 5) may be located closer to the n direction than the front side of the semiconductor substrate 8. + The electrode is terminated at a deeper position on the side of the drain region 15 (ie, inside the trench 5).

[0068] The interlayer insulating film 9 is provided on the front surface of the semiconductor substrate 8 and covers the gate electrode 7. A contact hole 9a is provided which penetrates the interlayer insulating film 9 in the depth direction and reaches the semiconductor substrate 8. The cross-sectional shape of the contact hole 9a may be a substantially rectangular shape or a substantially tapered (trapezoidal) shape whose width becomes narrower as it approaches the semiconductor substrate 8 side. In the case of having a source contact groove 8a described later, the aspect ratio (=depth / width) of the contact hole 9a may be reduced by making the thickness of the interlayer insulating film 9 relatively thin, or the upper surface corner (boundary between the upper surface and the side surface) of the interlayer insulating film 9 may be rounded by reflowing (flattening) the interlayer insulating film 9, thereby improving the embedding property of the metal plug 13 into the source contact groove 8a.

[0069] The interlayer insulating film 9 is composed of, for example, a silicon oxide (SiO2) film such as a BPSG (Boro Phospho Silicate Glass) film 9-2. For example, by setting the total boron (B) concentration and phosphorus (P) concentration of the BPSG film 9-2 to, for example, 6 mol% or less and reflowing the BPSG film 9-2, the width w1 of the contact hole 9a is relatively expanded on the opposite side to the semiconductor substrate 8 side (i.e., the portion continuous with the source contact trench 8a). As a result, the W film 13a (see Figure 5 ) when the contact hole 9a is not easily clogged, so the embedding property of the metal plug 13 into the source contact trench 8a can be improved.

[0070] The interlayer insulating film 9 may also include a deposited SiO2 film (hereinafter referred to as an HTO film) 9-1 deposited by conventional high temperature oxidation (HTO: High Temperature Oxide). In this case, the interlayer insulating film 9, for example, has a double-layer structure in which an HTO film 9-1 and a BPSG film 9-2 are stacked in sequence. The film density and insulating properties of the HTO film 9-1 are as high as those of a thermal oxide film, for example, and have good insulating properties compared to a deposited SiO2 film formed by PECVD or sputtering. By making the interlayer insulating film 9 include the HTO film 9-1, the short-circuit tolerance between the electrodes (between the gate electrode 7 and the front electrode 14) electrically insulated by the interlayer insulating film 9 is improved, and the reliability of the semiconductor device 10 is improved. Instead of the HTO film 9-1, a deposited SiO2 film using TEOS (TetraEthoxy Silane: ethyl orthosilicate) may be used.

[0071] A source contact groove 8a is provided on the front surface of the semiconductor substrate 8 so as to be continuous with the contact hole 9a of the interlayer insulating film 9. The source contact groove 8a penetrates the semiconductor substrate 8 from the front surface in the depth direction. + Type source region 3 and in p +The source contact trench 8a extends from the front surface of the semiconductor substrate 8 to the inner portion of the source contact region 4. + Type source region 3 is closer to n + The bottom surface of the source contact trench 8a is formed by the p + The source contact trench 8a is surrounded by the p-type contact region 4, and the entire bottom surface of the source contact trench 8a is exposed. + The source contact trench 8a has an n type contact region 4. + Type 3 source region and p + The source contact region 4a may have a substantially rectangular cross-sectional shape or a substantially tapered shape in which the width w2 becomes narrower toward the back surface side of the semiconductor substrate 8.

[0072] The width w2 of the source contact trench 8a is narrower than the width w1 of the contact hole 9a. The reason for this is that after the source contact trench 8a is formed in a self-adjusting manner to be continuous with the contact hole 9a using the etching mask used when forming the contact hole 9a, the interlayer insulating film 9 (BPSG film 9-2) is reflowed, so that the side surface of the interlayer insulating film 9 (the side wall of the contact hole 9a) moves (retres) by a predetermined distance d in a direction away from the source contact trench 8a, and the width w1 of the contact hole 9a is widened. Between the side surface of the interlayer insulating film 9 and the side wall of the source contact trench 8a, the front surface of the semiconductor substrate 8 is exposed by a distance d of about 10 nm or less, so that a step with a height difference of the distance d is generated.

[0073] By providing the source contact groove 8a, the contact area between the TiSix film 11 and the semiconductor substrate 8 becomes larger. Therefore, by narrowing the width between the adjacent grooves 5 to achieve miniaturization, even if the width w1 of the contact hole 9a is narrowed, the increase in the contact resistance between the front electrode 14 and the semiconductor substrate 8 can be suppressed. In addition, by providing the source contact groove 8a, when the semiconductor substrate 8 is turned off, the contact resistance between the front electrode 14 and the semiconductor substrate 8 can be reduced. - The holes in the drift region 1 are easily extracted to the front electrode 14, and the avalanche resistance is improved. When the semiconductor device 10 is set to a low withstand voltage category of about 250V or less or when miniaturization is performed, avalanche breakdown is easily caused by parasitic bipolar action, so a source contact groove 8a can be provided. By providing the source contact groove 8a, the avalanche resistance can be improved not only in the case of setting it to a low withstand voltage category, but also in all withstand voltage categories.

[0074] The source contact groove 8a may not be provided. In this case, on the front surface of the semiconductor substrate 8 exposed by the contact hole 9a, n + Type 3 source region and p +The type contact region 4 is in ohmic contact with the TiSix film 11. The TiSix film 11 and the TiN film 12 are arranged from the side wall of the contact hole 9a (the side of the interlayer insulating film 9) to the bottom surface (the front surface of the semiconductor substrate 8 exposed in the contact hole 9a), and the metal plug 13 is buried in the TiN film 12 inside the contact hole 9a. In the TiSix film 11 and the TiN film 12, the conditions of the side wall portion and the bottom surface portion of the contact hole 9a are the same as those of the side wall portion and the bottom surface portion of the source contact groove 8a.

[0075] Along the side wall of the contact hole 9a (the side of the interlayer insulating film 9), the surface connecting the side wall of the contact hole 9a and the side wall of the source contact groove 8a (hereinafter referred to as the step surface), and the inner wall of the source contact groove 8a, the TiSix film 11 and the TiN film 12 are stacked in sequence on these surfaces. The TiSix film 11 and the TiN film 12 are not provided on the upper surface of the interlayer insulating film 9. The upper surface of the interlayer insulating film 9 refers to the portion of the surface of the interlayer insulating film 9 other than the side wall where the contact hole 9a is formed. By making the front electrode 14 directly contact with the upper surface of the interlayer insulating film 9, the adhesion of the front electrode 14 is improved, and it is possible to suppress the front electrode 14 from peeling off from the interlayer insulating film 9.

[0076] In addition, since the TiSix film 11 and the TiN film 12 are not provided on the upper surface of the interlayer insulating film 9, damage to the TiSix film 11 and the TiN film 12, which have a relatively high hardness, caused by ultrasonic vibration during wire bonding to the front electrode 14 can be suppressed. In addition, since the TiSix film 11 and the TiN film 12 are not provided on the upper surface of the interlayer insulating film 9, the effect of hydrogen annealing for recovering crystal damage of the semiconductor substrate 8, for example, is not hindered. Therefore, for example, by irradiating with radiation such as electron beams, n - By controlling the carrier lifetime of the drift region 1, the crystal damage generated in the semiconductor substrate 8 can be recovered by hydrogen annealing, thereby recovering characteristics such as the gate threshold voltage.

[0077] The TiSix film 11 and the TiN film 12 are formed (deposited) by sputtering, and have a tendency to be thicker at the bottom surface of the source contact groove 8a than at the side wall of the contact hole 9a, the step surface (the front surface of the semiconductor substrate 8), and the source contact groove 8a. The thickness of the TiSix film 11 and the TiN film 12 is roughly the same from the side wall of the contact hole 9a to the side wall of the source contact groove 8a. Therefore, the stress applied to the interlayer insulating film 9 and the semiconductor substrate 8 is the same at the side wall of the contact hole 9a and the side wall of the source contact groove 8a. The thickness being roughly the same means that the thickness is roughly the same within the range of the allowable error caused by the manufacturing process deviation.

[0078] The TiSix film 11 is formed between the inner wall of the source contact trench 8a and the n + Type 3 source region and p + The source contact region 4 is in ohmic contact. By providing the source contact groove 8a, the contact area between the TiSix film 11 and the semiconductor substrate 8 can be increased, thereby reducing the contact resistance between the TiSix film 11 and the semiconductor substrate 8. Therefore, even if the width w1 of the contact hole 9a is narrowed due to miniaturization, the increase in the contact resistance between the front electrode 14 and the semiconductor substrate 8 can be suppressed. The TiN film 12 is a barrier metal having a diffusion prevention function of preventing metal atoms from diffusing from the front electrode 14 to the semiconductor substrate 8 side and a mutual reaction prevention function of preventing mutual reaction between the parts sandwiching the TiN film 12.

[0079] The end of the TiSix film 11 terminates on the surface of the interlayer insulating film 9 (for example, on the side surface of the interlayer insulating film 9). The end of the TiN film 12 terminates on the surface of the TiSix film 11. The adhesion between the TiSix film 11 and the interlayer insulating film 9 is higher than the adhesion between the TiN film 12 and the interlayer insulating film 9. Therefore, by providing the TiSix film 11 between the TiN film 12 and the interlayer insulating film 9, the adhesion of the front electrode 14 is improved. A metal plug 13 is provided on the TiN film 12 in such a manner as to bury the contact hole 9a and the source contact groove 8a. The height position of the upper surface of the metal plug 13 is located at the same height position as the end of the TiN film 12, or is located at a position lower than the height position of the end of the TiN film 12 toward the semiconductor substrate 8. The material of the metal plug 13 is, for example, tungsten (W) with high embedding property, and has poor adhesion to the semiconductor substrate 8. By providing the TiSix film 11 and the TiN film 12 between the semiconductor substrate 8 and the metal plug 13 , the adhesion of the metal plug 13 is improved.

[0080] The contact structure of the front electrode 14 is constituted by these TiSix films 11, TiN films 12 and metal plugs 13. The metal plugs 13 may be omitted, and the front electrode 14 may be buried in the contact holes 9a and the source contact grooves 8a instead of the metal plugs 13. In this case, the TiN film 12 may also be omitted. That is, the contact structure of the front electrode 14 may be constituted only by the TiSix film 11 in ohmic contact with the semiconductor substrate 8. The front electrode 14 is provided from the upper surface of the interlayer insulating film 9 to the upper surface of the metal plug 13 in contact with the upper surfaces of these interlayer insulating films 9 and the upper surfaces of the metal plugs 13. The front electrode 14 is, for example, an aluminum (Al) film or an Al alloy film. The front electrode 14 is connected to the p-type base region 2, n-type base region 3, and n-type base region 4 via the metal plugs 13, the TiN film 12 and the TiSix film 11. + Type 3 source region and p + The type contact region 4 is electrically connected and functions as a source electrode.

[0081] A method for manufacturing the semiconductor device 10 according to the first embodiment will be described. Figures 2 to 6 1 is a cross-sectional view showing a semiconductor device in the middle of manufacturing according to Embodiment 1. Figure 2 As shown, by the usual method, in becoming n - A trench gate structure, an interlayer insulating film 9 (HTO film 9-1 and BPSG film 9-2) and a contact hole 9a are formed on the front side of the semiconductor substrate 8 of the drift region 1 (first to third steps). Next, the front side of the semiconductor substrate 8 is etched using the same resist mask used when forming the contact hole 9a to form a source contact trench 8a continuous with the contact hole 9a (sixth step). Then, the resist mask used when forming the source contact trench 8a is removed. In this case, the resist mask can also be removed after forming the contact hole 9a, and the source contact trench 8a can be formed using the interlayer insulating film 9 as a mask.

[0082] Next, the BPSG film 9-2 is reflowed while the exposed surface of the semiconductor substrate 8 (here, the inner wall of the source contact groove 8a) is oxidized by heat treatment (the seventh step). As a result, the corner of the upper surface of the BPSG film 9-2 is rounded, and the side surface of the BPSG film 9-2 is retreated by a predetermined distance d in the direction away from the source contact groove 8a. Next, the oxide film covering the semiconductor substrate 8 is removed in the contact hole 9a. At this time, the end of the HTO film 9-1 (the portion exposed by retreating the side surface of the BPSG film 9-2 by a predetermined distance d) is removed together with the oxide film, and the side surface of the HTO film 9-1 is also retreated by a predetermined distance d in the direction away from the source contact groove 8a.

[0083] In this way, by making the side surface of the interlayer insulating film 9 (HTO film 9-1 and BPSG film 9-2) retreat by a predetermined distance d in the direction away from the source contact groove 8a, the width w1 of the contact hole 9a is widened. As a result, in the subsequent process, the W film 13a (see Figure 5 ) is embedded in the source contact groove 8a. In addition, by reflowing the BPSG film 9-2 while oxidizing the exposed surface of the semiconductor substrate 8, the distance d by which the side surface of the interlayer insulating film 9 retreats in the direction away from the source contact groove 8a can be reduced to about 10 nm or less. Therefore, in the subsequent process, the step coverage (step coverage) of the W film 13a deposited on the front surface of the semiconductor substrate 8 is improved.

[0084] Then, if Figure 3As shown, in a temperature environment of about 300°C or less (e.g., about 200°C), a TiSix film 11 is deposited (formed) along the surface (upper surface and side surface) of the interlayer insulating film 9 and the inner wall (bottom surface and side wall) of the source contact groove 8a by sputtering (first deposition process). The thickness of the TiSix film 11 is, for example, about 40nm. Since no special heat treatment such as silicide of the Ti film is performed, the TiSix film 11 maintains the thickness at the time of sputtering and does not expand in volume. Next, as Figure 4 As shown, in a temperature environment of about 300° C. or less (eg, about 200° C.), the TiN film 12 is deposited (formed) along the surface of the TiSix film 11 by sputtering (a second deposition step).

[0085] The TiSix film 11 and the TiN film 12 can be formed using different sputtering devices. Alternatively, for example, the same sputtering device that can carry multiple sputtering targets can be used to continuously form the TiSix film 11 and the TiN film 12 by appropriately switching the sputtering targets, the introduced gas, etc. By continuously forming the TiSix film 11 and the TiN film 12 using the same sputtering device, the process can be simplified and the cost can be reduced. The conditions such as the sputtering targets and the introduced gas used to form the TiSix film 11 and the TiN film 12 can use normal conditions.

[0086] Then, if Figure 5 As shown, WF6 gas is used as the material gas, and monosilane (SiH4) gas or hydrogen (H2) gas is used as the source gas, and a W film 13a is deposited (formed) on the outermost surface of the semiconductor substrate 8 by CVD in a manner that buries the contact hole 9a and the source contact trench 8a. At this time, the TiSix film 11 and the TiN film 12 covering the entire surface of the interlayer insulating film 9 function as a barrier metal. Therefore, even if the material gas of the W film 13a penetrates the TiN film 12 from a portion of the TiN film 12 where the function as a barrier metal is reduced, a chemical reaction that occurs when a titanium (Ti) film is set as a barrier metal and generates fluorine (F) and H2 that reduce the adhesion with the interlayer insulating film 9 will not be caused.

[0087] Then, if Figure 6As shown, the W film 13a is etched back, and the W film 13a remains only inside the contact hole 9a and the source contact trench 8a (third deposition process). The W film 13a remaining inside the contact hole 9a and the source contact trench 8a becomes the metal plug 13. Next, the TiN film 12 and the TiSix film 11 are etched back using the metal plug 13 as an etching mask, thereby exposing the upper surface of the interlayer insulating film 9 (removal process). The dry etching for etching back the W film 13a and the dry etching for etching back the TiN film 12 and the TiSix film 11 can be continuously performed by switching the etching gas, or the dry etching for etching back the W film 13a and the dry etching for etching back the TiN film 12 and the TiSix film 11 can be performed using different etching devices.

[0088] Next, the front electrode 14 is formed on the outermost surface of the front side of the semiconductor substrate 8 by sputtering and photoetching (fifth step). Then, the resist mask used to form the front electrode 14 is removed (ashing). Then, for example, the crystal damage of the semiconductor substrate 8 is restored by hydrogen annealing in a temperature environment of about 380°C (first annealing step). This hydrogen annealing can be performed at any time after the front electrode 14 is formed, but it is effective to perform it after the semiconductor substrate 8 is damaged by etching, ashing, etc. Then, an n + type drain region 15 and back electrode 16.

[0089] At any time after the hydrogen annealing, the semiconductor substrate 8 may be irradiated with radiation such as electron beams from the front or back surface (irradiation step). - The carrier lifetime of the drift region 1 can be controlled. In addition, after the radiation exposure, hydrogen annealing can be performed in a temperature environment of, for example, about 350°C to adjust the crystal damage of the semiconductor substrate 8 (second annealing process) so that the reverse recovery characteristics of the parasitic diode become a predetermined lifetime (reverse recovery time) instead of completely recovering the crystal damage caused by the radiation exposure. The crystal damage that is the cause of the gate threshold voltage being lowered can also be recovered by hydrogen annealing after the radiation exposure. Thus, Figure 1 The semiconductor device 10 shown is completed.

[0090] The operation of the semiconductor device 10 according to the first embodiment will be described. A positive voltage with respect to the source electrode (front electrode 14) is applied to the drain electrode (back electrode 16). + The p-type contact region 4 and the p-type base region 2 and the n-type - Type drift region 1 and n + The pn junction (main junction) between the type drain regions 15 is reverse biased. If the applied voltage applied to the gate electrode 7 is smaller than the gate threshold voltage in this state, the semiconductor device 10 (MOSFET) maintains the off state.

[0091] Only the front electrode 14 is arranged on the interlayer insulating film 9 of the semiconductor device 10, and the effect of hydrogen annealing is not hindered. Therefore, even if the semiconductor device 10 is irradiated with radiation such as electron beams for improving the switching characteristics of the parasitic diode, the crystal damage of the semiconductor substrate 8 is almost recovered by the subsequent hydrogen annealing, and the gate threshold voltage characteristics are restored (see Fig. 9 ). Therefore, the semiconductor device 10 remains normally off.

[0092] On the other hand, when a voltage higher than the gate threshold voltage is applied to the gate electrode 7 while a positive voltage relative to the source electrode is applied to the drain electrode, a channel (n-type inversion layer) is formed in the portion of the p-type base region 2 along the side wall of the trench 5. + The drain region 15 is connected to n - type drift region 1 and the channel towards n + The drift current (main current) of the source region 3 is turned on, and the semiconductor device 10 is turned on.

[0093] As described above, according to Embodiment 1, the front electrode and the semiconductor substrate are electrically connected via the TiSix film deposited on the semiconductor substrate by sputtering. By electrically connecting the front electrode and the semiconductor substrate via the TiSix film, the contact resistance between the front electrode and the semiconductor substrate can be reduced. In addition, according to Embodiment 1, since a particularly high temperature heat treatment such as silicidation or above 600° C. is not required when forming the TiSix film on the semiconductor substrate, the TiSix film is directly deposited by sputtering in a low temperature environment of below 300° C., and thus stress generated locally on the semiconductor substrate can be suppressed.

[0094] In addition, for example, in the case where a TiSix film is formed by a silicidation reaction with a semiconductor substrate, a Ti film as a material film of the TiSix film covers the entire surface of the interlayer insulating film. Therefore, the effect of hydrogen annealing for recovering the crystal damage of the semiconductor substrate is hindered, or in order to obtain the effect of hydrogen annealing, it is necessary to remove the portion of the Ti film covering the upper surface of the interlayer insulating film. On the other hand, according to Embodiment 1, since the TiSix film is directly deposited by sputtering, the Ti film is not formed on the surface of the interlayer insulating film, and thus the recovery of the crystal damage of the semiconductor substrate by hydrogen annealing becomes easy. For example, even a product (semiconductor device) that is irradiated with radiation such as an electron beam in order to improve the switching characteristics such as the reverse recovery time of the body diode can fully recover the crystal damage of the semiconductor substrate by hydrogen annealing.

[0095] That is, according to the first embodiment, it is not necessary to assume that the gate threshold voltage will be lowered due to crystal damage of the semiconductor substrate, and the gate threshold voltage is set high in advance by estimating the reduction amount caused by crystal damage of the semiconductor substrate by making the impurity dose of the predetermined diffusion region in the semiconductor substrate too high. Therefore, it is not easy to cause characteristic changes in reliability tests such as high temperature application tests, and the reliability of the product (the reliability of each characteristic evaluated in reliability tests such as high temperature application tests) is improved. In addition, according to the first embodiment, since the Ti film is not used as the barrier metal, the problem caused by the reaction between the material gas and the Ti film when forming the metal plug does not occur (refer to the comparative example described later). Therefore, it is possible to prevent the adhesion with the interlayer insulating film from being reduced.

[0096] In addition, for example, when the CVD method is used in the deposition of the TiSix film and the TiN film, since the conditions such as the type of gas used when forming the TiSix film and the TiN film are different, the TiSix film and the TiN film cannot be continuously formed using the same CVD device. On the other hand, according to Embodiment 1, by depositing the TiSix film by sputtering, the TiSix film and the TiN film can be continuously formed using the same sputtering device. Thus, since the process can be simplified, the cost can be reduced. In addition, since the process of transporting the semiconductor wafer can be omitted between the formation of the TiSix film and the formation of the TiN film, contamination during wafer transport is suppressed, the pass rate is improved, and the reliability of the product is improved.

[0097] (Details of Implementation Method 2) Hereinafter, a semiconductor device according to a second embodiment that solves the above-mentioned problems will be described. Figure 7 This is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment. Figure 8 2 is a cross-sectional view showing a semiconductor device of Embodiment 2 in the middle of manufacturing. The semiconductor device 20 of Embodiment 2 is different from the semiconductor device 10 of Embodiment 1 (see Figure 1 ) is that the TiSix film 21 and the TiN film 22 constituting the contact structure of the front electrode 14 extend between the front electrode 14 and the interlayer insulating film 9 to cover the entire surface of the interlayer insulating film 9.

[0098] The structures of the TiSix film 21 and the TiN film 22 inside the contact hole 9a and the source contact groove 8a are respectively the same as the TiSix film 11 and the TiN film 12 of Embodiment 1. The TiSix film 21 and the TiN film 22 function as a barrier metal that suppresses the diffusion of metal atoms from the front electrode 14 to the interlayer insulating film 9. The TiSix film 21 and the TiN film 22 have the function of suppressing damage to the interlayer insulating film 9 caused by ultrasonic vibration when the front electrode 14 is wire-bonded.

[0099] The method for manufacturing the semiconductor device 20 according to the second embodiment omits the etching back of the TiSix film 11 and the TiN film 12 in the method for manufacturing the semiconductor device 10 according to the first embodiment (see Figure 6 That is, the steps from forming the trench gate structure to forming the metal plug 13 are sequentially performed in the same manner as in the first embodiment ( Figures 2 to 5 , 8). Then, by leaving the TiSix film 11 and the TiN film 12 on the upper surface of the interlayer insulating film 9 ( Figure 8 ) The steps after the formation of the front electrode 14 are performed in sequence, thereby completing Figure 7 A semiconductor device 20 is shown.

[0100] Even if the TiSix film 11 and the TiN film 12 remain on the upper surface of the interlayer insulating film 9, the effect of hydrogen annealing for recovering the crystal damage of the semiconductor substrate 8 is not hindered. In addition, the adhesion between the TiSix film 21 and the interlayer insulating film 9 is higher than the adhesion between the TiN film 22 and the front electrode 14 and the interlayer insulating film 9. Therefore, the adhesion of the front electrode 14 is improved by the TiSix film 21. In addition, the process for removing a part of the TiSix film 11 and the TiN film 12 can be omitted, and the number of processes can be reduced and the number of particles can be reduced.

[0101] As described above, according to Embodiment 2, even if the upper surface of the interlayer insulating film is covered with the TiSix film and the TiN film, the same effects as those of Embodiment 1 can be obtained. According to Embodiment 2, the number of steps is reduced and particles are reduced, thereby improving the yield and reducing costs.

[0102] (Experimental example) The relationship between the crystal damage recovery degree of a semiconductor substrate by hydrogen annealing and the barrier metal was verified. Fig. 9 The graph shows the relationship between the crystal damage recovery degree of a semiconductor substrate by hydrogen annealing and the barrier metal. The results of verifying the crystal damage recovery degree of a semiconductor substrate by hydrogen annealing using four samples (hereinafter referred to as samples 1 to 4) with different conditions (presence or absence of barrier metal, presence or absence of crystal damage to the semiconductor substrate) for a conventional trench gate MOSFET (hereinafter referred to as an experimental example) are shown in the figure. Fig. 9 .

[0103] Sample 1 has a Ti film as a barrier metal on the interlayer insulating film, and has no crystal damage caused by radiation irradiation on the semiconductor substrate (with Ti, no damage). Sample 2 has a Ti film as a barrier metal on the interlayer insulating film, and has crystal damage caused by radiation irradiation on the semiconductor substrate (with Ti, with damage). Sample 3 does not have a barrier metal, and has crystal damage caused by radiation irradiation on the semiconductor substrate (without Ti, with damage). Sample 4 does not have a barrier metal, and has no crystal damage caused by radiation irradiation on the semiconductor substrate (without Ti, no damage).

[0104] Fig. 9 The "damage recovery degree" indicates whether the gate threshold voltage after the crystal damage of the semiconductor substrate based on hydrogen annealing is restored to the design value of the gate threshold voltage. The crystal damage recovery degree of the semiconductor substrate based on hydrogen annealing in Sample 4 is set as the benchmark (=100%). Fig. 9 In the figure, "damage / no damage" indicates the presence or absence of crystal damage due to radiation exposure. Samples 1 to 4 were all hydrogen annealed in a state where crystal damage was similarly generated in the semiconductor substrate during other manufacturing processes (eg, ion implantation, etc.).

[0105] like Fig. 9 As shown, according to the results of Sample 2, it was confirmed that the crystal damage of the semiconductor substrate caused by radiation irradiation could not be fully recovered due to the presence of a Ti film as a barrier metal. In addition, according to the results of Sample 3, it was confirmed that the crystal damage of the semiconductor substrate caused by radiation irradiation could be recovered to the same extent as Samples 1 and 4 without crystal damage caused by radiation irradiation due to the absence of a Ti film as a barrier metal. In addition, since the damage recovery degree of Sample 3 is higher than that of Sample 1, it can be seen that the recovery degree of crystal damage caused in the semiconductor substrate in processes other than radiation irradiation is also higher due to the absence of a Ti film as a barrier metal.

[0106] (Comparative Example) As a comparative example, a MOSFET is described in which the contact resistance between the front electrode and the semiconductor substrate is reduced by providing a metal film with high hardness and high melting point such as Ti or nickel (Ni) between the front electrode and the semiconductor substrate, or a titanium silicide (TiSi) film obtained by silicideing the Ti film. Fig.10 , 11 2 are cross-sectional views showing the structures of Comparative Examples 1 and 2, respectively. Fig.10 , 11 The semiconductor devices 110 and 120 (hereinafter referred to as Comparative Examples 1 and 2) shown are vertical MOSFETs of a common trench gate structure, and the contact structures between the front electrodes 114 and the semiconductor substrate 108 of the respective devices are different.

[0107] In Comparative Examples 1 and 2, the trench gate structure is composed of a p-type base region 102 and an n-type + Type source region 103, p + The gate electrode 107 is composed of a gate contact region 104, a trench 105, a gate insulating film 106 and a gate electrode 107, and is arranged on the front surface of the semiconductor substrate 108 and the n - The interlayer insulating film 109 is provided on the front surface of the semiconductor substrate 108 and covers the gate electrode 107. - n-type drift regions 101 are provided between + The back side of the semiconductor substrate 108 is connected to the n + A back surface electrode 116 serving as a drain electrode is provided in contact with the drain region 115 .

[0108] Comparative Example 1 ( Fig.10 The semiconductor device 110 shown in FIG. 1 has a source contact groove 108a on the front surface of the semiconductor substrate 108 and is continuous with the contact hole 109a of the interlayer insulating film 109. The inner wall of the source contact groove 108a is exposed. + Type source region 103 and p + Type contact region 104. A metal film 111 and a TiN film 112 having high hardness and high melting point such as Ti or Ni are sequentially formed by sputtering along the sidewalls of the contact hole 109a (side surfaces of the interlayer insulating film 109) and the inner wall of the source contact trench 108a.

[0109] The metal film 111 and the TiN film 112 extend toward the upper surface of the interlayer insulating film 109, covering the entire upper surface of the interlayer insulating film 109. A W plug 113 is provided on the TiN film 112 in such a manner as to bury the contact hole 109a and the source contact trench 108a. A front electrode 114 is provided on the TiN film 112 and the W plug 113. The front electrode 114 is connected to the n through the W plug 113, the TiN film 112, and the metal film 111. + Type source region 103 and p + The type contact region 104 is electrically connected to function as a source electrode.

[0110] Comparative Example 2 ( Fig.11 The semiconductor device 120 shown in the figure is different from the comparative example 1 in that a TiSi film 121 is provided only on the Si portion instead of the metal film 111. The comparative example 2 does not provide the source contact trench 108a, so that the thickness of the interlayer insulating film 109 remains thicker than that of the comparative example 1. The TiSi film 121 is formed by a Ti film (Ti film 121a described later: refer to Fig.13 , 14) is formed by a silicidation reaction between Ti atoms in the semiconductor substrate 108 and Si atoms in the semiconductor substrate 108, and is arranged only on the Si portion (ie, the front surface of the semiconductor substrate 108) in the contact hole 109a of the interlayer insulating film 109.

[0111] The TiSi film 121 is not provided on the surface of the interlayer insulating film 109. The thickness of the TiSi film 121 is, for example, about 60 nm. + The TiN film 122 is provided along the surface of the TiSi film 121 and the surface of the interlayer insulating film 109. The W plug 123 is buried in the TiN film 122 inside the contact hole 109a.

[0112] Comparative Example 2 ( Fig.11 A method for manufacturing the semiconductor device 120 shown in FIG. 1 is described below. Figures 12 to 18 2 is a cross-sectional view showing a state in the middle of manufacturing of Comparative Example 2. Fig.12 As shown, a p-type base region 102, an n-type base region 104, and a p-type base region 106 are formed on the front side of the semiconductor substrate 108 by a conventional method. + Type source region 103, p + A trench gate structure is formed of a type contact region 104, a trench 105, a gate insulating film 106, and a gate electrode 107. Next, an interlayer insulating film 109 is formed on the entire front surface of the semiconductor substrate 108. Next, a contact hole 109a is formed that penetrates the interlayer insulating film 109 in the depth direction and reaches the semiconductor substrate 108.

[0113] Then, if Fig.13 As shown, in a temperature environment of about 300° C., a Ti film 121a having a thickness of, for example, about 40 nm is formed along the surface of the interlayer insulating film 109 and the surface of the portion exposed in the contact hole 109a of the semiconductor substrate 108 by sputtering. Fig.14 As shown, for example, by rapid thermal annealing (RTA) at about 600°C, the Ti film 121a and the semiconductor substrate 108 undergo silicidation reaction, and a TiSi film 121 is formed on the front surface of the semiconductor substrate 108 in the contact hole 109a. The thickness of the TiSi film 121 increases to about 60nm due to volume expansion caused by silicidation.

[0114] Then, if Fig.15 As shown in FIG. 1 , the remaining portion of the Ti film 121a that remains on the surface of the interlayer insulating film 109 without reacting is removed. Fig.16As shown in FIG. 1 , a TiN film 122 is formed along the surface of the TiSi film 121 and the surface of the interlayer insulating film 109 by sputtering. Fig.17 As shown in FIG. 1 , a W film 123a is formed on the uppermost surface of the front surface of the semiconductor substrate 108 by CVD so as to fill the contact hole 109a. Fig.18 As shown, by etching back the W film 123a, only the portion to be the W plug 123 remains in the contact hole 109a.

[0115] Next, the front electrode 114 is formed on the outermost surface of the semiconductor substrate 108. + The n type drain region 115 and the back electrode 116 are then controlled by irradiating with radiation such as electron beams. - The carrier lifetime of the drift region 101 is reduced. During the process up to this point (especially for n - The radiation irradiation (which controls the carrier lifetime of the drift region 101) causes crystal damage in the semiconductor substrate 108, causing changes in various characteristics such as the gate threshold voltage. Therefore, the crystal damage of the semiconductor substrate 8 is then restored by hydrogen annealing, thereby completing Comparative Example 2.

[0116] In the above-mentioned comparative example 1, not only the Ti film (metal film 111) is known, but also a contact structure of two layers of a Ti film and a TiN film, or a contact structure of three layers of a Ti film, a TiN film, and a Ti film is known. The contact resistance between the Ti film and the n-type Si (semiconductor substrate 108) is low. Therefore, in comparative example 1, even if the width of the contact hole 109a is narrowed due to miniaturization, the increase in the contact resistance between the front electrode 114 and the semiconductor substrate 108 can be suppressed. However, in comparative example 1, when the metal film 111 between the front electrode 114 and the interlayer insulating film 109 is a Ti film, the effect of hydrogen annealing is hindered by the Ti film.

[0117] In addition, in Comparative Example 1, the WF6 gas, which is the material gas of the W plug 113, may penetrate the TiN film 12 and contact the Ti film. If the WF6 gas contacts the Ti film, fluorine and H2 are generated, which reduce the adhesion with the interlayer insulating film 109. In addition, a part of the Ti film disappears, and floating and cracks are generated in the upper TiN film 112. As a result, the adhesion of the front electrode 114 is reduced. For example, by setting the metal film 111 as a Ni film instead of the Ti film, or removing the part of the Ti film covering the surface of the interlayer insulating film 109, the above-mentioned problem can be solved, but the function of the metal film 111 as a barrier metal is also reduced.

[0118] In addition, when the portion of the Ti film (metal film 111) covering the surface of the interlayer insulating film 109 is removed, the interlayer insulating film 109 is damaged due to ultrasonic vibration when the front electrode 114 is wire-bonded. In addition, since the portion of the Ti film covering the surface of the interlayer insulating film 109 is removed, the number of processes increases, and the yield decreases due to the generation of particles, thereby increasing the cost. In addition, when the portion of the Ti film covering the surface of the interlayer insulating film 109 is removed, the TiN film 112, which has lower adhesion to the interlayer insulating film 109 than the Ti film, contacts the interlayer insulating film 109, thereby reducing the adhesion between the interlayer insulating film 109 and the front electrode 114.

[0119] In Comparative Example 2, the remaining portion of the Ti film 121a (see Fig.15 ), so as in Comparative Example 1, the number of steps increases and the yield decreases due to the generation of particles. If the remaining portion of the Ti film 121a is not removed and remains on the interlayer insulating film 109, the same problem as in Comparative Example 1 occurs when the W plug 123 is formed and during hydrogen annealing. In Comparative Example 2, the contact resistance between the TiSi film 121 and the semiconductor substrate 108 is reduced, but due to the volume expansion caused by silicidation, the thickness of the TiSi film 121 becomes thicker than the thickness when the Ti film 121a is deposited, and the greater the thickness, the greater the stress generated locally in the semiconductor substrate 108.

[0120] In Comparative Examples 1 and 2, it is assumed that the crystal damage of the semiconductor substrate 108 is not fully recovered by hydrogen annealing, and the amount of reduction caused by the crystal damage of the semiconductor substrate 108 is estimated by excessively increasing the impurity dose of the predetermined diffusion region in the semiconductor substrate 108, and the predetermined characteristic as a product is matched with the predetermined value by presetting the predetermined characteristic high. In the above case, the crystal damage of the semiconductor substrate 108 is recovered by hydrogen annealing, so the predetermined characteristic may become higher than the predetermined value. Therefore, the characteristic variation is likely to occur in the reliability test such as the high temperature application test, and the reliability of the product (semiconductor device 110, 120) is poor.

[0121] For example, in the above-mentioned Patent Document 4, a polycrystalline silicon (poly-Si) film deposited on a semiconductor substrate is silicided by reacting with titanium radicals generated in a state heated to about 500°C, thereby forming a TiSi film. Therefore, as in Comparative Example 2, due to the volume expansion of the TiSi film caused by silicide, the stress generated locally on the semiconductor substrate increases. In addition, when the silicide of the polycrystalline silicon film does not reach the semiconductor substrate from the upper surface of the polycrystalline silicon film in the depth direction, the contact resistance with the semiconductor substrate increases. In addition, since the Ti film is included in the metal wiring, the effect of hydrogen annealing is hindered as in Comparative Example 1.

[0122] For example, in the above-mentioned patent document 5, a TiSi film is directly formed on a semiconductor substrate by PECVD. However, if chlorine (Cl) included in the introduction gas composition of PECVD diffuses into the semiconductor substrate or is mixed into the TiSi film or the semiconductor substrate as a residue, it will cause corrosion of the TiSi film or the semiconductor substrate. In addition, the deposited film formed using the plasma-formed material gas has high stress and high resistance. Since it is assumed that in order to reduce the resistance value of the deposited film, it is necessary to make the thickness of the deposited film uniform in the surface by, for example, heat treatment to reduce the layer resistance, the number of steps increases.

[0123] In addition, in the above-mentioned Patent Document 5, after forming a Si film on a semiconductor substrate by CVD, when a Ti film is formed by PECVD, the Si film reacts with the Ti film to form a TiSi film, but it is difficult to form the Si film by a method other than crystal growth based on a chemical reaction between the introduced gas and the semiconductor substrate (Si substrate). Even if it is assumed that the Si film can be formed by CVD, then, if the Ti film formed on the entire surface of the semiconductor substrate including the surface of the Si film is reacted with the Si film, the stress of the TiSi film is increased due to volume expansion. In addition, as in Comparative Example 1, the remaining portion of the Ti film that remains without reaction hinders the effect of hydrogen annealing.

[0124] On the other hand, according to Embodiments 1 and 2 (see Figure 1 , 7 ), the metal films provided on at least a portion of the surface of the interlayer insulating film 9 and functioning as barrier metals are TiSix films 11, 21 and TiN films 12, 22, and no Ti film is provided. Therefore, the effect of hydrogen annealing is not hindered, and the adhesion with the interlayer insulating film 9 is not reduced due to the contact between the material gas of the metal plugs 13, 23 and the metal film functioning as a barrier metal. In addition, by forming the TiSix films 11, 21 in a low temperature environment of about 300°C or less by sputtering, the stress generated locally in the semiconductor substrate 8 can be suppressed. Therefore, the reliability of the product is improved.

[0125] In addition, according to Embodiment 2 (refer to Figure 7 ), by covering the entire surface of the interlayer insulating film 9 with the TiSix film 21 and the TiN film 22, the effect as a barrier metal is improved. In addition, the TiSix film 21 and the TiN film 22 can suppress the damage to the interlayer insulating film 9 caused by ultrasonic vibration when the front electrode 14 is wire-bonded. In addition, according to embodiment 2, since the TiSix film 21 and the TiN film 22 are not selectively removed, the number of processes can be reduced, the yield can be improved by reducing the number of particles, and the cost can be reduced.

[0126] In addition, in the above-mentioned patent documents 1 to 4, the TiSiN film included in the stacked structure of the front electrode is different from the TiSix films 11 and 21 of the present embodiments 1 and 2, which hinders the effect of hydrogen annealing for recovering the crystal damage of the semiconductor substrate. In addition, in the above-mentioned patent document 1, after the Ti film is formed, the TiSiN layer is formed by sputtering, and then the upper surface of the TiSiN layer is oxidized and heat-treated to form a titanium nitride silicon oxide layer as an oxide layer of the TiSiN layer, and a capacitor formed by stacking these layers is formed, which is different from the method of forming contact with the semiconductor substrate as in the present embodiments 1 and 2. In addition, in the above-mentioned patent document 1, since a high-temperature heat treatment exceeding 600°C is performed, the stress generated locally on the semiconductor substrate becomes large due to the volume expansion caused by alloying.

[0127] In the above-mentioned patent document 2, the TiSiN layer is formed between the semiconductor substrate and the interlayer insulating film, which is different from the structure of the TiSix films 11 and 21 of the present embodiments 1 and 2. In addition, since the high-temperature heat treatment is performed, the stress generated locally on the semiconductor substrate increases due to the volume expansion caused by alloying. The above-mentioned patent document 3 is the following structure: a first conductive layer containing Si, a second conductive layer containing a high-melting-point metal, Si, and nitrogen such as a TiSiN layer formed on the first conductive layer, and a third conductive layer containing a platinum group element formed on the second conductive layer are provided on the surface of the semiconductor substrate, and these conductive layers are connected. Since the mutual diffusion between Si and the platinum group element is prevented even if the high-temperature heat treatment is performed, it is different from the method of forming contact with the semiconductor substrate as in the present embodiments 1 and 2. In addition, in the above-mentioned patent document 3, since the high-temperature heat treatment is performed, the stress generated locally on the semiconductor substrate increases due to the volume expansion caused by alloying.

[0128] In the above-mentioned Patent Document 4, a contact hole with a high aspect ratio reaching the semiconductor substrate is formed in the interlayer insulating film, and a polycrystalline or amorphous Si film of a thickness that does not fill the contact hole is stacked on the surface of the interlayer insulating film, the side surface of the contact hole, and the bottom surface of the contact hole (the surface of the semiconductor substrate), and the Si film is converted into a TiSi film while depositing a Ti film by PECVD, and then a TiN film is formed on the surface of the Ti film, which is different from the formation method of the TiSix film 11 and 21 of the present embodiments 1 and 2. In addition, the difference from the present embodiments 1 and 2 is that a polycrystalline or amorphous Si film is stacked. In addition, in the above-mentioned Patent Document 4, due to the volume expansion of the TiSi film caused by silicidation in high-temperature plasma, the stress generated locally on the semiconductor substrate becomes larger, and plasma damage may remain.

[0129] In the first example of the method for forming a contact layer of the above-mentioned patent document 5, a contact hole with a high aspect ratio reaching the semiconductor substrate is formed in the interlayer insulating film, and a TiSi film of a thickness that does not fill the contact hole is stacked by PECVD, which is different from the method for forming the TiSix films 11 and 21 of the present embodiments 1 and 2. In addition, in the above-mentioned patent document 5, chlorine (Cl) included in the composition of the introduction gas of PECVD for forming the TiSi film causes characteristic variation, reliability reduction, and corrosion of the semiconductor substrate. In addition, plasma damage may remain. In addition, in the first example of the method for forming a contact layer of the above-mentioned patent document 5, if a high-temperature heat treatment at a temperature higher than the formation temperature of the TiSi film is performed after the TiSi film is formed, the stress generated locally in the semiconductor substrate becomes larger.

[0130] In the second example of the contact layer formation method of the above-mentioned patent document 5, a contact hole with a high aspect ratio reaching the semiconductor substrate is formed in the interlayer insulating film, and a Si film of a thickness that does not fill the contact hole is formed by reduced pressure CVD (LPCVD: Low Pressure CVD: low pressure chemical vapor deposition method), and a Ti film is formed by PECVD while reacting with the Si film to convert it into a TiSi film, which is different from the formation method of the TiSix film 11 and 21 of the present embodiments 1 and 2. In addition, in the second example of the contact layer formation method of the above-mentioned patent document 5, if Cl in the TiCl gas used remains, it causes characteristic changes and reliability reduction, and plasma damage may remain. In addition, due to silicidation in the plasma, the stress generated locally on the semiconductor substrate due to the volume expansion of the TiSi film increases.

[0131] In the above-mentioned Patent Document 6, a polysilicon film is formed as a gate electrode in order to reduce gate resistance, a TiSi film is formed on the polysilicon film by a PVD method, and an oxide film is formed on the side of the gate electrode in order to prevent the gate width from being narrowed due to large lateral etching of the TiSi film. The contact structure of the front electrode is not disclosed, which is different from the method of forming contact with the semiconductor substrate as in the present embodiments 1 and 2. In addition, in the above-mentioned Patent Document 6, since a high-temperature heat treatment is performed, the stress generated locally in the semiconductor substrate increases due to volume expansion caused by alloying.

[0132] On the other hand, in the first and second embodiments, the TiSix film is deposited on the semiconductor substrate by sputtering as described above, and the problems occurring in the above-mentioned cited documents 1 to 6 do not occur.

[0133] As mentioned above, the present invention is not limited to the above-mentioned embodiments, and various changes can be made within the scope of the main purpose of the present invention. For example, the above-mentioned embodiments are not limited to MOSFETs with trench gate structures, and can be applied to various semiconductor devices with a structure in which the contact structure of the front electrode is in ohmic contact with the semiconductor substrate in the contact hole of the interlayer insulating film. In addition, in each embodiment, the first conductivity type is set to n-type and the second conductivity type is set to p-type, but the present invention is also applicable to the first conductivity type being set to p-type and the second conductivity type being set to n-type.

[0134] Industrial Applicability As described above, the semiconductor device and the method for manufacturing the semiconductor device of the present invention are useful for power semiconductor devices used in power converters, power supply devices for various industrial machines, etc., and are particularly suitable for semiconductor devices miniaturized by using contact trenches.

Claims

1. A semiconductor device, characterized in that: have: A first semiconductor region of a first conductivity type, which is disposed inside the semiconductor substrate; A second semiconductor region of a second conductivity type, disposed between the front surface of the semiconductor substrate and the first semiconductor region; an element structure, which is arranged on the front side of the semiconductor substrate and includes a pn junction of the second semiconductor region and the first semiconductor region; An interlayer insulating film, which is arranged on the front surface of the semiconductor substrate and covers the element structure; a contact hole penetrating the interlayer insulating film in a depth direction and reaching the semiconductor substrate; a contact structure in contact with the semiconductor substrate in the contact hole; a first electrode electrically connected to the second semiconductor region via the contact structure; as well as A second electrode is provided on the back side of the semiconductor substrate, The contact structure is composed of a titanium silicide film, a titanium nitride film, and a metal plug. The titanium silicide film is in contact with the semiconductor substrate in the contact hole and extends on the surface of the interlayer insulating film along the side wall of the contact hole. The titanium nitride film is disposed along the surface of the titanium silicide film, The metal plug is buried inside the contact hole and on the titanium nitride film.

2. The semiconductor device according to claim 1, wherein: A contact groove of a predetermined depth is provided on the front surface of the semiconductor substrate in a manner continuous with the contact hole, The titanium silicide film is disposed along the sidewalls of the contact hole and the inner wall of the contact trench.

3. The semiconductor device according to claim 2, wherein: The thickness of the titanium silicide film is the same from the sidewall of the contact hole to the sidewall of the contact trench.

4. The semiconductor device according to claim 2, wherein: The interlayer insulating film is located at a position separated from the contact trench by a distance of 10 nm or less in a direction parallel to the front surface of the semiconductor substrate.

5. The semiconductor device according to claim 1, wherein: The titanium silicide film is terminated at the side of the interlayer insulating film, The first electrode is provided on an upper surface of the interlayer insulating film so as to be in contact with the interlayer insulating film.

6. The semiconductor device according to claim 1, wherein: The titanium silicide film covers the entire surface of the interlayer insulating film, The first electrode is provided on the upper surface of the interlayer insulating film via the titanium silicide film and the titanium nitride film.

7. A method for manufacturing a semiconductor device, characterized in that: include: In a first step, a second semiconductor region of a second conductivity type is formed on a surface area of ​​a front surface of a semiconductor substrate, the second semiconductor region being in contact with a first semiconductor region of a first conductivity type in the semiconductor substrate, and an element structure including a pn junction between the second semiconductor region and the first semiconductor region is formed; The second step is to form an interlayer insulating film covering the element structure on the front surface of the semiconductor substrate; A third step is to form a contact hole that penetrates the interlayer insulating film in a depth direction and reaches the semiconductor substrate; A fourth step is to form a contact structure in the contact hole that contacts the semiconductor substrate; A fifth step is to form a first electrode electrically connected to the second semiconductor region via the contact structure; and a first annealing step, after the fifth step, recovering crystal damage of the semiconductor substrate by heat treatment in a hydrogen atmosphere; The fourth step comprises: A first deposition step of depositing a titanium silicide film by sputtering, wherein the titanium silicide film covers the entire surface of the interlayer insulating film and contacts the semiconductor substrate in the contact hole; a second deposition step of depositing a titanium nitride film on the surface of the titanium silicide film by sputtering; and In the third deposition step, a metal plug is buried inside the contact hole on the titanium nitride film. The contact structure composed of the titanium silicide film, the titanium nitride film and the metal plug is formed.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: After the third step and before the fourth step, a sixth step is included, in which a contact groove having a predetermined depth and being continuous with the contact hole is formed on the front surface of the semiconductor substrate. In the first deposition step, the titanium silicide film is formed along the surface of the interlayer insulating film and the inner wall of the contact trench.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: A seventh step is included after the sixth step and before the fourth step, and in the seventh step, the interlayer insulating film is flattened.

10. The method for manufacturing a semiconductor device according to claim 7, wherein: The first deposition step and the second deposition step are continuously performed using the same sputtering device.

11. The method for manufacturing a semiconductor device according to claim 7, wherein: The fourth step further includes a removal step, in which the titanium nitride film and the titanium silicide film are etched back using the metal plug as a mask to expose the upper surface of the interlayer insulating film. In the fifth step, the first electrode is formed on the upper surface of the interlayer insulating film so as to be in contact with the interlayer insulating film.

12. The method for manufacturing a semiconductor device according to claim 7, wherein: The first deposition step is performed in a temperature environment below 300° C.

13. The method for manufacturing a semiconductor device according to claim 7, wherein: Also includes: an irradiation step of irradiating the semiconductor substrate with radiation after the first annealing step; as well as The second annealing step is to adjust the parasitic diode formed at the pn junction to a predetermined reverse recovery characteristic by heat treatment in a hydrogen atmosphere after the irradiation step.

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