Memory application method and device, electronic equipment and readable storage medium

Abstract

The invention discloses a memory application method and device, electronic equipment and a readable storage medium, and belongs to the technical field of memory management. The memory application method provided by the embodiment of the invention comprises the following steps: under the condition that a memory application request corresponding to first data is received, executing a memory application operation according to the memory application request; under the condition that the first cache memory block is applied, reading a first part of the first data to the first cache memory block; the data volume of the first part is matched with the memory size of the first cache memory block.

Description

Technical Field

[0001] The present application belongs to the field of memory management technology, and specifically relates to a memory application method, device, electronic device and readable storage medium. Background Art

[0002] Typically, when an electronic device needs to read certain data, the system of the electronic device can first apply for a cache memory for the data, and when the cache memory application is completed, the data is read into the cache memory, so that the electronic device can quickly read the data from the cache memory and use the data to perform corresponding tasks, and when the cache memory is not released, if the data needs to be read again, the data can be directly read again from the cache memory without reading the data from the disk, thereby improving the efficiency of reading the data.

[0003] However, in the case of a large amount of data to be read, it may take a long time for the system to apply for a cache memory for the data, and it may take a long time to read the data into the cache memory, thus resulting in low data reading efficiency of the electronic device. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a memory application method, device, electronic device and readable storage medium, which can solve the problem of low data reading efficiency of electronic devices.

[0005] In a first aspect, an embodiment of the present application provides a memory application method, the method comprising: upon receiving a memory application request corresponding to first data, executing a memory application operation according to the memory application request; and upon applying for a first cache memory block, reading a first part of the first data into the first cache memory block; the data volume of the first part matches the memory size of the first cache memory block.

[0006] In a second aspect, an embodiment of the present application provides a memory application device, which includes: an application module and a reading module. The application module is used to perform a memory application operation according to the memory application request when a memory application request corresponding to the first data is received. The reading module is used to read the first part of the first data into the first cache memory block when the application module applies for the first cache memory block; the data volume of the first part matches the memory size of the first cache memory block.

[0007] In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the program or instructions are executed by the processor, the steps of the method described in the first aspect are implemented.

[0008] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the steps of the method described in the first aspect are implemented.

[0009] In a fifth aspect, an embodiment of the present application provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a program or instruction to implement the steps of the method described in the first aspect.

[0010] In a sixth aspect, an embodiment of the present application provides a computer program product, which is stored in a storage medium and is executed by at least one processor to implement the steps of the method described in the first aspect.

[0011] In an embodiment of the present application, the electronic device can, when receiving a memory application request corresponding to the first data, perform a memory application operation according to the memory application request, and when applying for the first cache memory block, read the first part of the first data into the first cache memory block; wherein the data volume of the first part matches the memory size of the first cache memory block. Since the electronic device reads the first part whose data volume matches the memory size of the first cache memory block into the first cache memory block when applying for the first cache memory block with a smaller memory size, without waiting until the entire cache memory application is completed before reading the first data into the cache memory, the waiting time required for reading the first data can be reduced, thereby reducing the time consumption of data reading of the electronic device, that is, the data reading efficiency of the electronic device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of a process of driving an electronic device and / or a device reading a model file of an AI large model in the related art;

[0013] Figure 2 This is one of the flowcharts of the memory application method provided in the embodiment of the present application;

[0014] Figure 3 This is the second flowchart of the memory application method provided in the embodiment of the present application;

[0015] Figure 4 This is the third flowchart of the memory application method provided in the embodiment of the present application;

[0016] Figure 5 This is the fourth flowchart of the memory application method provided in the embodiment of the present application;

[0017] Figure 6 This is the fifth flowchart of the memory application method provided in the embodiment of the present application;

[0018] Figure 7 This is the sixth flowchart of the memory application method provided in the embodiment of the present application;

[0019] Figure 8 It is a flowchart of a memory application method in the related art;

[0020] Fig. 9 This is the seventh flowchart of the memory application method provided in the embodiment of the present application;

[0021] Fig.10 It is a schematic diagram comparing the average time consumption for data reading between the memory application method provided in the embodiment of the present application and the memory application method in the related art;

[0022] Fig.11 It is a structural diagram of a memory application device provided in an embodiment of the present application;

[0023] Fig.12 This is one of the hardware structure diagrams of the electronic device provided in the embodiment of the present application;

[0024] Fig.13 This is the second schematic diagram of the hardware structure of the electronic device provided in the embodiment of the present application. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0026] The professional terms involved in the embodiments of the present application are explained below.

[0027] 1. System read and write files

[0028] Currently, the system reads and writes files in two ways: Buffer Input Output (BIO) and Direct Input Output (DIO).

[0029] Among them, the BIO method is to establish a cache memory in the memory, so that the user space reading and writing files will not directly trigger the file reading and writing, but directly read and write to the cache memory. The DIO method is a method in which there is no need to establish a cache memory in the memory, and the driver can read files directly from the disk. Generally, the read and write efficiency of the BIO method is higher than that of the DIO method.

[0030] 2. Direct Memory Access-Buffer (DMA-BUF)

[0031] Typically, DMA-BUF memory is a specialized memory that can be shared between user space, kernel space, and DMA devices.

[0032] Among them, user space is the system location where the application uses memory, which is characterized by limited system permissions. The kernel memory management part is responsible for using memory, and memory is used in the form of user virtual addresses (each process has its own process address space). Usually, only when the process actually reads and writes will real physical memory be provided, and most of the memory (stack, file page) can be recycled. The embodiment of DMA-BUF in user space is that the actual physical address can be mapped to the user's process address space (UserVaddr), and the memory is accessed in the form of zero copy. The memory mapped to the process address space by DMA-BUF cannot be actively recycled by the system.

[0033] The kernel space is where the process-related drivers and kernel core subsystems are located. It is used to connect to hardware with higher permissions and provide services to upper-level applications. DMA-BUF memory can be mapped to the kernel address space (Kvaddr) to achieve zero-copy access and shared memory.

[0034] Usually, the device needs to access memory through the CPU, but this method will occupy the CPU's computing power. For example, if the CPU is required to participate in both file reading and writing, the CPU will need to wait for the file reading to be completed before running other applications. If the number of reads is large, it will affect the system throughput. A DMA device is a special device that has the ability to directly access memory. DMA-BUF memory can be mapped to a virtual address (iova) that can be accessed by a DMA device through the Input / Output Memory Management Unit (IOMMU).

[0035] Through the mapping of the above three methods, the physical address of the same DMA-BUF can share the same memory among the three forms, access the same memory in a zero-copy form, and complete business processing efficiently.

[0036] At present, since artificial intelligence (AI) models require coordinated processing by multiple devices (such as a central processing unit (CPU) and an AI processing unit (APU)), the cache memory for reading model files in the AI ​​field is usually DMA-BUF memory.

[0037] 3. Other terms

[0038] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0039] The terms "at least one (item)", "at least one of" and the like in the specification and claims of the present application refer to any one, any two or a combination of more than two of the objects included therein. For example, at least one (item) of a, b, and c can be represented by: "a", "b", "c", "a and b", "a and c", "b and c" and "a, b and c", where a, b, and c can be single or multiple. Similarly, "at least two (items)" refers to two or more, and its meaning is similar to that of "at least one (item)".

[0040] The memory application method, device, electronic device and readable storage medium provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings through specific embodiments and their application scenarios.

[0041] The memory application method provided in the embodiment of the present application can be applied to scenarios where an electronic device is driven and / or the device needs to read data.

[0042] Assume that the driver and / or device of the electronic device needs to read the model file of the AI ​​large model. In the related art, such as Figure 1As shown, the user space of the electronic device can send a memory application request corresponding to the model file to the system of the electronic device according to the data size of the model file of the AI ​​large model, so as to apply for a cache memory (such as DMA-BUF memory) with a memory size matching the data size for the model file, and then when the DMA-BUF memory application is completed, the system can use mmap / read calls to read the model file into the DMA-BUF memory using a user space zero-copy solution, so that the system can share the DMA-BUF memory with the driver and DMA device for AI word processing. However, since the model file of the large AI model may have a large amount of data, for example, the 3B model is 1.x gigabit GB, and the 7B model is 3.xGB, and the GB-level memory application takes 60 milliseconds at the fastest. If the memory is insufficient, the memory application may take 700ms-1.x seconds. Using mmap / read calls and a user space zero-copy solution to read the model file into the DMA-BUF memory requires waiting for the DMA-BUF memory application to be completed. Therefore, it takes a long time to apply for a DMA-BUF memory with a memory size that matches the data size for the model file, and it takes a long time to read the model file into the DMA-BUF memory; and because the memory size of the DMA-BUF memory is large, the electronic device may release the DMA-BUF memory quickly, so when the driver and / or device needs to read the data again, it may take a long time to apply for the DMA-BUF memory again. Therefore, it takes a long time for the driver and / or device of the electronic device to read the data, that is, the efficiency of the electronic device in reading data is low.

[0043] However, in an embodiment of the present application, the system of the electronic device can receive a memory application request for requesting to apply for a DMA-BUF memory, the DMA-BUF memory is used to cache the model file of the AI ​​large model, and perform a DMA-BUF memory application operation according to the memory application request. In the case of applying for a cache memory block of the DMA-BUF memory, the system of the electronic device can read part 1 of the model file of the AI ​​large model into the cache memory block; wherein the amount of data of the part 1 matches the memory size of the cache memory block. It can be understood that, since the electronic device can read part 1 of the model file of the AI ​​large model into the cache memory block when applying for a cache memory block with a smaller memory size of the DMA-BUF memory, without waiting until the entire DMA-BUF memory application is completed before reading data 1 into the DMA-BUF memory, the waiting time required to read the model file of the AI ​​large model can be reduced, thereby reducing the time consumption of data reading of the electronic device, that is, the data reading efficiency of the electronic device can be improved.

[0044] It should be noted that the above is illustrated by taking the example of the driver of the electronic device and / or the device reading the model file of the AI ​​large model. In actual applications, the driver of the electronic device and / or the device can also read other data, which is not limited to the embodiments of the present application.

[0045] The memory application method provided in the embodiment of the present application can be executed by a memory application device, an electronic device, or a functional module or entity in an electronic device. The memory application method provided in the embodiment of the present application is described by taking an electronic device executing the memory application method as an example.

[0046] Figure 2 FIG. 1 is a flow chart of a memory application method provided by an embodiment of the present application. Figure 2 As shown, the memory application method provided in the embodiment of the present application may include the following steps 101 and 102.

[0047] Step 101: When receiving a memory application request corresponding to first data, the electronic device performs a memory application operation according to the memory application request.

[0048] In some embodiments of the present application, the above-mentioned memory application request can be used to request a cache memory corresponding to the first data.

[0049] In some embodiments of the present application, the cache memory may specifically be a DMA-BUF memory.

[0050] In some embodiments of the present application, the first data may be a model file of an AI large model, or image data, or video data, or page data. Of course, the first data may also be other data, which is not limited in the embodiments of the present application.

[0051] In some embodiments of the present application, the total data size of the first data may be greater than or equal to the preset data size. It is understandable that the total data size of the first data is relatively large. Of course, the total data size of the first data may also be less than the preset data size, that is, the total data size of the first data may also be relatively small, and the embodiments of the present application do not limit this.

[0052] In some embodiments of the present application, the memory application request may include a memory size of a cache memory, and the memory size of the cache memory matches the data size of the first data.

[0053] It should be noted that the above “matching” can be understood as: being the same, or the difference between the two is less than or equal to a preset value.

[0054] In some embodiments of the present application, when a driver of an electronic device needs to read the first data, a user space of the electronic device may send a memory application request to a system of the electronic device, so that the system of the electronic device may receive the memory application request. The driver may include at least one of the following: a driver of a user space, a driver of a kernel space, a driver of a DMA device, etc.

[0055] Among them, the driver of the user space may include a camera driver. Of course, the driver of the user space may also include other drivers, which are not exhaustively listed in the embodiments of the present application. The driver of the kernel space may include a driver of a direct rendering manager (DirectRendering Manager, DRM). Of course, the driver of the kernel space may also include other drivers, which are not exhaustively listed in the embodiments of the present application. The DMA device may include a graphics processor (Graphics Processing Unit, GPU), APU, etc. Of course, the DMA device may also include other devices, which are not exhaustively listed in the embodiments of the present application.

[0056] Step 102: When the first cache memory block is applied for, the electronic device reads the first part of the first data into the first cache memory block; the data volume of the first part matches the memory size of the first cache memory block.

[0057] In some embodiments of the present application, the electronic device can determine in real time whether the first cache memory block is applied for during the execution of a memory application operation, and if it is determined that the first cache memory block is applied for, the first part of the first data can be read into the first cache memory block.

[0058] Wherein, when the memory size of the free memory in the electronic device is greater than or equal to the memory size carried in the memory application request, the system of the electronic device can directly apply for cache memory from the free memory. When the memory size of the free memory in the electronic device is less than the memory size carried in the memory application request, the system of the electronic device can first recycle at least part of the occupied memory, and then apply for cache memory from the reclaimed memory and the free memory.

[0059] The memory size of the first cache memory block may be a preset memory size, or a memory size determined according to the data volume of the first data. The system of the electronic device may count the memory size of the cache memory that has been applied for in real time, and when the memory size matches the preset memory size (or the memory size determined according to the data volume of the first data), the system of the electronic device may determine that the first cache memory block has been applied for.

[0060] The first part may be: a part of the first data corresponding to the first cache memory block. Here, the first data starting position of the first part is the data position corresponding to the first cache memory block. The first data position may be the data starting position of the first data, or other data positions in the first data.

[0061] In the case where the first cache memory block is the first cache memory block applied for by the system of the electronic device, the first data position may be the data starting position of the first data. In the case where the first cache memory block is the i-th cache memory block applied for by the system of the electronic device, the first data position may be other data positions in the first data, where i is a positive integer greater than 1.

[0062] Exemplarily, assuming that the first cache memory block is the first cache memory block applied for by the system of the electronic device, and the size of the first cache memory block is 128MB, then the first data starting position of the first part is the data starting position of the first data, and the first part is the 0-128MB part of the first data.

[0063] As another example, assuming that the first cache memory block is the second cache memory block applied for by the system of the electronic device, the memory size of the first cache memory block is 128MB, and the size of the first cache memory block is 128MB, then the starting position of the first data of the first part is other data positions of the first data (for example, the data position of 128MB), and the first part is the 128MB to 256MB part of the first data.

[0064] The following is an example to illustrate a specific solution for an electronic device to apply for a first cache memory block.

[0065] In some embodiments of the present application, Figure 2 ,like Figure 3 As shown, before the above step 102, the memory application method provided in the embodiment of the present application may also include the following steps 201 and 202.

[0066] Step 201: The electronic device records the requested cache memory block into a first list.

[0067] In some embodiments of the present application, the first list may be a list list. Of course, the first list may also be other lists, which is not limited in the embodiments of the present application.

[0068] Step 202: When the memory size of the cache memory block recorded in the first list matches the preset memory size, determine the cache memory block recorded in the first list as the first cache memory block.

[0069] In some embodiments of the present application, the preset memory size may be a memory size set by a user, or a preconfigured memory size, or an agreed memory size, or a memory size determined according to the data volume of the first data.

[0070] Wherein, in the case where the preset memory size is a memory size determined according to the data volume of the first data, the electronic device may determine the preset memory size according to the rate at which the electronic device reads data and the data volume of the first data. Wherein, the smaller the rate at which the electronic device reads data, the smaller the preset memory size; the larger the data volume of the first data, the larger the preset memory size.

[0071] In some embodiments of the present application, the above-mentioned preset memory size can be 128MB, or 256MB, or 512MB. Of course, the preset memory size can also be other memory sizes, which is not limited in the embodiments of the present application.

[0072] In some embodiments of the present application, the system of the electronic device can determine in real time the size relationship between the memory size of the cache memory block in the first list and the preset memory size, and when the memory size of the cache memory block in the first list matches the preset memory size, the electronic device can determine the cache memory block as the first cache memory block and determine to apply for the first cache memory block.

[0073] In some embodiments of the present application, after the electronic device determines the cache memory block recorded in the first list as the first cache memory block, the electronic device may clear the cache memory block recorded in the first list to facilitate recording other cache memory blocks and determining other cache memory blocks in subsequent steps.

[0074] It can be seen that since the electronic device can store the applied cache memory blocks in the first list to accurately count the memory size of the applied cache memory blocks, and the electronic device can accurately determine the cache memory blocks in the first list as the first cache memory blocks when the memory size of the cache memory blocks recorded in the first list matches the preset memory size, that is, when the memory size of the applied cache memory blocks matches the preset memory size, therefore, the accuracy of the electronic device in determining the first cache memory block can be improved.

[0075] In some embodiments of the present application, Figure 2 ,like Figure 4 As shown, the above step 102 can be specifically implemented through the following step 102a.

[0076] Step 102a: When the first cache memory block is applied for, the electronic device reads the first part into the virtual storage space corresponding to the first virtual address; the first virtual address corresponds to the first cache memory block.

[0077] In some embodiments of the present application, the first virtual address may be a kernel address. The virtual storage control may be a kernel storage space.

[0078] In some embodiments of the present application, the electronic device may determine the first virtual address based on the physical address of the first cache memory block.

[0079] In some embodiments of the application, Figure 4 ,like Figure 5 As shown, the above step 102a can be specifically implemented through the following step 102a1.

[0080] Step 102a1, when applying for the first cache memory block, the electronic device reads the first part into the virtual storage space corresponding to the first virtual address according to the first data position of the first part in the first data and the data amount of the first part through the data processing thread.

[0081] In some embodiments of the present application, the above-mentioned data processing thread may specifically be an IO processing thread.

[0082] In some embodiments of the present application, the electronic device may first submit a first task to a data processing thread so that the data processing thread can read the first part to a virtual storage space corresponding to a first virtual address based on the first task, the first data position of the first part in the first data, and the data amount of the first part.

[0083] The first task may carry the first data location and the data volume of the first part.

[0084] In some embodiments of the present application, when a data processing thread receives a first task, if the processing thread exits a sleep state, the data processing thread may obtain the first part from the first data in the disk according to the first task, the first data position and the data amount of the first part.

[0085] As can be seen, the electronic device can accurately obtain the corresponding first part from the first data through the data processing thread according to the first data position and the data amount of the first part.

[0086] In summary, since the electronic device can directly read the first part into the virtual storage space corresponding to the first virtual address, so as to directly read the first part of the first data in the disk into the first cache memory block, without the need for the electronic device to first read the first part of the first data in the disk into other memories, and then copy the first part in other memories to the first cache memory through the CPU, it is possible to avoid wasting memory resources while avoiding wasting CPU computing power due to the CPU copying the first part in other memories to the first cache memory.

[0087] In some embodiments of the application, Figure 4 ,like Figure 6 As shown, before "the electronic device reads the first part into the virtual storage space corresponding to the first virtual address" in the above step 102a, the memory application method provided in the embodiment of the present application may also include the following step 301, and the above step 102a can be specifically implemented through the following step 102a2.

[0088] Step 301: When a first cache memory block is applied for, the electronic device maps the physical address of the first cache memory block to a virtual storage space to obtain a first virtual address.

[0089] It should be noted that, for the description of how the electronic device maps the physical address of the first cache memory block to the virtual storage space, reference may be made to the specific description of the relevant technology, which will not be elaborated in the embodiments of the present application.

[0090] Step 102a2: The electronic device reads the first part into a virtual storage space corresponding to a first virtual address; the first virtual address corresponds to a first cache memory block.

[0091] In the related art, the system of the electronic device maps the physical address of the first cache memory block to the user address space. In this way, when reading the first part, since the design of the DMA-BUF memory is based on PFN and does not provide an access method in the form of PAGE to the upper layer, the system of the electronic device needs to apply for an additional PAGE CACHE memory block, and first read the first part into the PAGE CACHE memory block, and then use the CPU to copy part of the PAGE CACHE memory block to the first cache memory block. Therefore, when the total data size of the first data is greater than or equal to the preset data size, that is, when the total data size of the first data is large, on the one hand, it will cause a waste of memory resources, and on the other hand, copying part of the PAGE CACHE memory block to the first cache memory block will cause a waste of CPU computing power and increase the power consumption of the CPU.

[0092] However, in the embodiment of the present application, the system of the electronic device can directly map the physical address of the first cache memory block to the virtual storage space (i.e., the kernel address space) to obtain the first virtual address. In the kernel address space, the system of the electronic device can manage the DMA-BUF memory in the form of page, that is, the electronic device can directly read the first part of the first data in the disk into the first cache memory block by DIO. In the related art, the physical address of the first cache memory block is mapped to the user address space, and the user address space can only use DMA-BUF PFN. In this way, after reading the first part into the user address space, the consistency of the first part in the first cache memory block corresponding to the user address space may not be guaranteed, for example, the first cache memory block corresponding to the user address space may be recycled by the system; or due to memory rules and other reasons, memory migration occurs, and the cache memory block corresponding to the user address space changes, etc., so it must be accessed in the form of BIO, that is, in the related art, only a PAGE CACHE memory block can be applied first, and then part of the PAGE CACHE memory block is copied to the first cache memory block. In the embodiment of the present application, the system of the electronic device does not need to apply for an additional PAGE CACHE memory block, thereby avoiding the waste of memory resources while reducing the waste of CPU computing power and the power consumption of the CPU.

[0093] Thus, it can be known that the electronic device can map the physical address of the first cache memory block to the virtual storage space to accurately obtain the first virtual address, so in the subsequent steps, the electronic device can accurately store the first part in the virtual storage space corresponding to the first virtual address. In addition, since the above-mentioned virtual storage space can be a kernel address space, that is, the electronic device can map the physical address of the first cache memory block to the kernel address space to obtain the first virtual address, so in the subsequent steps, the electronic device can directly store the first part in the disk in the kernel address space without applying for PAGE CACHE, so that while avoiding the waste of memory resources, it can avoid the waste of CPU computing power caused by the CPU copying the data in PAGE CACHE to the cache memory.

[0094] The embodiment of the present application provides a memory application method, in which an electronic device can, when receiving a memory application request corresponding to first data, perform a memory application operation according to the memory application request, and when applying for a first cache memory block, read the first part of the first data into the first cache memory block; wherein the data volume of the first part matches the memory size of the first cache memory block. Since the electronic device reads the first part whose data volume matches the memory size of the first cache memory block into the first cache memory block when applying for a first cache memory block with a smaller memory size, without waiting until the entire cache memory application is completed before reading the first data into the cache memory, the waiting time required for reading the first data can be reduced, thereby reducing the time consumption of data reading of the electronic device, that is, the data reading efficiency of the electronic device can be improved.

[0095] Furthermore, when the electronic device releases the cache memory, the electronic device can read the first part into the first cache memory block each time the first cache memory block is applied for, that is, the electronic device can quickly read part of the first data, thereby reducing the time spent in reading part of the first data into the cache memory again.

[0096] In some embodiments of the present application, the first data further includes a second part, and the first part is adjacent to the second part. The memory application method provided in the embodiment of the present application may further include the following step 103.

[0097] Step 103: When the second cache memory block is applied for, the electronic device reads the second part into the second cache memory block; the data size of the second part matches the memory size of the second cache memory block.

[0098] In some embodiments of the present application, the first part and the second part being adjacent to each other can be understood as: the end position of the data of the first part is the start position of the data of the second part.

[0099] Exemplarily, assuming that the first portion is a portion of 0 to 128 MB of the first data, the second portion may be a portion of 128 MB to 300 MB of the first data.

[0100] In some embodiments of the present application, the data volume of the second part may be the same as or different from the data volume of the first part.

[0101] In some embodiments of the present application, the memory size of the first cache memory block is the same as or different from the memory size of the second cache memory block.

[0102] Exemplarily, the memory size of the first cache memory block may be 64 MB, and the memory size of the second cache memory block may be 128 MB.

[0103] In some embodiments of the present application, the memory size of the first cache memory block and the memory size of the second cache memory block are determined according to the data volume of the first data.

[0104] For example, if the data volume of the first data is 10G, the memory size of the first cache memory block can be 244MB, and the memory size of the second cache memory block can be 344MB. Of course, the memory sizes of the first cache memory block and the second cache memory block can also be other values, which are not limited in the embodiments of the present application.

[0105] The electronic device may determine the memory size of the first cache memory block and the memory size of the second cache memory block respectively according to at least one of the rate at which the electronic device reads data and the data volume of the first data.

[0106] Taking the first cache memory block as an example, the memory size of the first cache memory block may be positively correlated with the rate at which the electronic device reads data, that is, the lower the rate at which the electronic device reads data, the smaller the memory size of the first cache memory block. The memory size of the first cache memory block may be positively correlated with the amount of the first data, that is, the smaller the amount of the first data, the smaller the memory size of the first cache memory block.

[0107] It can be seen that since the electronic device can determine the memory size of the first cache memory block and the memory size of the second cache memory block respectively according to the data amount of the first data, that is, the electronic device can flexibly configure the memory size of the first cache memory block and the memory size of the second cache memory block, therefore, the flexibility of the electronic device in reading data can be improved.

[0108] It should be noted that, for the description of the electronic device reading the second part into the second cache memory block, reference may be made to the specific description of the electronic device reading the first part into the first cache memory block in the above embodiment, which will not be repeated herein in the embodiments of the present application.

[0109] In some embodiments of the present application, the electronic device may read the first part into the first cache memory block, and if the second cache memory block is applied for, the electronic device reads the second part into the second cache memory block.

[0110] In some embodiments of the present application, when the electronic device reads the second part into the second cache memory block, the electronic device may read the third part into the third cache memory block if the third cache memory block is applied for; the data size of the third part matches the memory size of the third cache memory block. The third part is adjacent to the second part.

[0111] It can be understood that the electronic device can repeat the above step 103 in the process of reading the second part into the second cache memory block, so as to simultaneously read different parts of the first data into each cache memory block applied for, thereby reading the first data into the cache memory. That is, in the process of the electronic device reading the previous data content into the cache memory block applied for last time, if the electronic device applies for another cache memory block, the electronic device can read the previous part into the cache memory block applied for last time, and read the current part into the other cache memory block at the same time.

[0112] That is to say, the memory application method provided in the embodiment of the present application can change the memory application and data reading method in the related art from serial to pipeline parallel, that is, in the memory application method provided in the embodiment of the present application, on the one hand, it is not necessary to wait until all cache memory applications are completed before starting to read part of the first data, so the waiting time required to read part of the first data can be reduced; on the other hand, it is not necessary to read the first data in a serial manner, but parts of the first data can be read at the same time, so the time required to read the first data can be reduced. In summary, compared with the related art, the time to read the first data is reduced from the time to apply for cache memory + the reading time of the first data to MAX (the time to apply for cache memory, the reading time of the first data) + the time to apply for the first cache memory block (such as the first cache memory block) + the application time of the last cache memory block (such as the second cache memory block) + the reading time of the last part (such as the second part), so the total time consumption of reading the first data is reduced, that is, the efficiency of the electronic device in reading the first data is improved.

[0113] In summary, since the electronic device can read the first part into the first cache memory block and read the second part into the second cache memory block when applying for the second cache memory block, that is, the electronic device can read multiple parts into multiple cache memory blocks at the same time, that is, the electronic device can read more parts of the first data into the cache memory block at the same time, therefore, the time required to read the first data into the cache memory can be reduced. That is, the efficiency of the electronic device in reading data can be improved.

[0114] The following is a complete example to illustrate the specific scheme of the memory application method provided in the embodiment of the present application.

[0115] like Figure 7As shown, it is assumed that the DMA device (such as GPU and APU) of the electronic device needs to read the model file of the AI ​​large model, which includes the weight file. Thus, the ioctl program can trigger the user space to send a memory application request corresponding to the model file to the system of the electronic device, and the memory application request is used to request to apply for DMA-BUF memory (i.e., the cache memory in the above embodiment), so that the system of the electronic device can receive the memory application request and perform the DMA-BUF memory application operation according to the memory application request. In the process of applying for DMA-BUF memory, the system of the electronic device can record the cache memory block applied for in the first list, and when the memory size of the cache memory block recorded in the first list matches the preset memory size, the cache memory block recorded in the first list is determined as the first cache memory block (e.g., chunkpage1). At this time, the system of the electronic device can submit task 1 (i.e., the first task in the above embodiment) to data processing thread 1, so that data processing thread 1 can directly obtain the first part (e.g., chunk 1) from the first data in the disk, and directly store chunk 1 in chunkpage1. When the electronic device system submits task 1 to data processing thread 1, the electronic device system can clear the cache memory block recorded in the first list, and then record the cache memory block applied for in the first list, and when the memory size of the memory block recorded in the first list matches the preset memory size, the cache memory block recorded in the first list is determined as the second cache memory block (e.g., chunkpage2). At this time, the electronic device system can submit task 2 to data processing thread 2, so that data processing thread 2 can directly obtain the second part (e.g., chunk2) from the first data in the disk, and directly store chunk2 in chunkpage2. When the electronic device system submits task 2 to processing thread 2, the electronic device system can clear the cache memory block recorded in the first list, and then record the cache memory block applied for in the first list, and when the memory size of the memory block recorded in the first list matches the preset memory size, the cache memory block recorded in the first list is determined as the third cache memory block (e.g., chunkpage3). Then, the system of the electronic device may submit task 3 to data processing thread 3, so that data processing thread 3 may directly obtain the third part (e.g., chunk 3) from the first data in the disk, and directly store chunk 3 in chunkpage 3. And so on, until all parts of the first data are stored in the DMA-BUF memory.

[0116] It can be understood that while the system of the electronic device reads chunk 1 into chunkpage1, the system of the electronic device can apply for chunkpage2 and read chunk 2 into chunkpage2, and the system of the electronic device can apply for chunkpage3 and read chunk3 into chunkpage3, that is, the system of the electronic device can apply for cache memory in a pipeline parallel manner and read the first data into the cache memory, thereby reducing the time consumed by driving the electronic device and / or the device reading the first data.

[0117] Furthermore, since the data processing thread can directly read the first data in the disk into the cache memory without first reading the first data in the disk into the PAGE CACHE and then copying the first data in the PAGE CACHE to the cache memory through the CPU, it is possible to avoid wasting memory resources while avoiding wasting CPU computing power due to the CPU having to copy data in other memories to the cache memory.

[0118] The following will compare the memory application method in the related art with the memory application method provided in the embodiment of the present application, and specifically explain the difference between the memory application method provided in the embodiment of the present application and the memory application method in the related art.

[0119] In the related art, it is assumed that the DMA device of the electronic device (such as GPU and APU) needs to read the model file of the AI ​​large model, which includes the weight file. Therefore, the user space can apply for DMA-BUF memory, such as Figure 8 As shown, at this time, the ioctl program can trigger the user space to send a memory application request corresponding to the model file to the system of the electronic device, and the memory application request is used to request an application for DMA-BUF memory (i.e., the cache memory in the above embodiment), so that the system of the electronic device can receive the memory application request, and according to the memory application request, perform a DMA-BUF memory application operation, and when the DMA-BUF memory application is completed, the user space can open the first data (for example, the model file of the AI ​​large model), and obtain the user address space (UserVaddr) according to the physical address mapping of the DMA-BUF memory, so that the user space can first apply for PAGE CACHE, and then read the model file of the AI ​​large model in the disk into the PAGE CACHE, and then copy the model file of the AI ​​large model in the PAGE CACHE to the user address space (User Vaddr) through the CPU, thereby completing the reading of the model file of the AI ​​large model into the DMA-BUF memory.

[0120] Depend on Figure 8As can be seen from the above description, in the related art, the first data read request can only be initiated after the DMA-BUF memory application is completed, and an additional PAGE CACHE application is required during the file reading process.

[0121] However, in the embodiment of the present application, it is assumed that the DMA device of the electronic device (such as GPU and APU) needs to read the model file of the AI ​​large model, which includes the weight file. Therefore, the user space can apply for DMA-BUF memory, such as Fig. 9 As shown, at this time, the ioctl program can trigger the user space to send a memory application request corresponding to the model file to the system of the electronic device, and the memory application request is used to request to apply for DMA-BUF memory (i.e., the cache memory in the above embodiment), so that the system of the electronic device can receive the memory application request, and according to the memory application request, perform the DMA-BUF memory application operation. In the process of applying for DMA-BUF memory, the system of the electronic device can record the cache memory block page applied for in the first list, and when the memory size of the page recorded in the first list matches the preset memory size (chunk limit), the page recorded in the first list is determined as the first cache memory block, and the memory size of the first cache memory block and the first data position corresponding to the first data (such as the model file of the AI ​​large model) are recorded. Thus, the system of the electronic device can clear the cache memory block page recorded in the first list while submitting task 1 to the data processing thread 1, and then record the cache memory block page applied for in the first list. In this way, when data processing thread 1 is in a sleep state, the system of the electronic device can wait for the data processing thread 1 to end its sleep state, and when the data processing thread 1 exits the sleep state, the system of the electronic device can directly read the first part corresponding to the first cache memory block into the first cache memory block through the data processing thread 1. Similarly, the electronic device can repeat the above steps until the model file of the AI ​​large model is read into the DMA-BUF memory.

[0122] It can be understood that while the system of the electronic device reads the first part into the first cache memory block, the system of the electronic device can also apply for a second cache memory block and read the second part into the second cache memory block, that is, the system of the electronic device can apply for DMA-BUF memory in a pipeline parallel manner, and read the model file of the AI ​​large model into the DMA-BUF memory, thereby reducing the time consumed by driving the electronic device and / or the device reading data.

[0123] The beneficial effects of the memory application method provided in the embodiment of the present application will be specifically described below from two aspects: no-load scenario and overload scenario.

[0124] In the no-load scenario, there is no pressure on memory application. The problems in related technologies are mainly reflected in the pressure on memory and power consumption caused by PAGECACHE memory application and CPU copy.

[0125] In overload scenarios, usually when multiple applications are open, the memory pressure is relatively high. In addition to the memory and power consumption pressure in no-load scenarios, the problems in related technologies also include the CPU power consumption pressure caused by memory recycling.

[0126] However, in the memory application method provided in the embodiment of the present application, the most important basic point for the optimization of the no-load scenario is to use the DIO method to omit the intermediate state memory (i.e., PAGE CACHE memory) and CPU copy. As for the impact of memory recycling in the heavy-load scenario, since the application-IO asynchronous CHUNK synchronization method is adopted, the memory application time can hide the IO time, which is faster than the pure serial memory application + IO time.

[0127] According to the current project test, the fastest speed in the no-load scenario is to reduce the model file reading time of the AI ​​7B large model from 2s to 1s, with an average of 1.2s. Fig.10 As shown, taking the camera device reading the model file of the AI ​​large model as an example, if the data size of the model file of the AI ​​large model is 500MB, it takes 1283.5ms to read the model file using the memory application method in the related art, while it only takes 309.0ms to read the model file using the memory application method provided in the embodiment of the present application. If the data size of the model file of the AI ​​large model is 1.2GB, it takes 1819.6ms to read the model file using the memory application method in the related art, while it only takes 620.9ms to read the model file using the memory application method provided in the embodiment of the present application. If the data size of the model file of the AI ​​large model is 1.6GB, it takes 2379.2ms to read the model file using the memory application method in the related art, while it only takes 751.3ms to read the model file using the memory application method provided in the embodiment of the present application.

[0128] The memory application method provided in the embodiment of the present application can be executed by a memory application device. In the embodiment of the present application, the memory application device provided in the embodiment of the present application is described by taking the memory application device executing the memory application method as an example.

[0129] Fig.11 FIG. 1 shows a schematic diagram of the structure of a memory application device provided in an embodiment of the present application. Fig.11 As shown, the memory application device 50 provided in the embodiment of the present application may include: an application module 51 and a reading module 52.

[0130] The application module 51 is used to perform a memory application operation according to the memory application request when receiving a memory application request corresponding to the first data. The reading module 52 is used to read the first part of the first data into the first cache memory block when the application module 51 applies for the first cache memory block; the data volume of the first part matches the memory size of the first cache memory block.

[0131] An embodiment of the present application provides a memory application device. When the memory application device applies for a first cache memory block with a smaller memory size, the memory application device reads a first part of the data that matches the memory size of the first cache memory block into the first cache memory block, without having to wait until the entire cache memory application is completed before reading the first data into the cache memory. Therefore, the waiting time required to read the first data can be reduced, thereby reducing the time spent on data reading by the memory application device, that is, the data reading efficiency of the memory application device can be improved.

[0132] In a possible implementation, the first data also includes a second part, and the first part is adjacent to the second part. The reading module 52 is further configured to read the second part into the second cache memory block when the application module 51 applies for the second cache memory block; the data size of the second part matches the memory size of the second cache memory block.

[0133] In a possible implementation manner, the memory size of the first cache memory block is the same as or different from the memory size of the second cache memory block.

[0134] In a possible implementation, the memory size of the first cache memory block and the memory size of the second cache memory block are determined according to the data volume of the first data.

[0135] In a possible implementation, the reading module 52 is specifically configured to read the first part into a virtual storage space corresponding to a first virtual address; the first virtual address corresponds to a first cache memory block.

[0136] In a possible implementation, the memory application device 50 provided in the embodiment of the present application may further include: a mapping module. The mapping module is used to map the physical address of the first cache memory block to the virtual storage space to obtain the first virtual address before the reading module 52 reads the first part to the virtual storage space corresponding to the first virtual address.

[0137] In a possible implementation, the reading module 52 is specifically configured to read the first part into a virtual storage space corresponding to a first virtual address according to a first data position of the first part in the first data and a data amount of the first part through a data processing thread.

[0138] In a possible implementation, the memory application device 50 provided in the embodiment of the present application may further include: a recording module and a determination module. The recording module is used to record the cache memory block applied for to the first list. The determination module is used to determine the memory block recorded in the first list as the first cache memory block when the memory size of the memory block recorded in the first list by the recording module matches the preset memory size.

[0139] The memory application device in the embodiment of the present application can be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or it can be other devices other than the terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile internet device (mobile internet device, MID), an augmented reality (augmentedreality, AR) / virtual reality (virtualreality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc., and can also be a server, a network attached storage (network attached storage, NAS), a personal computer (personalcomputer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0140] The memory application device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, a Linux operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0141] The memory application device provided in the embodiment of the present application can realize Figures 2 to 10 To avoid repetition, the various processes implemented by the method embodiment are not described here.

[0142] In some embodiments of the present application, Fig.12 As shown, an embodiment of the present application further provides an electronic device 60, including a processor 61 and a memory 62, wherein the memory 62 stores programs or instructions that can be executed on the processor 61, and when the program or instructions are executed by the processor 61, the various process steps of the above-mentioned memory application method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, they are not described here.

[0143] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0144] Fig.13 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of the present application.

[0145] The electronic device 100 includes but is not limited to components such as a radio frequency unit 101, a network module 102, an audio output unit 103, an input unit 104, a sensor 105, a display unit 106, a user input unit 107, an interface unit 108, a memory 109, and a processor 110.

[0146] Those skilled in the art will appreciate that the electronic device 100 may also include a power source (such as a battery) for supplying power to various components, and the power source may be logically connected to the processor 110 through a power management system, thereby implementing functions such as managing charging, discharging, and power consumption management through the power management system. Fig.13 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be described in detail here.

[0147] Among them, the processor 110 is used to perform a memory application operation according to the memory application request when a memory application request corresponding to the first data is received; and when the first cache memory block is applied for, the first part of the first data is read into the first cache memory block; the data amount of the first part matches the memory size of the first cache memory block.

[0148] An embodiment of the present application provides an electronic device. When the electronic device applies for a first cache memory block with a smaller memory size, the electronic device reads a first part of the data that matches the memory size of the first cache memory block into the first cache memory block, without having to wait until the entire cache memory application is completed before reading the first data into the cache memory. Therefore, the waiting time required to read the first data can be reduced, thereby reducing the time spent on data reading by the electronic device, that is, the data reading efficiency of the electronic device can be improved.

[0149] In some embodiments of the present application, the first data also includes a second part, and the first part is adjacent to the second part.

[0150] The processor 110 is further configured to read the second part into the second cache memory block when the second cache memory block is applied for; the data size of the second part matches the memory size of the second cache memory block.

[0151] In some embodiments of the present application, the processor 110 is specifically configured to read the first portion into a virtual storage space corresponding to a first virtual address; the first virtual address corresponds to a first cache memory block.

[0152] In some embodiments of the present application, the processor 110 is further configured to map the physical address of the first cache memory block to the virtual storage space before reading the first part into the virtual storage space corresponding to the first virtual address to obtain the first virtual address.

[0153] In some embodiments of the present application, the processor 110 is specifically configured to read the first part into a virtual storage space corresponding to a first virtual address through a data processing thread according to a first data position of the first part in the first data and a data amount of the first part.

[0154] In some embodiments of the present application, the processor 110 is further used to record the applied cache memory block into a first list; and when the memory size of the cache memory block recorded in the first list matches a preset memory size, the cache memory block recorded in the first list is determined as the first cache memory block.

[0155] It should be understood that in the embodiment of the present application, the input unit 104 may include a graphics processing unit (GPU) 1041 and a microphone 1042, and the graphics processor 1041 processes the image data of a static picture or video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The display unit 106 may include a display panel 1061, and the display panel 1061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 107 includes a touch panel 1071 and at least one of other input devices 1072. The touch panel 1071 is also called a touch screen. The touch panel 1071 may include two parts: a touch detection device and a touch controller. Other input devices 1072 may include, but are not limited to, a physical keyboard, function keys (such as a volume control button, a switch button, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0156] The memory 109 can be used to store software programs and various data. The memory 109 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory 109 may include a volatile memory or a non-volatile memory, or the memory 109 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM) and a direct memory bus random access memory (DRRAM). The memory 109 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0157] The processor 110 may include one or more processing units; optionally, the processor 110 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor 110.

[0158] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, each process of the above-mentioned memory application method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0159] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0160] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned memory application method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0161] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0162] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned memory application method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0163] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises one..." does not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0164] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0165] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A memory application method, characterized in that: include: When receiving a memory application request corresponding to the first data, performing a memory application operation according to the memory application request; When the first cache memory block is applied for, the first part of the first data is read into the first cache memory block; the data volume of the first part matches the memory size of the first cache memory block.

2. The method according to claim 1, characterized in that The first data further includes a second portion, the first portion being adjacent to the second portion; The method further comprises: When the second cache memory block is applied for, the second part is read into the second cache memory block; the data size of the second part matches the memory size of the second cache memory block.

3. The method according to claim 2, characterized in that The memory size of the first cache memory block is the same as or different from the memory size of the second cache memory block.

4. The method according to claim 2, characterized in that: The memory size of the first cache memory block and the memory size of the second cache memory block are determined according to the data volume of the first data.

5. The method according to claim 1, characterized in that The step of reading the first part of the first data into the first cache memory block includes: The first portion is read into a virtual storage space corresponding to a first virtual address; the first virtual address corresponds to the first cache memory block.

6. The method according to claim 5, characterized in that Before reading the first part into the virtual storage space corresponding to the first virtual address, the method further includes: The physical address of the first cache memory block is mapped to the virtual storage space to obtain the first virtual address.

7. The method according to claim 5, characterized in that The step of reading the first part into a virtual storage space corresponding to the first virtual address includes: Through the data processing thread, according to the first data position of the first part in the first data and the data amount of the first part, the first part is read into the virtual storage space corresponding to the first virtual address.

8. The method according to claim 1, characterized in that The method further comprises: Record the requested cache memory block into the first list; In a case where the memory size of the cache memory block recorded in the first list matches the preset memory size, the cache memory block recorded in the first list is determined as the first cache memory block.

9. A memory application device, characterized in that: include: Application module and reading module; The application module is configured to, upon receiving a memory application request corresponding to the first data, execute a memory application operation according to the memory application request; The reading module is used to read the first part of the first data into the first cache memory block when the application module applies for the first cache memory block; the data volume of the first part matches the memory size of the first cache memory block.

10. The device according to claim 9, characterized in that The first data further includes a second portion, the first portion being adjacent to the second portion; The reading module is also used to read the second part into the second cache memory block when the application module applies for the second cache memory block; the data size of the second part matches the memory size of the second cache memory block.

11. The device according to claim 10, characterized in that The memory size of the first cache memory block is the same as or different from the memory size of the second cache memory block.

12. The device according to claim 10, characterized in that The memory size of the first cache memory block and the memory size of the second cache memory block are determined according to the data volume of the first data.

13. The device according to claim 9, characterized in that The reading module is specifically used to read the first part into a virtual storage space corresponding to a first virtual address; the first virtual address corresponds to the first cache memory block.

14. The device according to claim 13, characterized in that The memory application device further includes: a mapping module; The mapping module is used to map the physical address of the first cache memory block to the virtual storage space to obtain the first virtual address before the reading module reads the first part into the virtual storage space corresponding to the first virtual address.

15. The device according to claim 13, characterized in that The reading module is specifically configured to read the first part into the virtual storage space corresponding to the first virtual address through a data processing thread according to a first data position of the first part in the first data and a data amount of the first part.

16. The device according to claim 9, characterized in that The memory application device further includes: a recording module and a determination module; The recording module is used to record the applied cache memory block into the first list; The determining module is configured to determine the memory block recorded in the first list as the first cache memory block if the memory size of the memory block recorded in the first list by the recording module matches a preset memory size.

17. An electronic device, characterized in that: It comprises a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the memory application method as described in any one of claims 1 to 8 are implemented.

18. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the memory application method according to any one of claims 1 to 8 are implemented.

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