Read-write permission allocation method and device and electronic equipment
By dynamically allocating the read and write permissions of the processor and adjusting the register modification level, the problem of low read and write permissions in multi-core chip systems is solved, and flexible management and stability improvement of GPIO module permissions are achieved.
Patent Information
- Application Number
- CN202411398763.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-30
- Publication Date
- 2025-01-14
AI Technical Summary
In multi-core chip systems, the prior art requires resetting the processor to modify read and write permissions, resulting in less flexibility and the inability to flexibly change the units that each CPU can modify in the GPIO module.
By obtaining permission modification instructions, determine the identity identity of the target processor and the target register, dynamically allocate read and write permissions, allow or restrict the processor's access to the register, adjust the modification level based on business needs, and reset the register's value when needed.
Improves the flexibility of processor read and write permissions, avoids the need to reset the processor, and enhances the flexibility and stability of GPIO module permission allocation.
Smart Images
Figure CN119311611A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the field of chip control technology, and in particular, relates to a method, device and electronic device for allocating read and write permissions. Background Art
[0002] The general-purpose input / output (GPIO) module is an interface widely used in embedded systems. It connects to external devices through the PAD port set on the GPIO module to achieve digital signal interaction between the chip and the external device.
[0003] In a single-core chip, the central processing unit (CPU) can modify the GPIO configuration accordingly to control the PAD port to implement corresponding functions, such as changing the signal transmission direction, controlling the pull-up or pull-down of the PAD port level, multiplexing digital signals or analog signals, etc. For multi-core chips, there will be a situation where multiple CPUs modify the GPIO configuration at the same time, resulting in inconsistent configuration data, unstable application systems, or even crashes.
[0004] Based on this, the modification permissions of GPIO can be distributed to reduce the situation where multiple CPUs modify the GPIO configuration at the same time. At present, distributed locks can be used to ensure that only one CPU has the modification permission for each unit in the GPIO module, or the physical access path of GPIO can be divided so that each CPU can only access the corresponding unit in the GPIO module, thereby reducing the situation where multiple CPUs modify the GPIO configuration at the same time.
[0005] However, in the above method, the units that can be modified by each CPU in the GPIO module are fixed and factory set. If it is necessary to change the units that can be modified by each CPU in the GPIO module, the chip needs to be reset to the initial state, which has the problem of low flexibility. Summary of the invention
[0006] The embodiments of the present application provide a method, device and electronic device for allocating read and write permissions, aiming to solve the problem of low flexibility in the existing process of modifying the read and write permissions of a processor by resetting the processor.
[0007] In a first aspect, an embodiment of the present application provides a method for allocating read and write permissions, the method being applied to a chip system, the chip system comprising at least two processors, at least two of the processors being connected to a general module, the general module comprising one or more registers, the method comprising:
[0008] Obtaining a permission modification instruction; wherein the permission modification instruction includes an identity identifier of at least one of the processors and number information of at least one target register, and the target register is a register of the one or more registers whose permissions are to be modified;
[0009] Determining, according to the permission modification instruction, a target processor corresponding to a port connected to the target register;
[0010] According to the identity of the target processor, the permission to read and write the target register is allocated to the target processor.
[0011] In a possible implementation manner of the first aspect, allocating, for the target processor, permission to read and write the target register according to the identity of the target processor includes:
[0012] The value of the target register is modified to a value corresponding to the identity of the target processor.
[0013] In a possible implementation manner of the first aspect, modifying the value of the target register to a value corresponding to the identity of the target processor includes:
[0014] Determine a main processor; wherein the main processor is a processor with modification authority, and the modification authority is an authority to modify the value of the register;
[0015] The main processor is used to modify the value of the target register to a value corresponding to the identity of the target processor.
[0016] In a possible implementation manner of the first aspect above, the method further includes:
[0017] When the processor accesses the universal module, the identity of the processor is matched with the value of each register, and when the identity of the processor matches the value of the register, the processor is allowed to perform a read and write task on the register;
[0018] When the identity of the processor does not match the value of the register, the processor is restricted from executing read and write tasks on the register.
[0019] In a possible implementation manner of the first aspect, before modifying the value of the target register to a value corresponding to the identity of the target processor, the method further includes:
[0020] Determining a modification level of each of the registers according to the business requirements of the chip system;
[0021] When the modification level of the target register is modification allowed, performing the step of modifying the value of the target register to a value corresponding to the identity of the target processor;
[0022] When the modification level of the target register is restricted, prompt information for restricting modification of the register is generated, and a prompt is given to the user based on the prompt information.
[0023] In a possible implementation manner of the first aspect above, the method further includes:
[0024] In the case where the modification level of the target register is restricted modification, responding to a reset instruction, modifying the value of the register to a reset value, and re-performing the step of defining the modification level of each register according to the business requirements of the chip system;
[0025] The reset value is related to the version configuration of the chip system, and the version configuration is written by the processor during iterative update.
[0026] In a possible implementation manner of the first aspect above, the general module further includes an access identification component, and the access identification component is used to identify the identity of the processor when the processor accesses the general module.
[0027] In a second aspect, an embodiment of the present application provides a device for allocating read and write permissions, the device being applied to a chip system, the chip system comprising at least two processors, at least two of the processors being connected to a general module, the general module comprising one or more registers, the device comprising:
[0028] An acquisition module, used for acquiring a permission modification instruction; wherein the permission modification instruction includes an identity identifier of at least one of the processors and number information of at least one target register, and the target register is a register of the one or more registers whose permissions are to be modified;
[0029] A determination module, configured to determine a target processor corresponding to a port connected to the target register according to the permission modification instruction;
[0030] The allocation module is used to allocate the permission of reading and writing the target register to the target processor according to the identity of the target processor.
[0031] In a third aspect, an embodiment of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the method for allocating read and write permissions provided in the first aspect above is implemented.
[0032] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method for allocating read and write permissions provided in the first aspect above is implemented.
[0033] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program. When the computer program is run on a computer, the computer executes the method for allocating read and write permissions provided in the first aspect above.
[0034] It can be understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.
[0035] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:
[0036] In an embodiment of the present application, by obtaining a permission modification instruction, the permission modification instruction includes the identity of at least one processor and the numbering information of at least one target register, the target register is a register of one or more registers whose permissions are to be modified, and according to the permission modification instruction, the target processor corresponding to the port connected to the target register is determined, and according to the identity of the target processor, the permission to read and write the target register is allocated to the target processor, so that the permission of the processor to read and write each register can be allocated through the identity of the processor, and the processor can be controlled to perform read and write tasks on the register based on the read and write permissions of each processor, thereby improving the flexibility of changing the read and write permissions of the processor. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] Figure 1 is an architecture diagram of a chip system provided by an embodiment of the present application;
[0038] Figure 2 This is a flowchart of a method for allocating read and write permissions provided by an embodiment of the present application;
[0039] Figure 3 It is a schematic diagram of allowing and restricting the execution of read and write tasks provided by an embodiment of the present application;
[0040] Figure 4 It is a flowchart of another method for allocating read and write permissions provided by an embodiment of the present application;
[0041] Figure 5 It is a structural diagram of a device for allocating read and write permissions provided in one embodiment of the present application;
[0042] Figure 6 It is a structural block diagram of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION
[0043] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0044] The general-purpose input / output (GPIO) module is an interface widely used in embedded systems. It connects to external devices through the PAD port set on the GPIO module to achieve digital signal interaction between the chip and the external device.
[0045] In a single-core chip, the central processing unit (CPU) can modify the GPIO configuration accordingly to control the PAD port to implement corresponding functions, such as changing the signal transmission direction, controlling the pull-up or pull-down of the PAD port level, multiplexing digital signals or analog signals, etc.
[0046] For example, when the processor needs to receive a signal returned by an external device, the configuration of the PAD port in the GPIO can be modified to input mode, that is, the signal transmission direction of the PAD port is changed, and then the external device transmits the data to be transmitted through the PAD port to the corresponding processor for processing.
[0047] For multi-core chips, multiple CPUs may modify the GPIO configuration at the same time, resulting in inconsistent configuration data, unstable application system, or even crash.
[0048] Based on this, the modification permissions of GPIO can be distributed to reduce the situation where multiple CPUs modify the GPIO configuration at the same time. At present, distributed locks can be used to ensure that only one CPU has the modification permission for each unit in the GPIO module, or the physical access path of GPIO can be divided so that each CPU can only access the corresponding unit in the GPIO module, thereby reducing the situation where multiple CPUs modify the GPIO configuration at the same time.
[0049] However, in the above method, the units that can be modified by each CPU in the GPIO module are fixed and factory set. If it is necessary to change the units that can be modified by each CPU in the GPIO module, the chip needs to be reset to the initial state, which has the problem of low flexibility.
[0050] Based on this, the present application provides a chip system, which may include a general module, at least two processors, at least one PAD port and at least one register. The general module may be used to connect the processor and the PAD port so that the processor and the PAD port can interact with digital signals, the processor can process different tasks, and the PAD port can be connected to an external device so that the processor can interact with the external device through the PAD port and process tasks of different external devices. Each PAD port may correspond to a register, and the register may include an identity register and a configuration register. The identity register may store the identity of the processor with the permission to read and write the register, and the configuration register may store the configuration information of the PAD port, such as the numbering information of the PAD port, the state configuration of the PAD port, the security configuration of the PAD port, and other information. The numbering information of the PAD port may be the port number of the PAD port.
[0051] Exemplarily, the chip system may further include an Advanced High Performance Bus (AHB), and connect the processor and the GPIO module via the AHB bus, so that each processor accesses the GPIO via the AHB bus.
[0052] In actual applications, the GPIO module may also include an access identification component, which can be used to identify the identity of the processor when the processor accesses the general module. The identity of the processor may be information such as the model and specifications of the processor, and the identity can be used to distinguish and identify the processor.
[0053] For details, see Figure 1 , Figure 1 FIG. 4 shows an architecture diagram of a chip system provided by an embodiment of the present application. Figure 1 As shown, the chip system 1 may include a processor 11, a high-performance bus 12, a general module 13, and a port 14. Among them, the port 14 may include at least one port. Exemplarily, the port 14 may include 8 ports, namely PAD0 to PAD7. The processor 11 may include at least two processors. Exemplarily, the processor 11 may include two processors, namely processor a and processor b. The processor 11 may be connected to the general module 13 through the high-performance bus 12. The general module 13 may include an access identification component and at least one register, and each register corresponds to a port 14. Exemplarily, the general module 13 may include 8 registers, namely PA0 to PA7, and register PA0 may correspond to port PAD0. By analogy, register PA7 may correspond to port PAD7.
[0054] In a specific implementation, the processor can access the general module, and the access identification component in the general module can identify the identity of the processor accessing the general module, and match the identity of the processor accessing the general module with the identity stored in each identity register in the general module, so as to determine the register that matches the processor accessing the general module, that is, determine the register whose stored identity matches the identity of the processor accessing the general module, and assign the processor permission to read and write the matching register, or permission to read and write the external device corresponding to the matching register, so that the processor can read and write the matching register or read and write the external device corresponding to the matching register, that is, read and write the external device through the port corresponding to the matching register.
[0055] It can be understood that by modifying the value of each identity register, the processor's permission to read and write the register or the external device corresponding to the register can be changed without resetting the chip to its initial state, thereby improving the flexibility of assigning read and write permissions to the processor.
[0056] See also Figure 2 , Figure 2 A flowchart of a method for allocating read and write permissions provided by an embodiment of the present application is shown. The method is applied to a chip system, the chip system includes at least two processors, the at least two processors are connected to a general module, the general module includes one or more registers, and specifically may include the following steps:
[0057] Step 201, obtaining permission modification instructions.
[0058] The permission modification instruction may be an instruction for modifying the permission of the processor to read and write registers in the general module. The permission modification instruction may be input by the user based on the requirements, or may be generated based on the version requirements of the chip system or processor. The version requirements of the chip system or processor may include requirements for iterative update or restoration of the original version of the chip system or processor. The permission modification instruction may include the identity of at least one processor and the numbering information of at least one target register. The target register may be a register of one or more registers whose permissions are to be modified, that is, a register in the general module whose permissions need to be modified.
[0059] When a user needs to modify the read and write permissions of the processor in the chip system, the user will input permission modification instructions based on his or her needs, and the chip system will be able to obtain the permission modification instructions input by the user, or when the read and write permissions of the processor in the chip system need to be modified based on the version requirements of the chip system or processor, the corresponding permission modification instructions will be obtained from the version requirements of the chip system or processor. For example, the chip system will obtain a data packet for iterative updates during iterative updates, and the data packet includes permission modification instructions for modifying the read and write permissions of the processor in the chip system.
[0060] Specifically, the permission modification instruction may include the identity of each processor in the chip system, and then the processor whose read and write permissions need to be modified can be determined from the chip system based on the identity; the permission modification instruction may also include the numbering information of the register whose permissions need to be modified, and then the register on which the processor can perform read and write tasks after the permissions are modified can be determined from the chip system based on the numbering information.
[0061] Step 202: Determine the target processor corresponding to the port connected to the target register according to the permission modification instruction.
[0062] The target processor may be a processor that allows reading and writing of the target register and allows reading and writing of an external device through a port connected to the target register.
[0063] After receiving the permission modification instruction, the permission modification instruction can be read, and based on the number information of the target register in the permission modification instruction, the corresponding target register in the chip system and the port connected to the target register can be determined. Then, based on the permission modification instruction, the processor that can read and write the target register and can read and write external devices through the port connected to the target register can be determined from all processors in the chip system, that is, the target processor.
[0064] Step 203: Allocate the permission to read and write the target register to the target processor according to the identity of the target processor.
[0065] After the target processor is determined, the identity of the target processor can be determined from the permission modification instruction, and the permission to read and write the target register can be allocated to the target processor according to the identity of the target processor.
[0066] In an embodiment of the present application, step 203 may include the following steps:
[0067] The value of the target register is modified to a value corresponding to the identity of the target processor.
[0068] In practical applications, the value of the target register can be modified to a value corresponding to the identity of the target processor. Specifically, the value of the identity register in the target register for storing the identity can be modified to a value corresponding to the identity of the target processor, so that the value of the identity register in the target register matches the identity of the target processor.
[0069] Specifically, the value stored in the identity register is usually 1 bit in size and is expressed in binary, that is, the value of the identity register is 0 or 1, and the number of identity registers may be related to the number of processors in the chip system. For example, the identity of the target processor may be 0, then the value corresponding to the identity of 0 may be represented by one identity register, and the value of the identity register may be 0, while the identity of another target processor may be 3, then the corresponding value may be represented by two identity registers, and the value of the identity register may be 11.
[0070] In an embodiment of the present application, the following steps may also be included:
[0071] When the processor accesses the general module, the processor's identity is matched with the value of each register, and when the processor's identity matches the register's value, the processor is allowed to perform read and write tasks on the register. When the processor's identity does not match the register's value, the processor is restricted from performing read and write tasks on the register.
[0072] After all processors are assigned permissions to read and write registers, the processor needs to access the general module in order to perform read and write tasks on the registers or corresponding external devices. When the processor accesses the general module, the access identification component in the general module can identify the identity of the processor currently accessing and match the identity with the value of each register in the general module.
[0073] For each register, when the identity of the processor currently accessing matches the value of the register, it can be determined that the processor currently accessing has the authority to read and write the register, and the processor can be allowed to perform read and write tasks on the register, such as performing read and write tasks on the configuration register in the register, or performing read and write tasks on an external device through a port connected to the register; and when the identity of the processor currently accessing does not match the value of the register, it can be determined that the processor currently accessing does not have the authority to read and write the register, and the processor can be restricted from performing read and write tasks on the register.
[0074] As an example, when the identity of the processor currently accessing does not match the value of the register, the register may also return an invalid value to the processor currently accessing.
[0075] See also Figure 3 , Figure 3 is a schematic diagram showing a method of allowing and restricting the execution of read and write tasks provided by an embodiment of the present application, such as Figure 3 As shown, the general module 3 may include a register 31 and a register 32. The processor 4 may be a processor with an identity identifier of 0, the processor 5 may be a processor with an identity identifier of 1, the register 31 may include a configuration register 311 and an identity register 312, and the value of the identity register 312 in the register 31 may be 1, the register 32 may include a configuration register 321 and an identity register 322, and the value of the identity register 322 in the register 32 may be 0.
[0076] When processor 4 accesses the general module, it can be determined that the value of identity register 312 in register 31 does not match the identity of processor 4, and the value of identity register 322 in register 32 matches the identity of processor 4, thereby allowing processor 4 to perform read and write tasks on register 32 and restricting processor 4 from performing read and write tasks on register 31; and when processor 5 accesses the general module, it can be determined that the value of identity register 322 in register 32 matches the identity of processor 5, and the value of identity register 312 in register 31 does not match the identity of processor 5, thereby allowing processor 5 to perform read and write tasks on register 32 and restricting processor 5 from performing read and write tasks on register 31.
[0077] In an embodiment of the present application, by obtaining a permission modification instruction, the permission modification instruction includes the identity of at least one processor and the numbering information of at least one target register, the target register is a register of one or more registers whose permissions are to be modified, and according to the permission modification instruction, the target processor corresponding to the port connected to the target register is determined, and according to the identity of the target processor, the permission to read and write the target register is allocated to the target processor, so that the permission of the processor to read and write each register can be allocated through the identity of the processor, and the processor can be controlled to perform read and write tasks on the register based on the read and write permissions of each processor, thereby improving the flexibility of changing the read and write permissions of the processor.
[0078] See also Figure 4 , Figure 4 A flowchart of another method for allocating read and write permissions provided by an embodiment of the present application is shown, which may specifically include the following steps:
[0079] Step 401, obtaining permission modification instructions.
[0080] Step 402: Determine the target processor corresponding to the port connected to the target register according to the permission modification instruction.
[0081] For the related descriptions of step 401 to step 402, please refer to step 201 to step 202, which will not be repeated.
[0082] Step 403: Determine the modification level of each register according to the business requirements of the chip system.
[0083] Among them, the business requirements may be planning requirements for each processor in the chip system and planning requirements for each register in the chip system. The planning requirements for registers may be requirements for allowing registers to be connected to external devices with higher security or restricting registers from being connected to external devices with higher security. External devices with higher security may be external devices that process, transmit or store sensitive data, such as storage devices for storing sensitive data, communication devices for encrypted communication, etc. Sensitive data may be data with higher security requirements, such as personal data such as fingerprints and facial patterns of users, or data related to financial transactions such as transaction records and account information. The business requirements of the chip system may be determined during the production process of the chip system, and the business requirements of the chip system may be adjusted during the update iteration of the chip system or processor. The modification level may be the permission level for modifying the value of the register, and the modification level may include a level that allows modification and a level that restricts modification.
[0084] After the target processor is determined, the business requirements of the current chip system can be determined, and the modification level of each register can be determined based on the business requirements of the chip system.
[0085] In practical applications, the business requirements of the chip system may include information on the modification level of each register in the chip system, and the modification level of each register may be obtained from the business requirements of the chip system.
[0086] In a specific implementation, the manufacturer of the chip system can plan the purpose of each register in the chip system, that is, it can define the registers in the chip system that can be connected to external devices with higher security requirements, and define the registers that restrict the connection with external devices with higher security requirements, and then determine the modification level of each register, and write the purpose of each register into the business requirements of the chip system, so that the modification level of each register can be determined according to the business requirements of the chip system.
[0087] Step 404, when the modification level of the target register is modification allowed, execute the step of modifying the value of the target register to a value corresponding to the identity of the target processor.
[0088] When the modification level of the target register is modification allowed, it can be indicated that the value of the target register is allowed to be modified, and then the step of modifying the value of the target register to a value corresponding to the identity of the target processor can be executed.
[0089] As an example, the business requirements of the chip system may also be planning requirements for each processor in the chip system, and the planning requirements for the processor may be requirements such as planning the processor to allow processing of higher security tasks or restrict processing of higher security tasks, and higher security tasks may be tasks for processing or transmitting sensitive data.
[0090] In actual applications, the manufacturer of the chip system can also plan the purpose of each processor in the chip system, that is, they can define processors in the chip system that can handle tasks with higher security, and define processors that are restricted from processing tasks with higher security. Furthermore, different execution levels can be defined for each processor, including levels that allow the execution of tasks with higher security and levels that restrict the execution of tasks with higher security.
[0091] In a specific implementation, when the modification level of the target register is allowed to be modified and the execution level of the target processor is allowed to be executed, the step of modifying the value of the target register to a value corresponding to the identity of the target processor can be executed; when the modification level of the target register is restricted to be modified or the execution level of the target processor is restricted to be executed, subsequent steps can be executed, such as the step of generating a prompt message for restricting the modification of the register and the step of modifying the value of the register to a reset value in response to a reset instruction.
[0092] In an embodiment of the present application, the following steps may also be included:
[0093] When the modification level of the target register is modification restriction, prompt information of the modification restriction register is generated, and a prompt is given to the user based on the prompt information.
[0094] The prompt information may be information for prompting the user to modify the value restriction of the register, and the prompt information may be information provided in the form of text, picture, voice, etc.
[0095] When the modification level of the target register is restricted modification, it can be indicated that the value of the target register is not allowed to be modified, and a prompt message of the restricted modification of the value of the target register is generated, and the prompt message can be transmitted to the user to prompt the user of the restricted modification of the value of the target register.
[0096] In actual applications, users can determine the registers that are allowed to be modified and the registers that are restricted from modification in the chip system based on the prompt information, and redetermine the need to modify the read and write permissions of the processor based on the registers that are allowed to be modified and the registers that are restricted from modification in the chip system, so as to re-enter the permission modification instructions, or still determine the current need to modify the read and write permissions of the processor, and use other methods to modify the value of the target register, such as iteratively updating the chip system to update the business needs of the chip system.
[0097] In an embodiment of the present application, the following steps may also be included:
[0098] In the case where the modification level of the target register is restricted modification, responding to the reset instruction, modifying the value of the register to the reset value, and re-executing the step of defining the modification level of each register according to the business requirements of the chip system;
[0099] Among them, the reset instruction can be for restoring the configuration of the chip system to the configuration corresponding to the current version of the chip system, including restoring the value of the register in the chip system to the value corresponding to the current version of the chip system. The reset value can be related to the version configuration of the chip system. The version configuration can be written by the chip system during iterative updates. The version configuration can include the configuration of all modules in the chip system, such as register configuration, processor configuration, port configuration, etc. The register configuration can include data such as register value and register modification level.
[0100] When the modification level of the target register is restricted modification, it means that the value of the target register is not allowed to be modified. In order to modify the value of the target register, the user can enter a reset instruction or call the reset instruction in the version configuration of the current chip system, and respond to the reset instruction to modify the value of each register in the chip system to the corresponding reset value.
[0101] In actual applications, the modification level of each register in the chip system may also be modified to a modification level corresponding to the version configuration.
[0102] In a specific implementation, different versions of chip systems can define different values for each register, that is, the reset values of registers in different version configurations are different, and the modification levels will also be different, while different registers in the same version configuration can correspond to different reset values and different modification levels, and the value and modification level of each register can be written into the version configuration, and then, in response to a reset instruction, the value of each register can be modified to the corresponding reset value, and the modification level of each register can be modified to the corresponding modification level.
[0103] After the value of the register is modified to the reset value, the step of defining the modification level of each register according to the business requirements of the chip system can be re-executed.
[0104] In actual applications, the reset instruction can be used to modify the value of each register in the chip system to the reset value corresponding to any version configuration. Different version configurations can correspond to different business needs, and thus it is necessary to re-execute the steps of defining the modification level of each register according to the business needs of the chip system.
[0105] In an embodiment of the present application, when the modification level of the target register is modification allowed, step 404 may further include the following steps:
[0106] A main processor is determined, and a value of a target register is modified by the main processor to a value corresponding to an identity of the target processor.
[0107] The main processor may be a processor with modification authority, and the modification authority may be authority to modify the value of a register.
[0108] When the modification level of the target register is allowed to be modified, it can be indicated that the value of the target register is allowed to be modified, and then the processor with modification authority can be determined from all the processors in the chip system, that is, the main processor, and then the main processor can be used to modify the value of the target register to a value corresponding to the identity of the target processor.
[0109] In actual applications, the processor used to modify the register in the chip system can be pre-defined, and modification permissions can be assigned to the processor, so that only this processor can be used to modify the value of the register to reduce the situation where multiple processors modify the value of the register at the same time and cause conflicts.
[0110] In an embodiment of the present application, by obtaining a permission modification instruction, a target processor corresponding to the port connected to the target register is determined according to the permission modification instruction, and different modification levels are assigned to each register according to the business needs of the chip system. Based on the different modification levels, different degrees of restrictions are imposed on the values of the modified registers, thereby improving the flexibility of modifying the values of different registers. By determining the modification level of each register, when the modification level of the target register is allowed to be modified, a step of modifying the value of the target register to a value corresponding to the identity of the target processor is executed, and the target processor is assigned permissions to read and write the target register, thereby being able to assign permissions to the processor to read and write each register through the processor's identity, and controlling the processor to perform read and write tasks on the register based on the read and write permissions of each processor, thereby improving the flexibility of changing the read and write permissions of the processor.
[0111] See also Figure 5 , Figure 5 A schematic diagram of the structure of a read / write permission allocation device provided by an embodiment of the present application is shown. The device is applied to a chip system. The chip system includes at least two processors. The at least two processors are connected to a general module. The general module includes one or more registers. The device may specifically include the following modules:
[0112] The acquisition module 501 is used to acquire a permission modification instruction; wherein the permission modification instruction includes the identity of at least one processor and the numbering information of at least one target register, and the target register is a register of one or more registers whose permissions are to be modified.
[0113] The determination module 502 is used to determine the target processor corresponding to the port connected to the target register according to the permission modification instruction.
[0114] The allocation module 503 is used to allocate the permission to read and write the target register to the target processor according to the identity of the target processor.
[0115] In one implementation, the allocation module 503 may also be used to:
[0116] The value of the target register is modified to a value corresponding to the identity of the target processor.
[0117] In one implementation, the allocation module 503 may also be used to:
[0118] Determine a main processor; wherein the main processor is a processor with modification authority, and the modification authority is an authority to modify the value of a register;
[0119] The main processor is used to modify the value of the target register to a value corresponding to the identity of the target processor.
[0120] In one implementation, the following modules may also be included:
[0121] A matching module is used to match the processor's identity with the value of each register when the processor accesses the general module, and to allow the processor to perform read and write tasks on the register when the processor's identity matches the register's value, and to restrict the processor from performing read and write tasks on the register when the processor's identity does not match the register's value.
[0122] In one implementation, the determination module 502 may also be used to:
[0123] Before modifying the value of the target register to a value corresponding to the identity of the target processor, the modification level of each register is determined according to the business requirements of the chip system.
[0124] In one implementation, the following modules may also be included:
[0125] The execution module is used to execute the step of modifying the value of the target register to a value corresponding to the identity of the target processor when the modification level of the target register is allowed to be modified.
[0126] The prompt module is used to generate prompt information of restricting the modification of the register when the modification level of the target register is restricted modification, and prompt the user based on the prompt information.
[0127] In one implementation, the following modules may also be included:
[0128] A reset module, for responding to a reset instruction, modifying the value of the register to a reset value, and re-executing the step of defining the modification level of each register according to the business requirements of the chip system, when the modification level of the target register is restricted modification;
[0129] The reset value is related to the version configuration of the chip system, and the version configuration is written by the processor during iterative updates.
[0130] In one implementation, the general module further includes an access identification component, and the access identification component is used to identify the identity of the processor when the processor accesses the general module.
[0131] In an embodiment of the present application, by obtaining a permission modification instruction, the permission modification instruction includes the identity of at least one processor and the numbering information of at least one target register, the target register is a register of one or more registers whose permissions are to be modified, and according to the permission modification instruction, the target processor corresponding to the port connected to the target register is determined, and according to the identity of the target processor, the permission to read and write the target register is allocated to the target processor, so that the permission of the processor to read and write each register can be allocated through the identity of the processor, and the processor can be controlled to perform read and write tasks on the register based on the read and write permissions of each processor, thereby improving the flexibility of changing the read and write permissions of the processor.
[0132] It should be noted that the information interaction, execution process and other contents between the above-mentioned devices are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.
[0133] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.
[0134] See also Figure 6 , Figure 6 A structural block diagram of an electronic device provided by an embodiment of the present application is shown. Figure 6 As shown, this embodiment provides an electronic device 61, which includes: at least one processor 611, a memory 612, and a computer program 6121 stored in the memory 612 and executable on at least one processor 611, and when the processor 611 executes the computer program 6121, the steps in any of the above-mentioned method embodiments are implemented.
[0135] The embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps in any one of the above method embodiments can be implemented.
[0136] An embodiment of the present application provides a computer program product, including a computer program. When the computer program is run on a computer, the computer executes the steps in the above-mentioned various method embodiments.
[0137] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may at least include: any entity or device capable of carrying the computer program code to the camera device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium.
[0138] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.
Claims
1. A method for allocating read and write permissions, characterized in that: The method is applied to a chip system, the chip system includes at least two processors, at least two of the processors are connected to a general module, the general module includes one or more registers, and the method includes: Obtaining a permission modification instruction; wherein the permission modification instruction includes an identity identifier of at least one of the processors and number information of at least one target register, and the target register is a register of the one or more registers whose permissions are to be modified; Determining, according to the permission modification instruction, a target processor corresponding to a port connected to the target register; According to the identity of the target processor, the permission to read and write the target register is allocated to the target processor.
2. The method for allocating read and write permissions as claimed in claim 1, characterized in that: The step of allocating permission for the target processor to read and write the target register according to the identity of the target processor includes: The value of the target register is modified to a value corresponding to the identity of the target processor.
3. The method for allocating read and write permissions as claimed in claim 2, characterized in that: The step of modifying the value of the target register to a value corresponding to the identity of the target processor includes: Determine a main processor; wherein the main processor is a processor with modification authority, and the modification authority is an authority to modify the value of the register; The main processor is used to modify the value of the target register to a value corresponding to the identity of the target processor.
4. The method for allocating read and write permissions according to claim 1, characterized in that: The method further comprises: When the processor accesses the universal module, the identity of the processor is matched with the value of each register, and when the identity of the processor matches the value of the register, the processor is allowed to perform a read and write task on the register; When the identity of the processor does not match the value of the register, the processor is restricted from executing read and write tasks on the register.
5. The method for allocating read and write permissions according to any one of claims 2 to 4, characterized in that: Before modifying the value of the target register to a value corresponding to the identity of the target processor, the method further includes: Determining a modification level of each of the registers according to the business requirements of the chip system; When the modification level of the target register is modification allowed, performing the step of modifying the value of the target register to a value corresponding to the identity of the target processor; When the modification level of the target register is restricted, prompt information for restricting modification of the register is generated, and a prompt is given to the user based on the prompt information.
6. The method for allocating read and write permissions as claimed in claim 5, characterized in that: The method further comprises: In the case where the modification level of the target register is restricted modification, responding to a reset instruction, modifying the value of the register to a reset value, and re-performing the step of defining the modification level of each register according to the business requirements of the chip system; The reset value is related to the version configuration of the chip system, and the version configuration is written by the processor during iterative update.
7. The method for allocating read and write permissions according to any one of claims 1 to 4 or 6, characterized in that: The universal module further includes an access identification component, and the access identification component is used to identify the identity of the processor when the processor accesses the universal module.
8. A device for allocating read and write permissions, characterized in that: The device is applied to a chip system, the chip system includes at least two processors, at least two of the processors are connected to a general module, the general module includes one or more registers, and the device includes: An acquisition module, used for acquiring a permission modification instruction; wherein the permission modification instruction includes an identity identifier of at least one of the processors and number information of at least one target register, and the target register is a register of the one or more registers whose permissions are to be modified; A determination module, configured to determine a target processor corresponding to a port connected to the target register according to the permission modification instruction; The allocation module is used to allocate the permission of reading and writing the target register to the target processor according to the identity of the target processor.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 7 is implemented.
10. A computer program product, comprising a computer program, characterized in that: When the computer program is executed on a computer, the computer is caused to execute the method according to any one of claims 1 to 7.