Manufacturing method for semiconductor structure and semiconductor structure

Abstract

The embodiment of the invention discloses a manufacturing method for a semiconductor structure and the semiconductor structure. The manufacturing method comprises the steps that a buffer layer is deposited on a graphite substrate through a chemical vapor deposition method; a carbide layer is deposited on the buffer layer through a chemical vapor deposition method, the buffer layer is composed of a plurality of transition layers, and each transition layer in the plurality of transition layers comprises components which are the same as the components of the carbide layer. And the multi-layer transition layer is configured to enable at least one part of a thermal expansion coefficient curve of the buffer layer along with temperature to be between a thermal expansion coefficient curve of the graphite matrix along with temperature and a thermal expansion coefficient curve of the carbide layer along with temperature in a deposition temperature range of the buffer layer.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor manufacturing technology, and in particular, to a manufacturing method for a semiconductor structure and a semiconductor structure. Background Art

[0002] Carbide materials, such as silicon carbide (SiC), tantalum carbide (TaC) and boron carbide (B4C), not only have excellent electrical properties of semiconductors, but also possess physical properties such as corrosion resistance, high thermal conductivity, thermal shock resistance and high chemical stability. These properties enable the above carbide materials to work stably in the semiconductor epitaxial growth atmosphere.

[0003] On the one hand, the above-mentioned carbide materials are often manufactured into structural products and directly applied in the semiconductor epitaxial growth process. For example, silicon carbide rings are used as bases for supporting silicon wafers. The specific manufacturing process is to form a carbide layer of a set thickness on a graphite substrate and then remove the graphite substrate to obtain a structural product of carbide of a set thickness, such as a silicon carbide ring. On the other hand, the above-mentioned carbide materials are also often used as coating materials to improve the performance and reliability of semiconductor structures. For example, the base formed by the graphite substrate is easy to oxidize and corrode, and graphite debris is easily generated during the corrosion process, which may have a negative impact on the semiconductor epitaxial growth process. Therefore, the above-mentioned carbide material is usually selected as a coating material to coat the surface of the graphite substrate.

[0004] However, when a carbide layer is formed on a graphite substrate, shear stress is generated at the interface between the two, and residual thermal stress is generated between the graphite substrate and the carbide layer due to the large difference in thermal expansion coefficient between the above-mentioned carbide material and the graphite substrate material. When the above-mentioned shear stress and residual thermal stress are greater than the bonding strength between the two, cracks are likely to occur between the graphite substrate and the carbide layer, and even the carbide layer may fall off the graphite substrate. Summary of the invention

[0005] In view of this, the embodiments of the present disclosure hope to provide a manufacturing method for a semiconductor structure and a semiconductor structure; it is possible to solve the problem of excessive stress at the interface between the graphite matrix and the carbide layer, improve the bonding strength between the graphite matrix and the carbide layer, and reduce the risk of cracking between the graphite matrix and the carbide layer.

[0006] The technical solution of the embodiment of the present disclosure is implemented as follows: In a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising: Depositing a buffer layer on a graphite substrate by a chemical vapor deposition method; and Depositing a carbide layer on the buffer layer by a chemical vapor deposition method, The buffer layer is composed of a plurality of transition layers, each of which includes a component that is the same as that of the carbide layer, and the plurality of transition layers are configured so that within the deposition temperature range of the buffer layer, at least a portion of the temperature-dependent thermal expansion coefficient curve of the buffer layer is between the temperature-dependent thermal expansion coefficient curve of the graphite substrate and the temperature-dependent thermal expansion coefficient curve of the carbide layer.

[0007] In some examples, the buffer layer is deposited at a temperature ranging from 0°C to 1600°C.

[0008] In some examples, the multi-layer transition layers are configured according to the respective proportions of carbon components and other components in the components of each transition layer and the thickness ratio of each transition layer so that within the deposition temperature range of the buffer layer, at least a portion of the thermal expansion coefficient curve of the buffer layer is between the thermal expansion coefficient curve of the graphite matrix and the thermal expansion coefficient curve of the carbide layer, wherein the thickness ratio is the ratio of the thickness of each transition layer to the thickness of the buffer layer.

[0009] In some examples, within the deposition temperature range of the buffer layer, the sum of the differences between the highest temperature and the lowest temperature in the temperature interval corresponding to each continuous portion in the at least one portion is greater than the sum of the differences between the highest temperature and the lowest temperature in the temperature interval corresponding to each continuous portion in other portions; wherein the other portions are portions of the thermal expansion coefficient curve of the buffer layer that are not between the thermal expansion coefficient curve of the graphite matrix and the thermal expansion coefficient curve of the carbide layer within the deposition temperature range of the buffer layer.

[0010] In some examples, the multilayer transition layer is configured such that within the deposition temperature range of the buffer layer, at least a portion of the thermal expansion coefficient curve of the buffer layer corresponds to a temperature-dependent curve of an intermediate value of the thermal expansion coefficient of the graphite substrate and the thermal expansion coefficient of the carbide layer.

[0011] In some examples, the manufacturing method further includes: Determine the thickness ratio of each transition layer according to the first linear relationship and the second linear relationship; The thickness of each transition layer is determined according to the thickness of the buffer layer and the thickness ratio. Among them, the first linear relationship is the relationship between the intermediate value and the temperature, the second linear relationship is the relationship between the thermal expansion coefficient of each transition layer and the temperature, and the thickness ratio is the ratio of the thickness of each transition layer to the thickness of the buffer layer.

[0012] In some examples, the step of depositing a buffer layer on a graphite substrate by a chemical vapor deposition method includes: A plurality of stacked buffer layers are deposited on the graphite substrate by a chemical vapor deposition method, wherein a thermal expansion coefficient curve of the buffer layer closest to the graphite substrate among the stacked plurality of buffer layers is closer to a thermal expansion coefficient curve of the graphite substrate than a thermal expansion coefficient curve of the carbide layer, and a thermal expansion coefficient curve of the buffer layer closest to the carbide layer is closer to a thermal expansion coefficient curve of the carbide layer than a thermal expansion coefficient curve of the graphite substrate.

[0013] In some examples, the stacked multiple buffer layers include a buffer layer structure, and from the graphite substrate to the carbide layer, the buffer layer structure is formed by alternating multiple buffer layers in a manner such that their thermal expansion coefficient curves are closer to the thermal expansion coefficient curve of the graphite substrate and closer to the thermal expansion coefficient curve of the carbide layer.

[0014] In some examples, the CTE curves of the plurality of buffer layers of the buffer layer structure include only two different CTE curves.

[0015] In some examples, from the graphite substrate to the carbide layer, the thermal expansion coefficient curves of the plurality of buffer layers in the buffer layer structure that are alternately closer to the thermal expansion coefficient curve of the graphite substrate than the thermal expansion coefficient curve of the carbide layer and the thermal expansion coefficient curves of the plurality of buffer layers that are closer to the thermal expansion coefficient curve of the carbide layer than the thermal expansion coefficient curve of the graphite substrate both gradually approach the thermal expansion coefficient curve of the carbide layer.

[0016] In some examples, the manufacturing method further includes: removing the graphite substrate from the buffer layer after the carbide layer is deposited.

[0017] In a second aspect, an embodiment of the present disclosure provides a semiconductor structure, the semiconductor structure comprising: Graphite matrix; a buffer layer laminated on the graphite substrate; and a carbide layer stacked on the buffer layer, The buffer layer is composed of multiple transition layers, each of the multiple transition layers includes components that are the same as those of the carbide layer, and within the deposition temperature range of the buffer layer, at least a portion of the temperature-dependent thermal expansion coefficient curve of the buffer layer is between the temperature-dependent thermal expansion coefficient curve of the graphite substrate and the temperature-dependent thermal expansion coefficient curve of the carbide layer.

[0018] In some examples, a curve of the thermal expansion coefficient of the buffer layer corresponds to a curve of an intermediate value of the thermal expansion coefficient of the graphite substrate and the thermal expansion coefficient of the carbide layer as a function of temperature.

[0019] In some examples, the semiconductor structure includes a plurality of the buffer layers stacked on the graphite substrate, wherein a thermal expansion coefficient curve of the buffer layer closest to the graphite substrate among the plurality of buffer layers is closer to a thermal expansion coefficient curve of the graphite substrate than a thermal expansion coefficient curve of the carbide layer, and a thermal expansion coefficient curve of the buffer layer closest to the carbide layer is closer to a thermal expansion coefficient curve of the carbide layer than a thermal expansion coefficient curve of the graphite substrate.

[0020] In some examples, the plurality of buffer layers include a buffer layer structure, and from the graphite substrate to the carbide layer, the buffer layer structure is formed by alternating a plurality of buffer layers in a manner such that a thermal expansion coefficient curve thereof is closer to a thermal expansion coefficient curve of the graphite substrate and a thermal expansion coefficient curve closer to the carbide layer.

[0021] In some examples, from the graphite substrate to the carbide layer, the thermal expansion coefficient curves of the plurality of buffer layers in the buffer layer structure that are alternately closer to the thermal expansion coefficient curve of the graphite substrate than the thermal expansion coefficient curve of the carbide layer and the thermal expansion coefficient curves of the plurality of buffer layers that are closer to the thermal expansion coefficient curve of the carbide layer than the thermal expansion coefficient curve of the graphite substrate both gradually approach the thermal expansion coefficient curve of the carbide layer.

[0022] In some examples, the buffer layer has a thickness in a range of 20 μm to 200 μm.

[0023] In a third aspect, an embodiment of the present disclosure provides a semiconductor structure, the semiconductor structure comprising: multiple buffer layers; and a carbide layer stacked on the buffer layer, Wherein, each buffer layer is composed of a plurality of transition layers, each transition layer in the plurality of transition layers includes a component that is the same as a component of the carbide layer, and within the deposition temperature range of the plurality of buffer layers, at least a portion of the temperature-varying thermal expansion coefficient curves of each of the plurality of buffer layers is close to the temperature-varying thermal expansion coefficient curve of the carbide layer, such that the thermal expansion coefficient curve of the buffer layer closest to the carbide layer among the plurality of buffer layers is closer to the thermal expansion coefficient curve of the carbide layer than the thermal expansion coefficient curve of the buffer layer farthest from the carbide layer among the plurality of buffer layers.

[0024] In some examples, the multiple buffer layers include a buffer layer structure, and from the buffer layer to the carbide layer, the buffer layer structure is formed by alternating multiple buffer layers in a manner such that their thermal expansion coefficient curves are farther away from the carbide layer and closer to the carbide layer.

[0025] In some examples, from the buffer layer to the carbide layer, the thermal expansion coefficient curves of the multiple buffer layers of the buffer layer structure that are alternately farther away from the thermal expansion coefficient curve of the carbide layer and the thermal expansion coefficient curves of the multiple buffer layers that are closer to the thermal expansion coefficient curve of the carbide layer than the thermal expansion coefficient curve of the carbide layer gradually approach the thermal expansion coefficient curve of the carbide layer.

[0026] In a fourth aspect, an embodiment of the present disclosure provides a semiconductor structure, wherein the semiconductor structure is manufactured by the manufacturing method for a semiconductor structure according to the first aspect.

[0027] The disclosed embodiments provide a manufacturing method for a semiconductor structure and a semiconductor structure; a buffer layer consisting of a plurality of transition layers is formed between a graphite substrate and a carbide layer, and each transition layer is configured so that within the deposition temperature range of the buffer layer, at least a portion of the temperature-dependent thermal expansion coefficient curve of the buffer layer is between the temperature-dependent thermal expansion coefficient curve of the graphite substrate and the temperature-dependent thermal expansion coefficient curve of the carbide layer, so as to reduce the thermal stress between the graphite substrate and the carbide layer, improve the bonding strength between the graphite substrate and the carbide layer, and thereby reduce the risk of cracking between the graphite substrate and the carbide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram of stress analysis between graphite matrix and carbide layer; Figure 2 A schematic flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure; Figure 3 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure; Figure 4 Schematic diagram of thermal expansion coefficient curves corresponding to the graphite substrate, carbide layer and buffer layer provided in the embodiment of the present disclosure; Figure 5 A schematic structural diagram of a semiconductor structure when the number of layers of the multi-layer transition layer provided in an embodiment of the present disclosure is 3; Figure 6 A schematic diagram of the relationship between the maximum shear stress of the SiC layer and the number of buffer layers provided in an embodiment of the present disclosure; Figure 7 A schematic diagram showing the relationship between the maximum normal stress of a SiC layer and the number of buffer layers provided in an embodiment of the present disclosure; Figure 8 A schematic diagram of a semiconductor structure in which three buffer layers are deposited on a graphite substrate to form a stacked structure according to an embodiment of the present disclosure; Fig. 9 A schematic diagram of thermal expansion coefficient curves of a graphite substrate, a carbide layer, and three buffer layers provided in an embodiment of the present disclosure; Fig.10 A schematic diagram of another semiconductor structure provided by an embodiment of the present disclosure; Fig.11 A schematic structural diagram of another semiconductor structure provided by an embodiment of the present disclosure; Fig.12 A schematic diagram of a structure of another semiconductor structure provided by an embodiment of the present disclosure; Fig.13 A schematic structural diagram of a semiconductor structure not including a graphite substrate provided in an embodiment of the present disclosure; Fig.14 A schematic structural diagram of another semiconductor structure not including a graphite substrate provided in an embodiment of the present disclosure; Fig.15 A schematic structural diagram of another semiconductor structure that does not include a graphite substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure.

[0030] Unless otherwise defined, the technical terms used in the present disclosure should be understood as the common meanings known to those of ordinary skill in the art to which the present disclosure belongs. The terms "first", "second", etc. in the present disclosure do not indicate any order, but are only used to distinguish, and the terms "upper", "lower", etc. are only used to indicate relative positional relationships.

[0031] It should be noted that, for the sake of clarity, not all features of a specific implementation are described and illustrated in the specification and drawings. Furthermore, in order to avoid unnecessary details that obscure the technical solution focused on by the present disclosure, only the device structures and parts closely related to the technical solution of the present disclosure are described and illustrated in the specification and drawings, while other details that are not closely related to the technical content of the present disclosure and are known to those skilled in the art are omitted.

[0032] like Figure 1As shown, when only the carbide layer 20 is formed on the graphite substrate 10, on the one hand, due to the bonding force between the graphite substrate 10 and the carbide layer 20 and the interface constraints between the two, shear stress ( Figure 1 ). On the other hand, since the thermal expansion coefficient curve of the graphite matrix 10 and the thermal expansion coefficient curve of the carbide layer 20 are not completely matched, when the temperature changes, the graphite matrix 10 will be subjected to compressive stress / tensile stress from the carbide layer 20, and the carbide layer 20 will be subjected to tensile stress / compressive stress from the graphite matrix 10, so residual thermal stress will be generated between the graphite matrix 10 and the carbide layer 20. The existence of the above-mentioned shear stress and residual thermal stress makes it easy for the carbide layer 20 and the graphite matrix 10 to crack, and even worse, the carbide layer 20 will fall off the graphite matrix 10. It should be noted that the thermal expansion coefficient curve of the graphite matrix 10 that changes with temperature is the relationship between the thermal expansion coefficient of the graphite matrix 10 and the temperature; the thermal expansion coefficient curve of the carbide layer 20 that changes with temperature is the relationship between the thermal expansion coefficient of the carbide layer 20 and the temperature.

[0033] In order to improve the bonding strength between the graphite substrate 10 and the carbide layer 20, taking the carbide layer 20 as a SiC layer as an example, in some related technologies, a chemical vapor infiltration (CVI) technology is usually used to form a buffer layer with a gradually increasing SiC content in the surface layer of the graphite substrate 10, and then a SiC layer is formed. The buffer layer helps to improve the bonding strength between the graphite substrate 10 and the SiC layer, reduce the possibility of cracking, and can buffer the residual thermal stress between the graphite substrate 10 and the SiC layer, and reduce the deformation caused by thermal shock. However, due to the insufficient thickness of the buffer layer, the effect of buffering thermal stress is not good. In other related technologies, a buffer layer is formed on the graphite substrate 10 by using atmospheric pressure chemical vapor deposition (APCVD) technology. The buffer layer is composed of a SiC component and a carbon component, wherein the proportion of the SiC component increases linearly, for example, gradually increases from 0% to 100%, and the proportion of the carbon component decreases linearly, for example, gradually decreases from 100% to 0%. However, when the proportion of the carbon component in the buffer layer is high, more pyrolytic carbon layers will be formed in the process of forming the buffer layer. Since the difference between the thermal expansion coefficient curve of the pyrolytic carbon layer that changes with temperature and the thermal expansion coefficient curve of the graphite matrix 10 and the thermal expansion coefficient curve of the SiC layer is large, the stability of the graphite matrix 10 will also change when the temperature changes, thereby affecting the use of the base formed by the graphite matrix 10, and since the proportion of the carbon component in the buffer layer changes linearly, the thermal expansion coefficient curve of the buffer layer cannot achieve a smooth transition between the thermal expansion coefficient curve of the graphite matrix 10 and the thermal expansion coefficient curve of the SiC layer, and then when the temperature changes, residual thermal stress will be generated between the graphite matrix 10 and the SiC layer, causing cracking between the SiC layer and the graphite matrix 10.

[0034] In response to the above technical problems, the inventors of the present disclosure expect to form a buffer layer consisting of multiple transition layers between the graphite substrate 10 and the carbide layer 20, and each transition layer includes components that are the same as those of the carbide layer, and then by controlling the relevant process parameters of each transition layer, the thermal expansion coefficient curve of the buffer layer is not much different from the thermal expansion coefficient curve of the graphite substrate 10 and the thermal expansion coefficient curve of the carbide layer 20, so as to buffer the residual thermal stress between the graphite substrate 10 and the carbide layer 20 and improve the bonding strength between the graphite substrate 10 and the carbide layer 20.

[0035] Based on this, Figure 2 and Figure 3 As shown, the present disclosure provides a method for manufacturing a semiconductor structure 1, the manufacturing method comprising: Step S201, depositing a buffer layer 30 on the graphite substrate 10 by a chemical vapor deposition method; and Step S202: depositing a carbide layer 20 on the buffer layer by a chemical vapor deposition method. The buffer layer 30 is composed of a plurality of transition layers 301, each of which includes components identical to those of the carbide layer, and the plurality of transition layers 301 are configured such that within the deposition temperature range of the buffer layer 30, at least a portion of the temperature-dependent thermal expansion coefficient curve of the buffer layer 30 is between the temperature-dependent thermal expansion coefficient curve of the graphite substrate 10 and the temperature-dependent thermal expansion coefficient curve of the carbide layer 20.

[0036] In some examples, the chemical vapor deposition method may be a normal pressure chemical vapor deposition method or a low pressure chemical vapor deposition (LPCVD) method.

[0037] In some examples, the carbide layer 20 may be a SiC layer, a TaC layer, or a B4C layer, etc., which is not specifically limited in the present disclosure.

[0038] It should be noted that, on the one hand, each of the above-mentioned transition layers 301 includes the same components as the carbide layer 20, which can ensure the chemical compatibility of the buffer layer 30 with the graphite substrate 10 and the carbide layer 20, and help to improve the bonding strength and interface stability between the graphite substrate 10 and the carbide layer 20. On the other hand, each of the above-mentioned transition layers 301 includes the same components as the carbide layer 20, which can ensure that no other impurities are generated during the formation of the buffer layer 30 and the carbide layer 20, and avoid defects in the buffer layer 30 and the carbide layer 20.

[0039] In other examples, the temperature-dependent thermal expansion coefficient curve of the buffer layer 30 is the relationship between the thermal expansion coefficient of the buffer layer 30 and the temperature.

[0040] like Figure 4As shown, within the deposition temperature range of the buffer layer 30, at least a portion of the temperature-dependent thermal expansion coefficient curve A of the buffer layer 30 is between the temperature-dependent thermal expansion coefficient curve B of the graphite substrate 10 and the temperature-dependent thermal expansion coefficient curve C of the carbide layer 20, which means that in at least part of the temperature range within the deposition temperature range of the buffer layer 30, the thermal expansion coefficient of the buffer layer 30 is between the thermal expansion coefficient of the graphite substrate 10 and the thermal expansion coefficient of the carbide layer 20. It can be understood that by configuring the transition layer 301 so that within the deposition temperature range of the buffer layer 30, at least a portion of the thermal expansion coefficient curve A of the buffer layer 30 is between the thermal expansion coefficient curve B of the graphite substrate 10 and the thermal expansion coefficient curve C of the carbide layer 20, the thermal expansion discontinuity from the graphite substrate 10 to the carbide layer 20 caused by the incomplete matching of the thermal expansion coefficient curve of the graphite substrate 10 and the thermal expansion coefficient curve of the carbide layer 20 can be alleviated, so as to reduce the residual thermal stress generated between the graphite substrate 10 and the carbide layer 20 due to temperature changes, and finally improve the bonding strength between the graphite substrate 10 and the carbide layer 20, and avoid cracking between the graphite substrate 10 and the carbide layer 20. It should be noted that in some examples, the deposition temperature range of the buffer layer 30 is 0°C to 1600°C.

[0041] In addition, by configuring the buffer layer 30 to be composed of multiple transition layers 301, in the specific implementation process, the relevant process parameters of each transition layer 301, such as the respective proportions of the carbon component and other components in each transition layer 301, can be adjusted so that within the deposition temperature range of the buffer layer 30, at least a portion of the thermal expansion coefficient curve A of the buffer layer 30 is between the thermal expansion coefficient curve B of the graphite substrate 10 and the thermal expansion coefficient curve C of the carbide layer 20, thereby improving the flexibility of the manufacturing method in the present disclosure.

[0042] for Figure 2 In the technical solution shown, in some possible embodiments, the multi-layer transition layer 301 is configured according to the respective proportions of the carbon component and other components in the above-mentioned components of each layer of the transition layer 301 and the thickness ratio of each layer of the transition layer 301 so that within the deposition temperature range of the buffer layer 30, at least a portion of the thermal expansion coefficient curve of the buffer layer 30 is between the thermal expansion coefficient curve of the graphite matrix 10 and the thermal expansion coefficient curve of the carbide layer 20, wherein the thickness ratio is the ratio of the thickness of each layer of the transition layer 301 to the thickness of the buffer layer 30.

[0043] On the one hand, by adjusting the respective proportions of the carbon component and other components in the above-mentioned components of each transition layer 301, the chemical composition and microstructure of each transition layer 301 can be changed, thereby affecting the thermal expansion coefficient of each transition layer 301, and ultimately affecting the thermal expansion coefficient of the buffer layer 30. In addition, as mentioned earlier, for example, when the carbide layer 20 is a SiC layer, when the carbon component in the buffer layer 30 is too high, a pyrolytic carbon layer will be formed in the process of forming the buffer layer 30, affecting the bonding strength between the graphite substrate 10 and the SiC layer 20. Therefore, in the present disclosure, by adjusting the respective proportions of the carbon component and other components in the above-mentioned components of each transition layer 301 to adjust the thermal expansion coefficient curve of the buffer layer 30, it is also possible to avoid the situation where the carbon component in each transition layer 301 is too high, thereby reducing or even avoiding the formation of a pyrolytic carbon layer.

[0044] On the other hand, the volume proportion of each transition layer 301 in the buffer layer 30 can be controlled by adjusting the thickness or thickness ratio of each transition layer 301. Specifically, a thicker transition layer 301 has a larger volume proportion in the buffer layer 30, which has a greater impact on the overall thermal expansion characteristics of the buffer layer 30.

[0045] for Figure 2 According to the technical solution shown, in some possible embodiments, within the deposition temperature range of the buffer layer 30, the sum of the differences between the highest temperature and the lowest temperature in the temperature interval corresponding to each continuous part in the above-mentioned at least one part is greater than the sum of the differences between the highest temperature and the lowest temperature in the temperature interval corresponding to each continuous part in other parts; wherein the above-mentioned other parts are parts of the thermal expansion coefficient curve of the buffer layer 30 within the deposition temperature range of the buffer layer 30, which are not between the thermal expansion coefficient curve of the graphite matrix 10 and the thermal expansion coefficient curve of the carbide layer 20.

[0046] In this case, within the deposition temperature range of the buffer layer 30, the thermal expansion coefficient curve A of the buffer layer matches the thermal expansion coefficient curve B of the graphite substrate 10 and the thermal expansion coefficient curve C of the carbide layer 20 within a wider temperature range, ensuring that the thermal expansion behavior of the buffer layer 30 is largely consistent with the thermal expansion behavior of the graphite substrate 10 and the carbide layer 20, thereby helping to reduce residual thermal stress and improve the thermal stability of the semiconductor structure 1.

[0047] for Figure 2 In the technical solution shown, in some possible embodiments, the multilayer transition layer 301 is configured so that within the deposition temperature range of the buffer layer 30, at least a portion of the thermal expansion coefficient curve of the buffer layer 30 corresponds to a curve of the change with temperature of the intermediate value of the thermal expansion coefficient of the graphite substrate 10 and the thermal expansion coefficient of the carbide layer 20.

[0048] It can be understood that, within the deposition temperature range of the buffer layer 30, when at least a portion of the thermal expansion coefficient curve of the buffer layer 30 matches the temperature-varying curve of the intermediate value of the thermal expansion coefficient of the graphite substrate 10 and the thermal expansion coefficient of the carbide layer 20, the difference between the thermal expansion coefficient curve of the buffer layer 30 and the thermal expansion coefficient curve of the graphite substrate 10 and the thermal expansion coefficient curve of the carbide layer 20 can be reduced, so that the thermal expansion behavior of the buffer layer 30 can better adapt to the thermal expansion behavior of the graphite substrate 10 and the carbide layer 20, thereby reducing the residual thermal stress between the graphite substrate 10 and the carbide layer 20 caused by temperature changes.

[0049] For the above-mentioned embodiments, in some examples, the manufacturing method further includes: Determine the thickness ratio of each transition layer 301 according to the first linear relationship and the second linear relationship; According to the thickness and thickness ratio of the buffer layer 30, the thickness of each transition layer 301 is determined. The first linear relationship is the relationship between the intermediate value and the temperature, the second linear relationship is the relationship between the thermal expansion coefficient of each transition layer 301 and the temperature, and the thickness ratio is the ratio of the thickness of each transition layer 301 to the thickness of the buffer layer 30 .

[0050] In some examples, the second linear relationship corresponding to each transition layer 301 is obtained by separately preparing and measuring each transition layer 301. In the specific implementation process, the thermal expansion coefficients of the graphite substrate 10, the carbide layer 20 and each transition layer 301 at different temperatures within the deposition temperature range of the buffer layer 30 can be prepared and measured in advance by experiments, and then the above-mentioned first linear relationship and the second linear relationship of each transition layer 301 can be obtained by fitting. For the second linear relationship of each transition layer 301, the corresponding transition layer materials can be prepared and the thermal expansion coefficients can be measured at different temperatures when the proportions of the carbon component and other components of each transition layer 301 are determined, and then the above-mentioned second linear relationship can be obtained by fitting.

[0051] In some examples, both the first linear relationship and the second linear relationship are fitted according to the number of layers of the multi-layer transition layer 301 .

[0052] Specifically, in the present disclosure, the first linear relationship can be expressed as a multi-order power series expansion of the intermediate value of the thermal expansion coefficient of the graphite substrate 10 and the thermal expansion coefficient of the carbide layer 20 and the temperature, and the specific form is shown in the following formula (1): (1) in, N 0 represents an intermediate value between the thermal expansion coefficient of the graphite substrate 10 and the thermal expansion coefficient of the carbide layer 20; TIndicates temperature; n = m -1, m represents the number of layers of the multi-layer transition layer 301, a , b , c ,……, z Represents the coefficient.

[0053] The second linear relationship mentioned above can be expressed as a multi-order power series expansion of the thermal expansion coefficient of each transition layer 301 and the temperature, and the specific form is shown in the following formula (2): (2) in, N i represents the thermal expansion coefficient of each transition layer 301; T Indicates temperature; n = m -1, m represents the number of layers of the multi-layer transition layer 301; a i , b i , c i ,……, z i represents the coefficients of each item; i =1,2,…, m .

[0054] Specific as Figure 5 For example, the number of layers of the multi-layer transition layer 301 shown is 3, and the first linear relationship is expressed as: From the graphite substrate 10 to the carbide layer 20, the second linear relationship of the transition layer 301-1 close to the graphite substrate 10 is expressed as: The second linear relationship of the transition layer 301-3 near the carbide layer 20 is expressed as: The second linear relationship of the transition layer 301-2 located between the transition layer 301-1 and the transition layer 301-3 is expressed as: .

[0055] In some examples, determining the thickness ratio of each transition layer 301 according to the first linear relationship and the second linear relationship includes: According to the above-mentioned first linear relationship and second linear relationship, and based on the above-mentioned intermediate value as the weighted average value of the thermal expansion coefficient of each transition layer 301, the thickness ratio of each transition layer 301 is determined; wherein the weight corresponding to the thermal expansion coefficient of each transition layer 301 is the thickness ratio of each transition layer 301.

[0056] Still taking the case where the number of layers of the multi-layer transition layer 301 is 3 as an example, after respectively obtaining the first linear relationship and the second linear relationship of each transition layer 301, the weighted average value of the thermal expansion coefficient of each transition layer 301 is taken based on the intermediate value, and the weight corresponding to the thermal expansion coefficient of each transition layer 301 is the thickness ratio of each transition layer 301, and the following is obtained:

[0057] Right now: (3) in, δ 1 represents the thickness ratio of the transition layer 301 - 1 ; δ 2 represents the thickness ratio of the transition layer 301 - 2; δ 3 represents the thickness ratio of the transition layer 301 - 3 .

[0058] Understandably, only when the coefficients a , b , c Corresponding to δ 1 a 1+ δ 2 a 2+ δ 3 a 3. δ 1 b 1+ δ 2 b 2+ δ 3 b 3. δ 1 c 1+ δ 2 c 2+ δ 3 c The above formula (3) is valid only when 3 are equal, that is: (4) When the above-mentioned first linear relationship and the second linear relationship of each transition layer 301 are obtained by fitting, the thickness ratio of each transition layer 301 can be obtained.

[0059] by Figure 5 Each transition layer 301 in the embodiment is composed of a carbon component and a silicon component. For example, the first linear relationship obtained by fitting is: ; When the proportion of carbon components in the transition layer 301-1 is 11.6%, the second linear relationship of the transition layer 301-1 is: ; When the proportion of carbon components in the transition layer 301-2 is 33.4%, the second linear relationship of the transition layer 301-2 is: When the proportion of silicon component in the transition layer 301-3 is 1 vol%, the second linear relationship of the transition layer 301-3 is: .

[0060] According to the above formula (4), we can get: (5) Based on the above formula (5), the thickness ratios of the transition layers 301 are: δ 1=0.516, δ 2=0.3475, δ 3=0.255.

[0061] It should be noted that when the calculated thickness ratio of each transition layer 301 does not meet the requirements, for example, when the thickness ratio of at least a portion of the transition layers 301 is negative or greater than or equal to 1, it indicates that the first linear relationship and / or the second linear relationship of each transition layer 301 need to be refitted. Figure 5 Each transition layer 301 in the embodiment is composed of a carbon component and a silicon component. For example, the first linear relationship obtained by fitting is: ; When the proportion of carbon components in the transition layer 301-1 is 11.6%, the second linear relationship of the transition layer 301-1 is: ; When the proportion of carbon components in the transition layer 301-2 is 33.4%, the second linear relationship of the transition layer 301-2 is: When the proportion of silicon component in the transition layer 301-3 is 1 vol%, the second linear relationship of the transition layer 301-3 is: When , the thickness ratios of the transition layers 301 are obtained as follows: δ 1=0.363, δ 2=1.016, δ 3=-0.16, so in the specific implementation process, it is necessary to refit the above-mentioned first linear relationship and / or the second linear relationship of each transition layer 301.

[0062] Further, the thickness of each transition layer 301 can be obtained when the thickness of the buffer layer 30 is known. It should be noted that, in some examples, the thickness of the buffer layer 30 is obtained by finite element simulation. And when the obtained thickness of the buffer layer 30 makes the stress between the buffer layer 30 and the carbide layer 20, between the buffer layer 30 and the graphite matrix 10, inside the carbide layer 20 and inside the graphite matrix 10 all minimized, the thickness of the buffer layer 30 can be considered as an optional thickness value.

[0063] It can be understood that, when the above-mentioned first linear relationship and the second linear relationship are obtained, the thickness ratio of each transition layer 301 is obtained by using the above-mentioned intermediate value as the weighted average value of the thermal expansion coefficient of each transition layer 301, and the weight corresponding to the thermal expansion coefficient of each transition layer 301 is the thickness ratio of each transition layer 301, so that the thermal expansion behavior of the buffer layer 30 can be more accurately controlled, so that the buffer layer 30 can better adapt to the thermal expansion behavior of the graphite matrix 10 and the carbide layer 20, so as to improve the bonding strength between the graphite matrix 10 and the carbide layer 20 and the stability of the interface.

[0064] In some examples, the number of layers of the multi-layer transition layer can be determined according to actual conditions. For example, the number of layers of the multi-layer transition layer can be set in the range of 2 to 20 layers, and the present disclosure does not make specific limitations on this.

[0065] It is understandable that the design of the multi-layer transition layer 301 can reduce the tensile stress or compressive stress on each transition layer 301, thereby improving the stability of the overall semiconductor structure 1. In addition, the multi-layer transition layer 301 can provide more internal interfaces, which help release thermal stress caused by temperature changes.

[0066] for Figure 2 In some possible implementations of the technical solution shown, a buffer layer 30 is formed by depositing on a graphite substrate 10 by a chemical vapor deposition method, including: A plurality of stacked buffer layers 30 are deposited on a graphite substrate 10 by a chemical vapor deposition method, wherein a thermal expansion coefficient curve of the buffer layer 30 closest to the graphite substrate 10 among the stacked plurality of buffer layers 30 is closer to the thermal expansion coefficient curve of the graphite substrate 10 than to the thermal expansion coefficient curve of the carbide layer 20, and a thermal expansion coefficient curve of the buffer layer 30 closest to the carbide layer 20 is closer to the thermal expansion coefficient curve of the carbide layer 20 than to the thermal expansion coefficient curve of the graphite substrate 10.

[0067] In the present disclosure, by forming a plurality of buffer layers 30 between the graphite substrate 10 and the carbide layer 20, the thermal expansion coefficient curve of the graphite substrate 10 can be smoothly transitioned to the thermal expansion curve of the carbide layer 20, which is conducive to alleviating the mismatch of the thermal expansion coefficients between the graphite substrate 10 and the carbide layer 20, so as to effectively reduce the stress inside the carbide layer 20. Figure 6 and Figure 7 , which respectively show the relationship between the maximum shear stress and the maximum normal stress and the number of buffer layers 30 when the carbide layer 20 is a SiC layer. Figure 6 and Figure 7It can be seen that the maximum shear stress and the maximum normal stress of the SiC layer 20 decrease as the number of buffer layers 30 increases, indicating that increasing the number of buffer layers 30 can effectively reduce the stress inside the SiC layer 20 and prevent microcracks in the SiC layer 20 .

[0068] See also Figure 8 and Fig. 9 For example, a buffer layer 30-1, a buffer layer 30-2 and a buffer layer 30-3 are deposited on a graphite substrate 10 to form a stacked buffer layer. Fig. 9 The double-dotted line in represents the thermal expansion coefficient curve A-1 of the buffer layer 30-1, the dotted line represents the thermal expansion coefficient curve A-2 of the buffer layer 30-2, and the dotted line represents the thermal expansion coefficient curve A-3 of the buffer layer 30-3. In the present disclosure, the thermal expansion coefficient curve of the buffer layer 30-1 is closer to the thermal expansion coefficient curve of the graphite substrate 10 than the thermal expansion coefficient curve of the carbide layer 20, which can reduce the residual thermal stress between the buffer layer 30-1 and the graphite substrate 10, thereby improving the bonding strength between the buffer layer 30-1 and the graphite substrate 10. The thermal expansion coefficient curve of the buffer layer 30-3 is closer to the thermal expansion coefficient curve of the carbide layer 20 than the thermal expansion coefficient curve of the graphite substrate 10, which can reduce the residual thermal stress between the buffer layer 30-3 and the carbide layer 20, thereby improving the bonding strength between the buffer layer 30-3 and the carbide layer 20, and finally improving the bonding strength between the graphite substrate 10 and the carbide layer 20.

[0069] For the above-mentioned embodiments, in some examples, the stacked multiple buffer layers 30 include a buffer layer structure, and from the graphite matrix 10 to the carbide layer 20, the buffer layer structure is formed alternately by the multiple buffer layers 30 in such a manner that their thermal expansion coefficient curves are closer to the thermal expansion coefficient curve of the graphite matrix 10 and closer to the thermal expansion coefficient curve of the carbide layer 20.

[0070] by Fig.10 Taking the semiconductor structure 1 shown as an example, ten stacked buffer layers 30 are deposited between the graphite substrate 10 and the carbide layer 20. The ten buffer layers 30 include a buffer layer structure 40 formed by alternating buffer layers 30-1, 30-2, and 30-3. Fig. 9It can be seen that the thermal expansion coefficient curves of the buffer layer 30-1, the buffer layer 30-2, and the buffer layer 30-3 are gradually closer to the thermal expansion coefficient curve of the carbide layer 20 than the thermal expansion coefficient curve of the graphite substrate 10. Therefore, from the graphite substrate 10 to the carbide layer 20, the buffer layer structure 40 is formed alternately in a manner that the thermal expansion coefficient curves of the buffer layer 30-1, the buffer layer 30-2, and the buffer layer 30-3 are closer to the thermal expansion coefficient curve of the graphite substrate 10 and closer to the thermal expansion coefficient curve of the carbide layer 20. That is, from the graphite substrate 10 to the carbide layer 20, in the buffer layer structure 40, the buffer layer 30-1 whose thermal expansion coefficient curve is closer to the thermal expansion coefficient curve of the graphite substrate 10, the buffer layer 30-2, and the buffer layer 30-3 whose thermal expansion coefficient curve is closer to the thermal expansion coefficient curve of the carbide 20 are formed alternately in the order. In this case, it helps to improve the elastic modulus of the buffer layer structure 40 and reduce the risk of cracking between the graphite substrate 10 and the carbide layer 20 .

[0071] Optionally, the thermal expansion coefficient curves of the plurality of buffer layers 30 of the buffer layer structure 40 include only two different thermal expansion coefficient curves. Fig.11 As shown, the buffer layer structure 40 is formed alternately of a buffer layer 30 - 1 and a buffer layer 30 - 2 having different thermal expansion coefficient curves.

[0072] Optionally, from the graphite matrix 10 to the carbide layer 20, the thermal expansion coefficient curves of the multiple buffer layers 30 of the buffer layer structure 40 that are closer to the thermal expansion coefficient curve of the graphite matrix 10 than the thermal expansion coefficient curve of the carbide layer 20 in alternation and the thermal expansion coefficient curves of the multiple buffer layers 30 that are closer to the thermal expansion coefficient curve of the carbide layer 20 than the thermal expansion coefficient curve of the graphite matrix 10 both gradually approach the thermal expansion coefficient curve of the carbide layer 20.

[0073] by Fig.12Taking the semiconductor structure 1 shown as an example, the thermal expansion coefficient curves corresponding to the buffer layer 30-1, the buffer layer 30-2, the buffer layer 30-3, the buffer layer 30-4, the buffer layer 30-5 and the buffer layer 30-6 are gradually approaching the thermal expansion coefficient curve of the carbide layer 20 compared with the thermal expansion coefficient curve of the graphite substrate 10. From the graphite substrate 10 to the carbide layer 20, first, the buffer layer 30-1 and the buffer layer 30-2 are formed by stacking and depositing in sequence, and then a buffer layer structure 40 is deposited on the buffer layer 30-2, which is alternately formed by the buffer layer 30-2, the buffer layer 30-3, the buffer layer 30-4, the buffer layer 30-5 and the buffer layer 30-6, and the buffer layer 30-2, the buffer layer 30-3, the buffer layer 30-4, the buffer layer 30-5 and the buffer layer 30-6 in the buffer layer structure 40 are alternately formed in the following manner: after the buffer layer 30-1 and the buffer layer 30-2 are formed based on stacking deposition, the buffer layer 30-3 in the buffer layer structure 40 is formed on the buffer layer 30-2, wherein the buffer layer 30-3 is a buffer layer among the multiple buffer layers 30 of the buffer layer structure 40, and the thermal expansion coefficient curve is closer to the thermal expansion coefficient of the carbide layer 20 than the thermal expansion coefficient curve of the graphite substrate 10. Next, a buffer layer 30-2 in a buffer layer structure 40 is formed on the buffer layer 30-3, wherein the buffer layer 30-2 is a buffer layer whose thermal expansion coefficient curve among the multiple buffer layers 30 in the buffer layer structure 40 is closer to the thermal expansion coefficient curve of the graphite substrate 10 than the thermal expansion coefficient curve of the carbide layer 20. Then, a buffer layer 30-4 is formed on the buffer layer 30-2 in the buffer layer structure 40. It can be understood that the buffer layer 30-4 is a buffer layer whose thermal expansion coefficient curve among the multiple buffer layers 30 in the buffer layer structure 40 is closer to the thermal expansion coefficient curve of the graphite substrate 10 than the thermal expansion coefficient curve of the graphite substrate 10, and so on. Fig.12 The buffer layer structure 40 is obtained in the manner shown. The thermal expansion coefficient curves of the multiple buffer layers 30 formed in this case can make the thermal expansion coefficient curve of the graphite matrix 10 gradually and smoothly transition to the thermal expansion coefficient curve of the carbide layer 20, thereby better adapting to the thermal expansion behavior of the graphite matrix 10 and the carbide layer 20, and reducing the residual thermal stress caused by temperature changes.

[0074] for Figure 2 In the technical solution shown, in some possible implementations, the manufacturing method further includes: after the carbide layer 20 is deposited and formed, removing the graphite substrate 10 from the buffer layer 30 .

[0075] It is understandable that when the buffer layer 30 is deposited on the graphite substrate 10 and the carbide layer 20 of a set thickness is stacked on the buffer layer 30, if a structural product composed of carbide material is manufactured, it can be achieved by removing the graphite substrate 10. The specific method of removing the graphite substrate 10 is not specifically limited in the present disclosure.

[0076] Based on the same inventive concept as the above technical solution, the present disclosure further provides a semiconductor structure 1, which includes: Graphite substrate 10; a buffer layer 30 laminated on the graphite substrate 10; and The carbide layer 20 stacked on the buffer layer 30, The buffer layer 30 is composed of a plurality of transition layers 301, each of which includes components that are the same as those of the carbide layer 20, and within the deposition temperature range of the buffer layer 30, at least a portion of the temperature-dependent thermal expansion coefficient curve of the buffer layer 30 is between the temperature-dependent thermal expansion coefficient curve of the graphite matrix 10 and the temperature-dependent thermal expansion coefficient curve of the carbide layer 20.

[0077] In some possible implementations, the thermal expansion coefficient curve of the buffer layer 30 corresponds to a curve of an intermediate value of the thermal expansion coefficient of the graphite substrate 10 and the thermal expansion coefficient of the carbide layer 20 as a function of temperature.

[0078] In some possible embodiments, the semiconductor structure 1 includes a plurality of buffer layers 30 stacked on a graphite substrate 1, wherein a thermal expansion coefficient curve of the buffer layer 30 closest to the graphite substrate 10 among the plurality of buffer layers 30 is closer to the thermal expansion coefficient curve of the graphite substrate 10 than to the thermal expansion coefficient curve of the carbide layer 20, and a thermal expansion coefficient curve of the buffer layer 30 closest to the carbide layer 20 is closer to the thermal expansion coefficient curve of the carbide layer 20 than to the thermal expansion coefficient curve of the graphite substrate 10.

[0079] In some possible embodiments, the plurality of buffer layers 30 include a buffer layer structure 40, and from the graphite substrate 10 to the carbide layer 20, the buffer layer structure is formed alternately by the plurality of buffer layers 30 in such a manner that their thermal expansion coefficient curves are closer to the thermal expansion coefficient curve of the graphite substrate 10 and closer to the thermal expansion coefficient curve of the carbide layer 20.

[0080] In some examples, from the graphite substrate 10 to the carbide layer 20, the thermal expansion coefficient curves of the plurality of buffer layers 30 of the buffer layer structure 40 that are closer to the thermal expansion coefficient curve of the graphite substrate 10 in alternation and the thermal expansion coefficient curves of the plurality of buffer layers 30 that are closer to the thermal expansion coefficient curve of the carbide layer 20 than the thermal expansion coefficient curve of the graphite substrate 10 both gradually approach the thermal expansion coefficient curve of the carbide layer 20.

[0081] In some possible implementations, the buffer layer 30 has a thickness ranging from 20 μm to 200 μm.

[0082] It is understandable that after the semiconductor structure 1 is manufactured according to the above technical solution, the semiconductor structure 1A is obtained by removing the graphite substrate 10. Fig.13 As shown, the semiconductor structure 1A includes: a plurality of buffer layers 30; and The carbide layer 20 stacked on the buffer layer 30, Wherein, each buffer layer 30 is composed of a plurality of transition layers 301, each transition layer 301 in the plurality of transition layers 301 includes components that are the same as components of the carbide layer 20, and within the deposition temperature range of the plurality of buffer layers 30, at least a portion of the temperature-varying thermal expansion coefficient curves of the plurality of buffer layers 30 are closer to the temperature-varying thermal expansion coefficient curve of the carbide layer 20 than the temperature-varying thermal expansion coefficient curve of the buffer layer 30 among the plurality of buffer layers 30, so that the thermal expansion coefficient curve of the buffer layer 30 closest to the carbide layer 20 among the plurality of buffer layers 30 is closer to the thermal expansion coefficient curve of the carbide layer 20 than the thermal expansion coefficient curve of the buffer layer 30 farthest from the carbide layer 20 among the plurality of buffer layers 30.

[0083] In some examples, such as Fig.14 As shown, the plurality of buffer layers 30 include a buffer layer structure 40 , and the buffer layer structure 40 is formed by alternating the plurality of buffer layers 30 in a manner such that the thermal expansion coefficient curves thereof are farther from the thermal expansion coefficient curve of the carbide layer 20 and closer to the thermal expansion coefficient curve of the carbide layer 20 .

[0084] In some examples, such as Fig.15 As shown, from the buffer layer 30 to the carbide layer 20, the thermal expansion coefficient curves of the multiple buffer layers 30 of the buffer layer structure 40 that are farther away from the thermal expansion coefficient curve of the carbide layer 20 in alternation and the thermal expansion coefficient curves of the multiple buffer layers 30 that are closer to the thermal expansion coefficient curve of the carbide layer 20 compared to the thermal expansion coefficient curve of the carbide layer 20 gradually approach the thermal expansion coefficient curve of the carbide layer 20.

[0085] Finally, the present disclosure also provides a semiconductor structure, which is manufactured by the manufacturing method for a semiconductor structure according to the aforementioned technical solution.

[0086] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0087] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The manufacturing method comprises: Depositing a buffer layer on a graphite substrate by a chemical vapor deposition method; and Depositing a carbide layer on the buffer layer by a chemical vapor deposition method, The buffer layer is composed of a plurality of transition layers, each of which includes a component that is the same as that of the carbide layer, and the plurality of transition layers are configured so that within the deposition temperature range of the buffer layer, at least a portion of the temperature-dependent thermal expansion coefficient curve of the buffer layer is between the temperature-dependent thermal expansion coefficient curve of the graphite substrate and the temperature-dependent thermal expansion coefficient curve of the carbide layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The deposition temperature of the buffer layer ranges from 0°C to 1600°C.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The multi-layer transition layers are configured according to the respective proportions of the carbon component and other components in the components of each transition layer and the thickness ratio of each transition layer so that within the deposition temperature range of the buffer layer, at least a portion of the thermal expansion coefficient curve of the buffer layer is between the thermal expansion coefficient curve of the graphite matrix and the thermal expansion coefficient curve of the carbide layer, wherein the thickness ratio is the ratio of the thickness of each transition layer to the thickness of the buffer layer.

4. The method for manufacturing a semiconductor structure according to any one of claims 1 to 3, characterized in that: Within the deposition temperature range of the buffer layer, the sum of the differences between the highest temperature and the lowest temperature in the temperature interval corresponding to each continuous part in the at least one part is greater than the sum of the differences between the highest temperature and the lowest temperature in the temperature interval corresponding to each continuous part in other parts; wherein the other parts are parts of the thermal expansion coefficient curve of the buffer layer that are not between the thermal expansion coefficient curve of the graphite matrix and the thermal expansion coefficient curve of the carbide layer within the deposition temperature range of the buffer layer.

5. The method for manufacturing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The multi-layer transition layer is configured such that within the deposition temperature range of the buffer layer, the at least a portion of the thermal expansion coefficient curve of the buffer layer corresponds to a temperature-dependent curve of an intermediate value of the thermal expansion coefficient of the graphite substrate and the thermal expansion coefficient of the carbide layer.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: The manufacturing method further comprises: Determine the thickness ratio of each transition layer according to the first linear relationship and the second linear relationship; The thickness of each transition layer is determined according to the thickness of the buffer layer and the thickness ratio. Among them, the first linear relationship is the relationship between the intermediate value and the temperature, the second linear relationship is the relationship between the thermal expansion coefficient of each transition layer and the temperature, and the thickness ratio is the ratio of the thickness of each transition layer to the thickness of the buffer layer.

7. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The method of depositing a buffer layer on a graphite substrate by a chemical vapor deposition method comprises: A plurality of stacked buffer layers are deposited on the graphite substrate by a chemical vapor deposition method, wherein a thermal expansion coefficient curve of the buffer layer closest to the graphite substrate among the stacked plurality of buffer layers is closer to a thermal expansion coefficient curve of the graphite substrate than a thermal expansion coefficient curve of the carbide layer, and a thermal expansion coefficient curve of the buffer layer closest to the carbide layer is closer to a thermal expansion coefficient curve of the carbide layer than a thermal expansion coefficient curve of the graphite substrate.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: The stacked multiple buffer layers include a buffer layer structure, and from the graphite substrate to the carbide layer, the buffer layer structure is formed alternately by multiple buffer layers in a manner in which their thermal expansion coefficient curves are closer to the thermal expansion coefficient curve of the graphite substrate and closer to the thermal expansion coefficient curve of the carbide layer.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: The thermal expansion coefficient curves of the plurality of buffer layers of the buffer layer structure include only two different thermal expansion coefficient curves.

10. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: From the graphite matrix to the carbide layer, the thermal expansion coefficient curves of the multiple buffer layers in the buffer layer structure that are closer to the thermal expansion coefficient curve of the graphite matrix than the thermal expansion coefficient curve of the carbide layer in alternation and the thermal expansion coefficient curves of the multiple buffer layers that are closer to the thermal expansion coefficient curve of the carbide layer than the thermal expansion coefficient curve of the graphite matrix both gradually approach the thermal expansion coefficient curve of the carbide layer.

11. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The manufacturing method further comprises: after the carbide layer is deposited and formed, removing the graphite substrate from the buffer layer.

12. A semiconductor structure, characterized in that: The semiconductor structure comprises: Graphite matrix; a buffer layer laminated on the graphite substrate; and a carbide layer stacked on the buffer layer, The buffer layer is composed of multiple transition layers, each of the multiple transition layers includes components that are the same as those of the carbide layer, and within the deposition temperature range of the buffer layer, at least a portion of the temperature-dependent thermal expansion coefficient curve of the buffer layer is between the temperature-dependent thermal expansion coefficient curve of the graphite substrate and the temperature-dependent thermal expansion coefficient curve of the carbide layer.

13. The semiconductor structure according to claim 12, characterized in that: The thermal expansion coefficient curve of the buffer layer corresponds to a curve of an intermediate value of the thermal expansion coefficient of the graphite substrate and the thermal expansion coefficient of the carbide layer as a function of temperature.

14. The semiconductor structure according to claim 12 or 13, characterized in that: The semiconductor structure includes a plurality of buffer layers stacked on the graphite substrate, wherein a thermal expansion coefficient curve of the buffer layer closest to the graphite substrate among the plurality of buffer layers is closer to a thermal expansion coefficient curve of the graphite substrate than a thermal expansion coefficient curve of the carbide layer, and a thermal expansion coefficient curve of the buffer layer closest to the carbide layer is closer to a thermal expansion coefficient curve of the carbide layer than a thermal expansion coefficient curve of the graphite substrate.

15. The semiconductor structure according to claim 14, characterized in that: The plurality of buffer layers include a buffer layer structure, and the buffer layer structure is formed alternately of a plurality of buffer layers in such a manner that a thermal expansion coefficient curve thereof is closer to a thermal expansion coefficient curve of the graphite substrate and a thermal expansion coefficient curve closer to the carbide layer from the graphite substrate to the carbide layer.

16. The semiconductor structure according to claim 15, characterized in that From the graphite matrix to the carbide layer, the thermal expansion coefficient curves of the multiple buffer layers in the buffer layer structure that are closer to the thermal expansion coefficient curve of the graphite matrix than the thermal expansion coefficient curve of the carbide layer in alternation and the thermal expansion coefficient curves of the multiple buffer layers that are closer to the thermal expansion coefficient curve of the carbide layer than the thermal expansion coefficient curve of the graphite matrix both gradually approach the thermal expansion coefficient curve of the carbide layer.

17. The semiconductor structure according to claim 12, characterized in that: The thickness of the buffer layer is in the range of 20 μm to 200 μm.

18. A semiconductor structure, characterized in that: The semiconductor structure comprises: multiple buffer layers; and a carbide layer stacked on the buffer layer, Wherein, each buffer layer is composed of a plurality of transition layers, each transition layer in the plurality of transition layers includes a component that is the same as a component of the carbide layer, and within the deposition temperature range of the plurality of buffer layers, at least a portion of the temperature-varying thermal expansion coefficient curves of each of the plurality of buffer layers is close to the temperature-varying thermal expansion coefficient curve of the carbide layer, such that the thermal expansion coefficient curve of the buffer layer closest to the carbide layer among the plurality of buffer layers is closer to the thermal expansion coefficient curve of the carbide layer than the thermal expansion coefficient curve of the buffer layer farthest from the carbide layer among the plurality of buffer layers.

19. The semiconductor structure according to claim 18, characterized in that The plurality of buffer layers include a buffer layer structure, and the buffer layer structure is formed by alternating a plurality of buffer layers with a thermal expansion coefficient curve farther from the carbide layer and a thermal expansion coefficient curve closer to the carbide layer from the buffer layer to the carbide layer.

20. The semiconductor structure according to claim 19, characterized in that From the buffer layer to the carbide layer, the thermal expansion coefficient curves of the multiple buffer layers in the buffer layer structure that are alternately farther away from the thermal expansion coefficient curve of the carbide layer and the thermal expansion coefficient curves of the multiple buffer layers that are closer to the thermal expansion coefficient curve of the carbide layer than the thermal expansion coefficient curve of the carbide layer gradually approach the thermal expansion coefficient curve of the carbide layer.

21. A semiconductor structure, characterized in that: The semiconductor structure is obtained by manufacturing the semiconductor structure according to any one of claims 1 to 11.

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