Gallium arsenide system-level fan-out packaging method and structure

Abstract

The present application provides a gallium arsenide system-level fan-out packaging method and structure thereof, and relates to the field of semiconductor packaging technology. The packaging method includes providing a wafer with a first encapsulation body. The wafer includes a plurality of chips; the chips use a gallium arsenide substrate, and the front of the chips has a pad; the first encapsulation body covers the back and side of the chip. A first photoresist with a first opening is formed on the front of the wafer; the first opening is used to expose the pad. A redistribution layer electrically connected to the pad is formed on the first photoresist. A conductive block connected to the redistribution layer is formed on the redistribution layer. A second encapsulation body covering the conductive block and the redistribution layer is formed. The second encapsulation body is located on the side of the first photoresist away from the first encapsulation body. A solder ball electrically connected to the conductive block is formed. The first encapsulation body and the second encapsulation body are used to encapsulate the reconstructed wafer on all sides, thereby improving the structural reliability and solving the delamination problem of the substrate and the redistribution layer in the reliability test.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a gallium arsenide system-level fan-out packaging method and structure thereof. Background Art

[0002] Fan-out wafer-level packaging technology uses high-density wiring manufacturing processes to form a chip packaging structure with lower power loss and stronger functionality. In the wafer-level packaging process that uses gallium arsenide materials as chip substrates, the front side of the substrate is in direct contact with the metal wiring layer, resulting in poor bonding between gallium arsenide materials and metal materials. When conducting reliability tests on the packaging structure, such as high-voltage accelerated aging tests, water vapor can easily intrude from the edge of the metal wiring layer on the front side of the substrate, causing delamination of the substrate and the metal wiring layer, reducing the reliability of the packaging structure. Summary of the invention

[0003] The objectives of the present invention include, for example, providing a gallium arsenide system-level fan-out packaging method and structure thereof, which can solve the delamination problem of the substrate and the metal wiring layer and improve the reliability of the packaging structure.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] In a first aspect, the present invention provides a gallium arsenide system-level fan-out packaging method, comprising:

[0006] A wafer with a first encapsulation body is provided; wherein the wafer includes a plurality of chips; the chips use a gallium arsenide substrate, and the front side of the chips has a pad; the first encapsulation body covers the back side and side of the chips;

[0007] Forming a first photoresist having a first opening on the front side of the wafer; the first opening is used to expose the pad;

[0008] forming a redistribution layer electrically connected to the pad on the first photoresist;

[0009] forming a conductive block connected to the redistribution layer on the redistribution layer;

[0010] Forming a second encapsulation body encapsulating the conductive block and the redistribution layer; wherein the second encapsulation body is located on a side of the first photoresist away from the first encapsulation body;

[0011] A solder ball is formed to be electrically connected to the conductive block.

[0012] In an optional embodiment, the step of providing a wafer having a first encapsulation body comprises:

[0013] Providing a carrier board with a thermal release film;

[0014] Mounting a plurality of chips with different functions on a side of the thermal release film away from the carrier; wherein the pads of the chips face the carrier;

[0015] Forming a first encapsulation body covering the chip on the carrier; the first encapsulation body covers the back and side surfaces of the chip;

[0016] Grinding the first encapsulation body from a side of the first encapsulation body away from the pad; the grinding thickness is a preset thickness;

[0017] The carrier plate and the thermal release film are removed to obtain the wafer.

[0018] In an optional embodiment, the step of forming a redistribution layer electrically connected to the pad on the first photoresist includes:

[0019] forming a first seed layer on the first photoresist; wherein the first seed layer covers the entire first photoresist;

[0020] forming a second photoresist having a second opening on the first seed layer; the shape of the second opening is consistent with the shape of the redistribution layer pattern;

[0021] Electroplating metal in the second opening to form the redistribution layer;

[0022] The second photoresist is removed.

[0023] In an optional embodiment, the step of forming a conductive block connected to the redistribution layer on the redistribution layer includes:

[0024] forming a third photoresist having a third opening on the redistribution layer, wherein the position of the third opening is arranged corresponding to the output port of the redistribution layer;

[0025] Electroplating metal in the third opening to form the conductive block;

[0026] The third photoresist and a portion of the first seed layer are removed, and the remaining first seed layer is disposed corresponding to the redistribution layer.

[0027] In an optional embodiment, the step of forming a solder ball electrically connected to the conductive block includes:

[0028] Grinding the second encapsulation body so that the surface of the conductive block is flush with the surface of the second encapsulation body;

[0029] The solder balls are formed on the surfaces of the conductive blocks.

[0030] In an optional embodiment, after the step of forming a first photoresist having a first opening on the front side of the wafer, the method further includes:

[0031] A nano-roughened groove is formed on a surface of the first photoresist which is away from the wafer.

[0032] In an optional embodiment, the step of forming a first photoresist having a first opening on the front side of the wafer includes:

[0033] The mask is arranged between the first photoresist and the light source; wherein the mask has a first light shielding area and a second light shielding area, the first light shielding area is arranged corresponding to the pad of the chip; the second light shielding area is arranged corresponding to the cutting path on the wafer; the mask is also provided with a secondary light-seeing area; the secondary light-seeing area is located at the annular edge of the cutting path;

[0034] The first photoresist is exposed twice; wherein, in the first exposure process, the light source irradiates the area on the mask except the first light-shielding area and the second light-shielding area; in the second exposure process, the light source irradiates the secondary light-visible area.

[0035] In an optional embodiment, the exposure amount of the first exposure process is equal to the exposure amount of the second exposure process.

[0036] In an optional embodiment, the width of the cutting road of the wafer is L1, and in the first exposure pattern, the distance between the package edge pattern of the chip on the mask and the cutting road edge pattern is indented L2, and L2 is 0.04 to 0.08 times of L1; the indented L2 area and the cutting road area together constitute the second shading area, that is, the width of the second shading area is L4, L4=L1+2L2;

[0037] In the second exposure pattern, the distance between the chip packaging edge pattern on the mask and the cutting line edge is retracted by L3, and L3 is 0.09 to 0.2 times of L1; the retracted L3 area forms the secondary light-seeing area, and the width of the secondary light-seeing area is L3.

[0038] In a second aspect, the present invention provides a GaAs system-level fan-out packaging structure, which is manufactured using the GaAs system-level fan-out packaging method described in any one of the aforementioned embodiments.

[0039] The beneficial effects of the embodiments of the present invention include, for example:

[0040] The gallium arsenide system-level fan-out packaging method provided by the embodiment of the present invention uses a first encapsulation body and a second encapsulation body to encapsulate the reconstructed wafer on all sides, and the second encapsulation body simultaneously covers the end faces and surfaces of the redistribution layer and the conductive block to prevent water vapor intrusion, solve the delamination problem of the substrate and the redistribution layer in reliability testing, and improve structural reliability. In addition, there is a first photoresist between the front side of the wafer and the redistribution layer, which can further improve the bonding force between the redistribution layer and the surface of the gallium arsenide substrate and reduce the risk of structural delamination.

[0041] The GaAs system-level fan-out packaging structure provided by the embodiment of the present invention is manufactured by the above-mentioned packaging method. The packaging process is simple and reliable, which is conducive to improving the packaging reliability and packaging quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0043] Figure 1 A schematic diagram of a process for forming a first encapsulation body in a gallium arsenide system-level fan-out packaging method provided in an embodiment of the present invention;

[0044] Figure 2 A schematic diagram of a process for forming a redistribution layer in a GaAs system-level fan-out packaging method provided by an embodiment of the present invention;

[0045] Figure 3 A schematic diagram of a process for forming a conductive block on a redistribution layer and a second encapsulation body in a GaAs system-level fan-out packaging method provided by an embodiment of the present invention;

[0046] Figure 4 A schematic diagram of the process of grinding the second package, forming solder balls, and separating into single products in the GaAs system-level fan-out packaging method provided by an embodiment of the present invention;

[0047] Figure 5 A schematic diagram of a first exposure pattern on a mask provided by an embodiment of the present invention;

[0048] Figure 6 for Figure 5 A local enlarged schematic diagram of the middle A;

[0049] Figure 7 A schematic diagram of a second exposure pattern on a mask provided by an embodiment of the present invention.

[0050] Icons: 110-chip; 111-pad; 201-carrier; 202-thermal release film; 120-first package; 130-first photoresist; 131-first opening; 132-cutting groove; 141-first seed layer; 150-rewiring layer; 160-second photoresist; 161-second opening; 170-third photoresist; 171-third opening; 180-conductive block; 181-solder ball; 190-second package. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0052] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0054] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0055] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0056] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0057] Please combine Figures 1 to 5, this embodiment provides a gallium arsenide system-level fan-out packaging method, including providing a wafer with a first encapsulation body 120. The wafer includes a plurality of chips 110. The chip 110 uses a gallium arsenide substrate, and the front side of the chip 110 has a pad 111; the first encapsulation body 120 covers the back and side of the chip 110. A first photoresist 130 with a first opening 131 is formed on the front side of the wafer; the first opening 131 is used to expose the pad 111. A redistribution layer 150 electrically connected to the pad 111 is formed on the first photoresist 130. A conductive block 180 connected to the redistribution layer 150 is formed on the redistribution layer 150. A second encapsulation body 190 covering the conductive block 180 and the redistribution layer 150 is formed. The second encapsulation body 190 is located on a side of the first photoresist 130 away from the first encapsulation body 120. A solder ball 181 electrically connected to the conductive block 180 is formed. The first encapsulation body 120 and the second encapsulation body 190 are used to encapsulate the reconstructed wafer on six sides, thereby improving the structural reliability and solving the delamination problem of the substrate and the redistribution layer 150 in the reliability test. In addition, a first photoresist 130 is provided between the front side of the wafer and the redistribution layer 150, which can further improve the bonding force between the redistribution layer 150 and the surface of the gallium arsenide substrate and reduce the risk of structural delamination.

[0058] Optional, the specific packaging method is as follows:

[0059] Step S1: providing a wafer having a first encapsulation body 120. The steps generally include:

[0060] Step S11: providing a carrier board 201. The carrier board 201 plays a role in supporting and alleviating the warping deformation of the plastic package.

[0061] Step S12: a thermal release film 202 is disposed on the carrier 201. Both sides of the thermal release film 202 have a certain degree of stickiness, and the chip 110 can be fixed on the carrier 201. Specifically, one side of the thermal release film 202 is bonded to the carrier 201, and the other side is bonded to the chip 110. Later, the thermal release film 202 can lose its stickiness by heating or irradiating with light, so as to separate the carrier 201 and the chip 110.

[0062] Step S13: mount multiple chips 110 with different functions on the side of the thermal release film 202 away from the carrier 201. The pads 111 of the chips 110 face the carrier 201. That is, the chips 110 are fixed on the carrier 201 through the thermal release film 202. The thermal release film 202 is located between the chips 110 and the carrier 201.

[0063] Step S14: forming a first encapsulation body 120 encapsulating the chip 110 on the carrier 201; the first encapsulation body 120 encapsulates the back and side surfaces of the chip 110. The thickness of the first encapsulation body 120 is greater than that of the chip 110. The first encapsulation body 120 can be made of a plastic encapsulation material such as epoxy resin.

[0064] Step S15: remove the carrier 201 and the thermal release film 202 to obtain a wafer consisting of multiple chips 110. After removing the carrier 201, the front surface of the chip 110 is flush with the surface of the first package 120. The pads 111 of the chip 110 are exposed from the surface of the first package 120.

[0065] Optionally, before removing the carrier 201, the side of the first encapsulation body 120 away from the pad 111 is ground to obtain a wafer having a preset thickness, such as a grinding depth of 30um to um. In this embodiment, the grinding depth is 80um. According to actual needs, the grinding depth can also be 30um, 40um, 50um, 60um, 70um, 80um or any other value between 30um and um.

[0066] It can be understood that in this embodiment, the chips 110 with different functions are combined and partitioned and mounted on the carrier 201 and sealed as one, which belongs to the system-level packaging with high integration. Multiple functional modules can be implemented in one package, reducing the occupied space and power consumption, improving system performance and reliability, and higher packaging efficiency. In addition, the fan-out wafer-level packaging is adopted, which has higher integration density and higher packaging efficiency. Therefore, this embodiment belongs to the hybrid packaging of system-level packaging and fan-out wafer-level packaging, which can realize high-density wiring and form a chip 110 packaging structure with lower power loss and stronger functionality. In addition, the gallium arsenide substrate is adopted, which has a more perfect crystal structure, better thermal conductivity, better electrical properties and high electron mobility compared to the traditional silicon substrate, can achieve faster electron transmission speed, and has better performance, which is conducive to improving the performance of the packaged product.

[0067] Step S2: forming a first photoresist 130 having a first opening 131 on the front side of the wafer. The first opening 131 is used to expose the pad 111 .

[0068] Optionally, step S2 includes:

[0069] Step S21: Clean the dirt and impurities on the surface of the wafer. Mainly clean the surface of the wafer with the pad 111. This can improve the bonding force between the wafer and the first photoresist 130.

[0070] Optionally, laser ablation or chemical treatment is performed on the surface of the wafer with the pad 111 to form a nano-roughened groove, which can improve the bonding force between the wafer and the first photoresist 130. The nano-roughened groove needs to avoid the pad 111.

[0071] Step S22: Spin coating is used to form a first photoresist 130 with uniform thickness on the surface of the wafer. Spin coating specifically includes the steps of pre-spin → glue dripping → glue pushing → glue spreading → back washing, edge washing → spin drying and the like.

[0072] Step S23: pre-baking: The wafer is soft-baked to promote full volatilization of the solvent in the first photoresist 130 and dry the first photoresist 130 .

[0073] Combination Figures 5 to 7 , step S24: exposure. Use a mask to block the first photoresist 130. It can be understood that the mask is located between the light source and the first photoresist 130. The light emitted by the illumination light source is irradiated on the mask through the converging lens, and diffracted light beams are generated through the mask. These diffracted light beams carry the graphic information on the mask. The diffracted light beams are focused onto the surface of the first photoresist 130 through the projection lens, and an image of the mask pattern is formed on the surface of the first photoresist 130.

[0074] The mask has a first shading area and a second shading area, and the first shading area is arranged corresponding to the pad 111 of the chip 110; the first shading area is Figure 5 The area where the small and medium black blocks are located. Each small black block corresponds to a pad 111 on the chip 110. The second light shielding area is set corresponding to the cutting path on the wafer. The second light shielding area is Figure 5 The area shown by the shaded area. The cutting path is located between adjacent chips 110. Optionally, the cutting path is in a grid shape, and after the wafer is reconstructed, it is necessary to cut and separate along the cutting path to finally form a single product. The mask is also provided with a secondary light-seeing area; the secondary light-seeing area is located at the annular edge of the cutting path. The secondary light-seeing area is as shown in FIG. Figure 7 The shaded area in .

[0075] The first photoresist 130 is exposed twice. In the first exposure process, the light source irradiates the area on the mask except the first shading area and the second shading area. Optionally, the first photoresist 130 uses a negative photoresist. In this way, the area irradiated by light will be left after development, and the blocked part will be dissolved and removed after development. In the second exposure process, the light source irradiates the secondary light-seeing area. In this way, the position on the first photoresist 130 corresponding to the secondary light-seeing area is reinforced due to the secondary illumination and will not fall off in subsequent development. Using two exposure processes can improve the development quality of the pad 111 and the cutting path position, overcome the problem of unclean development at the pad 111 position, and overcome the problem of falling off at the cutting path.

[0076] Optionally, the exposure amount of the first exposure process is equal to the exposure amount of the second exposure process. In this embodiment, the exposure amounts of the two exposures are 450 mj / cm 2 Of course, in some other implementations, the two exposure amounts may also be different and can be flexibly set according to actual conditions.

[0077] Step S25: Development. The process of developing the photoresist is to dissolve the soluble area of ​​the first photoresist 130 caused by exposure with a chemical developer, and the main purpose is to accurately copy the pattern of the mask into the first photoresist 130. The development includes three sub-steps: development, cleaning and drying. In this embodiment, after development, the first photoresist 130 has a first opening 131 exposing the pad 111 and a cutting groove 132.

[0078] Step S26: Hardening the film. The first photoresist 130 is made to adhere more firmly to the surface of the wafer by heating and baking, and the etching resistance of the first photoresist 130 can be increased.

[0079] It should be noted that if the exposure process is performed only once, for fan-out packaging products with small photolithography sizes (such as 20um~35um), high exposure will cause the pad position to be uncleanly developed, while low exposure will cause the cutting path to fall off, making it difficult to balance the development quality of both the pad and the cutting path. Therefore, in this embodiment, two exposure processes are used to overcome the problems of unclean development at the pad 111 position and the problem of falling off at the cutting path.

[0080] Optionally, the cutting road width of the wafer is L1. In the first exposure pattern, the distance between the package edge pattern of the chip 110 on the mask and the edge of the cutting road is unilaterally retracted by L2, and L2 is 0.04 to 0.08 times of L1. In this embodiment, L1 is 220um and L2 is 10um. In order to reserve a certain cutting road margin, that is, the width of the cutting road groove 132 after development is greater than the cutting road width. In the first exposure process, the exposure pattern on the mask corresponding to the cutting road is unilaterally retracted by 10um along the chip 110 package edge. The retracted L2 area and the cutting road area together constitute a second shading area. The width of the second shading area L4, that is, the exposure width L4 of the exposure pattern corresponding to the cutting road is 240um, and the calculation method is L4=L1+2L2, that is, (220+10×2)um, such as Figure 5 , Figure 6 As shown by the shadow in the figure, the width of the second light shielding area in the length and width directions is L4. The shaded part forms a cutting groove 132 after development. In other words, the width of the cutting groove 132 formed on the first photoresist 130 after development is L4. It should be noted that Figure 5 and Figure 6 The dotted line in the middle indicates the width of the corresponding cutting path, which is drawn to show the size relationship. There is no dotted line on the actual mask pattern. The solid line is the boundary of the exposed pattern. The exposure pattern corresponding to the position of the pad 111 on the mask is consistent with the size of the pad 111. Figure 5 As shown by the small black block in the figure, the position corresponding to the small black block is developed to form the first opening 131 exposing the pad 111.

[0081] In the second exposure pattern, the distance between the package edge pattern of the chip 110 on the mask and the edge of the cutting road is a single-side indentation L3, and L3 is 0.09 to 0.2 times of L1. The indentation L3 area forms a secondary light-seeing area, and the width of the secondary light-seeing area is L3. Figure 7 As shown by the shadow in . In this embodiment, L3 is 30um. In the second exposure process, only the secondary light-seeing area is subjected to light treatment. The pattern on the mask used for the second exposure process is: the pattern along the edge of the chip 110 package is shrunk 30um on one side. It can be understood that the secondary light-seeing area has been irradiated by the light source in the first exposure process, and is irradiated again in the second exposure process, so that the position corresponding to the secondary light-seeing area on the first photoresist 130 is reinforced, and no peeling phenomenon will occur in the subsequent development.

[0082] It should be noted that the specific values ​​of the above-mentioned various widths L1, L2, L3 and L4 can be flexibly set according to actual conditions and are not specifically limited here. The first photoresist 130 is made of insulating material.

[0083] In this embodiment, the exposure patterns required for the two exposures are set on the same mask, the process flow is simpler, the number of masks used is reduced, the lithography efficiency is higher, and the use of the same mask avoids cumulative errors and installation errors. Using the same positioning reference, the lithography accuracy is higher, which is conducive to improving the lithography quality, improving the subsequent wiring accuracy, and then improving the packaging quality.

[0084] Step S3: forming a redistribution layer 150 electrically connected to the pad 111 on the first photoresist 130. Specifically, the redistribution layer 150 includes:

[0085] Step S31: forming a first seed layer 141 on the first photoresist 130; the first seed layer 141 covers the entire first photoresist 130. The surface of the first photoresist 130 is first cleaned and baked to remove moisture and increase adhesion. A vacuum thin film metal sputtering machine can be used to sputter metal on the surface of the first photoresist 130 to form the first seed layer 141.

[0086] Optionally, the first seed layer 141 is a copper layer or a titanium layer, or a copper-titanium alloy layer. In this embodiment, the first seed layer 141 includes two layers of metal, namely a titanium layer and a copper layer sequentially laid on the first photoresist 130. The titanium layer acts as a diffusion barrier layer to improve the bonding strength and conductivity. The copper layer can provide an electron carrier layer in the subsequent electroplating process, and can also improve the bonding strength between the redistribution layer 150 and the pad 111.

[0087] Optionally, before sputtering the first seed layer 141, a nano-roughened groove may be formed on the surface of the first photoresist 130 away from the pad 111, which may enhance the bonding strength between the first photoresist 130 and the first seed layer 141, and may enhance the bonding strength between the first photoresist 130 and the subsequently formed second encapsulant 190.

[0088] Step S32: forming a second photoresist 160 having a second opening 161 on the first seed layer 141; the shape of the second opening 161 is consistent with the pattern shape of the redistribution layer 150. The second opening 161 is formed by exposure, development, etc. The specific process steps can refer to the corresponding description in step S2.

[0089] Step S33: electroplating metal in the second opening 161 to form a redistribution layer 150. The redistribution layer 150 is electrically connected to the first seed layer 141.

[0090] The second photoresist 160 is removed.

[0091] Step S4: forming a conductive block 180 connected to the redistribution layer 150 on the redistribution layer 150. The specific steps include:

[0092] Step S41: forming a third photoresist 170 having a third opening 171 on the redistribution layer 150, wherein the position of the third opening 171 is arranged corresponding to the output port of the redistribution layer 150. The third opening 171 is formed by exposure, development, etc. The specific process steps can refer to the corresponding description in step S2.

[0093] Step S42: Electroplating metal in the third opening 171 to form a conductive block 180. The conductive block 180 can be made of copper. In this embodiment, the height of the conductive block 180 is less than the depth of the third opening 171, that is, the conductive block 180 is lower than the upper surface of the third photoresist 170, which is conducive to complete photoresist removal.

[0094] Step S43: remove the third photoresist 170 and part of the first seed layer 141, and the remaining first seed layer 141 is disposed corresponding to the redistribution layer 150. The third photoresist 170 may be removed by dissolving with a degumming liquid. The first seed layer 141 may be removed by wet etching.

[0095] It should be noted that when exposing and developing the second photoresist 160 and the third photoresist 170, a two-exposure method can also be adopted. Similar to step S24, the exposure pattern on the mask can be flexibly adjusted according to the shape of the redistribution layer 150 and the conductive block 180, and the exposure energy of each exposure can also be flexibly set.

[0096] Step S5: forming a second encapsulation body 190 encapsulating the conductive block 180 and the redistribution layer 150. The second encapsulation body 190 is formed on the front side of the wafer by means of a plastic encapsulation process, such as coating, injection molding or steel screen printing. The second encapsulation body 190 is made of resin. The second encapsulation body 190 encapsulates the surface and end face of the conductive block 180 and the surface and end face of the redistribution layer 150, and contacts the first photoresist 130. The nano-roughened grooves on the first photoresist 130 can improve the bonding force between the second encapsulation body 190 and the first photoresist 130. It can be understood that the upper surface of the second encapsulation body 190 is higher than the upper surface of the conductive block 180.

[0097] In addition, the first photoresist 130 also has a cutting groove 132, and the second encapsulant 190 enters the cutting groove 132 and can cover the sidewall of the cutting groove 132, further improving the bonding force between the first photoresist 130 and the second encapsulant 190. It is easy to understand that after the second encapsulant 190 enters the cutting groove 132, it contacts the first encapsulant 120. Since the materials of the first encapsulant 120 and the second encapsulant 190 are similar or the same, the bonding between the two is better. This is conducive to improving the bonding force between the first encapsulant 120 and the second encapsulant 190.

[0098] In this embodiment, the end surfaces of the redistribution layer 150 and the conductive block 180 are fully covered to prevent moisture from entering, thereby solving the problem of delamination between the redistribution layer 150 and the substrate surface.

[0099] The first photoresist 130 , the second photoresist 160 and the third photoresist 170 are all made of insulating materials. The material types of the three can be the same, or different types of materials can be used, which is not specifically limited here.

[0100] Step S6: Grind the surface of the second encapsulation body 190 to expose the surface of the conductive block 180. Only the second encapsulation body 190 may be ground, or both the second encapsulation body 190 and the conductive block 180 may be ground, as long as the surface of the second encapsulation body 190 and the surface of the conductive block 180 are flush.

[0101] Optionally, the first encapsulation body 120 may be ground again according to the target thickness of the packaged product.

[0102] In this embodiment, the first encapsulation body 120 is ground first, that is, the back surface is thinned first, and then the second encapsulation body 190 is ground until the conductive block 180 is exposed.

[0103] Step S7: forming solder balls 181 electrically connected to the conductive block 180. By grinding the second package 190, the surface of the conductive block 180 is flush with the surface of the second package 190. Solder balls 181 are formed on the surface of the conductive block 180. Optionally, flux is coated on the conductive block 180, and the ball is planted using a ball planting machine. The solder balls 181 can be made of at least one or more of tin, silver, copper, zinc and gold. Finally, they are cut along the cutting path to separate into single products, completing the hybrid packaging of gallium arsenide (GaAs) system-level wafer fan-out.

[0104] In the packaging method, six-sided encapsulation is adopted, which solves the problem of weak bonding and easy delamination between the gallium arsenide substrate and the redistribution layer 150, can effectively prevent water vapor from invading the redistribution layer 150, and improves the packaging reliability. In addition, copper is directly electroplated on the surface of the redistribution layer 150 to form the conductive block 180, and two electroplatings are adopted (electroplating to form the redistribution layer 150 and electroplating to form the conductive block 180), the process is simpler, the amount of photoresist is reduced, the process is simplified, and the packaging efficiency is improved, while avoiding a series of problems caused by the processes of cleaning, coating, edge washing, baking, etc. of the photoresist. When the first photoresist 130 is exposed and developed, two exposures are adopted, and the patterns of the two exposures are set on the same mask, which improves the exposure quality, solves the problems of unclean development and falling off of the cutting path, and is also conducive to improving the wiring accuracy of the redistribution layer 150 and improving the packaging quality. In addition, the bonding force between the second encapsulation body 190 and the first photoresist 130 and the first encapsulation body 120 is improved, and the packaging structure is more reliable.

[0105] The embodiment of the present invention also provides a gallium arsenide system-level fan-out packaging structure, which is made by the above-mentioned gallium arsenide system-level fan-out packaging method. The packaging structure includes a chip 110 of a gallium arsenide substrate, a first encapsulation body 120, a first photoresist 130, a first seed layer 141, a redistribution layer 150, a conductive block 180, a solder ball 181, and a second encapsulation body 190. Among them, the surface of the first encapsulation body 120 is flush with the front of the chip 110, and the pad 111 on the front of the chip 110 is exposed from the first encapsulation body 120. The first seed layer 141 is arranged between the redistribution layer 150 and the pad 111, and is used to electrically conduct the redistribution layer 150 and the pad 111, and can enhance the bonding force between the two. A first photoresist 130 is arranged between the first seed layer 141 and the substrate surface. The second encapsulant 190 covers the first seed layer 141, the redistribution layer 150 and the conductive block 180, and is respectively connected to the first photoresist 130 and the first encapsulant 120, which can improve the bonding strength of the structure, prevent water vapor from invading the redistribution layer 150, prevent stratification between structural levels, and improve reliability.

[0106] In summary, the gallium arsenide system-level fan-out packaging method and structure provided in the embodiment of the present invention adopts a hybrid packaging of system-level and wafer-level fan-out, and adopts a gallium arsenide substrate, which greatly improves the performance and reliability of the packaged product, improves the packaging efficiency, and improves the product integration. It also solves the problems of unclean development, cutting path shedding, and structural stratification during the packaging process, and effectively improves the packaging quality. The use of two electroplating processes eliminates one photolithography process, makes the process simpler, reduces the amount of photoresist used, simplifies the process, improves the packaging efficiency, and avoids a series of problems caused by processes such as photoresist cleaning, gluing, edge washing, and baking.

[0107] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A gallium arsenide system-level fan-out packaging method, characterized in that: include: A wafer having a first encapsulation body (120) is provided; wherein the wafer comprises a plurality of chips (110); the chips (110) adopt a gallium arsenide substrate, and the front surface of the chips (110) has a pad (111); the first encapsulation body (120) covers the back surface and side surfaces of the chips (110); A first photoresist (130) having a first opening (131) is formed on the front side of the wafer; the first opening (131) is used to expose the pad (111); and the method comprises: The mask is arranged between the first photoresist (130) and the light source; wherein the mask has a first light shielding area and a second light shielding area, the first light shielding area is arranged corresponding to the pad (111) of the chip (110); the second light shielding area is arranged corresponding to the cutting path on the wafer; the mask is also provided with a secondary light-seeing area; the secondary light-seeing area is located at the annular edge of the cutting path; The first photoresist (130) is subjected to two exposure processes; wherein, in the first exposure process, the light source irradiates the area on the mask except the first light-shielding area and the second light-shielding area; and in the second exposure process, the light source irradiates the secondary light-seeing area; forming a redistribution layer (150) electrically connected to the pad (111) on the first photoresist (130); forming a conductive block (180) connected to the redistribution layer (150) on the redistribution layer (150); forming a second encapsulation body (190) encapsulating the conductive block (180) and the redistribution layer (150); wherein the second encapsulation body (190) is located on a side of the first photoresist (130) away from the first encapsulation body (120); A solder ball (181) electrically connected to the conductive block (180) is formed.

2. The gallium arsenide system-level fan-out packaging method according to claim 1, characterized in that: The step of providing a wafer having a first encapsulation body (120) comprises: Providing a carrier plate (201) with a thermal release film (202) attached thereto; Mounting a plurality of chips (110) with different functions on a side of the thermal release film (202) away from the carrier (201); wherein the pads (111) of the chips (110) face the carrier (201); A first encapsulation body (120) encapsulating the chip (110) is formed on the carrier board (201); the first encapsulation body (120) encapsulates the back side and side surfaces of the chip (110); Grinding a side of the first encapsulation body (120) away from the pad (111); The carrier plate (201) and the thermal release film (202) are removed to obtain the wafer.

3. The gallium arsenide system-level fan-out packaging method according to claim 1, characterized in that: The step of forming a redistribution layer (150) electrically connected to the pad (111) on the first photoresist (130) comprises: forming a first seed layer (141) on the first photoresist (130); the first seed layer (141) covers the entire first photoresist (130); forming a second photoresist (160) having a second opening (161) on the first seed layer (141); the shape of the second opening (161) is consistent with the pattern shape of the redistribution layer (150); Electroplating metal in the second opening (161) to form the redistribution layer (150); The second photoresist (160) is removed.

4. The gallium arsenide system-level fan-out packaging method according to claim 3, characterized in that: The step of forming a conductive block (180) connected to the redistribution layer (150) on the redistribution layer (150) comprises: forming a third photoresist (170) having a third opening (171) on the redistribution layer (150), wherein the position of the third opening (171) is arranged corresponding to an output port of the redistribution layer (150); Electroplating metal in the third opening (171) to form the conductive block (180); The third photoresist (170) and a portion of the first seed layer (141) are removed, and the remaining first seed layer (141) is arranged corresponding to the redistribution layer (150).

5. The gallium arsenide system-level fan-out packaging method according to claim 1, characterized in that: The step of forming a solder ball (181) electrically connected to the conductive block (180) comprises: Grinding the second encapsulation body (190) so that the surface of the conductive block (180) is flush with the surface of the second encapsulation body (190); The solder ball (181) is formed on the surface of the conductive block (180).

6. The gallium arsenide system-level fan-out packaging method according to claim 1, characterized in that: After the step of forming a first photoresist (130) having a first opening (131) on the front side of the wafer, the method further comprises: A nano-roughened groove is formed on a surface of the first photoresist (130) on one side away from the wafer.

7. The gallium arsenide system-level fan-out packaging method according to any one of claims 1 to 6, characterized in that: The exposure amount of the first exposure process is equal to the exposure amount of the second exposure process.

8. The gallium arsenide system-level fan-out packaging method according to any one of claims 1 to 6, characterized in that: The width of the cutting path of the wafer is L1, and in the first exposure pattern, the distance between the package edge pattern of the chip (110) on the mask and the edge of the cutting path is indented L2, and L2 is 0.04 to 0.08 times of L1; the indented L2 area and the cutting path area together constitute the second light shielding area, that is, the width of the second light shielding area is L4, and L4=L1+2L2; In the second exposure pattern, the distance between the package edge pattern of the chip (110) on the mask and the edge of the cutting path is indented by L3, and L3 is 0.09 to 0.2 times of L1; the indented L3 area forms the secondary light-seeing area, and the width of the secondary light-seeing area is L3.

9. The gallium arsenide system-level fan-out packaging method according to claim 8, characterized in that: The L1 is 220um, L2 is 10um, and L3 is 30um.

10. A gallium arsenide system-level fan-out packaging structure, characterized in that: The method is manufactured by adopting the gallium arsenide system-level fan-out packaging method as described in any one of claims 1 to 9.

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