Packaging method and packaging structure of silicon optical chip

Abstract

The invention belongs to the technical field of semiconductors, and discloses a silicon optical chip packaging method which comprises the specific steps of S1, cutting, S2, temporary bonding, S3, plastic packaging, S4, grinding, S5, de-bonding, S6, coating, S7, exposure, S8, development, S9, through hole drilling, S10, sputtering, S11, pattern transfer, S12, pattern electroplating, S13, film stripping, S14, differential etching, S15, secondary fan-out of a circuit, S16, resistance welding, S17, surface treatment, S18, electrical testing, S19, cutting and S20, flip-chip bonding. And S21, implanting solder balls. According to the fan-out packaging technology, interlayer copper interconnection and surface circuit reconstruction are directly achieved on the silicon optical chip, the signal transmission distance is remarkably shortened, the packaging density is improved, and the limitation of a traditional wire bonding technology is overcome; meanwhile, according to the board-level fan-out packaging method, the processing efficiency and the makeup utilization rate are further improved, the fan-out design of a circuit with a larger area is supported, and the cost advantage and the superiority of technical adaptation are shown.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and specifically relates to a packaging method and a packaging structure of a silicon photonic chip. Background Art

[0002] The generative AI and large-model AI-related technologies driven by ChatGPT will become the intelligent foundation for the development of a new round of science and technology industries. The resulting explosion in computing power demand will enable silicon photonic chips to help the future AI industry. Computing power will be the basic means of production for the future digital technology industry. AI computing power centers will give rise to massive server demand and accelerate the construction of server clusters. However, traditional chip packaging faces pain points in bandwidth and power consumption. A large amount of data needs to be stored, transmitted and processed, and the demand for high-bandwidth transmission increases. With the continuous increase in multi-core processors, memory requirements and I\O bandwidth requirements, the pressure on connection and network transmission increases. At the same time, the growth of bandwidth will also lead to a rapid increase in power consumption. As a strong competitor for the next generation of interconnection technology, optical interconnection has obvious advantages over electrical interconnection solutions, such as wide bandwidth, anti-electromagnetic interference, strong confidentiality, low transmission loss, and low power consumption. The proportion of optical interconnection in future data center interconnection will become larger and larger, and silicon photonic integration technology will give full play to the broadband advantages of optical interconnection. Traditional silicon photonic chip packaging uses wire bonding for interconnection, which has a long transmission distance, inconsistent impedance matching, and certain delays in the transmission of high-frequency and high-speed signals, as well as low packaging density. This type of process can no longer meet the future transmission needs of silicon photonic chips at 800G and optical devices above 1.6T. Summary of the invention

[0003] The object of the present invention is to provide a packaging method and packaging structure of a silicon photonic chip to solve the problems raised in the above background technology.

[0004] In order to achieve the above object, the present invention provides the following technical solution: a packaging method for a silicon photonic chip, the specific steps of the packaging method for a silicon photonic chip are:

[0005] S1, cutting: prepare a silicon photonic chip with LD cavity and coupling groove;

[0006] S2, temporary bonding: the silicon photonic chip with the LD cavity and the coupling groove is temporarily bonded face down on a glass substrate pre-coated with a layer of temporary bonding glue for temporary chip adhesion through a die bonder. Further, the chip facing up can also meet the packaging requirements of this solution;

[0007] S3, plastic encapsulation: using epoxy molding compound to encapsulate the bonded silicon photonic chip on the mold under high temperature and high pressure;

[0008] S4, grinding: Grinding the cured plastic sealing material to remove the excess plastic sealing material on the surface of the plate and thin it to the required thickness;

[0009] S5, debonding: after heating and baking, the bond is debonded, the plastic-sealed plate is disassembled from the glass substrate, and the glass-based transfer plate serving as a support is removed;

[0010] S6, coating: coating a layer of photosensitive PI material on the front of the silicon photonic chip. The coating thickness needs to be coated to a certain thickness according to the actual product design. Further use of a resin material with photosensitive curing properties can also meet the requirements of this solution;

[0011] S7, exposure: the holes corresponding to the pins on the silicon photonic chip, the LD cavity and the coupling groove are not exposed by exposure, and the rest are exposed and cured;

[0012] S8, development: removing the PI photosensitive material in the unexposed area by an alkaline solution to expose the underlying pads and pin metal connection parts;

[0013] S9, drilling through holes: making through holes in the fan-out area to form subsequent lines connecting the upper and lower fan-outs;

[0014] S10, sputtering: firstly, a layer of metal titanium is sputtered on the surface of the plate, and then a layer of copper is sputtered on the metal titanium layer as a main conductive layer. Further, the types of sputtered metals include one metal among gold, silver, aluminum, and tungsten, or a composite form of several metals can meet the requirements of this solution;

[0015] S11, pattern transfer: the pattern is thickened by electroplating and the holes filled by electroplating are exposed, so that the pattern can be produced by coating photoresist, exposing and developing;

[0016] S12, pattern electroplating: thicken the copper thickness of the exposed part of the pattern and fill the exposed holes;

[0017] S13, film stripping: removing all photoresist on the board;

[0018] S14, differential etching: first etching the copper layer, then etching the titanium layer, until the substrate layer of the etched area is exposed;

[0019] S15, secondary fan-out circuit: according to the above steps S6-S14, a circuit fan-out is made again to obtain the first layer and the fourth layer fan-out circuits respectively;

[0020] S16, solder mask: a solder mask layer is made on the first layer and the sixth layer of the board by coating or rolling, and then the pattern is transferred to the solder mask layer by exposure, and finally the unexposed part is removed by development to expose the LD cavity, coupling groove and pad components, and finally the solder mask layer is finally thermally cured by baking;

[0021] S17, surface treatment: depositing an inert metal layer or organic film on the surface of the copper pad component to prevent oxidation and corrosion;

[0022] S18, electrical test: conduct continuity test on the product;

[0023] S19, splitting: splitting the product into individual products;

[0024] S20, flip chip bonding: soldering the electric power chip (EIC) on the silicon photonic chip packaging substrate by flip chip bonding;

[0025] S21, solder ball planting: a layer of solder paste is printed on the BGA surface of the product through a mold, and then the solder ball is implanted through the mold, and finally the solder ball is fixed on the BGA pad through reflow soldering to complete the production.

[0026] Preferably, the glass substrate has a size of 510 mm*515 mm, and the temporary bonding is made using FOPLP technology, so the arrangement of the chips will be as close as possible to the designed fan-out area, making full use of the area of ​​the large board.

[0027] Preferably, the thickness of the plastic encapsulation in S3 is generally thicker than the thickness of the silicon photonic chip, so as to prevent the chip from being damaged when grinding and thinning are performed after the plastic encapsulation is completed.

[0028] Preferably, the thickness of the metal titanium layer sputtered in S10 is less than 50 nm, and the thickness of the sputtered copper layer is 400 nm.

[0029] Preferably, it comprises a silicon photonic chip body and a packaging structure, wherein the silicon photonic chip body comprises: a silicon substrate, a plastic sealing layer, a PIC pin, and a PIC;

[0030] The packaging structure includes: PI medium, solder resist layer, EIC and solder balls.

[0031] Preferably, the silicon substrate and the plastic sealing layer are bonded by temporary bonding adhesive, the PIC pin is installed at the end of the PIC, and the LD cavity and the coupling groove are opened at the bottom of the PIC.

[0032] Preferably, the silicon photonic chip body is inverted, the solder balls are arranged at the ends of the PIC pins and the PIC ends, the EIC is installed at the ends of the solder balls, the PI medium is located between the plastic encapsulation layer, the PIC, and the silicon substrate, and the solder resist layer is located at the bottom of the plastic encapsulation layer.

[0033] The beneficial effects of the present invention are as follows:

[0034] The present invention proposes an innovative silicon photonic chip packaging technology, which first bonds the silicon photonic chip downward to a temporary glass-based adapter plate, then protects the chip through a plastic sealing process, and then coats PI on the chip surface to make a hole pattern and perform preliminary insulation. After that, the pattern transfer and electroplating technology is used to thicken the pattern copper layer and fill the holes, and at the same time, TMV (i.e., through holes in the plastic sealing material layer are combined with sputtering and electroplating to form copper pillars) technology is used to connect the upper and lower fan-out circuits. After the first circuit fan-out is completed, this process is repeated to construct a multi-layer fan-out circuit. Finally, a solder resist insulating layer is applied and a surface treatment is performed, and the EIC is mounted on the silicon photonic chip packaging substrate by flip-chip welding, and solder balls are implanted to complete the packaging. This fan-out packaging technology directly realizes inter-layer copper interconnection and surface circuit reconstruction on the silicon photonic chip, significantly shortens the signal transmission distance, improves the packaging density, and overcomes the limitations of the traditional wire bonding process. At the same time, the FOPLP (fan-out packaging at panel level) method further improves processing efficiency and panel utilization, supports larger area circuit fan-out design, and demonstrates the superiority of cost advantage and technical adaptation. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 The figure is a simplified flow chart of the packaging method of the silicon photonic chip of the present invention;

[0036] Figure 2 This is a schematic diagram of the packaging structure of the silicon photonic chip of the present invention. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0038] like Figure 1 As shown, an embodiment of the present invention provides a packaging method for a silicon photonic chip, and the specific steps of the packaging method for the silicon photonic chip are:

[0039] S1, cutting: prepare a silicon photonic chip with a LD (Laser Diode) cavity and a coupling groove;

[0040] S2, temporary bonding: the silicon photonic chip with the LD cavity and the coupling groove is temporarily bonded face down on a glass substrate pre-coated with a layer of temporary bonding glue for temporary chip adhesion through a die bonding machine;

[0041] S3, plastic encapsulation: Use epoxy molding compound to encapsulate the bonded silicon photonic chip on the mold under high temperature and high pressure; its purpose is to protect the silicon photonic chip from the influence of the external environment and ensure the electrical insulation of the silicon photonic chip from the external environment.

[0042] S4, grinding: Grinding the cured plastic sealing material to remove the excess plastic sealing material on the surface of the plate and thin it to the required thickness;

[0043] S5, debonding: after heating and baking, the bond is debonded, the plastic-sealed plate is disassembled from the glass substrate, and the glass-based transfer plate serving as a support is removed;

[0044] S6, coating: coating a layer of photosensitive PI material on the front of the silicon photonic chip. This PI material is a material with photosensitive curing properties, and the coating thickness needs to be coated according to the actual product design.

[0045] S7, exposure: the holes corresponding to the pins on the silicon photonic chip, the LD cavity and the coupling groove are not exposed by exposure, and the rest are exposed and cured;

[0046] S8, development: removing the PI photosensitive material in the unexposed area by an alkaline solution to expose the underlying pads and pin metal connection parts;

[0047] S9, drilling through holes: making through holes in the fan-out area to form subsequent lines connecting the upper and lower fan-outs;

[0048] S10, sputtering: firstly, a layer of metal titanium is sputtered on the surface of the plate, and then a layer of copper is sputtered on the metal titanium layer as the main conductive layer; since the bonding force between metal titanium and PI is better than that between copper and PI, a thin layer of metal titanium is sputtered first;

[0049] S11, pattern transfer: the pattern is thickened by electroplating and the holes filled by electroplating are exposed, so that the pattern can be produced by coating photoresist, exposing and developing;

[0050] S12, pattern electroplating: thicken the copper thickness of the exposed part of the pattern and fill the exposed holes;

[0051] S13, film stripping: removing all photoresist on the board;

[0052] S14, differential etching: first etching the copper layer, then etching the titanium layer, until the substrate layer of the etched area is exposed;

[0053] S15, secondary fan-out circuit: according to the above steps S6-S14, a circuit fan-out is made again to obtain the first layer and the fourth layer fan-out circuits respectively;

[0054] S16, solder mask: a solder mask layer is made on the first layer and the sixth layer of the board by coating or rolling, and then the pattern is transferred to the solder mask layer by exposure, and finally the unexposed part is removed by development to expose the LD cavity, coupling groove and pad components, and finally the solder mask layer is finally thermally cured by baking;

[0055] Solder mask is used to protect the circuit pattern outside the pad, and to prevent abnormalities such as bridging caused by subsequent welding. Solder mask can also play a certain insulating role.

[0056] S17, surface treatment: depositing an inert metal layer or an organic film on the surface of the copper pad component to prevent oxidation and corrosion; the metal layer deposited on the surface includes single-layer metals such as gold, silver, nickel, palladium, etc. or multi-layer composite metals.

[0057] S18, electrical test: conduct continuity test on the product;

[0058] S19, splitting: splitting the product into individual products;

[0059] S20, flip chip bonding: soldering the electric power chip (EIC) on the silicon photonic chip packaging substrate by flip chip bonding;

[0060] S21, solder ball planting: a layer of solder paste is printed on the BGA surface of the product through a mold, and then the solder ball is implanted through the mold, and finally the solder ball is fixed on the BGA pad through reflow soldering to complete the production.

[0061] The glass substrate has a size of 510 mm*515 mm, and the temporary bonding is made using FOPLP technology, so the arrangement of the chips will be as close to the designed fan-out area as possible, making full use of the area of ​​the large board.

[0062] The thickness of the plastic encapsulation in S3 is generally thicker than the thickness of the silicon photonic chip, so as to prevent the chip from being damaged when grinding and thinning are performed after the plastic encapsulation is completed.

[0063] Wherein, the thickness of the metal titanium layer sputtered in S10 is less than 50 nm, and the thickness of the sputtered copper layer is 400 nm.

[0064] Metal titanium is not used as the main conductive layer, so generally sputtering less than 50nm is sufficient. The thickness of copper is selected to be around 400nm. Since fine circuits are produced, the sputtered copper layer should not be too thick to avoid subsequent etching difficulties.

[0065] Among them, it includes a silicon photonic chip body and a packaging structure, and the silicon photonic chip body includes: a silicon substrate, a plastic sealing layer, a PIC pin, and a PIC;

[0066] The packaging structure includes: PI medium, solder resist layer, EIC and solder balls.

[0067] The silicon substrate and the plastic sealing layer are bonded by temporary bonding adhesive, the PIC pin is installed at the end of the PIC, and the LD cavity and the coupling groove are opened at the bottom of the PIC.

[0068] Among them, the silicon photonic chip body is inverted, the solder balls are set at the ends of the PIC pins and the PIC ends, the EIC is installed at the ends of the solder balls, the PI medium is located between the plastic sealing layer, the PIC, and the silicon substrate, and the solder resist layer is located at the bottom of the plastic sealing layer.

[0069] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0070] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for packaging a silicon photonic chip, characterized in that: The specific steps of the packaging method of the silicon photonic chip are as follows: S1, cutting: preparing a silicon photonic chip with LD cavity and coupling groove; S2, temporary bonding: the silicon photonic chip with the LD cavity and the coupling groove is temporarily bonded face down on a glass substrate pre-coated with a layer of temporary bonding glue for temporary chip adhesion through a die bonder. Further, the chip facing up can also meet the packaging requirements of this solution; S3, plastic encapsulation: using epoxy molding compound to encapsulate the bonded silicon photonic chip on the mold under high temperature and high pressure; S4, grinding: Grinding the cured plastic sealing material to remove the excess plastic sealing material on the surface of the plate and thin it to the required thickness; S5, debonding: after heating and baking, the bond is debonded, the plastic-sealed plate is disassembled from the glass substrate, and the glass-based transfer plate serving as a support is removed; S6, coating: coating a layer of photosensitive PI material on the front of the silicon photonic chip. The coating thickness needs to be coated to a certain thickness according to the actual product design. Further use of a resin material with photosensitive curing properties can also meet the requirements of this solution; S7, exposure: the holes corresponding to the pins on the silicon photonic chip, the LD cavity and the coupling groove are not exposed by exposure, and the rest are exposed and cured; S8, development: removing the PI photosensitive material in the unexposed area by an alkaline solution to expose the underlying pads and pin metal connection parts; S9, drilling through holes: making through holes in the fan-out area to form subsequent lines connecting the upper and lower fan-outs; S10, sputtering: firstly, a layer of metal titanium is sputtered on the surface of the plate, and then a layer of copper is sputtered on the metal titanium layer as a main conductive layer; further, the types of sputtered metals include one metal among gold, silver, aluminum, and tungsten, or a composite form of several metals can meet the requirements of this scheme; S11, pattern transfer: the pattern is thickened by electroplating and the holes filled by electroplating are exposed, so that the pattern can be produced by coating photoresist, exposing and developing; S12, pattern electroplating: thicken the copper thickness of the exposed part of the pattern and fill the exposed holes; S13, film stripping: removing all photoresist on the board; S14, differential etching: first etching the copper layer, then etching the titanium layer, until the substrate layer of the etched area is exposed; S15, secondary fan-out circuit: according to the above steps S6-S14, a circuit fan-out is made again to obtain the first layer and the fourth layer fan-out circuits respectively; S16, solder mask: a solder mask layer is made on the first layer and the sixth layer of the board by coating or rolling, and then the pattern is transferred to the solder mask layer by exposure, and finally the unexposed part is removed by development to expose the LD cavity, coupling groove and pad components, and finally the solder mask layer is finally thermally cured by baking; S17, surface treatment: depositing an inert metal layer or organic film on the surface of the copper pad component to prevent oxidation and corrosion; S18, electrical test: conduct continuity test on the product; S19, splitting: splitting the product into individual products; S20, flip chip bonding: soldering the electric power chip (EIC) on the silicon photonic chip packaging substrate by flip chip bonding; S21, solder ball planting: a layer of solder paste is printed on the BGA surface of the product through a mold, and then the solder ball is implanted through the mold, and finally the solder ball is fixed on the BGA pad through reflow soldering to complete the production.

2. The method for packaging a silicon photonic chip according to claim 1, characterized in that: The glass substrate has a size of 510 mm*515 mm, and the temporary bonding is made using the FOPLP technology, so the arrangement of the chips will be as close to the designed fan-out area as possible, making full use of the area of ​​the large board.

3. The packaging method and packaging structure of a silicon photonic chip according to claim 1, characterized in that: The thickness of the plastic encapsulation in S3 is generally thicker than the thickness of the silicon photonic chip, to prevent damage to the chip during grinding and thinning after the plastic encapsulation is completed.

4. The packaging method and packaging structure of a silicon photonic chip according to claim 1, characterized in that: The thickness of the metal titanium layer sputtered in S10 is less than 50 nm, and the thickness of the sputtered copper layer is 400 nm.

5. A packaging structure of a silicon photonic chip, characterized in that: It includes a silicon photonic chip body and a packaging structure, wherein the silicon photonic chip body includes: a silicon substrate, a plastic sealing layer, a PIC pin, and a PIC; The packaging structure includes: PI medium, solder resist layer, EIC and solder balls.

6. The packaging structure of a silicon photonic chip according to claim 5, characterized in that: The silicon substrate and the plastic sealing layer are bonded by temporary bonding adhesive, the PIC pin is installed at the end of the PIC, and the LD cavity and the coupling groove are opened at the bottom of the PIC.

7. The packaging structure of a silicon photonic chip according to claim 5, characterized in that: The silicon photonic chip body is inverted, the solder balls are set at the ends of the PIC pins and the PIC ends, the EIC is installed at the ends of the solder balls, the PI medium is located between the plastic sealing layer, the PIC, and the silicon substrate, and the solder resist layer is located at the bottom of the plastic sealing layer.

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