PMU technology for ultra-low leakage

Abstract

A DC-DC converter that improves efficiency in a window mode and a method of operating the same are provided. Generally, the method begins with a coasting period in which a windowed mode enable signal is received in the converter and a switch is turned off through which the low reference voltage generator is coupled to a switching reference (SR) of a capacitor charged on a first input of the low-side comparator. Operation of all circuits and devices except the comparator in the converter is paused. The voltage on the SR is compared with a feedback voltage (vfb) coupled from a regulated rail coupled to the output of the converter to a second input of the comparator to sense a change in the voltage on the regulated rail as it discharges through a load to which the regulated rail is coupled. When vfb is less than the SR voltage, operation of the circuits and devices resumes during the burst period, and the switch is closed to recharge the SR.

Description

Technical Field

[0001] The present disclosure relates generally to power management units, and more particularly to power management units including DC-DC converters that reduce static leakage current and methods of operating the same. Background Art

[0002] The growth of miniaturized portable electronic devices, including wireless Internet of Things (IoT) applications, implantable medical devices, and wearable devices (such as smart watches, smart glasses, and activity trackers) that use batteries or other DC power sources with limited stored energy has created a challenge to extend the time between recharging and / or replacement cycles of the power sources of these devices.

[0003] One way to extend the recharge and / or replacement cycles of these devices is to introduce "standby or sleep" or "deep sleep" in which the computer or controller in these devices cuts off power to unneeded subsystems (including sensors and transceivers) and places the device in a minimum power state.

[0004] Although this approach provides significant improvements in extending the time between recharge and replacement, it is not completely satisfactory for many reasons. Although these modes are opposite to the "active" mode and usually no significant activity is seen, many subsystems are still "active" and draw current from internal voltage rails to power various internal functions. Chief among these is the DC-DC converter within the device's power management unit (PMU), which is typically used to regulate the voltage rails. These internal functions consume very low current even in "sleep" or "deep sleep" modes. However, the regulated voltage rails need to maintain a predefined level of accuracy in all operating modes including "active", "sleep" and "deep sleep" modes to power the wake-up circuits and associated sensors. Therefore, in order to regulate these internal or external rails, conventional DC-DC converters typically include a voltage regulator that includes some combination of an "always on" (AON) reference, a comparator, an amplifier, a buffer, and a driver, and thus draws continuous or "DC" or static leakage current from a battery or other DC power source.

[0005] Therefore, a PMU and power management method are needed to extend the recharging and / or replacement period of these portable devices.It is also desirable that the PMU and management be compatible with the design of the PMU and the operating methods of existing portable devices. Summary of the invention

[0006] A DC-DC converter and its operation method for use in a power management unit (PMU) are provided to reduce the static quiescent current in the DC-DC converter when the PMU is in window mode. The method begins with storing a low reference voltage (Vref_low) from a Vref_low generator to a switch reference (SR) charged by a local capacitor coupled to an input of a low-side comparator. During the "coasting period" of the window mode, a first switch is disconnected, SR is isolated from the Vref_low generator, and the operation of all circuits and devices including the Vref_low generator in the DC-DC converter except the low-side comparator is suspended. The low-side comparator continues to operate, and the Vref_low stored on the SR is compared with a feedback voltage (Vfb), which is coupled to a second input from a reference voltage (Vref) on a regulation rail coupled to the output of the DC-DC converter, and by comparing the SR with the Vfb, the change of the Vref on the regulation rail is sensed when the regulation rail is discharged through a load coupled thereto. When Vref decreases to Vref_low stored on SR, a low voltage signal (V L ). A burst enable (en_burst) signal generated in the window logic circuit is coupled to at least some of the circuits and devices in the DC-DC converter (including the Vref_low generator), signaling these circuits and devices to resume operation and signaling the first switch to close, thereby recharging SR to Vref_low. During the burst period, the inductor and output capacitor (through which the regulation rail is coupled to the output of the DC-DC converter) are charged to increase Vref on the regulation rail from Vref_low to a high reference voltage (Vref_high). Typically, raising Vref on the regulation rail includes generating a duty cycle (duty_cycle) signal in a window logic circuit, coupling the en_burst signal and the duty_cycle signal to a driver logic circuit, and operating the driver logic circuit to alternately drive a first transistor and a second transistor to charge an inductor and an output capacitor, thereby raising Vref from Vref_low to Vref_high, wherein the output of the DC-DC converter is coupled to a positive voltage (VDD) through the first transistor, and the output is coupled to a negative voltage (VSS) through the second transistor.

[0007] The DC-DC converter also includes a high-side comparator having a first input coupled to Vfb received from the regulation rail, a second input coupled to the Vref_high generator, and an output coupled to the window logic circuit. During the burst period, the high-side comparator is used to compare Vfb with Vref_high, and when Vfb is equal to or greater than Vref_high, the high-side comparator outputs a high voltage signal (VH) to the window logic circuit to terminate the en_burst signal, suspend the operation of all circuits and devices in the DC-DC converter except the low-side comparator, and disconnect the first switch to isolate the SR from the Vref_low generator, thereby returning the DC-DC generator to the idle period in the window mode.

[0008] The method can be extended to a switched reference from a capacitor charge of a main reference generator. The operation of the main reference generator is suspended during the idle period, thereby improving the efficiency of the PMU system in window mode. In one embodiment, the PMU also includes: a main reference generator, which is coupled to a bandgap reference (BG) charged by a local capacitor in the PMU through a second switch (S0), and the bandgap reference (BG) charged by the local capacitor is coupled to a Vref_low generator in a DC-DC converter. Both the main reference generator and the second switch (S0) are operable to receive a window mode enable (en_window) signal and a burst enable (en_burst) signal. In active mode, the main reference generator is operating and the second switch (S0) is closed, thereby storing the main reference voltage (Vref_bg) on ​​BG. During the idle period in window mode, the operation of the main reference generator is suspended and the second switch (S0) is opened. During the burst period, operation of the main reference generator is resumed and the second switch (S0) is closed, storing Vref_bg on BG and then coupling Vref_bg to the Vref_low generator in the DC-DC converter.

[0009] It will be appreciated that providing a switched reference (SR) to charge a local capacitor to a low-side comparator and suspending operation of all other circuits and devices in the DC-DC converter during the coasting period in window mode provides efficient operation in operation in window mode. It will also be appreciated that the efficiency of a PMU including such a DC-DC converter can be further improved in window mode by suspending operation of a main reference generator coupled to the DC-DC converter and isolating a bandgap reference (BG) in the PMU that charges a capacitor that couples the main reference generator to the DC-DC converter from the main reference generator.

[0010] Other features and advantages of embodiments of the present invention and the structure and operation of various embodiments of the present invention are described in detail below with reference to the accompanying drawings. Note that the present invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Based on the teachings contained herein, additional embodiments will be apparent to those skilled in the relevant art. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments of the present invention will now be described by way of example only with reference to the accompanying drawings, in which corresponding reference numerals indicate corresponding parts. In addition, the accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present invention and, together with the specification, further serve to explain the principles of the present invention and enable those skilled in the relevant art to make and use the present invention.

[0012] Figure 1 is a schematic block diagram showing a portion of a power management unit (PMU) including a main reference generator and a DC-DC converter exhibiting low leakage current in sleep mode according to an embodiment of the present disclosure;

[0013] Figure 2 is a schematic block diagram illustrating a portion of a PMU including a bandgap reference generator and a DC-DC converter according to an embodiment of the present disclosure;

[0014] Figure 3 is shown for operation Figure 1 and / or Figure 2 A flow chart of a method of a PMU and a DC-DC converter;

[0015] Figure 4 Shows Figure 1 and Figure 2 timing diagrams of signals in a DC-DC converter, and graphs of various currents and voltages generated by the DC-DC converter;

[0016] Figure 5A is a block diagram illustrating a battery-powered portable electronic device for which the PMU and methods of the present disclosure are particularly useful; and

[0017] Figure 5B FIG. 1 is a diagram showing a main reference generator and a DC-DC converter according to an embodiment of the present disclosure. Figure 5B Block diagram of the details of the PMU. DETAILED DESCRIPTION

[0018] A power management unit (PMU) and / or a DC-DC converter for improving efficiency in a sleep mode or window mode is provided. In short, the DC-DC converter includes a capacitor charging switch reference (SR) coupled to a low-side comparator, and the DC-DC converter is operable to isolate the SR from a low voltage reference (Vref_low) generator during the idle period of the window mode, and suspend the operation of all circuits and devices except the low-side comparator. By providing a local SR to the comparator and suspending the operation of all circuits and devices except the low-side comparator, the duration or time length of the idle period in the window mode is extended relative to the burst period, reducing the current / power consumption of the DC-DC converter during the window mode.

[0019] In the following description, for the purpose of illustration, many specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be practiced without these specific details. In other cases, in order to avoid unnecessarily obscuring the understanding of this specification, well-known structures and techniques are not shown in detail or are shown in block diagram form.

[0020] References in the specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in different places in the specification do not necessarily all refer to the same embodiment. The term coupling as used herein may include both directly electrically connecting two or more parts or elements and indirectly connecting two or more parts or elements through one or more intermediate parts.

[0021] Figure 1 1 is a schematic block diagram showing a portion of a power management unit (PMU 100) including a DC-DC converter 102, a main reference generator 104, and a regulation rail 106 coupled to an output 108 of the DC-DC converter through an inductor (L). An output capacitor (CO) coupled in parallel with a load between the regulation rail 106 and the negative terminal of a battery or power source 110 provides a reference voltage (Vref) on the regulation rail when the PMU is in active mode and sleep mode.

[0022] Reference Figure 1 , the main reference generator 104 may include, for example, a bandgap reference generator, and is configured or operable to receive a bandgap enable signal (en_bg) and provide various voltage references and current references to the DC-DC converter 102. These references may include a positive quiescent drain voltage (vdd), a negative quiescent source voltage (vss), and a main reference voltage (Vref_bg).

[0023] The DC-DC converter 102 typically includes: a low reference voltage (Vref_low) generator 112 coupled to a window logic circuit 116 via a low-side comparator 114; a high reference voltage (Vref_high) generator 118 coupled to the window logic circuit via a high-side comparator 120; and a driver logic circuit 122, which is coupled to the window logic circuit and is configured or operable to drive the circuit to alternately drive a first transistor 124 and a second transistor 126 to charge an inductor L and an output capacitor CO, thereby providing Vref to the load, wherein the output 108 of the DC-DC converter is coupled to a PMOS of a positive voltage (vdd) via the first transistor 124, and the output 108 is coupled to an NMOS of a negative voltage (vss) via the second transistor 126. Typically, the DC-DC converter 102 also includes: a peak current detector (PCD 128) coupled to the output 108 and to the window logic circuit 116, the PCD being operable to detect a peak current through the inductor L and transmitting a pkdet signal to the window logic circuit; and a zero current detector (ZCD 130) coupled to the output and the window logic circuit, the ZCD being operable to detect a minimum current or zero current through the inductor L and transmitting a zerol signal to the window logic circuit.

[0024] When PMU 100 operates in active mode, all circuits and devices in DC-DC converter 102 are powered and operate normally to receive a main reference voltage (Vref_bg) and provide a reference voltage (Vref) on regulation rail 106 coupled to output 108 of the DC-DC converter.

[0025] The Vref_low generator 112 is coupled to the main reference generator 104 and is operable to receive Vref_bg therefrom and generate a plurality of voltage references and current references for use in the DC-DC converter 102, including a low reference voltage (Vref_low) coupled to a capacitor charging switch reference (SR) connected to a first non-inverting input of a low-side comparator 114 via a switch S1. The operation of the Vref_low generator 112 is controlled by a first demultiplexer or combinational logic element 132 based on an enable SR signal (en_SR) and an enable window mode signal (en_window) from the PMU 100. The switch S1 is controlled by a second combinational logic element 134 based on the en_SR signal and the en_window signal from the PMU 100 and is normally closed during active mode to allow Vref_low to be stored on SR.

[0026] The window logic circuit 116 generates a duty cycle signal (duty_cycle) and couples it to the driver logic circuit 122. The driver logic circuit 122 is coupled to each of the first transistor 124 and the second transistor 126 through a level shifter (LS) and a buffer or a gate driver (GD), and is operable to alternately drive the first transistor and the second transistor. When the peak inductor current is sensed, the PCD 128 provides a pkdet signal to the window logic circuit 116, and when zero inductor current is sensed, the ZCD 130 provides a zerol signal to the window logic circuit, so that the window logic circuit provides duty_cycle to the driver logic circuit 122 to provide a slightly fluctuating active mode reference voltage Vref synchronized with the inductor current at the output 108 on the output capacitor CO.

[0027] When the PMU 100 enters a sleep mode after a predetermined period of inactivity in an electronic device including the PMU or in response to a user command, a window mode enable signal (en_window) is generated and coupled to the DC-DC converter 102, thereby placing the DC-DC converter 102 in a window mode. When the DC-DC converter 102 initially enters the window mode, it operates in a coasting period in which the operation of all circuits and devices in the DC-DC converter except the low-side comparator 114 is suspended. In particular, the first combinational logic element 132 receives the en_SR signal and the en_window signal and suspends the operation of the Vref_low generator 112, and the second combinational logic element 134 receiving the same signal operates the switch S1 to decouple the SR from the Vref_low generator 112.

[0028] During the coasting period, the low-side comparator 114 continues to operate to sense changes in Vref as the regulation rail discharges through the load by comparing Vref_low stored on SR with a feedback voltage (Vfb) coupled from the regulation rail through a resistor-capacitor (RC) network or filter 136 and proportional to Vref. When Vfb is less than or equal to Vref_low, the low-side comparator 114 outputs a low voltage signal (VL) to the window logic circuit 116.

[0029] In response to VL, the window logic circuit 116 generates a burst enable signal (en_burst) and couples it to substantially all circuits and devices in the DC-DC converter 102, thereby causing the DC-DC converter 102 to enter a burst period. During the burst period, the circuits and devices in the DC-DC converter 102 (including the Vref_low generator 112, the window logic circuit 116, the Vref_high generator 118, the high-side comparator 120, the driver logic circuit 122, the PCD 128, and the ZCD 130) resume operation and begin charging the inductor L and the output capacitor CO, thereby raising the Vref on the regulation rail 106 from a low voltage substantially equal to Vref_low to a high reference voltage (Vref_high).

[0030] In addition, the en_burst signal is coupled to the first combinatorial logic element 132 to control the Vref_low generator 112 to resume operation, and the en_burst signal is coupled to the second combinatorial logic element 134 to operate the switch S1 to couple SR to the Vref_low generator 112 to recharge the Vref_low stored on SR.

[0031] During the burst period, the high-side comparator 120 operates to sense the rising Vref on the regulation rail 106 by comparing Vref_high coupled from the Vref_high generator 118 with a feedback voltage (Vfb) coupled from the regulation rail through the RC filter 136. When Vfb is equal to Vref_high, the high-side comparator 120 outputs a high voltage signal (VH) to the window logic circuit 116, causing it to terminate the en_burst signal and cause the DC-DC converter 102 to resume or re-enter the freewheeling period, in which the operation of all circuits and devices except the low-side comparator is suspended, and the switch S1 is opened to decouple SR from the Vref_low generator 112.

[0032] Figure 2 is a schematic block diagram illustrating another embodiment of a portion of a PMU 200 including a bandgap or main reference generator that can be isolated from a DC-DC converter and whose operation can be suspended during a sleep mode. Figure 2 , except that it is basically the same as above Figure 1In addition to the DC-DC converter 202, which is the same as the DC-DC converter described above, the PMU 200 also includes a bandgap or main reference generator 204, the operation of which can be suspended in the window mode, and the bandgap or main reference generator 204 can be isolated from the DC-DC converter by a switch S0. The operation of the main reference generator 204 is controlled by the PMU 200 and the DC-DC converter 202 through a third combinational logic element 206, and the switch S0 is controlled by the PMU and the DC-DC converter through a fourth combinational logic element 208.

[0033] In the active mode, the third combinational logic element 206 receives the high bandgap enable signal (en_bg) and the low window mode enable signal (en_window) from the PMU 200, and receives the low enable burst signal (en_burst) from the DC-DC converter 202, and the main reference generator 204 is operated to provide various voltage references and current references to the DC-DC converter. These references may include: a positive reference voltage or drain reference voltage (vdd), a negative reference voltage or source reference voltage (vss), and a main reference voltage (Vref_bg), which is coupled to the Vref_bg capacitor 210 through the switch S0 to form a capacitively charged bandgap reference (BG) coupled to the Vref_low generator (not shown in this figure) in the DC-DC converter 202. The switch S0 is normally closed during the active mode and during the burst period in the window mode to charge the Vref_bg capacitor 210 to Vref_bg.

[0034] When the PMU 200 enters the sleep mode, a high en_window (window mode enable signal) from the PMU to the third combinatorial logic element 206 suspends the operation of the main reference generator 204 and causes the fourth combinatorial logic element 208 to operate the switch S0 open to isolate the main reference generator 204 from the DC-DC converter 202. Substantially simultaneously, the DC converter 202 enters the window mode in response to the high en_window, and when the regulation rail has been discharged through the load after the freewheeling period so that the feedback voltage (Vfb) from the regulation rail is less than or equal to the low reference voltage (Vref_low), the DC-DC converter 202 enters the burst period, and the window logic circuit (not shown in this figure) generates a high en_burst (enable burst signal) and couples it to the third combinatorial logic element 206 and the fourth combinatorial logic element 210. High en_burst causes the third combinatorial logic element 206 to resume the operation of the main reference generator 204 and causes the fourth combinatorial logic element 210 to close the switch S0 , through which Vref_bg is coupled to the DC-DC converter 202 .

[0035] Now refer to Figure 3 and Figure 4 A method for operating a PMU including a switched main reference generator and a DC-DC converter with a switched reference (SR) for capacitor charging is described, wherein Figure 3 is shown for operation Figure 1 and Figure 2 A flow chart of a method of a PMU and a DC-DC converter, and Figure 4 Included are timing diagrams of signals in a DC-DC converter and graphs showing the various currents and voltages generated in the DC-DC converter.

[0036] Reference Figure 3 and Figure 4 , the method begins at time (t0) when the PMU operates in active mode, generates a main reference voltage (Vref_bg) and couples it to the DC-DC converter, and operates the DC-DC converter to provide a regulated reference voltage (Vref 402) on a regulation rail coupled to the DC-DC converter (step 302). At this time, the bandgap enable signal (en_bg 404) and the SR enable signal (en_SR 406) are both high, so the first switch (S0) is closed or operable to couple Vref_bg to the DC-DC converter, and the second switch (S1) is closed or operable to couple SR to the Vref_low generator. From time t0 to t1, all circuits and devices in the main voltage reference generator and the DC-DC converter operate normally, wherein the window logic circuit provides a duty window or duty cycle signal (duty_cycle 408) to the driver logic circuit, and operates the driver logic circuit to alternately drive the first transistor and the second transistor to provide an inductor current 410 that varies between a peak detection current (pkdet) and a zero current (zerol). During this period, the DC-DC converter operates in an active mode, wherein Vref 402 is higher than an active mode reference voltage (Vref_active-mode 412) on the output capacitor that fluctuates slightly in sync with the inductor current 410.

[0037] At time t1, the PMU enters sleep mode after a predetermined period of inactivity or a user command, and generates and couples a window mode enable signal (en_window 414) to the DC-DC converter to place the DC-DC converter in window mode, and Figure 4In the case of the configuration in , the window mode enable signal (en_window 414) is coupled to the main reference generator and the first switch (S0), and Vref_bg is coupled to the DC-DC converter through the first switch (S0) (step 304). Initially, the DC-DC converter is placed or operated in the idle period of the window mode, during which Vref_bg is decoupled from the DC-DC converter, SR is decoupled from the Vref_low generator, and the operation of all circuits and devices in the main reference generator and the DC-DC converter except the low-side comparator is suspended (step 306). As described above, during the idle period, the regulation rail is allowed to discharge through one or more loads coupled thereto, and the inductor and output capacitor provide any necessary Vref to the one or more loads.

[0038] Next, from time t1 to t2, the feedback voltage (Vfb) from the regulation rail is compared to the low reference voltage (Vref_low 416) on the SR using a low-side comparator, and when Vfb is less than or equal to Vref_low at time t2, a low voltage signal (VL 418) is output to the window logic circuit (step 308). In response to VL418, the window logic circuit starts the burst period by generating an enable burst signal (en_burst 420) and sending it to other circuits and devices in the DC-DC converter, and generating duty_cycle 408 and sending it to the driver logic circuit (step 310). During the burst period, all circuits and devices in the DC-DC converter are restarted or restored, as well as in the case of Figure 4 The operation of the main reference generator in the case of the configuration in FIG. The driver logic circuit operates to alternately drive the first transistor and the second transistor to provide an inductor current 410 that varies between a peak detection current (pkdet) and a zero current (zerol) to charge the inductor and the output capacitor, thereby raising the Vref on the regulation rail. Also during the burst period, the main reference voltage (Vref_bg) is coupled to the Vref_low generator in the DC-DC converter through the first switch, and the SR is coupled to the Vref_low generator through the second switch to charge the SR and restore the voltage to Vref_low.

[0039] During the burst period from time t2 to t3, the feedback voltage (Vfb) from the regulation rail is compared to the high reference voltage (Vref_high 422) from the Vref_high generator using a high-side comparator, and when Vfb is equal to or greater than Vref_high, the high-side comparator outputs a high voltage signal (VH 424) to the window logic circuit to stop generating and sending the en_burst 420 signal and the duty_cycle 408 signal, ending or terminating the burst period at time t3, and decoupling the SR from the Vref_low reference generator, and decoupling the Vref_low reference generator from the main reference generator, thereby starting or returning to the second idle period (step 312).

[0040] exist Figure 4 In the second freewheeling period shown in FIG. 1 extending from time t3 to t4, the first switch (S0) is operated to isolate the main reference generator from the DC-DC converter, the second switch (S1) is operated to decouple the SR from the Vref_low generator, and the main reference generator (wherein Figure 4 The configuration shown) and the operation of all circuits and devices in the DC-DC converter except the low-side comparator are suspended.

[0041] After the second coasting period begins, the method continues from step 308 where Vfb is compared to Vref_low on SR using a low-side comparator while allowing the regulation rail to discharge, supply or provide Vref 402 to one or more loads. Figure 4 In an embodiment, the second coasting period is followed by a subsequent burst period from time t4 to t5, and then by a subsequent coasting period from time t5 to t6.

[0042] The method continues until the PMU “wakes up”, terminating the en_window 414 signal and returning the DC-DC converter to active mode.

[0043] It will be appreciated that by suspending operation of all circuits and devices in the main reference generator and DC-DC converter except the low-side comparator, the coasting period is extended and the static, quiescent current consumed in the DC-DC converter is reduced when the PMU is in sleep mode.

[0044] It will also be understood that the combinational logic elements 132, 134 and 206, 208 function so that en_burst 420 operates the first switch (S0) and the second switch (S1), the Vref_low generator, and the main reference generator only during window mode. There is no need to remove the en_window 414 signal (or make it low) during the burst period, nor is it necessary to apply the en_burst 420 signal during active mode to operate the Vref_low generator and the main reference generator, or close the first switch (S0) and the second switch (S1). In addition, the output of the low-side comparator 114 can be extended to the duty cycle or pause operation of any other always-on (AON) function in the entire chip during window mode, and therefore the methods described herein are not limited to circuits in only PMUs 100, 200.

[0045] 5 is a block diagram illustrating a battery-powered portable electronic device for which the PMU and methods of the present disclosure are particularly useful. The electronic device 500 may include a wireless Internet of Things (IoT) device, an implantable medical device, or a wearable device. Common types of wearable devices include smart watches, smart glasses, and activity trackers. The electronic device 500 typically includes or is coupled to a battery 502 that has limited stored energy and requires frequent recharging or replacement. Therefore, it is desirable that the electronic device 500 include a PMU 504, such as the PMU described above, that is capable of significantly reducing the static, quiescent current in a DC-DC converter (not shown in this figure) in sleep mode to extend the battery replacement or recharging interval.

[0046] Reference Figure 5A In addition to the battery 502 and the PMU 504, the electronic device 500 typically includes a plurality of sensors and / or actuators (collectively referred to as 506) for detecting and responding to the collected information, a processor and memory 508 for analyzing and recording the collected information, and a user interface 510, such as a transmitter, display, or audio alarm, for providing information or feedback to the user.

[0047] Figure 5B It is shown Figure 5A5 is a block diagram of the details of the PMU 504, which includes a main reference generator 512, one or more DC-DC converters 514, and a controller or control logic 516. As described above, in active mode, the main reference generator 512 generates a main voltage reference (Vref_bg) and provides it to (one or more) DC-DC converters 514, and the DC-DC converters receive Vref_bg and provide a reference voltage (Vref) on a regulation rail. When the PMU 504 enters a sleep mode after a predetermined period of inactivity in the electronic device 500 or in response to a user command, the control logic 516 generates a window mode enable signal (en_window) and couples it to the main reference generator 512 and / or the DC-DC converter 514 to place the DC-DC converter in a window mode that exhibits an ultra-low quiescent current.

[0048] Thus, a PMU including a DC-DC converter and a method of operating the same have been disclosed to reduce static, quiescent current during sleep mode. Embodiments of the present invention have been described above with the aid of functional block diagrams and schematic block diagrams illustrating implementations of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for ease of description. Alternative boundaries may be defined as long as the specified functions and relationships thereof are appropriately performed.

[0049] The foregoing description of specific embodiments will so fully reveal the general nature of the invention that others can easily modify such specific embodiments and / or adapt them to various applications without undue experimentation by applying knowledge within the art without departing from the overall concept of the invention.

[0050] It should be understood that the Detailed Description section, rather than the Summary and Abstract sections, is intended to be used to interpret the claims. The Summary and Abstract sections may set forth one or more, but not all, exemplary embodiments of the invention contemplated by the inventors, and therefore, are not intended to limit the invention and the appended claims in any way.

[0051] The breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A method of operating a DC-DC converter in window mode, the method comprising: A window mode enable (en_window) signal is received in the DC-DC converter, and during a coasting period: A switch is opened, through which a low reference voltage (Vref_low) generator is coupled to a switched reference (SR) charged by a capacitor on a first input of a low-side comparator; Suspending the operation of all circuits and devices in the DC-DC converter including the Vref_low generator except the low-side comparator; comparing the SR to a feedback voltage (Vfb) coupled to a second input of the low-side comparator from a reference voltage (Vref) on a regulation rail coupled to an output of the DC-DC converter; as well as By comparing the SR to the Vfb, changes in the Vref on the regulation rail are sensed as the regulation rail is discharged through a load coupled to the regulation rail.

2. The method according to claim 1, further comprising: When Vref has decreased to the Vref_low stored on the SR, the low voltage signal (V L ) is coupled from the output of the low-side comparator to a window logic circuit, in which a burst enable (en_burst) signal is generated to at least some of the circuits and devices in the DC-DC converter including the Vref_low generator, and operations of all of the circuits and devices in the circuits and devices are restored during a burst period, and an inductor and an output capacitor are charged, the regulation rail being coupled to the output of the DC-DC converter through the inductor and the output capacitor to increase the Vref on the regulation rail from Vref_low to a high reference voltage (Vref_high).

3. The method according to claim 2, further comprising: The switch through which the Vref_low generator is coupled to the SR is closed in response to an en_burst signal coupled to the Vref_low generator, and the SR is recharged to Vref_low.

4. The method according to claim 3, wherein: Operating the DC-DC converter during the burst period also includes: operating the window logic circuit to generate a duty cycle (duty_cycle) signal, coupling the en_burst signal and the duty_cycle signal to a driver logic circuit, and operating the driver logic circuit to alternately drive a first transistor and a second transistor to charge the inductor and an output capacitor, thereby raising the Vref from Vref_low to Vref_high, wherein the output of the DC-DC converter is coupled to a positive voltage (VDD) through the first transistor, and the output is coupled to a negative voltage (VSS) through the second transistor.

5. The method according to claim 3, wherein: The circuits and devices in the DC-DC converter include a high-side comparator including a first input coupled to receive Vfb from the regulation rail, a second input coupled to a Vref_high generator, and a high-side comparator output coupled to the window logic circuit, and wherein operating the DC-DC converter in the burst period further includes: comparing the Vfb with the Vref_high, and outputting a high voltage signal (Vfb) to the window logic circuit when the Vfb is equal to or greater than the Vref_high. H ) to terminate the en_burst signal, suspend the operation of all circuits and devices in the DC-DC converter except the low-side comparator, disconnect the switch through which the Vref_low generator is coupled to the SR, and return to the idling period.

6. The method according to claim 3, wherein: Operating the DC-DC converter in window mode also includes receiving an SR enable (en_SR) signal, and wherein the en_SR signal, the en_window signal, and the en_burst signal are coupled to the switch via a first combinational logic element, the first combinational logic element being operable to open the switch when only the en_SR signal and the en_window signal are present, and to close the switch when the en_SR signal, the en_window signal, and the en_burst signal are all present.

7. The method according to claim 6, wherein: The en_SR signal, the en_window signal, and the en_burst signal are coupled to the Vref_low generator via a second combinational logic element, which is operable to suspend the operation of the Vref_low generator when only the en_SR signal and the en_window signal are present, and to resume the operation of the Vref_low generator when the en_SR signal, the en_window signal, and the en_burst signal are all present.

8. A method of operating a power management unit (PMU) in a windowed mode, the method comprising: A window mode enable (en_window) signal is received in a DC-DC converter and a main reference generator in the PMU, and during a coasting period: The first switch (S0) is opened, the main reference generator is coupled to the capacitor-charged bandgap reference (BG) through the first switch, and the capacitor-charged bandgap reference (BG) is coupled to the low reference voltage (Vref_low) generator in the DC-DC converter; In the DC-DC converter, a second switch (S1) is opened, and the Vref_low generator is coupled to a switched reference (SR) charged by a capacitor on a first input of a low-side comparator via the second switch; suspending the operation of all circuits and devices in the main reference generator and the DC-DC converter, including the Vref_low generator, except the low-side comparator; comparing the Vref_low stored on the SR with a feedback voltage (Vfb) coupled to a second input of the low-side comparator from a reference voltage (Vref) on a regulation rail coupled to an output of the DC-DC converter; as well as By comparing the SR to the Vfb, changes in the Vref on the regulation rail are sensed as the regulation rail is discharged through a load coupled to the regulation rail.

9. The method according to claim 8, further comprising: When Vref has decreased to the Vref_low stored on the SR, the low voltage signal (V L ) is coupled from the output of the low-side comparator to a window logic circuit, in which a burst enable (en_burst) signal is generated to at least some of the circuits and devices in the DC-DC converter including the Vref_low generator, and in a burst period, operations of the main reference generator and all of the circuits and devices in the circuits and devices are restored, and an inductor and an output capacitor are charged, through which the regulation rail is coupled to the output of the DC-DC converter to increase the Vref on the regulation rail from Vref_low to a high reference voltage (Vref_high).

10. The method according to claim 9, further comprising: Closing switches S0 and S1 in response to the en_burst signal recharges the BG to a main reference voltage (Vref_bg) and recharges the SR to Vref_low.

11. The method according to claim 10, wherein: Operating the DC-DC converter during the burst period also includes: operating the window logic circuit to generate a duty cycle signal (duty_cycle), coupling the en_burst signal and the duty_cycle signal to a driver logic circuit, and operating the driver logic circuit to alternately drive a first transistor and a second transistor to charge the inductor and an output capacitor, thereby raising the Vref from Vref_low to Vref_high, wherein the output of the DC-DC converter is coupled to a positive voltage (VDD) through the first transistor, and the output is coupled to a negative voltage (VSS) through the second transistor.

12. The method according to claim 10, wherein: The circuits and devices in the DC-DC converter include a high-side comparator including a first input coupled to receive Vfb from the regulation rail, a second input coupled to a Vref_high generator, and a high-side comparator output coupled to the window logic circuit, and wherein operating the DC-DC converter in the burst period further includes: comparing the Vfb with the Vref_high, and outputting a high voltage signal (Vfb) to the window logic circuit when the Vfb is equal to or greater than the Vref_high. H ) to terminate the en_burst signal, suspend the operation of all circuits and devices in the DC-DC converter except the low-side comparator, turn off switches S0 and S1, and return to the coasting period.

13. The method according to claim 12, wherein: Operating the DC-DC converter in window mode also includes: receiving an SR enable (en_SR) signal, and wherein the en_SR signal, the en_window signal, and the en_burst signal are coupled to S0 through a first combinational logic element and to S1 through a second combinational logic element, the first combinational logic element being operable to disconnect S0 when only the en_SR signal and the en_window signal are present, and to close S0 when the en_SR signal, the en_window signal, and the en_burst signal are all present, and the second combinational logic element being operable to disconnect S1 when only the en_SR signal and the en_window signal are present, and to close S1 when the en_SR signal, the en_window signal, and the en_burst signal are all present.

14. The method according to claim 13, wherein: The en_SR signal, the en_window signal and the en_burst signal are coupled to the main reference generator through a third combinational logic element, and are coupled to the Vref_low generator through a fourth combinational logic element, and wherein the third combinational logic element is operable to suspend the operation of the main reference generator when only the en_SR signal and the en_window signal are present, and to resume the operation of the main reference generator when the en_SR signal, the en_window signal and the en_burst signal are all present, and the third combinational logic element is operable to suspend the operation of the Vref_low generator when only the en_SR signal and the en_window signal are present, and to resume the operation of the Vref_low generator when the en_SR signal, the en_window signal and the en_burst signal are all present.

15. A power management unit (PMU), comprising: DC-DC converters, It is operable to provide a reference voltage (Vref) on a regulation rail coupled to an output of the DC-DC converter, the DC-DC converter comprising: a low reference voltage (Vref_low) generator operable to generate a low reference voltage (Vref_low); a capacitively charged switched reference (SR) coupled to said Vref_low generator via a first switch (S1) and operable to receive and store said Vref_low; and a low-side comparator having a first input coupled to the SR and a second input coupled to receive a feedback voltage (Vfb) from the Vref on the regulation rail, Wherein, the DC-DC converter is operable to receive a window mode enable (en_window) signal and, during a coasting period: turn off the first switch; suspend operation of all circuits and devices in the DC-DC converter except the low-side comparator; and compare the Vref_low stored on the SR with the Vfb to sense changes in the Vref on the regulation rail when the regulation rail is discharged through a load coupled to the regulation rail.

16. The PMU of claim 15, wherein: The low-side comparator is operable to output a low voltage signal (V L ), and the PMU further comprises a window logic circuit coupled to the output of the low-side comparator, the window logic circuit being operable to generate a burst enable (en_burst) signal to at least some of the circuits and devices in the DC-DC converter, thereby initiating a burst period, causing the first switch (S1) to close to recharge the SR to Vref_low, and causing all of the circuits and devices in the circuits and devices to resume operation to charge an inductor and an output capacitor, the regulation rail being coupled to the output of the DC-DC converter through the inductor and the output capacitor, thereby raising the Vref on the regulation rail from Vref_low to a high reference voltage (Vref_high).

17. The PMU of claim 16, wherein: The window logic circuit is also operable to generate a duty cycle (duty_cycle) signal during the burst period, and the PMU further comprises a driver logic circuit coupled to the window logic circuit, the driver logic circuit being operable to receive the en_burst signal and the duty_cycle signal and alternately drive a first transistor and a second transistor to charge the inductor and the output capacitor, thereby raising the Vref from Vref_low to Vref_high, wherein the output of the DC-DC converter is coupled to a positive voltage (VDD) through the first transistor, and the output is coupled to a negative voltage (VSS) through the second transistor.

18. The PMU of claim 16, wherein: The circuit and device in the DC-DC converter include a high-side comparator, the high-side comparator including a first input coupled to receive Vfb from the regulation rail, a second input coupled to a high reference voltage (Vref_high) generator to receive a high reference voltage (Vref_high) therefrom, and a high-side comparator output coupled to the window logic circuit, and wherein the high-side comparator is operable to compare the Vfb with Vref_high during the burst period, and is operable to output a high voltage signal (Vref_high) to the window logic circuit when the Vfb is equal to or greater than the Vref_high. H ) to terminate the en_burst signal, suspend the operation of all circuits and devices in the DC-DC converter except the low-side comparator, and turn off the first switch (S1) to return to the coasting period.

19. The PMU of claim 16, wherein: The DC-DC converter is also operable to receive an SR enable (en_SR) signal in window mode, and wherein the DC-DC converter further comprises a first combinational logic element, the en_SR signal, the en_window signal and the en_burst signal being coupled to the first switch (S1) through the first combinational logic element, the first combinational logic element being operable to open the first switch (S1) in window mode when only the en_SR signal and the en_window signal are present, and to close the first switch (S1) when the en_SR signal, the en_window signal and the en_burst signal are all present.

20. The PMU of claim 19, wherein: The DC-DC converter also includes a second combinational logic element, and the en_SR signal, the en_window signal and the en_burst signal are coupled to the Vref_low generator through the second combinational logic element, and the second combinational logic element is capable of operating to suspend the operation of the Vref_low generator in the window mode when only the en_SR signal and the en_window signal are present, and to resume the operation of the Vref_low generator when the en_SR signal, the en_window signal and the en_burst signal are all present.

21. The PMU of claim 20, further comprising: a main reference generator coupled to a capacitively charged bandgap reference (BG) via a second switch (S0), the BG coupled to the Vref_low generator in the DC-DC converter, and wherein the PMU further comprises a third combinational logic element, the en_SR signal, the en_window signal and the en_burst signal are coupled to the second switch (S0) via the third combinational logic element, the third combinational logic element being operable to open the second switch (S0) in window mode when only the en_SR signal and the en_window signal are present, and to close the second switch (S0) when the en_SR signal, the en_window signal and the en_burst signal are all present.

22. The PMU of claim 21, wherein: The PMU also includes a fourth combinational logic element, through which the en_SR signal, the en_window signal and the en_burst signal are coupled to the main reference generator, and wherein the fourth combinational logic element is operable to suspend the operation of the main reference generator in the window mode when only the en_SR signal and the en_window signal are present, and to resume the operation of the main reference generator when the en_SR signal, the en_window signal and the en_burst signal are all present.

Images