Memory structure and forming method thereof, memory circuit and working method thereof

Abstract

The invention discloses a memory structure and a forming method thereof, a memory circuit and a working method thereof. The memory cell structure comprises a first selection gate, a second selection gate, an erase gate located between the first selection gate and the second selection gate, a first floating gate located between the erase gate and the first selection gate, a second floating gate located between the erase gate and the second selection gate, and a first control gate located on the first floating gate, the first control gate is located on the first floating gate, the second control gate is located on the second floating gate, a first channel region is arranged in the substrate at the bottom of the first selection gate, a second channel region is arranged in the substrate at the bottom of the second selection gate, and the turn-on voltage of the first channel region is different from that of the second channel region; the source doped region is positioned in the substrate at the bottom of the erasing gate; the drain electrode doping regions are respectively positioned in the substrate at two sides of the storage unit structure; and the word line electric connection structures electrically connect the first selection gates and the second selection gates of the adjacent storage unit structures respectively, so that the storage density is improved, and meanwhile, the writing time is shortened.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a storage structure and a forming method thereof, a memory circuit and a working method thereof. Background Art

[0002] Flash memory is a non-volatile memory that can retain data for a long time even without current supply, that is, data will not be lost even when power is off. Floating gate flash memory is widely used in various embedded electronic products such as financial IC cards, automotive electronics, etc. because it helps save chip area and improve storage integration density.

[0003] The existing floating gate flash memory structure usually includes an erase gate, a control gate and a floating gate. The control gate is located on the floating gate and is isolated by a dielectric layer. The erase gate is located between two pairs of control gates and floating gates and is a common erase gate. The two word lines are located on both sides of the two pairs of control gates and floating gates and are isolated by a dielectric layer. The oxide layer between the erase gate and the floating gate is a tunnel dielectric layer.

[0004] Usually, a storage unit can only store one bit, that is, a binary number "0" or "1". For an 8-BIT mode flash memory, one byte of data requires three storage units to store 0 to 7. Therefore, the existing flash memory structure has a low storage density. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a storage structure and a forming method thereof, a memory circuit and a working method thereof, so as to improve the performance of the formed storage structure.

[0006] To solve the above technical problems, the technical solution of the present invention provides a storage structure, including: a substrate; a plurality of storage cell structures located on the substrate, the storage cell structure including a first selection gate, a second selection gate, an erase gate located between the first selection gate and the second selection gate, a first floating gate located between the erase gate and the first selection gate, a second floating gate located between the erase gate and the second selection gate, a first control gate located on the first floating gate, and a second control gate located on the second floating gate, a first channel region is provided in the substrate at the bottom of the first selection gate, a second channel region is provided in the substrate at the bottom of the second selection gate, and a turn-on voltage of the first channel region is different from a turn-on voltage of the second channel region; a source doped region in the substrate at the bottom of the erase gate; a drain doped region in the substrate respectively located on both sides of the storage cell structure; and a word line electrical connection structure, which electrically connects the first selection gate and the second selection gate of adjacent storage cell structures respectively.

[0007] Optionally, a well region is provided in the substrate, and the source doping region and the drain doping region are both located in the well region; the doping ion concentrations in the well region under the first selection gate and the second selection gate are different; the doping ions include conductive ions, and the conductive ions include one or both of N-type conductive ions and P-type conductive ions.

[0008] Optionally, it also includes: a first tunnel oxide layer located between the first selection gate and the substrate; a second tunnel oxide layer located between the second selection gate and the substrate; one or both of the thickness and dielectric constant value of the first tunnel oxide layer and the second tunnel oxide layer are different.

[0009] Optionally, the first selection gate and the second selection gate have different widths.

[0010] Optionally, several of the storage cell structures are arranged in an array along a first direction; the storage structure also includes: several word lines arranged along the first direction, one of the word lines being electrically connected to the word line electrical connection structure located in the same column in the storage structure; several source lines arranged along the first direction, one of the source lines being electrically connected to the source doping region located in the same column in the storage structure; and several bit lines arranged along a second direction, the second direction being perpendicular to the first direction, one of the bit lines being electrically connected to the drain doping region located in the same row in the storage structure.

[0011] Correspondingly, the technical solution of the present invention also provides a method for forming a storage structure, comprising: providing a substrate; forming a plurality of storage cell structures on the substrate, the storage cell structure comprising a first selection gate, a second selection gate, an erase gate located between the first selection gate and the second selection gate, a first floating gate located between the erase gate and the first selection gate, a second floating gate located between the erase gate and the second selection gate, a first control gate located on the first floating gate, and a second control gate located on the second floating gate, a first channel region being provided in the substrate at the bottom of the first selection gate, a second channel region being provided in the substrate at the bottom of the second selection gate, and a turn-on voltage of the first channel region being different from a turn-on voltage of the second channel region; forming a source doping region in the substrate at the bottom of the erase gate; forming drain doping regions in the substrate at both sides of the storage cell structure respectively; forming a word line electrical connection structure on the substrate, the word line electrical connection structure electrically connecting the first selection gate and the second selection gate of adjacent storage cell structures respectively.

[0012] Optionally, a well region is provided in the substrate, and the source doping region and the drain doping region are both located in the well region; the doping ion concentrations in the well region under the first selection gate and the second selection gate are different; the method for forming the well region comprises: forming an initial well region in the substrate; injecting doping ions into part of the initial well region to form a well region with different doping concentration distributions, the doping ions comprising conductive ions, and the conductive ions comprising one or both of N-type conductive ions and P-type conductive ions.

[0013] Optionally, it also includes: forming a first tunnel oxide layer between the substrate and the first selection gate; forming a second tunnel oxide layer between the second selection gate and the substrate; one or both of the thickness and dielectric constant value of the first tunnel oxide layer and the second tunnel oxide layer are different.

[0014] Optionally, the first selection gate and the second selection gate have different widths.

[0015] Optionally, several of the storage cell structures are arranged in an array along a first direction; after forming the word line electrical connection structure, it also includes: forming several word lines arranged along the first direction, one of the word lines is electrically connected to the word line electrical connection structure located in the same column in the storage structure; forming several source lines arranged along the first direction, one of the source lines is electrically connected to the source doping region located in the same column in the storage structure; forming several bit lines arranged along a second direction, the second direction is perpendicular to the first direction, and one of the bit lines is electrically connected to the drain doping region located in the same row in the storage structure.

[0016] Correspondingly, the technical solution of the present invention also provides a memory circuit, comprising: a plurality of memory cells arranged in an array, each memory cell comprising a first multi-gate transistor, a second multi-gate transistor, an erase gate, a source, a first drain, and a second drain, the first multi-gate transistor comprising a first floating gate, a first control gate coupled to the first floating gate, and a first selection gate for controlling the first multi-gate transistor to be turned on, the second multi-gate transistor comprising a second floating gate, a second control gate coupled to the second floating gate, and a second selection gate for controlling the second multi-gate transistor to be turned on, and the threshold voltage of the second multi-gate transistor is greater than the threshold voltage of the first multi-gate transistor, the erase gate is coupled to the first floating gate and the second floating gate, the source is a common end of the first multi-gate transistor and the second multi-gate transistor, the first drain is the other end of the first multi-gate transistor, and the second drain is the other end of the second multi-gate transistor; a plurality of word line nodes, each word line node is electrically connected to the first selection gate and the second selection gate of adjacent memory cells in the same row; a word line is electrically connected to the word line node in the same column; a bit line is electrically connected to the first drain and the second drain of memory cells in the same row; and a source line is electrically connected to the source of memory cells in the same column.

[0017] Optionally, it also includes: a writing unit, used to apply a writing voltage to the word line node, and write logic 1 into one or both of the first floating gate and the second floating gate corresponding to the word line node.

[0018] Optionally, it also includes: a signal reading unit connected to the bit line, and used to read the storage state of the first floating gate and the second floating gate.

[0019] Correspondingly, the technical solution of the present invention also provides a method for forming the operation of the above-mentioned memory circuit, including: performing a write operation on two adjacent memory cells to be operated, and applying a write voltage to the word line node between the two adjacent memory cells; when the write voltage is greater than the threshold voltage of the first multi-gate transistor and less than the threshold voltage of the second multi-gate transistor, and the channel is opened by the first control gate and the channel is closed by the second control gate, a logic 1 is written to the first floating gate; when the write voltage is greater than the threshold voltage of the second multi-gate transistor and the channel is opened by the first control gate, a logic 1 is written to the first floating gate; when the write voltage is greater than the threshold voltage of the second multi-gate transistor and the channel is opened by the second control gate, a logic 1 is written to the second floating gate.

[0020] Optionally, after performing a write operation on two adjacent memory cells to be operated, a read operation is performed on the two adjacent memory cells; the read operation includes: applying a turn-on voltage to a word line node between the two adjacent memory cells, the turn-on voltage being greater than a threshold voltage of the second multi-gate transistor, and applying a first read voltage to the first control gate and the second control gate, respectively, grounding the source line, applying a second read voltage to the bit line, obtaining a read current of the bit line corresponding to the two adjacent memory cells, and obtaining the storage state of the two adjacent memory cells according to the size of the read current.

[0021] Optionally, it includes: before the reading operation, obtaining several reference current values; the method for obtaining the storage state of the two adjacent storage cells includes: comparing the reading current and each reference current value, obtaining the grading result of the reading current, and obtaining the total storage state of the first floating gate and the second floating gate in the two adjacent storage cells according to the grading result.

[0022] Optionally, it also includes: providing a reference voltage, the reference voltage is greater than the threshold voltage of the second multi-gate transistor; when the write voltage is greater than the threshold voltage of the second multi-gate transistor and lower than the reference voltage, performing a first write operation, the first write operation including: opening the channel through the first control gate and closing the channel through the second control gate, storing charges in the first floating gate, and not storing charges in the second floating gate; after the first write operation, performing the read operation to obtain a first read current; when the write voltage is greater than the reference voltage, performing a second write operation, the second write operation including: opening the channel through the first control gate and closing the channel through the second control gate, storing charges in the first floating gate, and not storing charges in the second floating gate; after the second write operation, performing the read operation to obtain a second read current; When the write voltage is greater than the threshold voltage of the second multi-gate transistor and lower than the reference voltage, a third write operation is performed, and the third write operation includes: opening the channel through the second control gate and closing the channel through the first control gate, storing charges in the second floating gate, and not storing charges in the first floating gate; after the third write operation, the read operation is performed to obtain a third read current; when the write voltage is greater than the reference voltage, a fourth write operation is performed, and the fourth write operation includes: opening the channel through the second control gate and closing the channel through the first control gate, storing charges in the second floating gate, and not storing charges in the second floating gate; after the fourth write operation, the read operation is performed to obtain a fourth read current; the grading results of the first read current, the second read current, the third read current and the fourth read current are different.

[0023] Optionally, it also includes: when the write voltage is greater than the threshold voltage of the second multi-gate transistor and lower than the reference voltage, a fifth write operation is performed, and the fifth write operation includes: opening the channel through the first control gate and opening the channel through the second control gate, and storing charges in the first floating gate and the second floating gate respectively; after the fifth write operation, the read operation is performed to obtain a fifth read current; when the write voltage is greater than the reference voltage, a sixth write operation is performed, and the sixth write operation includes: opening the channel through the first control gate and opening the channel through the second control gate, and storing charges in the first floating gate and the second floating gate respectively; after the sixth write operation, the read operation is performed to obtain a sixth read current; when the write voltage is greater than the threshold voltage of the first multi-gate transistor and lower than the second multi-gate The threshold voltage of the first multi-gate transistor is determined by the control gate to open the channel and the second control gate to close the channel, and the first floating gate is charged, while the second floating gate is not charged. After the seventh write operation, the read operation is performed to obtain a seventh read current. When the write voltage is less than the threshold voltage of the first multi-gate transistor, an eighth write operation is performed, and the eighth write operation includes: no charge is stored in both the first floating gate and the second floating gate. After the eighth write operation, the read operation is performed to obtain an eighth read current. The grading results of the first read current, the second read current, the third read current, the fourth read current, the fifth read current, the sixth read current, the seventh read current and the eighth read current are all different.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] In a storage structure provided by the technical solution of the present invention, the first selection gate and the second selection gate of adjacent storage cell structures are electrically connected through a word line electrical junction. Since the turn-on voltages of the first channel region and the second channel region are different, by controlling the magnitude of the voltage applied to the word line electrical junction structure, the first channel region and the second channel region can be simultaneously controlled to achieve different conduction states. In addition, the first channel region also needs to be controlled to be turned on by the first control gate, and the second channel region also needs to be controlled to be turned on by the second control gate. When the first channel region is turned on, electrons enter the first floating gate from the first channel region to achieve writing logic 1 on the first floating gate. When the second channel region is turned on, electrons enter the second floating gate from the second channel region to achieve writing logic 1 on the second floating gate. Therefore, by applying different voltages to the word line electrical structure, the first control gate and the second control gate, different combinations of write states of the first floating gate and the second floating gate can be achieved. The write state can include eight states. Therefore, two adjacent storage cells can store one byte of data. In addition, the first selection gate and the second selection gate of adjacent memory cell structures are electrically connected, so that two adjacent memory cells can be written at the same time, thereby improving the storage density and shortening the writing time. The first selection gate and the second selection gate of the adjacent memory cell structure are electrically connected through a word line electrical junction. Since the turn-on voltages of the first channel region and the second channel region are different, by controlling the magnitude of the voltage applied to the word line electrical junction structure, the first channel region and the second channel region can be simultaneously controlled to achieve different conduction states. In addition, the first channel region also needs to be controlled to be turned on by the first control gate, and the second channel region also needs to be controlled to be turned on by the second control gate. When the first channel region is turned on, electrons enter the first floating gate from the first channel region to achieve writing logic 1 on the first floating gate. When the second channel region is turned on, electrons enter the second floating gate from the second channel region to achieve writing logic 1 on the second floating gate. Therefore, by applying different voltages to the word line electrical structure, the first control gate and the second control gate, different combinations of write states of the first floating gate and the second floating gate can be achieved. The write state can include eight states. Therefore, two adjacent memory cells can store one byte of data. In addition, the first selection gate and the second selection gate of adjacent memory cell structures are electrically connected, so that two adjacent memory cells can be written at the same time, thereby improving the storage density and shortening the writing time.

[0026] In a method for forming a storage structure provided by the technical solution of the present invention, the first selection gate and the second selection gate of adjacent storage cell structures are electrically connected through a word line electrical junction. Since the turn-on voltages of the first channel region and the second channel region are different, by controlling the magnitude of the voltage applied to the word line electrical junction structure, the first channel region and the second channel region can be simultaneously controlled to achieve different conduction states. In addition, the first channel region also needs to be controlled to be turned on by the first control gate, and the second channel region also needs to be controlled to be turned on by the second control gate. When the first channel region is turned on, electrons enter the first floating gate from the first channel region to achieve writing logic 1 on the first floating gate. When the second channel region is turned on, electrons enter the second floating gate from the second channel region to achieve writing logic 1 on the second floating gate. Therefore, by applying different voltages to the word line electrical structure, the first control gate and the second control gate, different combinations of write states of the first floating gate and the second floating gate can be achieved. The write state can include eight states. Therefore, two adjacent storage cells can store one byte of data. In addition, the first selection gate and the second selection gate of adjacent memory cell structures are electrically connected, so that two adjacent memory cells can be written at the same time, thereby improving the storage density and shortening the writing time.

[0027] In a memory circuit provided by the technical solution of the present invention, the first multi-gate transistor includes a first floating gate, a first control gate coupled to the first floating gate, and a first selection gate for controlling the first multi-gate transistor to be turned on; the second multi-gate transistor includes a second floating gate, a second control gate coupled to the second floating gate, and a second selection gate for controlling the second multi-gate transistor to be turned on; and the threshold voltage of the second multi-gate transistor is greater than the threshold voltage of the first multi-gate transistor; a plurality of word line nodes, each word line node is electrically connected to the first selection gate and the second selection gate of adjacent memory cells in the same row; when a write operation is performed on two adjacent memory cells to be operated, the write voltage applied to the word line node between the two adjacent memory cells is controlled, and the opening state of the first control gate and the second control gate to the channel is controlled to realize the write state of different combinations of the first floating gate and the second floating gate; the write state may include eight states; in addition, since the bit line is electrically connected to the first drain and the second drain of the memory cell in the same row, when a read operation is performed, a read current is obtained from the bit line, and the total storage information of the first floating gate and the second floating gate of the two adjacent memory cells can be obtained, so that the two adjacent memory cells can store one byte of data. Furthermore, since two adjacent storage cells are written at the same time, the storage density is improved and the writing time is shortened. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1is a schematic diagram of the storage structure in an embodiment of the present invention;

[0029] Figure 2 is a schematic diagram of a memory circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0031] As described in the background art, the existing flash memory structure has a low storage density and its performance needs to be improved urgently.

[0032] In order to solve the above problems, the present invention provides a storage structure and a forming method thereof, a memory circuit and a working method thereof. When performing a write operation on two adjacent memory cells to be operated, the write voltage applied to the word line node between the two adjacent memory cells is controlled, and the opening state of the first control gate and the second control gate to the channel is controlled to realize the write state of different combinations of the first floating gate and the second floating gate. The write state may include eight states. In addition, since the bit line is electrically connected to the first drain and the second drain of the same row memory cell, when performing a read operation, the read current is obtained from the bit line, and the total storage information of the first floating gate and the second floating gate of the two adjacent memory cells can be obtained. Therefore, the two adjacent memory cells can store one byte of data. Furthermore, since the two adjacent memory cells are written at the same time, the write time is shortened while the storage density is improved.

[0033] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] Figure 1 It is a structural diagram of the storage structure in an embodiment of the present invention.

[0035] Please refer to Figure 1The storage structure includes: a substrate 100; a plurality of storage cell structures located on the substrate 100, wherein the storage cell structure includes a first selection gate 101, a second selection gate 102, an erase gate 103 located between the first selection gate 101 and the second selection gate 102, a first floating gate 104 located between the erase gate 103 and the first selection gate 101, a second floating gate 105 located between the erase gate 103 and the second selection gate 102, a first control gate 106 located on the first floating gate 104, and a second control gate 107 located on the second floating gate 105 , a first channel region (not shown in the figure) is provided in the substrate 100 at the bottom of the first selection gate 101, a second channel region (not shown in the figure) is provided in the substrate 100 at the bottom of the second selection gate 102, and the turn-on voltage of the first channel region is different from the turn-on voltage of the second channel region; a source doping region 108 in the substrate 100 at the bottom of the erase gate 103; drain doping regions 109 in the substrate 100 respectively located on both sides of the memory cell structure; a word line electrical connection structure 110, which electrically connects the first selection gate 101 and the second selection gate 102 of adjacent memory cell structures respectively.

[0036] In the above storage structure, the first selection gate 101 and the second selection gate 102 of the adjacent storage cell structure are electrically connected through the word line electrical connection structure 110. Since the opening voltages of the first channel region and the second channel region are different, by controlling the magnitude of the voltage applied to the word line electrical connection structure 110, the first channel region and the second channel region can be controlled to achieve different conduction states at the same time. In addition, the first channel region also needs to be controlled to be turned on by the first control gate 106, and the second channel region also needs to be controlled to be turned on by the second control gate 107. When the first channel region is turned on, electrons from the first The channel region enters the first floating gate 104, and the first floating gate 104 is written with logic 1. When the second channel region is turned on, electrons enter the second floating gate 105 from the second channel region, and the second floating gate 105 is written with logic 1. Therefore, by applying different voltages to the word line electrical connection structure 110, the first control gate 106 and the second control gate 107, different combinations of the first floating gate 104 and the second floating gate 105 can be written. The write state can include eight states, so two adjacent storage cells can store one byte of data. In addition, the first selection gate 101 and the second selection gate 102 of the adjacent storage cell structure are electrically connected, so that the two adjacent storage cells can be written at the same time, so that the storage density is improved and the writing time is shortened.

[0037] In this embodiment, the substrate 100 has a well region (not shown in the figure), and the source doping region 108 and the drain doping region 109 are both located in the well region.

[0038] In this embodiment, the doping ion concentrations in the well region under the first selection gate 101 and the second selection gate 102 are different; the doping ions include conductive ions, and the conductive ions include one or both of N-type conductive ions and P-type conductive ions.

[0039] In this embodiment, the storage structure further includes: a first tunnel oxide layer 111 located between the first select gate 101 and the substrate 100 ; and a second tunnel oxide layer 112 located between the second select gate 102 and the substrate 100 .

[0040] In this embodiment, the turn-on voltage of the first channel region is different from the turn-on voltage of the second channel region by using well regions with different doping ion concentrations under the first selection gate 101 and the second selection gate 102. In another embodiment, one or both of the thickness and dielectric constant value of the first tunnel oxide layer and the second tunnel oxide layer are different, that is, the first tunnel oxide layer and the second tunnel oxide layer with different performance are selected to make the turn-on voltage of the first channel region different from the turn-on voltage of the second channel region. In other embodiments, the first selection gate and the second selection gate with different widths can also be selected to make the turn-on voltage of the first channel region different from the turn-on voltage of the second channel region.

[0041] In this embodiment, a plurality of the storage unit structures are arranged in an array along a first direction (not shown in the figure).

[0042] In this embodiment, the storage structure also includes: a plurality of word lines (not shown in the figure) arranged along the first direction, one of the word lines being electrically connected to the word line electrical connection structure 110 located in the same column in the storage structure; a plurality of source lines (not shown in the figure) arranged along the first direction, one of the source lines being electrically connected to the source doping region 108 located in the same column in the storage structure; and a plurality of bit lines (not shown in the figure) arranged along the second direction (not shown in the figure), the second direction being perpendicular to the first direction, one of the bit lines being electrically connected to the drain doping region 109 located in the same row in the storage structure.

[0043] Accordingly, the embodiment of the present invention also provides a method for forming the above storage structure, please continue to refer to Figure 1The method for forming the storage structure comprises: providing a substrate 100; forming a plurality of storage cell structures on the substrate 100, wherein the storage cell structures comprise a first selection gate 101, a second selection gate 102, an erase gate 103 located between the first selection gate 101 and the second selection gate 102, a first floating gate 104 located between the erase gate 103 and the first selection gate 101, a second floating gate 105 located between the erase gate 103 and the second selection gate 102, a first control gate 106 located on the first floating gate 104, and a second control gate 107 located on the second floating gate 105, wherein the first selection gate A first channel region (not shown in the figure) is provided in the substrate 100 at the bottom of the gate 101, and a second channel region (not shown in the figure) is provided in the substrate 100 at the bottom of the second selection gate 102, wherein the turn-on voltage of the first channel region is different from the turn-on voltage of the second channel region; a source doping region 108 is formed in the substrate 100 at the bottom of the erase gate 103; drain doping regions 109 are respectively formed in the substrate 100 on both sides of the memory cell structure; a word line electrical connection structure 110 is formed on the substrate 100, and the word line electrical connection structure 110 electrically connects the first selection gate 101 and the second selection gate 102 of the adjacent memory cell structures respectively.

[0044] In the storage structure formed by the above method, the first selection gate 101 and the second selection gate 102 of the adjacent storage cell structure are electrically connected through the word line electrical connection structure 110. Since the opening voltages of the first channel region and the second channel region are different, by controlling the magnitude of the voltage applied to the word line electrical connection structure 110, the first channel region and the second channel region can be simultaneously controlled to achieve different conduction states. In addition, the first channel region also needs to be controlled to be turned on by the first control gate 106, and the second channel region also needs to be controlled to be turned on by the second control gate 107. When the first channel region is turned on, electrons are generated. The first channel region enters the first floating gate 104, and the first floating gate 104 is written with logic 1. When the second channel region is turned on, electrons enter the second floating gate 105 from the second channel region, and the second floating gate 105 is written with logic 1. Therefore, by applying different voltages to the word line electrical connection structure 110, the first control gate 106 and the second control gate 107, different combinations of the first floating gate 104 and the second floating gate 105 can be written. The write state can include eight states, so two adjacent storage cells can store one byte of data. In addition, the first selection gate 101 and the second selection gate 102 of the adjacent storage cell structure are electrically connected, so that the two adjacent storage cells can be written at the same time, so that the storage density is improved and the writing time is shortened.

[0045] In this embodiment, the substrate 100 has a well region (not shown in the figure), and the source doping region 108 and the drain doping region 109 are both located in the well region.

[0046] In this embodiment, the doping ion concentrations in the well region under the first selection gate 101 and the second selection gate 102 are different.

[0047] In this embodiment, the method for forming the well region includes: forming an initial well region (not shown in the figure) in the substrate 100; injecting doping ions into part of the initial well region to form a well region with different doping concentration distributions, the doping ions include conductive ions, and the conductive ions include one or both of N-type conductive ions and P-type conductive ions.

[0048] In this embodiment, a first tunnel oxide layer 111 is formed between the substrate 100 and the first select gate 101 ; and a second tunnel oxide layer 112 is formed between the second select gate 102 and the substrate 100 .

[0049] In this embodiment, the turn-on voltage of the first channel region is different from the turn-on voltage of the second channel region by using well regions with different doping ion concentrations under the first selection gate 101 and the second selection gate 102. In another embodiment, one or both of the thickness and dielectric constant value of the first tunnel oxide layer and the second tunnel oxide layer are different, that is, the first tunnel oxide layer and the second tunnel oxide layer with different performance are selected to make the turn-on voltage of the first channel region different from the turn-on voltage of the second channel region. In other embodiments, the first selection gate and the second selection gate with different widths can also be selected to make the turn-on voltage of the first channel region different from the turn-on voltage of the second channel region.

[0050] In this embodiment, a plurality of the storage unit structures are arranged in an array along a first direction (not shown in the figure).

[0051] In this embodiment, after the word line electrical connection structure 110 is formed, it also includes: forming a plurality of word lines (not shown in the figure) arranged along the first direction, one of the word lines is electrically connected to the word line electrical connection structure 110 located in the same column in the storage structure; forming a plurality of source lines (not shown in the figure) arranged along the first direction, one of the source lines is electrically connected to the source doping region 108 located in the same column in the storage structure; forming a plurality of bit lines (not shown in the figure) arranged along the second direction (not shown in the figure), the second direction is perpendicular to the first direction, and one of the bit lines is electrically connected to the drain doping region 109 located in the same row in the storage structure.

[0052] Accordingly, the embodiment of the present invention further provides a memory circuit, please refer to Figure 2, the memory circuit includes: a plurality of memory cells arranged in an array, each memory cell (as shown by the dotted line) includes a first multi-gate transistor T1, a second multi-gate transistor T2, an erase gate EG, a source S, a first drain D1, and a second drain D2, the first multi-gate transistor T1 includes a first floating gate FG1, a first control gate CG1 coupled to the first floating gate FG1, and a first selection gate PG1 for controlling the first multi-gate transistor T1 to be turned on, the second multi-gate transistor T2 includes a second floating gate FG2, a second control gate CG2 coupled to the second floating gate FG2, and a second selection gate PG2 for controlling the second multi-gate transistor T2 to be turned on, and the threshold voltage of the second multi-gate transistor T2 is greater than a threshold voltage of the first multi-gate transistor T1, the erase gate EG is coupled with the first floating gate FG1 and the second floating gate FG2, the source S is a common end of the first multi-gate transistor T1 and the second multi-gate transistor T2, the first drain D1 is the other end of the first multi-gate transistor T1, and the second drain D2 is the other end of the second multi-gate transistor T2; a plurality of word line nodes N, each word line node N is electrically connected to the first selection gate PG1 and the second selection gate PG2 of adjacent memory cells in the same row; a word line WL is electrically connected to the word line node N in the same column; a bit line BL is electrically connected to the first drain D1 and the second drain D2 of the memory cells in the same row; a source line SL is electrically connected to the source S of the memory cells in the same column.

[0053] In the above storage circuit, each word line node N is electrically connected to the first selection gate PG1 and the second selection gate PG2 of the adjacent storage cells in the same row, and the word line WL is electrically connected to the word line node N in the same column. By controlling the write voltage applied to the word line node N between the two adjacent storage cells, and controlling the opening state of the first control gate CG1 and the second control gate CG2 to the channel, the write state of different combinations of the first floating gate FG1 and the second floating gate FG2 is realized. The write state may include eight states. In addition, since the bit line BL is electrically connected to the first drain D1 and the second drain D2 of the same row storage cell, when performing a read operation, the read current is obtained from the bit line BL, and the total storage information of the first floating gate FG1 and the second floating gate FG2 of the two adjacent storage cells can be obtained. Therefore, two adjacent storage cells can store one byte of data. Furthermore, since the two adjacent storage cells are written at the same time, the writing time is shortened while the storage density is improved.

[0054] In this embodiment, the storage circuit further includes: a write unit (not shown in the figure) for applying a write voltage to the word line node N and writing logic 1 to one or both of the first floating gate FG1 and the second floating gate FG2 corresponding to the word line node N.

[0055] In this embodiment, the storage circuit further includes: a signal reading unit (not shown in the figure), connected to the bit line BL, and used for reading the storage states of the first floating gate FG1 and the second floating gate FG2.

[0056] Accordingly, the embodiment of the present invention further provides a working method of the above memory circuit, please continue to refer to Figure 2 , the working method of the memory circuit includes:

[0057] Perform a write operation on two adjacent memory cells to be operated, and apply a write voltage to a word line node N between the two adjacent memory cells;

[0058] When the write voltage is greater than the threshold voltage Vt1 of the first multi-gate transistor T1 and less than the threshold voltage Vt2 of the second multi-gate transistor T2, and the channel is opened by the first control gate CG1 and closed by the second control gate CG2, logic 1 is written in the first floating gate FG1;

[0059] When the write voltage is greater than the threshold voltage Vt2 of the second multi-gate transistor T2 and the channel is opened through the first control gate CG1, logic 1 is written into the first floating gate FG1;

[0060] When the write voltage is greater than the threshold voltage Vt2 of the second multi-gate transistor T2 and the channel is turned on by the second control gate CG2, logic 1 is written into the second floating gate FG2.

[0061] In the above working method, when performing a write operation on two adjacent memory cells to be operated, the write voltage applied to the word line node N between the two adjacent memory cells is controlled, and the opening state of the channel by the first control gate CG1 and the second control gate CG2 is controlled to achieve different combinations of write states of the first floating gate FG1 and the second floating gate FG2. The write state may include eight states. In addition, since the bit line BL is electrically connected to the first drain D1 and the second drain D2 of the same row memory cell, when performing a read operation, the read current is obtained from the bit line BL, and the total storage information of the first floating gate FG1 and the second floating gate FG2 of the two adjacent memory cells can be obtained. Therefore, the two adjacent memory cells can store one byte of data. Furthermore, since the two adjacent memory cells are written at the same time, the writing time is shortened while the storage density is improved.

[0062] In the write operation, the write voltage is applied to the first selection gate PG1 and the second selection gate PG2 of the two adjacent memory cells, respectively. By controlling the magnitude of the write voltage and further controlling the magnitude of the voltage applied to the first control gate CG1 and the second control gate CG2, the opening of the channels of the first multi-gate transistor T1 and the second multi-gate transistor T2 are controlled respectively. When the channel of the first multi-gate transistor T1 is opened, electrons enter the first floating gate FG1, and logic 1 is written to the first floating gate FG1. When the channel of the second multi-gate transistor T2 is opened, electrons enter the second floating gate FG2, and logic 1 is written to the second floating gate FG2.

[0063] In this embodiment, after the write operation is performed on the two adjacent storage cells to be operated, the read operation is performed on the two adjacent storage cells.

[0064] In this embodiment, the read operation includes: applying a turn-on voltage to a word line node N between the two adjacent memory cells, the turn-on voltage being greater than a threshold voltage Vt2 of the second multi-gate transistor T2, and applying a first read voltage to the first control gate CG1 and the second control gate CG2, respectively, grounding the source line SL, applying a second read voltage to the bit line BL, obtaining a read current of the bit line BL corresponding to the two adjacent memory cells, and obtaining the storage state of the two adjacent memory cells according to the magnitude of the read current. The read current of the bit line BL corresponding to the two adjacent memory cells is related to the total number of electrons stored in the first floating gate FG1 and the second floating gate FG2.

[0065] The reading operation further includes: before the reading operation, obtaining a plurality of reference current values, wherein the reference current values ​​are used as reference values ​​for grading according to the reading current.

[0066] In this embodiment, the method for obtaining the storage state of the two adjacent memory cells includes: comparing the read current and each reference current value, obtaining the grading result of the read current, and obtaining the total storage state of the first floating gate FG1 and the second floating gate FG2 in the two adjacent memory cells according to the grading result.

[0067] In this embodiment, during the write operation, different write voltages are applied to the word line node N between the two adjacent memory cells to store different numbers of electrons in the first floating gate FG1 (the second floating gate FG2) to represent different storage states.

[0068] Table 1 shows various states in the read and write operations of the memory circuit, which will be described in detail below.

[0069] Write voltage T1 FG1 T2 FG2 Iread State 1 In <Vt1 closure 0 closure 0 "0” State 2 Vt1 <V<Vt2 Open 1 closure 0 "1” State 3 Vt2<V<Vc Open 1 closure 0 "2” State 4 Vt2<V<Vc closure 0 Open 1 "3” State 5 Vt2<V<Vc Open 1 Open 1 "4” State 6 V>Vc closure 0 Open 1 "5” Status 7 V>Vc Open 1 closure 0 "6” State 8 V>Vc Open 1 Open 1 "7”

[0070] Table 1 is a state table of the read and write operations of the memory circuit in the embodiment of the present invention.

[0071] In this embodiment, the operating method of the memory circuit further includes: providing a reference voltage Vc, where the reference voltage is greater than a threshold voltage of the second multi-gate transistor T2.

[0072] Please continue to refer to "State 3" in Table 1. When the write voltage is greater than the threshold voltage Vt2 of the second multi-gate transistor T2 and lower than the reference voltage Vc, a first write operation is performed, and the first write operation includes: opening the channel through the first control gate CG1 and closing the channel through the second control gate CG2, storing charges in the first floating gate FG1, and not storing charges in the second floating gate FG2; after the first write operation, the read operation is performed to obtain the first read current I1. In this embodiment, the first read current I1 obtained is in the third current range, and the two adjacent storage cells store logic "2".

[0073] Please continue to refer to "State 7" in Table 1. When the write voltage is greater than the reference voltage, a second write operation is performed. The second write operation includes: opening the channel through the first control gate CG1 and closing the channel through the second control gate CG2, storing charges in the first floating gate FG1, and not storing charges in the second floating gate FG2; after the second write operation, the read operation is performed to obtain a second read current I2. In this embodiment, the obtained second read current I2 is in the seventh current level, and the two adjacent memory cells store logic "6".

[0074] Please continue to refer to "State 4" in Table 1. When the write voltage V is greater than the threshold voltage Vt2 of the second multi-gate transistor T2 and lower than the reference voltage Vc, a third write operation is performed, and the third write operation includes: opening the channel through the second control gate CG2 and closing the channel through the first control gate CG1, storing charges in the second floating gate FG2, and not storing charges in the first floating gate FG1; after the third write operation, the read operation is performed to obtain a third read current. In this embodiment, the obtained third read current I3 is in the fourth current gear, and the two adjacent storage cells store logic "3".

[0075] Please continue to refer to "State 6" in Table 1. When the write voltage V is greater than the reference voltage Vc, a fourth write operation is performed, and the fourth write operation includes: opening the channel through the second control gate CG2 and closing the channel through the first control gate CG1, storing charges in the second floating gate FG2, and not storing charges in the second floating gate FG2; after the fourth write operation, the read operation is performed to obtain a fourth read current I4. In this embodiment, the fourth read current I4 obtained is in the fifth current level, and the two adjacent memory cells store logic "5".

[0076] The first read current I1 , the second read current I2 , the third read current I3 , and the fourth read current I4 have different binning results.

[0077] Please continue to refer to "State 5" in Table 1. When the write voltage V is greater than the threshold voltage of the second multi-gate transistor T2 and lower than the reference voltage Vc, a fifth write operation is performed, and the fifth write operation includes: opening the channel through the first control gate CG1 and opening the channel through the second control gate CG2, and storing charges in the first floating gate FG1 and the second floating gate FG2 respectively; after the fifth write operation, the read operation is performed to obtain the fifth read current I5. In this embodiment, the fifth read current I5 obtained is in the fifth current gear, and the two adjacent storage cells store logic "4".

[0078] Please continue to refer to "State 8" in Figure 1. When the write voltage V is greater than the reference voltage Vc, a sixth write operation is performed, and the sixth write operation includes: opening the channel through the first control gate CG1 and opening the channel through the second control gate CG2, and storing charges in the first floating gate FG1 and the second floating gate FG2 respectively; after the sixth write operation, the read operation is performed to obtain a sixth read current I6. In this embodiment, the obtained sixth read current I6 is in the sixth current range, and the two adjacent memory cells store logic "7".

[0079] Please continue to refer to "State 2" in Figure 1. When the write voltage is greater than the threshold voltage Vt1 of the first multi-gate transistor T1 and less than the threshold voltage Vt2 of the second multi-gate transistor T2, the seventh write operation is performed, and the seventh write operation includes: opening the channel through the first control gate CG1 and closing the channel through the second control gate CG2, storing charges in the first floating gate FG1, and not storing charges in the second floating gate FG2; after the seventh write operation, the read operation is performed to obtain the seventh read current I7. In this embodiment, the obtained seventh read current I7 is in the seventh current range, and the two adjacent storage cells store logic "1".

[0080] Please continue to refer to "State 1" in Figure 1. When the write voltage is less than the threshold voltage Vt1 of the first multi-gate transistor T1, an eighth write operation is performed, and the eighth write operation includes: no charge is stored in the first floating gate FG1 and the second floating gate FG2; after the eighth write operation, the read operation is performed to obtain an eighth read current. In this embodiment, the obtained eighth read current I8 is 0, and the two adjacent memory cells store logic "0".

[0081] In this embodiment, the first read current I1, the second read current I2, the third read current I3, the fourth read current I4, the fifth read current I5, the sixth read current I6, the seventh read current I7 and the eighth read current I8 have different binning results.

[0082] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A storage structure, characterized in that: include: substrate; A plurality of memory cell structures located on the substrate, the memory cell structures comprising a first selection gate, a second selection gate, an erase gate located between the first selection gate and the second selection gate, a first floating gate located between the erase gate and the first selection gate, a second floating gate located between the erase gate and the second selection gate, a first control gate located on the first floating gate, and a second control gate located on the second floating gate, a first channel region being provided in the substrate at the bottom of the first selection gate, a second channel region being provided in the substrate at the bottom of the second selection gate, and a turn-on voltage of the first channel region being different from a turn-on voltage of the second channel region; a source doped region in the substrate at the bottom of the erase gate; Drain doping regions in the substrate located at two sides of the memory cell structure; The word line electrical connection structure electrically connects the first selection gate and the second selection gate of the adjacent memory cell structures respectively.

2. The storage structure according to claim 1, characterized in that: A well region is provided in the substrate, and the source doping region and the drain doping region are both located in the well region; the doping ion concentrations in the well region under the first selection gate and the second selection gate are different; the doping ions include conductive ions, and the conductive ions include one or both of N-type conductive ions and P-type conductive ions.

3. The storage structure according to claim 1, characterized in that: Also includes: a first tunnel oxide layer between the first select gate and the substrate; a second tunnel oxide layer between the second select gate and the substrate; The first tunnel oxide layer and the second tunnel oxide layer have different thicknesses and dielectric constants, or both.

4. The storage structure according to claim 1, characterized in that: The first selection gate and the second selection gate have different widths.

5. The storage structure according to claim 1, characterized in that: Several of the memory cell structures are arranged in an array along a first direction; the memory structure further includes: several word lines arranged along the first direction, one of the word lines being electrically connected to the word line electrical connection structure located in the same column in the memory structure; several source lines arranged along the first direction, one of the source lines being electrically connected to the source doping region located in the same column in the memory structure; and several bit lines arranged along a second direction, the second direction being perpendicular to the first direction, one of the bit lines being electrically connected to the drain doping region located in the same row in the memory structure.

6. A method for forming a storage structure, characterized in that: include: providing a substrate; A plurality of memory cell structures are formed on the substrate, the memory cell structures comprising a first selection gate, a second selection gate, an erase gate located between the first selection gate and the second selection gate, a first floating gate located between the erase gate and the first selection gate, a second floating gate located between the erase gate and the second selection gate, a first control gate located on the first floating gate, and a second control gate located on the second floating gate, a first channel region is provided in the substrate at the bottom of the first selection gate, a second channel region is provided in the substrate at the bottom of the second selection gate, and a turn-on voltage of the first channel region is different from a turn-on voltage of the second channel region; forming a source doping region in the substrate at the bottom of the erase gate; forming drain doping regions in the substrate at both sides of the memory cell structure respectively; A word line electrical connection structure is formed on the substrate, and the word line electrical connection structure electrically connects the first selection gate and the second selection gate of adjacent memory cell structures respectively.

7. The method for forming a storage structure according to claim 6, wherein: The substrate has a well region, and the source doping region and the drain doping region are both located in the well region; The doping ion concentrations in the well region under the first selection gate and the second selection gate are different; The method for forming the well region comprises: forming an initial well region in the substrate; Doping ions are implanted into a portion of the initial well region to form well regions with different doping concentration distributions, wherein the doping ions include conductive ions, and the conductive ions include one or both of N-type conductive ions and P-type conductive ions.

8. The method for forming a storage structure according to claim 6, wherein: Also includes: forming a first tunnel oxide layer between the substrate and the first select gate; forming a second tunnel oxide layer between the second select gate and the substrate; The first tunnel oxide layer and the second tunnel oxide layer have different thicknesses and dielectric constants, or both.

9. The method for forming a storage structure according to claim 6, wherein: The first selection gate and the second selection gate have different widths.

10. The method for forming a storage structure according to claim 6, wherein: Several memory cell structures are arranged in an array along a first direction; after forming the word line electrical connection structure, it also includes: forming several word lines arranged along the first direction, one of the word lines is electrically connected to the word line electrical connection structure located in the same column in the memory structure; forming several source lines arranged along the first direction, one of the source lines is electrically connected to the source doping region located in the same column in the memory structure; forming several bit lines arranged along a second direction, the second direction is perpendicular to the first direction, one of the bit lines is electrically connected to the drain doping region located in the same row in the memory structure.

11. A memory circuit, characterized in that: include: A plurality of memory cells arranged in an array, each memory cell comprising a first multi-gate transistor, a second multi-gate transistor, an erase gate, a source, a first drain, and a second drain, wherein the first multi-gate transistor comprises a first floating gate, a first control gate coupled to the first floating gate, and a first selection gate for controlling the first multi-gate transistor to be turned on, the second multi-gate transistor comprises a second floating gate, a second control gate coupled to the second floating gate, and a second selection gate for controlling the second multi-gate transistor to be turned on, and a threshold voltage of the second multi-gate transistor is greater than a threshold voltage of the first multi-gate transistor, the erase gate is coupled to the first floating gate and the second floating gate, the source is a terminal shared by the first multi-gate transistor and the second multi-gate transistor, the first drain is the other terminal of the first multi-gate transistor, and the second drain is the other terminal of the second multi-gate transistor; A plurality of word line nodes, each word line node being electrically connected to a first selection gate and a second selection gate of adjacent memory cells in the same row; A word line electrically connected to a word line node in the same column; A bit line is electrically connected to a first drain and a second drain of a memory cell in the same row; The source line is electrically connected to the sources of the memory cells in the same column.

12. The memory circuit according to claim 11, wherein: Also includes: The writing unit is used for applying a writing voltage to a word line node and writing a logic 1 into one or both of a first floating gate and a second floating gate corresponding to the word line node.

13. The memory circuit according to claim 11, wherein: Also includes: A signal reading unit is connected to the bit line and is used to read the storage states of the first floating gate and the second floating gate.

14. A method for operating a memory circuit according to any one of claims 11 to 13, characterized in that: include: Perform a write operation on two adjacent memory cells to be operated, and apply a write voltage to a word line node between the two adjacent memory cells; When the write voltage is greater than the threshold voltage of the first multi-gate transistor and less than the threshold voltage of the second multi-gate transistor, and the channel is opened by the first control gate and closed by the second control gate, logic 1 is written in the first floating gate; When the write voltage is greater than the threshold voltage of the second multi-gate transistor and the channel is opened by the first control gate, logic 1 is written into the first floating gate; When the write voltage is greater than the threshold voltage of the second multi-gate transistor and the channel is turned on by the second control gate, logic 1 is written into the second floating gate.

15. The operating method of the memory circuit according to claim 14, characterized in that: After performing a write operation on two adjacent memory cells to be operated, performing a read operation on the two adjacent memory cells; the read operation includes: applying a turn-on voltage to a word line node between the two adjacent memory cells, the turn-on voltage being greater than a threshold voltage of the second multi-gate transistor, and applying a first read voltage to the first control gate and the second control gate respectively, grounding the source line, applying a second read voltage to the bit line, obtaining a read current of the bit line corresponding to the two adjacent memory cells, and obtaining the storage states of the two adjacent memory cells according to the magnitude of the read current.

16. The operating method of the memory circuit according to claim 15, characterized in that: include: Before the reading operation, obtaining a plurality of reference current values; The method for obtaining the storage state of the two adjacent storage cells includes: comparing the read current and each reference current value, obtaining the grading result of the read current, and obtaining the total storage state of the first floating gate and the second floating gate in the two adjacent storage cells according to the grading result.

17. The operating method of the memory circuit according to claim 16, characterized in that: Also includes: providing a reference voltage, wherein the reference voltage is greater than a threshold voltage of the second multi-gate transistor; When the write voltage is greater than the threshold voltage of the second multi-gate transistor and lower than the reference voltage, a first write operation is performed, wherein the first write operation includes: opening the channel through the first control gate and closing the channel through the second control gate, storing charges in the first floating gate, and not storing charges in the second floating gate; after the first write operation, the read operation is performed to obtain a first read current; when the write voltage is greater than the reference voltage, a second write operation is performed, wherein the second write operation includes: opening the channel through the first control gate and closing the channel through the second control gate, storing charges in the first floating gate, and not storing charges in the second floating gate; after the second write operation, the read operation is performed to obtain a second read current; when the write voltage is greater than the threshold voltage of the second multi-gate transistor , and is lower than the reference voltage, a third write operation is performed, the third write operation comprising: opening the channel through the second control gate, and closing the channel through the first control gate, storing charges in the second floating gate, and not storing charges in the first floating gate; after the third write operation, the read operation is performed to obtain a third read current; when the write voltage is greater than the reference voltage, a fourth write operation is performed, the fourth write operation comprising: opening the channel through the second control gate, and closing the channel through the first control gate, storing charges in the second floating gate, and not storing charges in the second floating gate; after the fourth write operation, the read operation is performed to obtain a fourth read current; the grading results of the first read current, the second read current, the third read current and the fourth read current are different.

18. The operating method of the memory circuit according to claim 17, characterized in that: Also includes: When the write voltage is greater than the threshold voltage of the second multi-gate transistor and lower than the reference voltage, a fifth write operation is performed, and the fifth write operation includes: opening a channel through the first control gate and opening a channel through the second control gate, and storing charges in the first floating gate and the second floating gate respectively; after the fifth write operation, the read operation is performed to obtain a fifth read current; when the write voltage is greater than the reference voltage, a sixth write operation is performed, and the sixth write operation includes: opening a channel through the first control gate and opening a channel through the second control gate, and storing charges in the first floating gate and the second floating gate respectively; after the sixth write operation, the read operation is performed to obtain a sixth read current; when the write voltage is greater than the threshold voltage of the first multi-gate transistor and lower than the threshold voltage of the second multi-gate transistor threshold voltage, performing a seventh write operation, the seventh write operation comprising: opening a channel through the first control gate and closing the channel through the second control gate, storing charges in the first floating gate, and not storing charges in the second floating gate; after the seventh write operation, performing the read operation to obtain a seventh read current; when the write voltage is less than the threshold voltage of the first multi-gate transistor, performing an eighth write operation, the eighth write operation comprising: not storing charges in both the first floating gate and the second floating gate; after the eighth write operation, performing the read operation to obtain an eighth read current; the grading results of the first read current, the second read current, the third read current, the fourth read current, the fifth read current, the sixth read current, the seventh read current and the eighth read current are all different.

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