Solid-state imaging element, imaging system, and method for controlling solid-state imaging element

Abstract

The present invention improves the convenience of a solid-state imaging element capable of cutting out a partial region of an image. In the solid-state imaging element, a pixel array section has an array of a plurality of pixels, each of which is configured to generate an analog signal and sample and hold the analog signal. The vertical scanning circuit drives each of a plurality of rows in the pixel array section to output a pixel signal. The signal processing circuit reads a pixel signal and performs predetermined signal processing on the pixel signal. The control circuit controls at least one of the vertical scanning circuit and the signal processing circuit to generate compressed data obtained by compressing image data including an array of pixel signals. And a control circuit that controls at least one of the vertical scanning circuit and the signal processing circuit to output cut-out data corresponding to a predetermined region cut out from the image data in accordance with a result of performing a predetermined detection process on the compressed data.

Description

Technical Field

[0001] The present technology relates to a solid-state imaging element, and more particularly to a solid-state imaging element that detects a predetermined object, an imaging system, and a control method of the solid-state imaging element. Background Art

[0002] In the related art, technology for detecting objects such as faces or people has been applied to various fields such as crime prevention and transportation. For example, a camera device has been proposed that reads the entire first image to detect a person, cuts out an area around the person appearing in the first image from a second image, and analyzes the area to determine whether a person has passed through an entrance or exit, etc. (for example, see Patent Document 1).

[0003] Citation List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2020-086961 Summary of the invention

[0006] Problems to be solved by the present invention

[0007] In the above-mentioned related art technology, it is intended to reduce the processing amount of the analysis processing by using a part of the area cut out from the second image. However, if the movement speed of the person is faster than the expected movement speed, the person may not be captured in the area to be cut out of the second image. As a result, there is a possibility that the success rate of the analysis processing of the cut-out data will be reduced, and therefore, the convenience of the system will be reduced.

[0008] The present technology has been proposed in view of such a situation, and therefore, an object of the present technology is to improve the convenience of a solid-state imaging element capable of cutting out a partial area of ​​an image.

[0009] Technical solutions to the problem

[0010] The present technology is completed to solve the above-mentioned problems, and according to the first aspect of the present technology, a solid-state imaging element and a control method of the solid-state imaging element are provided. The solid-state imaging element includes: a pixel array unit having an arrangement of multiple pixels, each of the multiple pixels is configured to generate a pixel signal and sample and hold the pixel signal; a vertical scanning circuit that drives each of the multiple rows in the pixel array unit to output the pixel signal; a signal processing circuit that reads the pixel signal and performs predetermined signal processing on the pixel signal; and a control circuit, the control circuit controls at least one of the vertical scanning circuit and the signal processing circuit to generate compressed data obtained by compressing image data containing the arrangement of the pixel signal, and the control circuit controls at least one of the vertical scanning circuit and the signal processing circuit according to the result of processing the compressed data to output cut-out data corresponding to a predetermined area cut out from the image data. Thereby, an effect of improving convenience is brought about.

[0011] Furthermore, in the first aspect, the control circuit may generate data obtained by thinning out the image data in units of lines and / or columns as the compressed data, thereby achieving an effect of being able to compress the image data with simple processing.

[0012] Furthermore, in the first aspect, the signal processing circuit may include a compression processing unit that generates the compressed data by pixel addition, thereby achieving an effect of reducing noise.

[0013] In addition, in the first aspect, the signal processing circuit may further include a plurality of analog-to-digital converters, each of which converts the pixel signal into a digital signal. The pixel signal may include an analog signal, and the compression processing unit may generate the compressed data by adding the digital signals. This brings about an effect of being able to reduce noise.

[0014] In addition, in the first aspect, the signal processing circuit may further include a plurality of analog-to-digital converters, each of which converts the pixel signal into a digital signal. The pixel signal may include an analog signal, and the compression processing unit may generate the compressed data by adding the pixel signals. This brings about an effect of being able to reduce noise.

[0015] In addition, in the first aspect, a detection processing unit may be further included that performs a predetermined detection process on the compressed data. This brings about an effect that the detection object can be detected in the solid-state imaging element.

[0016] Furthermore, in the first aspect, the signal processing circuit may output the result of the processing to the outside of the solid-state imaging element, thereby bringing about an effect of making the processing result available outside the solid-state imaging element.

[0017] Furthermore, in the first aspect, the detection processing unit may detect whether a face is present, thereby achieving an effect of being able to cut out a region during face detection.

[0018] Furthermore, in the first aspect, the detection processing unit can detect whether a person is present, thereby bringing about an effect of being able to cut out a region when detecting a person.

[0019] Furthermore, in the first aspect, the detection processing unit may detect a difference between the compressed data and predetermined background data, thereby achieving an effect of being able to detect the detection object with simple processing.

[0020] In addition, in the first aspect, a communication interface may be further included that receives the result of the processing and supplies the result to the control circuit. This brings about an effect that the processing amount of the solid-state imaging element can be reduced.

[0021] In addition, in the first aspect, the pixel signal may include a predetermined reset level and a signal level corresponding to the exposure amount. Moreover, each of the plurality of pixels may include: a first capacitor element and a second capacitor element; a front-stage circuit that sequentially generates the reset level and the signal level, and causes the first capacitor element and the second capacitor element to respectively maintain the reset level and the signal level; a selection circuit that sequentially performs control for connecting one of the first capacitor element and the second capacitor element to a predetermined rear-stage node, control for disconnecting both the first capacitor element and the second capacitor element from the rear-stage node, and control for connecting the other of the first capacitor element and the second capacitor element to the rear-stage node; a rear-stage reset transistor that initializes the level of the rear-stage node when both the first capacitor element and the second capacitor element are disconnected from the rear-stage node; and a rear-stage circuit that sequentially reads the reset level and the signal level from the first capacitor element and the second capacitor element via the rear-stage node, and outputs the reset level and the signal level. Thereby, an effect of being able to reduce kTC noise is brought about.

[0022] In addition, according to a second aspect of the present technology, there is provided an imaging system, which includes a solid-state imaging element and a host. The solid-state imaging element includes: a pixel array unit having an arrangement of a plurality of pixels, each of the plurality of pixels being configured to generate a pixel signal and sample and hold the pixel signal; a vertical scanning circuit that drives each of a plurality of rows in the pixel array unit to output the pixel signal; a signal processing circuit that reads the pixel signal and performs predetermined signal processing on the pixel signal; and a control circuit that controls at least one of the vertical scanning circuit and the signal processing circuit to generate compressed data obtained by compressing image data containing the arrangement of the pixel signal, and the control circuit controls at least one of the vertical scanning circuit and the signal processing circuit according to the result of the processing of the compressed data to output cut-out data corresponding to a predetermined area cut out from the image data. The host performs processing different from the processing according to the cut-out data. Thereby, an effect of being able to improve the convenience of the imaging system is brought about. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 : is a diagram showing a configuration example of an image pickup system according to a first embodiment of the present technology.

[0024] Figure 2 is a block diagram showing a configuration example of a solid-state image pickup element according to a first embodiment of the present technology.

[0025] Figure 3 is a circuit diagram showing a configuration example of a pixel according to the first embodiment of the present technology.

[0026] Figure 4 : is a block diagram showing a configuration example of a load MOS (metal-oxide-semiconductor) circuit block and a column signal processing circuit according to the first embodiment of the present technology.

[0027] Figure 5 : is a diagram showing a use example of the imaging system according to the first embodiment of the present technology.

[0028] Figure 6 is a diagram showing one example of a detection area and a cutout area according to the first embodiment of the present technology.

[0029] Figure 7 is a diagram showing another example of the detection area and the cutout area according to the first embodiment of the present technology.

[0030] Figure 8 : is a diagram showing an example of an overall view of a solid-state image pickup element according to a first embodiment of the present technology.

[0031] Fig. 9 is a timing chart showing an example of how the imaging system according to the first embodiment of the present technology operates.

[0032] Fig.10 is a timing chart showing one example of the global shutter operation according to the first embodiment of the present technology.

[0033] Fig.11 is a timing chart showing an example of a read operation according to the first embodiment of the present technology.

[0034] Fig.12 is a timing chart showing another example of the read operation according to the first embodiment of the present technology.

[0035] Fig.13 is a timing chart showing an example of how the imaging system according to the first comparative example operates.

[0036] Fig.14 is a timing chart showing an example of how the imaging system according to the second comparative example operates.

[0037] Fig.15 is a diagram showing an example of image data, compressed data, and cutout data according to the first embodiment of the present technology.

[0038] Fig.16 is a flowchart showing an example of how the solid-state imaging element according to the first embodiment of the present technology operates.

[0039] Fig.17 is a flowchart showing an example of how the host according to the first embodiment of the present technology operates.

[0040] Fig.18 is a block diagram showing a configuration example of a column signal processing circuit according to a second embodiment of the present technology.

[0041] Fig.19 is a diagram showing an example of image data and compressed data according to the second embodiment of the present technology.

[0042] Fig. 20 is a block diagram showing another example of the column signal processing circuit according to the second embodiment of the present technology.

[0043] Fig.21 is a block diagram showing a configuration example of a solid-state image pickup element according to a third embodiment of the present technology.

[0044] Fig. 22 is a timing chart showing an example of how the imaging system according to the third embodiment of the present technology operates.

[0045] Fig.23 : is a diagram showing a configuration example of an imaging system according to a fourth embodiment of the present technology.

[0046] Fig.24 is a timing chart showing an example of how the imaging system according to the fourth embodiment of the present technology operates.

[0047] Fig.25 is a diagram showing a configuration example of an imaging system according to a fifth embodiment of the present technology.

[0048] Fig.26 It is a diagram for explaining a usage example of an imaging system according to a fifth embodiment of the present technology.

[0049] Fig. 27 is a diagram showing an example of background data, compressed data, and cutout data according to a sixth embodiment of the present technology.

[0050] Fig.28 is a circuit diagram showing a configuration example of a pixel according to a first modification example of the present technology.

[0051] Fig.29 : is a timing chart showing an example of the global shutter operation according to the first modification example of the present technology.

[0052] Fig.30 is a timing chart showing an example of a read operation according to the first modification example of the present technology.

[0053] Fig.31 : is a diagram showing an example of a stacked structure of a solid-state imaging element according to a second modification example of the present technology.

[0054] Fig.32 is a circuit diagram showing a configuration example of a pixel according to a second modification example of the present technology.

[0055] Fig.33 : is a diagram showing an example of a stacked structure of a solid-state imaging element according to a third modification example of the present technology.

[0056] Fig.34 is a circuit diagram showing a configuration example of a pixel according to a seventh embodiment of the present technology.

[0057] Fig.35 is a timing chart showing one example of a global shutter operation according to the seventh embodiment of the present technology.

[0058] Fig.36 is a circuit diagram showing a configuration example of a pixel according to an eighth embodiment of the present technology.

[0059] Fig.37It is a diagram for explaining reset feedthrough according to an eighth embodiment of the present technology.

[0060] Fig.38 is a diagram for explaining a level difference caused by reset feedthrough according to an eighth embodiment of the present technology.

[0061] Fig.39 is a timing chart showing an example of voltage control according to the eighth embodiment of the present technology.

[0062] Fig.40 : is a timing chart showing an example of the global shutter operation of the odd-numbered frame according to the ninth embodiment of the present technology.

[0063] Fig.41 is a timing chart showing an example of a read operation of an odd-numbered frame according to the ninth embodiment of the present technology.

[0064] Fig.42 is a timing chart showing an example of a global shutter operation of an even-numbered frame according to the ninth embodiment of the present technology.

[0065] Fig.43 is a timing chart showing an example of a read operation of an even-numbered frame according to the ninth embodiment of the present technology.

[0066] Fig.44 is a circuit diagram showing a configuration example of a column signal processing circuit according to a tenth embodiment of the present technology.

[0067] Fig.45 is a timing chart showing one example of a global shutter operation according to the tenth embodiment of the present technology.

[0068] Fig.46 is a timing chart showing an example of a read operation according to the tenth embodiment of the present technology.

[0069] Fig.47 is a timing chart showing an example of a rolling shutter operation according to the eleventh embodiment of the present technology.

[0070] Fig.48 : is a block diagram showing a configuration example of a solid-state image pickup element according to a twelfth embodiment of the present technology.

[0071] Fig.49 is a circuit diagram showing a configuration example of a dummy pixel, a regulator, and a switching section according to a twelfth embodiment of the present technology.

[0072] Fig.50 is a timing chart showing an example of how the dummy pixel and the regulator operate according to the twelfth embodiment of the present technology.

[0073] Fig.51 is a circuit diagram showing a configuration example of an effective pixel according to a twelfth embodiment of the present technology.

[0074] Fig.52 is a timing chart showing an example of a global shutter operation according to the twelfth embodiment of the present technology.

[0075] Fig.53 is a timing chart showing an example of a read operation according to the twelfth embodiment of the present technology.

[0076] Fig.54 It is a diagram for explaining the effects of the twelfth embodiment according to the present technology.

[0077] Fig.55 is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0078] Fig.56 It is an explanatory diagram showing an example of the installation position of the imaging unit. DETAILED DESCRIPTION

[0079] Modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described below. The description will be given in the following order.

[0080] 1. First Embodiment (Example of Cutting Out Based on Processing Result of Compressed Data)

[0081] 2. Second Embodiment (Example of Cutting Out Based on Processing Results of Compressed Data Generated by Pixel Addition)

[0082] 3. Third Embodiment (Example in which switching is performed according to the processing result of compressed data and the host enters the sleep state)

[0083] 4. Fourth Embodiment (Example in which the host computer processes compressed data and the solid-state imaging element performs cutting out based on the result of the processing)

[0084] 5. Fifth Embodiment (Example in which the solid-state imaging element performs cutting out based on the processing result of compressed data and the host performs behavior determination)

[0085] 6. Sixth Embodiment (Example of Cutting Out Based on Difference Between Compressed Data and Background)

[0086] 7. Seventh Embodiment (Example in which a drain transistor is added and the first capacitor element and the second capacitor element hold a pixel signal)

[0087] 8. Eighth Embodiment (Example in which the first capacitor element and the second capacitor element hold pixel signals and the reset power supply voltage is controlled)

[0088] 9. Ninth Embodiment (Example in which the first capacitor element and the second capacitor element hold a pixel signal, and the level to be held is switched for each frame)

[0089] 10. Tenth Embodiment (Example in which the first capacitor element and the second capacitor element hold pixel signals and a black dot phenomenon is suppressed)

[0090] 11. Eleventh Embodiment (Example in which the First Capacitor Element and the Second Capacitor Element Hold Pixel Signals and a Rolling Shutter Operation is Performed)

[0091] 12. Twelfth Embodiment (Example in which noise is reduced and the first capacitor element and the second capacitor element hold pixel signals)

[0092] 13. Application examples of mobile objects

[0093] <1. First Implementation Method>

[0094] [Configuration example of camera system]

[0095] Figure 1 1 is a diagram showing a configuration example of an imaging system 100 according to a first embodiment of the present technology. The imaging system 100 is a system configured to be able to capture image data (ie, frames) and perform various processes such as authentication processing, and includes a solid-state imaging element 200 and a host 110.

[0096] The solid-state imaging element 200 captures image data. The solid-state imaging element 200 cuts out an area to be an authentication object such as a face or eyes from the captured image data, and supplies the cutout area as cutout data to the host 110 via a predetermined number of signal lines 208 .

[0097] In addition, control signals related to control are sent and received between the solid-state imaging element 200 and the host 110 via a predetermined number of signal lines 209. For example, the control signal includes a vertical synchronization signal, imaging parameters, authentication results, and status information. The imaging parameters include ISO (International Organization for Standardization) sensitivity, exposure time, and setting values ​​such as aperture value and white balance.

[0098] The host 110 is a device or circuit that performs authentication processing based on the cut-out data. The host 110 includes a communication interface 111 , a communication interface 112 , a database 113 , an authentication processing unit 114 , and an image capture control unit 115 .

[0099] The communication interface 111 receives the cutout data, and supplies the cutout data to the authentication processing section 114. Examples of the standard adopted by the communication interface 111 include a relatively high-speed standard such as SLVS-EC (scalable low voltage signaling with embedded clock).

[0100] Control signals are transmitted and received between the communication interface 112 and the imaging control unit 115. Examples of the standard adopted by the communication interface 112 include relatively low-speed standards such as I2C (Inter-Integrated Circuit) and SPI (Serial Peripheral Interface).

[0101] The database 113 stores registration information pre-registered before authentication. The authentication processing unit 114 performs authentication processing based on the cut-out data. The authentication processing unit 114 obtains the feature quantity of the cut-out data received from the communication interface 111, and compares the obtained feature quantity with the feature quantity of the registration information to determine whether the similarity between the two feature quantities is greater than or equal to a specific value. If the similarity is greater than or equal to the specific value, the authentication processing unit 114 determines that the authentication is successful, and if the similarity is less than the specific value, the authentication processing unit 114 determines that the authentication fails. The authentication processing unit 114 supplies the authentication result to the camera control unit 115.

[0102] Note that the database 113 may also be deployed in a server located outside the host 110. In this case, the host 110 receives the registration information from the server through a network such as the Internet.

[0103] The imaging control unit 115 controls the solid-state imaging element 200. The imaging control unit 115 and the solid-state imaging element 200 exchange control signals as necessary via the communication interface 112. When receiving the authentication result, the imaging control unit 115 transmits the authentication result to the solid-state imaging element 200.

[0104] [Configuration Example of Solid-State Image Pickup Element]

[0105] Figure 21 is a block diagram showing a configuration example of a solid-state imaging element 200 according to a first embodiment of the present technology. The solid-state imaging element 200 includes a vertical scanning circuit 211, a control circuit 212, and a DAC (digital-to-analog converter) 213. In addition, the solid-state imaging element 200 also includes a pixel array section 220, a load MOS (metal oxide semiconductor: metal oxide semiconductor) circuit block 250, a column signal processing circuit 260, and communication interfaces 214 and 215.

[0106] In the pixel array section 220, a plurality of pixels 300 are arranged in a two-dimensional grid. In addition, for example, each circuit in the solid-state imaging element 200 is provided in a single semiconductor chip.

[0107] Hereinafter, a set of pixels 300 arranged in the horizontal direction will be referred to as a “row”, and a set of pixels 300 arranged in a direction orthogonal to the row will be referred to as a “column”.

[0108] The control circuit 212 controls the operation of each of the vertical scanning circuit 211 , the DAC 213 , and the column signal processing circuit 260 according to a control signal received from the communication interface 215 .

[0109] The DAC 213 generates a sawtooth-shaped ramp signal by digital-to-analog (DA) conversion and supplies the generated ramp signal to the column signal processing circuit 260 .

[0110] The vertical scanning circuit 211 sequentially selects and drives each row to output an analog pixel signal. The pixel 300 photoelectrically converts incident light to generate an analog pixel signal. The pixel 300 supplies the pixel signal to the column signal processing circuit 260 via the load MOS circuit block 250 .

[0111] In the load MOS circuit block 250 , MOS transistors for supplying a constant current are provided for each column.

[0112] The column signal processing circuit 260 performs signal processing such as AD (analog-to-digital) conversion processing or CDS (correlated double sampling) processing on the pixel signal for each column. The column signal processing circuit 260 generates cutout data in the signal processing and supplies the cutout data to the communication interface 214. Note that the column signal processing circuit 260 is an example of a signal processing circuit described in the claims.

[0113] The communication interface 214 transmits the cut-out data to the host 110. The communication interface 215 and the host 110 transmit and receive control signals.

[0114] [Pixel Structure Example]

[0115] Figure 3 3 is a circuit diagram showing a configuration example of a pixel 300 according to a first embodiment of the present technology. The pixel 300 includes a previous stage circuit 310 , capacitor elements 321 and 322 , a selection circuit 330 , a subsequent stage reset transistor 341 , and a subsequent stage circuit 350 .

[0116] The previous stage circuit 310 includes a photoelectric conversion element 311 , a transfer transistor 312 , an FD (floating diffusion) reset transistor 313 , an FD 314 , a previous stage amplifier transistor 315 , and a current source transistor 316 .

[0117] The photoelectric conversion element 311 generates electric charge by photoelectric conversion. The transfer transistor 312 transfers the electric charge from the photoelectric conversion element 311 to the FD 314 according to the transfer signal trg received from the vertical scanning circuit 211 .

[0118] The FD reset transistor 313 extracts charge from the FD 314 according to the FD reset signal rst received from the vertical scanning circuit 211 to initialize the FD 314. The FD 314 is used to accumulate charge and generate a voltage corresponding to the amount of charge. The pre-stage amplifier transistor 315 amplifies the level of the voltage of the FD 314 and outputs the amplified voltage to the pre-stage node 320.

[0119] Furthermore, the sources of the FD reset transistor 313 and the pre-stage amplifier transistor 315 are each connected to the power supply voltage VDD. The current source transistor 316 is connected to the drain of the pre-stage amplifier transistor 315. The current source transistor 316 supplies the current id1 under the control of the vertical scanning circuit 211.

[0120] One end of each of the capacitor elements 321 and 322 is commonly connected to the previous stage node 320, and the other end of each of them is respectively connected to the selection circuit 330. Note that the capacitor elements 321 and 322 are examples of the first capacitor element and the second capacitor element described in the claims.

[0121] The selection circuit 330 includes a selection transistor 331 and a selection transistor 332. The selection transistor 331 opens (opens (disconnects)) and closes (closes (connects)) a path between the capacitor element 321 and the subsequent node 340 according to a selection signal Φr received from the vertical scanning circuit 211. The selection transistor 332 opens and closes a path between the capacitor element 322 and the subsequent node 340 according to a selection signal Φs received from the vertical scanning circuit 211.

[0122] The subsequent reset transistor 341 initializes the level of the subsequent node 340 to a predetermined potential Vreg according to the subsequent reset signal rstb received from the vertical scanning circuit 211. The potential Vreg is set to a potential different from the power supply voltage VDD (eg, a potential lower than VDD).

[0123] The post-stage circuit 350 includes a post-stage amplifier transistor 351 and a post-stage selection transistor 352. The post-stage amplifier transistor 351 amplifies the level of the post-stage node 340. The post-stage selection transistor 352 outputs a signal indicating the level amplified by the post-stage amplifier transistor 351 as a pixel signal to the vertical signal line 309 according to the post-stage selection signal selb received from the vertical scanning circuit 211.

[0124] Note that as various transistors in the pixel 300 (transfer transistor 312 and the like), for example, nMOS (n-channel metal oxide semiconductor) transistors are used.

[0125] At the start of exposure, the vertical scanning circuit 211 supplies a high-level FD reset signal rst and a high-level transfer signal trg to all pixels. As a result, the photoelectric conversion element 311 is initialized. Hereinafter, this control is referred to as "PD reset".

[0126] Then, just before the exposure ends, while the subsequent reset signal rstb and the selection signal Φr are set to high level for all pixels, the vertical scanning circuit 211 supplies a high-level FD reset signal rst during one pulse. As a result, the FD 314 is initialized, and a level corresponding to the level of the FD 314 at this time is held in the capacitor element 321. This control is hereinafter referred to as "FD reset".

[0127] The level of the FD 314 at the time of FD reset and the level corresponding to the level of the FD 314 (the level held in the capacitor element 321 and the level of the vertical signal line 309 ) will hereinafter be collectively referred to as “P phase” or “reset level”.

[0128] At the end of exposure, while the subsequent reset signal rstb and the selection signal Φs are set to high level for all pixels, the vertical scanning circuit 211 supplies a high-level transfer signal trg during one pulse. As a result, a signal charge corresponding to the exposure amount is transferred to the FD 314, and a level corresponding to the level of the FD 314 at this time is held in the capacitor element 322.

[0129] The level of the FD 314 when the signal charge is transferred and the level corresponding to the level of the FD 314 (the level held in the capacitor element 322 and the level of the vertical signal line 309 ) will hereinafter be collectively referred to as “D phase” or “signal level”.

[0130] This exposure control that starts and ends exposure for all pixels at the same time is called a global shutter method. Through such exposure control, the front circuit 310 of all pixels generates a reset level and a signal level in sequence. The reset level is maintained in the capacitor element 321, and the signal level is maintained in the capacitor element 322.

[0131] After the exposure is completed, the vertical scanning circuit 211 selects each row in sequence and outputs the reset level and signal level of the selected row in sequence. In order to output the reset level, the vertical scanning circuit 211 supplies the high-level selection signal Φr for a predetermined period while both the FD reset signal rst and the subsequent stage selection signal selb of the selected row are set to high levels. As a result, the capacitor element 321 is connected to the subsequent stage node 340, and the reset level is read.

[0132] After the reset level is read, while the FD reset signal rst and the rear stage selection signal selb of the selected row are both kept at a high level, the vertical scanning circuit 211 supplies a high level rear stage reset signal rstb during one pulse. As a result, the level of the rear stage node 340 is initialized. At this time, both the selection transistor 331 and the selection transistor 332 are in an open state, and the capacitor elements 321 and 322 are disconnected from the rear stage node 340.

[0133] After initialization of the subsequent node 340, the vertical scanning circuit 211 supplies a high-level selection signal Φs for a predetermined period while both the FD reset signal rst and the subsequent selection signal selb of the selected row are kept at a high level. As a result, the capacitor element 322 is connected to the subsequent node 340, and the signal level is read.

[0134] Through the above-mentioned reading control, the selection circuit 330 of the selected row sequentially performs: control for connecting the capacitor element 321 to the subsequent node 340, control for disconnecting the capacitor elements 321 and 322 from the subsequent node 34, and control for connecting the capacitor element 322 to the subsequent node 340. In addition, when the capacitor elements 321 and 322 are disconnected from the subsequent node 340, the subsequent reset transistor 341 of the selected row initializes the level of the subsequent node 340. In addition, the subsequent circuit 350 of the selected row sequentially reads the reset level and the signal level from the capacitor elements 321 and 322 via the subsequent node 340, and outputs the reset level and the signal level to the vertical signal line 309.

[0135] [Configuration Example of Column Signal Processing Circuit]

[0136] Figure 4 : is a block diagram showing a configuration example of the load MOS circuit block 250 and the column signal processing circuit 260 according to the first embodiment of the present technology.

[0137] In the load MOS circuit block 250, vertical signal lines 309 are arranged for each column. If the number of columns is I (where I is an integer), there are I vertical signal lines 309. In addition, a load MOS transistor 251 for supplying a constant current id2 is connected to each vertical signal line 309.

[0138] The column signal processing circuit 260 is provided with a plurality of analog to digital converters (ADCs) 270, a data processing unit 262, a demultiplexer 263, a detection processing unit 265, and a cut-out region calculation unit 266. The ADCs 270 are provided one-to-one for each column. If the number of columns is one, one ADC 270 is provided.

[0139] Each of the ADCs 270 converts an analog pixel signal received from a corresponding column into a digital signal using a ramp signal Rmp received from the DAC 213. The ADC 270 supplies the digital signal to the data processing section 262. As the ADC 270, for example, a single slope type ADC including a comparison section and a counter is provided.

[0140] Here, it is assumed that the control circuit 212 is capable of controlling at least one of the vertical scanning circuit 211 and the column signal processing circuit 260 to generate compressed data obtained by compressing image data.

[0141] For example, the control circuit 212 generates data obtained by thinning the image data in row units and / or in column units as compressed data. In the case where thinning is performed in row units, the control circuit 212 controls the vertical scanning circuit 211 to sequentially select and drive each row except the row to be skipped. In addition, in the case where thinning is performed in column units, the control circuit 212 controls each of the ADCs 270 so that the ADC 270 corresponding to the column to be skipped is invalid, and the remaining ADCs 270 are valid.

[0142] Note that the control circuit 212 can also generate compressed data by pixel addition as described later.

[0143] Here, it is assumed that the control circuit 212 can control at least one of the vertical scanning circuit 211 and the column signal processing circuit 260 to generate cutout data obtained by cutting out a partial region of the image data.

[0144] When the cut-out data is generated, the control circuit 212 controls the vertical scanning circuit 211 to sequentially drive all rows in the cut-out region, and makes the ADC 270 corresponding to all columns in the cut-out region effective, and makes the remaining ADC 270 ineffective. Since the cut-out region is cut out from the uncompressed image data, the resolution of the cut-out region is higher than the resolution of the compressed data. Such a region is also called a region of interest (ROI).

[0145] The data processing section 262 performs predetermined signal processing such as CDS processing on the digital signal for each column, and supplies the processed digital signal to the demultiplexer 263 .

[0146] The demultiplexer 263 selects one of the detection processing section 265 and the communication interface 214 as an output destination according to an authentication-enabling flag, and outputs the data from the data processing section 262 to the output destination.

[0147] Here, when a predetermined object (such as a face) is detected in the compressed data, the authentication enable flag is used as a flag for indicating whether the area of ​​the object has a sufficiently high image quality to enable authentication. For example, in the case where authentication cannot be performed, the authentication enable flag is set to "0". For example, in the case where authentication can be performed, the authentication enable flag is set to "1". In the initial state, the authentication enable flag is set to "0".

[0148] When the authentication enable flag is "0", the control circuit 212 generates compressed data. In addition, the demultiplexer 263 outputs the compressed data to the detection processing unit 265. On the other hand, when the authentication enable flag is "1", the control circuit 212 outputs the cut-out data, and the demultiplexer 263 outputs the cut-out data to the host 110 via the communication interface 214.

[0149] The detection processing section 265 performs detection processing for detecting whether a predetermined detection object (such as a face, etc.) exists on the compressed data. The detection processing section 265 supplies the detection result to the cutout region operation section 266. The detection result includes: information indicating success or failure of the detection; and a detection region as a region to be detected.

[0150] The cutout region calculation unit 266 performs calculations to obtain a cutout region as necessary. If the detection processing unit 265 does not detect the object, the cutout region calculation unit 266 sets the authentication enable flag to “0” and supplies the authentication enable flag to the demultiplexer 263 and the control circuit 212 .

[0151] On the other hand, when the detection processing unit 265 detects an object, the cut-out region calculation unit 266 determines whether the region of the object has a sufficiently high image quality to enable authentication. If authentication is not possible, the cut-out region calculation unit 266 sets the authentication enable flag to "0" and supplies the authentication enable flag to the demultiplexer 263 and the control circuit 212.

[0152] When authentication is possible, the cut-out region operation unit 266 sets the authentication enable flag to "1" and supplies the authentication enable flag to the demultiplexer 263 and the control circuit 212. When the detection object and the authentication object are the same, the cut-out region operation unit 266 sets the detection area directly as the cut-out region and supplies information indicating the region to the control circuit 212. On the other hand, when a part of the detection object (such as the face) (such as the eyes) is the authentication object, the cut-out region operation unit 266 operates the region to be the authentication object as the cut-out region and supplies the region to the control circuit 212.

[0153] When the authentication enable flag is "1", the control circuit 212 controls at least one of the vertical scanning circuit 211 and the column signal processing circuit 260 to output pixel signals of all pixels in the cut-out area. In addition, when the authentication enable flag is "0" in the second frame and subsequent frames after the start of imaging, the control circuit 212 changes the imaging parameters (ISO sensitivity, aperture, exposure time, white balance, etc.) as needed.

[0154] Figure 5 1 is a diagram showing a use example of the camera system 100 according to the first embodiment of the present technology. For example, the camera system 100 is used in an access control system including a camera device 150. The camera device 150 is installed near a gate and captures the face of a person who is about to pass through the gate in the direction of an arrow. A solid-state image pickup element 200 is provided in the camera device 150.

[0155] In the access control system shown in the figure, in order to ensure security, authentication is performed to determine whether the person entering or leaving is a pre-registered individual. Although authentication is possible when using an IC (integrated circuit) card, due to concerns about hygiene issues or the risk of losing the IC card, biometric authentication is sometimes performed using the face or eyes.

[0156] In the case of performing facial authentication and the like based on the image data captured by the camera device 150, the host 110 needs to perform authentication processing at a speed corresponding to the speed at which the person passes through the gate. For example, in the case of a person walking fast, the number of steps per hour is about 8,000 steps, and the number of steps per second is about 2.2 steps. Since the average stride of an adult is 70 cm, the distance traveled per second is about 1.5 meters (m). In the case where the distance at which the image can be captured with a sufficiently high image quality to enable authentication is about 1.5 meters (m) from the camera device 150, the camera system 100 needs to complete the processing from capturing to authentication within 1 second, and therefore requires a high throughput. In the case where the throughput is not high enough, the person needs to stop before the processing is completed, which reduces convenience.

[0157] Figure 6 1 is a diagram showing an example of a detection area and a cutout area according to the first embodiment of the present technology. It is assumed that the solid-state imaging element 200 detects whether there is a face, and the host 110 authenticates the eyes in the face.

[0158] The solid-state imaging element 200 captures image data, compresses the image data to generate compressed data 500, and performs face detection processing on the compressed data 500. From the detection of the face, etc. to the identification of the authentication area such as the eyes, it is a general process. Therefore, the detection processing can be performed in the solid-state imaging element 200. In addition, the detection processing can also be performed using a rough image, so compressed data can be used in the detection processing.

[0159] Here, since each pixel 300 can sample and hold a pixel signal, the raw image data before compression is held in the pixel array section 220 during the period from reading the compressed data to the end of the next exposure. Thus, the solid-state imaging element 200 can read the raw image data again before the end of the next exposure. When a face is detected, the solid-state imaging element 200 cuts out an area such as eyes to be an authentication object from the detection area 510 of the raw image data as a cut-out area 511, and outputs the cut-out area 511 to the host 110. Then, the host 110 performs authentication processing on the cut-out area 511.

[0160] Since high accuracy is required in the authentication process, a high-resolution image cut out from the original image data before compression is used.

[0161] In addition, the authentication process also requires the registration data of the person to be authenticated, and from the perspective of security and privacy, advanced security technology is also required to protect the registration data. Therefore, the authentication process is performed by the host 110 located outside the solid-state imaging element 200.

[0162] Figure 7 1 is a diagram showing another example of the detection area and the cut-out area according to the first embodiment of the present technology. Figure 5 and Figure 6 In the embodiment, the camera system 100 is applied in an access control system, but the camera system 100 can also be applied in the field of transportation. In this case, for example, Figure 7 As shown in a of FIG. 1 , the solid-state imaging element 200 detects whether there is a vehicle in the compressed data 600. When a vehicle is detected, as shown in FIG. Figure 7 As shown in FIG. 2 b , the solid-state imaging element 200 cuts out the area of ​​the license plate from the cut-out area 610 of the original image data as a cut-out area 611 , and outputs the cut-out area 611 to the host 110 .

[0163] Note that the detection area and the cutout area are not limited to the above-mentioned areas such as face and eyes, vehicle and license plate, etc. Depending on the use case, the solid-state imaging element 200 can set any desired area as the detection area and can cut out the area as the cutout area.

[0164] Figure 8 1 is a diagram showing an example of an overall view of the solid-state image pickup element 200 according to the first embodiment of the present technology. Each of the plurality of pixels 300 arranged in the pixel array section 220 generates an analog pixel signal, and samples and holds the analog pixel signal.

[0165] The vertical scanning circuit 211 drives each of the plurality of rows in the pixel array section 220 to output a pixel signal. The column signal processing circuit 260 performs signal processing such as analog-to-digital (AD) conversion processing on the pixel signal for each column.

[0166] The control circuit 212 controls the vertical scanning circuit 211 in synchronization with the vertical scanning signal so that all pixels are exposed at the same time.

[0167] In addition, in the initial state, the authentication enable flag is set to "0". When the authentication enable flag is "0", the control circuit 212 controls at least one of the vertical scanning circuit 211 and the column signal processing circuit 260 to generate compressed data obtained by compressing the image data. For example, data obtained by thinning the image data in units of rows and / or columns is generated as compressed data.

[0168] In the case where the authentication enable flag is "0", the demultiplexer 263 supplies the compressed data to the detection processing section 265. The detection processing section 265 performs detection processing such as face detection on the compressed data. When the detection object is detected, the cut-out area operation section 266 determines whether the image in the detection area has a sufficiently high image quality to the extent that authentication can be performed, and in the case that authentication can be performed, the cut-out area operation section 266 sets the authentication enable flag to "1" and supplies the authentication enable flag to the demultiplexer 263 and the control circuit 212. In addition, the cut-out area operation section 266 performs operations as needed to obtain a cut-out area, and supplies information indicating the area to the control circuit 212.

[0169] The control circuit 212 controls at least one of the vertical scanning circuit 211 and the column signal processing circuit 260 according to the processing result of the compressed data (authentication enable flag, etc.), and outputs the cut-out data obtained by cutting out the cut-out area from the original image data. For example, when the authentication enable flag is "1", the cut-out data is output. In addition, when the authentication enable flag is "0" in the second frame and subsequent frames after the start of imaging, the control circuit 212 changes the imaging parameters as needed.

[0170] [Example of how the camera system operates]

[0171] Fig. 9 1 is a timing chart showing an example of how the imaging system 100 according to the first embodiment of the present technology operates. Fig. 9 In FIG. 1 , a shows how the entire camera system 100 operates. Fig. 9 In FIG. 1 , b shows the thinning operation of the solid-state imaging element 200, and in FIG. Fig. 9 In FIG. 1 , c shows a cutout operation in the solid-state imaging element 200 .

[0172] like Fig. 9As shown in a in FIG. 1 , it is assumed that the image capture starts at time T1. The control circuit 212 simultaneously exposes all pixels in the pixel array unit 220 during the exposure time from time T1 to time T2 in synchronization with the vertical synchronization signal VSYNC. That is, the exposure is controlled by a global shutter method. In addition, all pixels in the pixel array unit 220 maintain pixel signals at the end of exposure. As a result, the first image data (first frame) F1 is maintained.

[0173] In the reading period from time T2 to time T3, the column signal processing circuit 260 generates compressed data by thinning out the frame F1. Then, after time T3, the column signal processing circuit 260 performs detection processing on the compressed data. It is assumed that the detection processing fails.

[0174] On the other hand, in the exposure time from the time T3 to the time T4, all pixels in the pixel array section 220 are simultaneously exposed, and thus the second frame F2 is held.

[0175] During the reading period from time T4 to time T5, the column signal processing circuit 260 generates compressed data by thinning the frame F2. Then, after time T5, the column signal processing circuit 260 performs a detection process on the compressed data. It is assumed that the detection process is successful and can be authenticated. In this case, after time T6, the column signal processing circuit 260 outputs the cut-out data obtained by cutting out a part of the original frame F2 to the host 110. Here, by implementing sampling and holding pixel by pixel, the frame F2 can be kept without being destroyed until the exposure of the next frame F3 ends. Therefore, the column signal processing circuit 260 can read the pixel signal in the frame F2 again after time T6.

[0176] Furthermore, when the detection performed on the compressed data of the frame F1 fails, the control circuit 212 changes the imaging parameters and simultaneously exposes all the pixels in the pixel array section 220 during the exposure time from time T5 to time T7. For example, by increasing the ISO sensitivity, a frame F3 brighter than the frames F1 and F2 can be generated.

[0177] The host 110 is started at or before the time T1 corresponding to the start of the video recording, and performs the authentication process on the cut-out data after the time T7. The cut-out data is data cut out from the original frame F2 of the compressed data to be subjected to the detection process. That is, the frame as the detection object and the frame as the authentication object are the same. In addition, since each pixel samples and holds the pixel signal respectively, there is no need to set up a frame memory for holding the frame F2 during the detection period outside the pixel.

[0178] After outputting the cut-out data, the camera system 100 may perform the detection processing and authentication processing again, or may put the detection processing and authentication processing to sleep for a certain period of time. In the case of sleep, for example, the camera system 100 may enter the sleep state when the authentication processing is successful, and repeat the detection processing and authentication processing when the authentication processing fails. This is because it is not necessary to repeatedly authenticate the same identification object. In the case of entering sleep when successful, the host 110 notifies the solid-state imaging element 200 whether the authentication is successful.

[0179] exist Fig. 9 In b and c, "Rn" indicates the nth row. Fig. 9 As shown in b in FIG. 1 , when sparse reading is performed, rows R3, R4, etc. are skipped, and rows R1, R2, R5, R6, etc. are read in sequence.

[0180] In addition, if Fig. 9 As shown in c in FIG. 1 , when the cutout after R6 is performed, all rows such as R6, R7, R8 and R9 in the cutout area are read in sequence.

[0181] Fig.10 1 is a timing chart showing an example of the global shutter operation according to the first embodiment of the present technology. During the period from time T10 immediately before the start of exposure to time T1 after one pulse period, the vertical scanning circuit 211 supplies a high-level FD reset signal rst and a high-level transfer signal trg to all rows (in other words, all pixels). As a result, PD reset is performed on all pixels, and all rows start exposure at the same time.

[0182] here, Fig.10 rst_[n] and trg_[n] in _ represent signals supplied to pixels in the nth row among N rows. N is an integer representing the total number of rows, and n is an integer from 1 to N.

[0183] Then, at time T11 immediately before the end of the exposure period, while the subsequent reset signal rstb and the selection signal Φr are set to high level for all pixels, the vertical scanning circuit 211 supplies a high-level FD reset signal rst during one pulse period. As a result, FD reset is performed on all pixels, and the reset level is sampled and held. Here, Fig.10 rstb_[n] and Φr_[n] in φ represent signals supplied to the pixels in the nth row.

[0184] At time T12 after time T11, the vertical scanning circuit 211 returns the selection signal Φr to the low level.

[0185] At the moment T2 when the exposure ends, while the rear-stage reset signal rstb and the selection signal Φs are set to a high level for all pixels, the vertical scanning circuit 211 supplies a high-level transfer signal trg during one pulse. As a result, the signal level is sampled and held. In addition, the level of the front-stage node 320 drops from the reset level (i.e., VDD-Vgs) to the signal level (i.e., VDD-Vgs-Vsig). Here, VDD represents the power supply voltage, and Vsig represents the net signal level obtained by CDS processing. Vgs represents the gate-source voltage of the front-stage amplifier transistor 315. In addition, Fig.10 Φs_[n] in Φs_[n] represents a signal supplied to pixels in the n-th row.

[0186] At time T13 after time T2, the vertical scanning circuit 211 returns the selection signal Φs to the low level.

[0187] In addition, the vertical scanning circuit 211 controls the current source transistors 316 of all rows (all pixels) to supply the current id1. Here, Fig.10 id1_[n] in represents the current of the nth row of pixels. The larger the current id, the larger the IR drop; therefore, the current id1 must be on the order of a few nanoamperes (nA) to tens of nanoamperes (nA). On the other hand, the load MOS transistors 251 of all columns are in the off state, and therefore the current id2 is not supplied to the vertical signal line 309.

[0188] Fig.11 1 is a timing diagram showing an example of a read operation according to the first embodiment of the present technology. During the reading period of the nth row from time T20 to time T27, the vertical scanning circuit 211 sets the FD reset signal rst and the subsequent stage selection signal selb of the nth row to a high level. Here, Fig.11 selb_[n] in represents the signal supplied to the pixels in the nth row.

[0189] During the period from time T21 immediately after time T20 to time T23, the vertical scanning circuit 211 supplies the selection signal Φr of the high level to the n-th row. The potential of the subsequent node 340 becomes the reset level Vrst.

[0190] During the period from time T22 after time T21 to time T23, the DAC 213 gradually increases the ramp signal Rmp. The ADC 270 compares the ramp signal Rmp with the level Vrst′ of the vertical signal line 309, and counts the count value during the period until the comparison result is inverted. As a result, the P-phase level (reset level) is read.

[0191] The vertical scanning circuit 211 supplies a high-level subsequent reset signal rstb to the nth row during one pulse period starting from time T24 immediately after time T23. As a result, when a parasitic capacitance exists in the subsequent node 340, the history of the previous signal held in the parasitic capacitance can be eliminated.

[0192] During the period from time T25 to time T27 immediately after the initialization of the subsequent node 340, the vertical scanning circuit 211 supplies the high-level selection signal Φs to the nth row. The potential of the subsequent node 340 becomes the signal level Vsig. During exposure, the signal level is lower than the reset level, but during reading, because the subsequent node 340 is used as a reference, the signal level is higher than the reset level. The difference between the reset level Vrst and the signal level Vsig is equivalent to the net signal level from which the reset noise (reset noise) and offset noise (offset noise) of the FD have been removed.

[0193] During the period from time T26 after time T25 to time T27, the DAC 213 gradually increases the ramp signal Rmp. The ADC 270 compares the ramp signal Rmp with the level Vrst′ of the vertical signal line 309, and counts the count value until the comparison result is inverted. As a result, the D-phase level (signal level) is read.

[0194] In addition, during the period from time T20 to time T27, the vertical scanning circuit 211 controls the current source transistor 316 of the nth row to be read to supply current id1. In addition, during the reading period of all rows, the control circuit 212 controls the load MOS transistors 251 of all columns to supply current id2.

[0195] Note that the solid-state imaging element 200 reads the signal level after reading the reset level, but the reading order is not limited to this order. Fig.12 As shown in FIG. 1 , the solid-state imaging element 200 may also read the reset level after reading the signal level. In this case, as shown in the figure, the vertical scanning circuit 211 supplies the high-level selection signal Φr after supplying the high-level selection signal Φs. In addition, in this case, the inclination of the ramp signal needs to be reversed.

[0196] Here, an image pickup system in which pixels do not sample and hold pixel signals and the host computer 110 performs detection processing is assumed as a first comparative example.

[0197] Fig.131 is a timing chart showing an example of how the camera system 100 according to the first comparative example operates. During the exposure period from time T1 to time T2, the control circuit 212 exposes only the rows that are not skipped. Then, during the reading period from time T2 to time T3, the column signal processing circuit 260 reads the columns that are not skipped to generate compressed data of the frame F1, and outputs the compressed data to the host 110.

[0198] After time T3, the host 110 performs a detection process on the compressed data. It is assumed that the detection process is successful and can be authenticated. In addition, during the period from time T3 to time T4, the control circuit 212 only exposes the rows that are not skipped.

[0199] Then, since the detection is successful in the first frame, the control circuit 212 stops the thinning after time T4, and exposes all the rows in the cut-out area during the exposure period from time T5 to time T7. After time T7, the column signal processing circuit 260 outputs the cut-out data obtained by cutting out a part of the frame F3 to the host 110, and the host 110 performs authentication processing on the cut-out data.

[0200] Next, an image pickup system in which pixels do not sample and hold pixel signals and the solid-state image pickup element 200 outputs image data to the host 110 without compressing the image data is assumed as a second comparative example.

[0201] Fig.14 1 is a timing chart showing an example of how the imaging system 100 according to the second comparative example operates. During the exposure period from time T1 to time T2, the control circuit 212 exposes all rows. Then, during the reading period from time T2 to time T3, the column signal processing circuit 260 reads the frame F1 and outputs the frame F1 to the host 110.

[0202] During the period from time T3 to time T4, the host 110 holds frame F1 in the frame memory and compresses it, and performs face detection processing. Then, after time T4, the host 110 performs authentication processing. It is assumed here that the authentication processing fails due to reasons such as the face being obscured by the image of another object.

[0203] Furthermore, during the exposure period from time T5 to time T6, the control circuit 212 exposes all rows. Then, during the reading period after time T6, the column signal processing circuit 260 reads the frame F3. Based on the above authentication failure, the control circuit 212 changes the imaging parameters of the next frame F4. For example, the ISO sensitivity is increased to make the image brighter.

[0204] exist Fig.13In the first comparative example shown, the frame F1 as the detection object and the frame F3 as the authentication object are different. Therefore, if the subject moves between the frames F1 and F3, the eyes of the authentication object may fall outside the cut-out area, or the pattern may change due to blinking or the like.

[0205] exist Fig.14 In the second comparative example shown, the frame F1 as the detection object and the frame F1 as the authentication object are the same. Therefore, the problem of the first comparative example is solved. However, all pixels are exposed to generate uncompressed frames, which leads to an increase in the amount of data transmitted between the solid-state imaging element 200 and the host 110, and an increase in power consumption. In addition, in the case where the authentication process performed on frame F1 fails, the camera parameters are changed according to the result after frame F4, and in the case where the authentication process needs to be performed more than twice, the throughput is reduced. Even in the case where compression and detection processing are performed in the solid-state imaging element 200, the problem of reduced throughput cannot be solved.

[0206] In contrast, Fig. 9 In the configuration shown in which the pixel samples and holds the pixel signal, since the same frame can be read multiple times, the frame to be detected and the frame to be authenticated can be the same. Thus, the time delay between detection and authentication when the host 110 performs the smart authentication process is eliminated, and therefore, authentication failure due to image changes during the time delay can be prevented.

[0207] In addition, since compressed data or cut-out data is read instead of all pixels, the amount of data and power consumption can be reduced compared to the second comparative example. Therefore, it is possible to achieve high-speed processing in the solid-state imaging element 200. In addition, when the detection of the frame F1 fails, the imaging parameters are changed after the frame F3, which improves the throughput compared to the second comparative example.

[0208] Fig.15 : is a diagram showing an example of image data, compressed data, and cut-out data according to the first embodiment of the present technology. Fig.15 In FIG. 1 , a shows an example of image data before compression. Fig.15 , b shows an example of compressed data, and c shows an example of cut-out data.

[0209] Assume that each pixel in the image data receives any one of red (R) light, green (G) light, and blue (B) light. Fig.15 As shown in a in FIG. 1 , pixels in the image data are arranged in a Bayer array.

[0210] like Fig.15As shown in b in FIG. 1 , data obtained by thinning the image data in units of rows or columns is generated as compressed data. Fig.15 The dotted lines in b indicate skipped pixels.

[0211] In addition, by Fig.15 The area surrounded by the bold line in a is the cut-out area. Fig.15 As shown in c in FIG. 1 , all pixels in the cut-out area are read as cut-out data. Since all pixels in the cut-out area are read, the resolution of the cut-out data becomes higher than that of the compressed data.

[0212] Fig.16 1 is a flowchart showing an example of how the solid-state image pickup element 200 according to the first embodiment of the present technology operates. For example, when a predetermined application for capturing image data is executed, the operation starts.

[0213] First, the solid-state imaging element 200 exposes all pixels by a global shutter method and holds the pixel signals of each pixel (step S901). Then, the solid-state imaging element 200 reads the compressed data (step S902), and determines whether a face is detected (step S903). In the case of detecting a face (step S903: Yes), the solid-state imaging element 200 determines whether authentication such as eye-based authentication is possible (step S904).

[0214] If no face is detected (step S903: No) or authentication cannot be performed (step S904: No), the solid-state imaging element 200 checks the imaging parameters and changes the imaging parameters as necessary (step S906). After step S906, the solid-state imaging element 200 repeats step S901 and subsequent steps.

[0215] If authentication is possible (step S904: Yes), the solid-state imaging element 200 reads the cut-out data and outputs the cut-out data to the host 110 (step S905), and determines whether an authentication success notification is received from the host 110 (step S907). If no authentication success notification is received (step S907: No), the solid-state imaging element 200 repeats step S901 and subsequent steps. On the other hand, if an authentication success notification has been received (step S907: Yes), the solid-state imaging element 200 ends the imaging operation and sleeps for a certain period of time.

[0216] Fig.17 1 is a flowchart showing an example of how the host computer 110 according to the first embodiment of the present technology operates. For example, when a predetermined application for capturing image data is executed, the operation starts.

[0217] The host 110 determines whether the cutout data has been received from the solid-state imaging element 200 (step S910). In the case where the cutout data has been received (step S910: Yes), the host 110 performs authentication processing and determines whether the authentication processing is successful (step S911). In the case where the authentication processing is successful (step S911: Yes), the host 110 provides an authentication success notification (step S912), and repeats step S910 and subsequent steps.

[0218] When the cut-out data is not received (step S910 : No) or when the authentication process fails (step S911 : No), the host 110 repeatedly executes step S910 and subsequent steps.

[0219] As described above, according to the first embodiment of the present technology, since the solid-state imaging element 200 outputs data cut out from the original image data according to the result of the detection processing of the compressed data, the host 110 can perform authentication using the same image as the image at the time of detection. Therefore, the success rate of the authentication processing increases, which makes it possible to improve the convenience of the imaging system 100.

[0220] <2. Second Implementation Method>

[0221] In the first embodiment described above, the solid-state imaging element 200 generates compressed data by thinning, but with this configuration, it is difficult to reduce noise in the compressed data. The solid-state imaging element 200 according to the second embodiment is different from the solid-state imaging element 200 according to the first embodiment in that the compressed data is generated by pixel addition.

[0222] Fig.18 2 is a block diagram showing a configuration example of a column signal processing circuit 260 according to a second embodiment of the present technology. The column signal processing circuit 260 of the second embodiment is different from the column signal processing circuit 260 of the first embodiment in that a compression processing section 264 is further provided.

[0223] In the second embodiment, when the authentication enable flag is "0", the control circuit 212 controls the data processing section 262 to perform AD conversion on all pixels. When the authentication enable flag is "0", the demultiplexer 263 supplies the image data received from the data processing section 262 to the compression processing section 264.

[0224] The compression processing unit 264 compresses the image data obtained as a result of the AD conversion by pixel addition, and supplies the compressed data generated by the compression to the detection processing unit 265 .

[0225] In the case where the authentication enable flag is “1”, the second embodiment is similar to the first embodiment in terms of the operation of the column signal processing circuit 260 .

[0226] Fig.19 : is a diagram showing an example of image data and compressed data according to the second embodiment of the present technology. Fig.19 , a shows an example of image data before compression, and b shows an example of compressed data.

[0227] The compression processing unit 264 adds a plurality of digital pixel signals of the same color adjacent to each other to obtain a compressed pixel signal. Fig.19 As shown in a in FIG. 1 , the added average value of the pixel signals of the four R pixels in the Bayer array is calculated. Fig.19 As shown in b in FIG. 1 , the signal after the addition and averaging is arranged as the pixel signal of the R pixel in the compressed data.

[0228] like Fig.19 As shown, by adding and averaging a plurality of pixel signals (ie, digital signals) using the compression processing unit 264, noise can be reduced.

[0229] Note that although the compression processing unit 264 adds digital signals, analog pixel signals before AD conversion may be added. In this case, Fig. 20 As shown in FIG. 2 , a compression processing section 261 for adding analog pixel signals is arranged at a preceding stage of the ADC 262. As a circuit in the compression processing section 261, for example, the circuit disclosed in Japanese Patent Application Laid-Open No. 2008-042478 can be used. Figure 6 The circuit described in .

[0230] As described above, according to the second embodiment of the present technology, since the compression processing section 264 generates compressed data by adding a plurality of pixel signals, noise can be reduced compared to the first embodiment.

[0231] <3. Third Implementation Plan>

[0232] In the first embodiment described above, the host 110 is activated when imaging starts, but it is desirable to further reduce the power consumption of the host 110. The imaging system 100 according to the third embodiment is different from the imaging system 100 according to the first embodiment in that the host 110 remains dormant until the eye or the like can be recognized.

[0233] Fig.211 is a block diagram showing a configuration example of a solid-state imaging element 200 according to a third embodiment of the present technology. The solid-state imaging element 200 of the third embodiment is different from the solid-state imaging element 200 of the first embodiment in that the column signal processing circuit 260 outputs an authentication enable flag to the host 110.

[0234] Fig. 22 1 is a timing chart showing an example of how the imaging system 100 according to the third embodiment of the present technology operates. In the initial state, the host 110 is in a sleep state. Here, for example, the sleep state refers to a state in which only circuits (communication circuits, control circuits, etc.) required for processing signals received from the solid-state imaging element 200 in the host 110 are in an operating state, while other circuits (authentication processing section 114, etc.) in the host 110 are in a sleep state.

[0235] At time T6, the column signal processing circuit 260 sends an authentication enable flag set to "1" to the host 110. According to this flag, the host 110 shifts from the sleep state to the start-up state in which the authentication processing section 114 and the like are operating. Then, if the cut-out data is output after time T7, the host 110 performs the authentication process using the cut-out data after time T7.

[0236] like Fig. 22 As shown, since the host 110 remains in sleep mode until authentication can be performed, the power consumption of the camera system 100 can be reduced compared to the first embodiment.

[0237] Note that the second embodiment in which pixel addition is performed can also be applied to the third embodiment.

[0238] As described above, according to the third embodiment of the present technology, since the column signal processing circuit 260 outputs the authentication enable flag and the host 110 remains in sleep mode until authentication can be performed, the power consumption of the camera system 100 can be reduced.

[0239] <4. Fourth Implementation Plan>

[0240] In the above-described first embodiment, the solid-state imaging element 200 performs detection processing such as face detection, but the detection processing may be performed by the host computer 110 instead of the solid-state imaging element 200. The imaging system 100 according to the present fourth embodiment is different from the imaging system 100 according to the first embodiment in that the host computer 110 performs the detection processing.

[0241] Fig.231 is a diagram showing a configuration example of an imaging system 100 according to a fourth embodiment of the present technology. The imaging system 100 of the fourth embodiment is different from the imaging system 100 of the first embodiment in that the main body 110 further includes a detection processing section 116 and a cutout region operation section 117 .

[0242] Furthermore, the solid-state image sensor 200 according to the fourth embodiment is provided with neither the detection processing section 265 nor the cutout region calculation section 266 .

[0243] The detection processing section 116 and the cutout region operation section 117 are similar in configuration to the detection processing section 265 and the cutout region operation section 266 in the aforementioned solid-state imaging element 200. Note that the cutout region operation section 117 sends the authentication enable flag and the cutout region to the solid-state imaging element 200 via the communication interface 112, for example.

[0244] Fig.24 1 is a timing chart showing an example of how the imaging system 100 according to the fourth embodiment of the present technology operates. During the reading period from time T2 to time T3, the column signal processing circuit 260 generates compressed data by thinning out the frame F1 and transmits the compressed data to the host 110.

[0245] Immediately after time T3, the host 110 performs detection processing on the compressed data. Due to the transmission and reception of the compressed data, a slight time delay occurs between time T3 and the start time of the detection processing. Assume that the detection processing fails. In this case, the host 110 feeds back the authentication enable flag set to "0" to the solid-state imaging element 200.

[0246] Then, immediately after time T5 , assuming that the host 110 performs detection processing on the compressed data and can authenticate, the host 110 feeds back the authentication enable flag set to “1” and the cutout region to the solid-state imaging element 200 .

[0247] After time T6, the column signal processing circuit 260 outputs the cut-out data, and after time T7, the host 110 performs the authentication process using the cut-out data.

[0248] like Fig.24 As shown, the host computer 110 also performs the detection processing, so although the feedback timing is delayed, the processing amount on the solid-state imaging element 200 can be reduced.

[0249] Note that the second embodiment in which pixel addition is performed can also be applied to the fourth embodiment.

[0250] As described above, according to the fourth embodiment of the present technology, since the host computer 110 executes the detection process, the amount of processing on the solid-state imaging element 200 can be reduced.

[0251] <5. Fifth Implementation Plan>

[0252] In the first embodiment described above, the host 110 performs authentication processing such as eye-based authentication using the cut-out data, but processing other than authentication processing may also be performed. The camera system 100 according to the fifth embodiment is different from the camera system 100 according to the first embodiment in that the solid-state imaging element 200 detects the presence of a person and the host 110 performs behavior determination.

[0253] Fig.25 1 is a diagram showing a configuration example of an imaging system 100 according to a fifth embodiment of the present technology. The imaging system 100 of the fifth embodiment is different from the imaging system 100 of the first embodiment in that the host 110 includes a behavior determination section 118 instead of the authentication processing section 114 .

[0254] Furthermore, the solid-state image pickup element 200 according to the fifth embodiment detects whether or not there is a person in the compressed data, and cuts out the region of the detected person from the original image data.

[0255] The behavior determination section 118 analyzes the cutout data to determine whether the behavior of the person is a specific behavior, and outputs the determination result to the outside.

[0256] Fig.26 1 is a diagram for explaining a use example of the imaging system 100 according to the fifth embodiment of the present technology. Fig.26 As shown in a in FIG. 1 , the imaging device 150 provided with the solid-state imaging element 200 generates compressed data of the image data 700. The solid-state imaging element 200 detects two persons in the compressed data, cuts out cutout areas 710 and 720 corresponding to the two persons, respectively, from the original image data 700, and outputs the two cutout areas to the host 110.

[0257] The host 110 analyzes the cut-out areas 710 and 720 to determine whether the behavior of each person is a specific behavior. For example, the host 110 detects the clothing and belongings of each person through object detection, etc., to determine the behavior based on this information.

[0258] For example, Fig.26 As shown in b, the person in the detection area 710 wears clothes with pockets, carries a mobile phone, and wears a mask, a helmet and gloves. Based on this information, the host 110 determines that the person is performing a task such as inspection work.

[0259] In contrast, if Fig.26As shown in c, the person in the detection area 720 wears clothes with pockets and carries a mobile phone, but does not wear a mask, a helmet or gloves. The host 110 determines that the person is performing non-business activities based on this information.

[0260] Then, if a person is performing an act outside of job duties, the host 110 outputs the determination result to an alarm device or the like to sound an alarm.

[0261] Note that each of the second, third, and fourth embodiments can also be applied to the fifth embodiment.

[0262] As described above, according to the fifth embodiment of the present technology, since the solid-state imaging element 200 detects the presence or absence of a person and the host 110 determines the behavior of the person, it is possible to execute processing other than the authentication processing.

[0263] <6. Sixth Implementation Plan>

[0264] In the first embodiment described above, the host 110 uses the cut-out data to perform authentication processing such as eye-based authentication, but processing other than authentication processing may also be performed. The camera system 100 according to the sixth embodiment is different from the camera system 100 according to the first embodiment in that the solid-state imaging element 200 detects a difference with background data and the host 110 saves the cut-out data.

[0265] Fig. 27 : is a diagram showing an example of background data, compressed data, and cut-out data according to a sixth embodiment of the present technology. Fig. 27 In FIG. 8 , a shows an example of background data 800. Fig. 27 In FIG. 8 , b shows an example of compressed data 810. Fig. 27 In FIG. 8 , c shows an example of cut-out data.

[0266] The detection processing section 265 in the solid-state imaging element 200 detects the difference between the background data 800 and the compressed data 810, and sets the area corresponding to the difference as the cutout area 811. Then, the control circuit 212 outputs the cutout data obtained by cutting out the cutout area 811 from the original image data.

[0267] The host 110 saves the cut-out data. Alternatively, the host 110 analyzes the cut-out data to determine whether there is an abnormality.

[0268] Since the background difference method is simpler than detection processing such as face detection in the solid-state imaging element 200 , the processing load on the solid-state imaging element 200 can be reduced by using the background difference method.

[0269] Note that each of the second to fifth embodiments can also be applied to the sixth embodiment.

[0270] As described above, according to the sixth embodiment of the present technology, since the solid-state imaging element 200 can detect the difference from the background, the processing load can be reduced.

[0271] [First Modification]

[0272] In the first embodiment described above, the front-stage circuit 310 realizes signal reading in a state where the front-stage circuit 310 is connected to the front-stage node 320, but this structure cannot block noise from the front-stage node 320 during reading. The pixel 300 of the first variation of the first embodiment is different from the pixel 300 in the first embodiment in that a transistor is further provided between the front-stage circuit 310 and the front-stage node 320.

[0273] Fig.28 : is a circuit diagram showing a configuration example of a pixel 300 according to a first modification example of the first embodiment of the present technology. The pixel 300 of the first modification example of the first embodiment is different from the pixel 300 in the first embodiment in that a front-stage reset transistor 323 and a front-stage selection transistor 324 are further provided. In addition, the power supply voltage of each of the front-stage circuit 310 and the rear-stage circuit 350 of the first modification example of the first embodiment is set to VDD1.

[0274] The previous stage reset transistor 323 initializes the level of the previous stage node 320 by the power supply voltage VDD2. Preferably, the power supply voltage VDD2 is set to a value that satisfies the following equation.

[0275] VDD2=VDD1–Vgs……Formula 1

[0276] In the above formula, Vgs represents the gate-source voltage of the pre-stage amplifier transistor 315 .

[0277] By setting the value to satisfy Expression 1, the potential variation between the front-stage node 320 and the rear-stage node 340 in the dark can be reduced. Therefore, the photo response non-uniformity (PRNU) can be improved.

[0278] The previous stage selection transistor 324 opens and closes a path between the previous stage circuit 310 and the previous stage node 320 according to the previous stage selection signal sel received from the vertical scanning circuit 211 .

[0279] Fig.291 is a timing chart showing an example of global shutter operation according to the first variant of the first embodiment of the present technology. The timing chart of the first variant of the first embodiment is different from the timing chart of the first embodiment in that the vertical scanning circuit 211 also provides a front-stage reset signal rsta and a front-stage selection signal sel. Fig.29 In FIG. 1 , rsta_[n] and sel_[n] represent signals supplied to pixels in the nth row.

[0280] During the period from time T2 immediately before the end of exposure to time T5, the vertical scanning circuit 211 supplies the previous stage selection signal sel of high level to all pixels, and the previous stage reset signal rsta is controlled to be low level.

[0281] Fig.30 1 is a timing diagram showing an example of a read operation according to a first variant of the first embodiment of the present technology. When reading each row, the front-stage selection signal sel is controlled to a low level. This control causes the front-stage selection transistor 324 to be turned on, thereby disconnecting the front-stage node 320 from the front-stage circuit 310. Therefore, it is possible to block noise from the front-stage node 320 during reading.

[0282] Furthermore, during the reading period of the n-th row from the time T10 to the time T17 , the vertical scanning circuit 211 supplies the previous-stage reset signal rsta of a high level to the n-th row.

[0283] In addition, during reading, the vertical scanning circuit 211 controls the current source transistors 316 of all pixels to stop the supply of the current id1. In addition, the current id2 is supplied in a manner similar to the current id2 in the first embodiment. Therefore, the control of the current id1 becomes simpler than in the first embodiment.

[0284] As described above, according to the first modification of the first embodiment of the present technology, since the previous stage selection transistor 324 turns to the on state during reading to disconnect the previous stage circuit 310 from the previous stage node 320 , noise from the previous stage circuit 310 can be blocked.

[0285] [Second Modification]

[0286] In the first embodiment described above, each circuit in the solid-state imaging element 200 is arranged in a single semiconductor chip, but in the case where the pixel 300 is miniaturized, this configuration may result in that the element may not be accommodated in the semiconductor chip. The solid-state imaging element 200 of the second modified example of the first embodiment is different from the solid-state imaging element 200 in the first embodiment in that each circuit in the solid-state imaging element 200 is dispersedly arranged in two semiconductor chips.

[0287] Fig.311 is a diagram showing an example of a stacked structure of a solid-state imaging element 200 according to a second modification of the first embodiment of the present technology. The solid-state imaging element 200 of the second modification of the first embodiment includes a circuit chip 202 and a pixel chip 201 stacked on the circuit chip 202. For example, the two chips are electrically connected by Cu-Cu bonding. Note that the connection can be made not only by Cu-Cu bonding but also by vias (via: vertical interconnection path) or bumps.

[0288] An upper pixel array section 221 is provided in the pixel chip 201. A lower pixel array section 222 and a column signal processing circuit 260 are provided in the circuit chip 202. For each pixel in the pixel array section 220, a part of the pixels are arranged in the upper pixel array section 221, and the remaining pixels are arranged in the lower pixel array section 222.

[0289] In addition, a vertical scanning circuit 211, a control circuit 212, a DAC 213, and a load MOS circuit block 250 are also provided in the circuit chip 202. These circuits are not Fig.31 Shown in.

[0290] In addition, for example, the pixel chip 201 is manufactured by a pixel-specific process, and for example, the circuit chip 202 is manufactured by a CMOS (complementary MOS) process. Note that the pixel chip 201 is an example of a first chip described in the claims, and the circuit chip 202 is an example of a second chip described in the claims.

[0291] Fig.32 2 is a circuit diagram showing a configuration example of a pixel 300 according to a second modification of the first embodiment of the present technology. In the pixel 300, the pre-stage circuit 310 is arranged in the pixel chip 201, and other circuits and elements (such as capacitor elements 321 to 322, etc.) are arranged in the circuit chip 202. Note that a current source transistor 316 may be further arranged in the circuit chip 202. Fig.32 As shown, the elements included in the pixel 300 are dispersedly arranged in the pixel chip 201 and the circuit chip 202 stacked on each other, which makes it possible to reduce the pixel area, thereby facilitating the miniaturization of the pixel.

[0292] As described above, according to the second modification example of the first embodiment of the present technology, since the circuits and elements included in the pixel 300 are dispersedly arranged in two semiconductor chips, miniaturization of the pixel becomes easy.

[0293] [Third Modification]

[0294] In the second modified example of the first embodiment described above, a part of the pixel 300 and peripheral circuits (such as the column signal processing circuit 260, etc.) are provided in the lower circuit chip 202. However, in this configuration, the layout area of ​​each circuit and each element included in the circuit chip 202 is larger than the layout area of ​​the pixel chip 201 by an amount equivalent to the peripheral circuit, and therefore there is a possibility that unnecessary space where no circuit or element exists may appear in the pixel chip 201. The solid-state imaging element 200 of the third modified example of the first embodiment is different from the solid-state imaging element 200 of the second modified example of the first embodiment in that each circuit included in the solid-state imaging element 200 is dispersedly arranged in three semiconductor chips.

[0295] Fig.33 1 is a diagram showing an example of a stacked structure of a solid-state imaging element 200 according to a third modification of the first embodiment of the present technology. The solid-state imaging element 200 according to the third modification of the first embodiment includes an upper pixel chip 203, a lower pixel chip 204, and a circuit chip 202. These three chips are stacked and electrically connected, for example, by Cu-Cu bonding. Note that connection can be made not only by Cu-Cu bonding but also by vias or bumps.

[0296] An upper pixel array section 221 is provided in the upper pixel chip 203. A lower pixel array section 222 is provided in the lower pixel chip 204. For each pixel in the pixel array section 220, a part of the pixels are arranged in the upper pixel array section 221, and the remaining pixels are arranged in the lower pixel array section 222.

[0297] In addition, a column signal processing circuit 260, a vertical scanning circuit 211, a timing control circuit 212, a DAC 213, and a load MOS circuit block 250 are provided in the circuit chip 202. The circuits other than the column signal processing circuit 260 are not included in the circuit chip 202. Fig.33 Shown in.

[0298] Note that the upper pixel chip 203 is an example of a first chip described in the claims, and the lower pixel chip 204 is an example of a second chip described in the claims. The circuit chip 202 is an example of a third chip described in the claims.

[0299] By like Fig.33 The three-layer structure as shown can reduce unnecessary space compared to the two-layer structure and enable further miniaturization of pixels. In addition, the lower pixel chip 204 as the second layer can be manufactured by a dedicated process for capacitors or switches.

[0300] As described above, in the third modification of the first embodiment of the present technology, since the circuits included in the solid-state imaging element 200 are dispersedly arranged in three semiconductor chips, the pixel can be further miniaturized compared to the case where the circuits are dispersedly arranged in two semiconductor chips.

[0301] <7. Seventh Implementation Plan>

[0302] In the first embodiment described above, the reset level is sampled and held during the exposure period, but this configuration prevents the exposure period from being shorter than the sampling and holding period of the reset level. The solid-state imaging element 200 of this seventh embodiment is different from the solid-state imaging element 200 of the first embodiment in that a transistor for discharging charge from the photoelectric conversion element is added to make the exposure period shorter.

[0303] Fig.34 is a circuit diagram showing a configuration example of a pixel 300 according to a seventh embodiment of the present technology. The pixel 300 of the seventh embodiment is different from the pixel 300 of the first embodiment in that the pixel 300 further includes a discharge transistor 317 in the previous stage circuit 310 .

[0304] The drain transistor 317 functions as an overflow drain that discharges charges from the photoelectric conversion element 311 in accordance with a drain signal ofg received from the vertical scanning circuit 211. As the drain transistor 317, for example, an nMOS transistor can be used.

[0305] In a configuration in which the drain transistor 317 is not provided as in the first embodiment, blooming may be caused when all pixels transfer charges from the photoelectric conversion element 311 to the FD 314. Then, when the FD is reset, the potential of the FD 314 and the potential of the previous node 320 drop. In response to the drop in the potential, the charge and discharge currents of the capacitor elements 321 and 322 continue to be generated, and the IR drop of the power supply or the ground changes from a steady state without blooming.

[0306] On the other hand, when the signal levels of all pixels are sampled and held, after the transfer of the signal charge, the charge in the photoelectric conversion element 311 becomes an empty state, so that blooming does not occur, and the IR voltage drop of the power supply or the ground enters a steady state without blooming. Stripe noise occurs due to the difference between the IR voltage drop when the reset level is sampled and held and the IR voltage drop when the signal level is sampled and held.

[0307] In contrast, in the seventh embodiment in which the discharge transistor 317 is provided, the charge in the photoelectric conversion element 311 is discharged toward the overflow channel. Therefore, the IR drop when sampling and holding the reset level and the IR drop when sampling and holding the signal level become almost the same, so that the stripe noise can be suppressed.

[0308] Fig.35 1 is a timing chart showing an example of the global shutter operation according to the seventh embodiment of the present technology. At time T0 before the exposure start time, while the discharge signal ofg is set to a high level for all pixels, the vertical scanning circuit 211 supplies a high-level FD reset signal rst to all pixels during one pulse. As a result, PD reset and FD reset are performed on all pixels. In addition, the reset level is sampled and held. Here, Fig.35 ofg_[n] in represents a signal supplied to pixels in the nth row among N rows.

[0309] Then, at the time T1 when exposure starts, the vertical scanning circuit 211 returns the discharge signal ofg to a low level for all pixels. Then, during the period from the time T2 immediately before the end of exposure to the time T3 when the exposure ends, the vertical scanning circuit 211 supplies the transmission signal trg of a high level to all pixels. As a result, the signal level is sampled and held.

[0310] In a configuration in which the discharge transistor 317 is not provided as in the first embodiment, both the transfer transistor 312 and the FD reset transistor 313 must be turned on at the start of exposure (i.e., at the time of PD reset). By this control, at the time of PD reset, the FD 314 must also be reset at the same time. Therefore, it is necessary to perform FD reset again during the exposure period to sample and hold the reset level, and therefore, the exposure period cannot be shorter than the sampling and holding period of the reset level. When the reset levels of all pixels are sampled and held, a certain degree of waiting time is required until the voltage or current settles, and, for example, a sampling and holding period of several microseconds (μs) to several tens of microseconds (μs) is required.

[0311] In contrast, in the seventh embodiment in which the drain transistor 317 is provided, the PD reset and the FD reset can be performed separately. Fig.35 As shown, by performing FD reset before PD reset is released (exposure starts), the reset level can be sampled and held. Therefore, the exposure period can be made shorter than the sampling and holding period of the reset level.

[0312] Note that the first to third modifications of the first embodiment and the second to sixth embodiments can also be applied to the seventh embodiment.

[0313] As described above, according to the seventh embodiment of the present technology, since the discharge transistor 317 for discharging charge from the photoelectric conversion element 311 is provided, the reset level can be sampled and held by performing FD reset before the start of exposure. Therefore, the exposure period can be made shorter than the sampling and holding period of the reset level.

[0314] <8. Eighth Implementation Plan>

[0315] In the first embodiment described above, the FD 314 is initialized using the power supply voltage, but in this configuration, there is a possibility that the light response non-uniformity (PRNU) may be deteriorated due to the difference or parasitic capacitance of the capacitor elements 321 and 322. The solid-state imaging element 200 of the eighth embodiment is different from the solid-state imaging element 200 of the first embodiment in that the PRNU is improved by reducing the power supply of the FD reset transistor 313 at the time of reading.

[0316] Fig.36 is a circuit diagram showing a configuration example of a pixel 300 according to an eighth embodiment of the present technology. The pixel 300 of the eighth embodiment is different from the pixel 300 of the first embodiment in that the power supply of the FD reset transistor 313 is separate from the power supply voltage VDD of the pixel 300.

[0317] The drain of the FD reset transistor 313 of the third embodiment is connected to a reset power supply voltage VRST. The reset power supply voltage VRST is controlled by the control circuit 212, for example.

[0318] Here, refer to Fig.37 and Fig.38 Let us consider the degradation of PRNU in the pixel 300 of the first embodiment. In the first embodiment, Fig.37 As shown, at time T0 before the exposure start time, the potential of the FD 314 drops due to the reset feedthrough of the FD reset transistor 313. This variation is set to Vft.

[0319] In the first embodiment, since the power supply voltage of the FD reset transistor 313 is VDD, the potential of the FD 314 changes from VDD to VDD-Vft at time T0. In addition, during the exposure period, the potential of the previous stage node 320 becomes equal to VDD-Vft-Vgs.

[0320] Furthermore, in the first embodiment, if Fig.38As shown, at the time of reading, the FD reset transistor 313 is turned on to clamp the FD 314 to the power supply voltage VDD. The potential of the previous node 320 and the potential of the subsequent node 340 at the time of reading are shifted to a higher level by about the variation amount Vft of the FD 314. However, due to the difference in capacitance value or parasitic capacitance of the capacitor elements 321 and 322, the amount of voltage shifted is different for each pixel, which leads to the degradation of PRNU.

[0321] For example, when the previous node 320 changes Vft, the change amount of the subsequent node 340 is expressed by the following equation.

[0322] {(Cs+δCs) / (Cs+δCs+Cp)}×Vft…Equation 2

[0323] In the above formula, Cs represents the capacitance value of the capacitor element 322 on the signal level side, and δCs represents the difference of Cs. Cp is the capacitance value of the parasitic capacitance of the subsequent-stage node 340.

[0324] Formula 2 can be approximated as follows.

[0325] {1-(δCs / Cs)×(Cp / Cs)}×Vft……Formula 3

[0326] According to Formula 3, the difference of the subsequent node 340 can be expressed by the following formula.

[0327] {(δCs / Cs)×(Cp / Cs)}×Vft……Formula 4

[0328] According to Formula 4, when (δCs / Cs) is set to 10-2, (Cp / Cs) is set to 10-1, and Vft is set to 400 millivolts (mV), PRNU is 400 μVrms, which is a relatively large value.

[0329] In particular, in order to reduce the kTC noise during the sampling and holding of the input conversion capacitance, the charge-to-voltage conversion efficiency of FD314 must be improved. In order to improve the charge-to-voltage conversion efficiency, it is necessary to reduce the capacitance of FD314, but the smaller the capacitance of FD314, the greater the variation Vft will be, which may reach several hundred millivolts (mV). In this case, according to Equation 4, the influence of PRNU may not be negligible.

[0330] Fig.39 is a timing chart showing an example of voltage control according to the eighth embodiment of the present technology.

[0331] During the reading period in row units after the time T9, the control circuit 212 performs control so that the reset power supply voltage VRST differs from the value during the exposure period.

[0332] For example, during the exposure period, the control circuit 212 makes the reset power supply voltage VRST the same as the power supply voltage VDD. On the other hand, during the reading period, the timing control circuit 212 reduces the reset power supply voltage VRST to VDD-Vft. That is, during the reading period, the control circuit 212 reduces the reset power supply voltage VRST by an amount substantially equal to the variation amount Vft caused by the reset feedthrough. By this control, the reset level of the FD 314 can be made consistent during the exposure period and during the reading period.

[0333] By controlling the reset supply voltage VRST, such as Fig.39 As shown, it is possible to reduce the voltage variation of the FD 314 and the previous node 320. Therefore, it is possible to suppress the difference between the capacitor elements 321 and 322 and the degradation of the PRNU due to the parasitic capacitance.

[0334] Note that the first to third modifications of the first embodiment and the second to seventh embodiments can also be applied to the eighth embodiment.

[0335] As described above, according to the eighth embodiment of the present technology, since the control circuit 212 reduces the reset power supply voltage VRST by the variation amount Vft caused by the reset feedthrough during reading, the reset level can be made consistent during exposure and during reading. Therefore, it is possible to suppress the degradation of the photo response non-uniformity (PRNU).

[0336] <9. Ninth Implementation Plan>

[0337] In the first embodiment described above, the reset level and the signal level are sequentially read for each frame, but in this configuration, the light response non-uniformity (PRNU) may be deteriorated due to the difference or parasitic capacitance of the capacitor elements 321 and 322. The solid-state imaging element 200 of the present ninth embodiment is different from the solid-state imaging element 200 of the first embodiment in that the level held in the capacitor element 321 and the level held in the capacitor element 322 are switched for each frame, thereby improving the PRNU.

[0338] The solid-state image pickup element 200 of the ninth embodiment continuously captures a plurality of frames in synchronization with a vertical synchronization signal. An odd-numbered frame is referred to as an "odd-numbered frame", and an even-numbered frame is referred to as an "even-numbered frame".

[0339] Fig.401 is a timing chart showing an example of global shutter operation of odd-numbered frames according to the ninth embodiment. During the exposure period of each odd-numbered frame, the front-stage circuit 310 in the solid-state imaging element 200 sequentially sets the selection signal Φr and the selection signal Φs to a high level to first keep the capacitor element 321 at a reset level and then keep the capacitor element 322 at a signal level.

[0340] Fig.41 1 is a timing diagram showing an example of the reading operation of the odd-numbered frame according to the ninth embodiment of the present technology. During the reading period of each odd-numbered frame, the post-stage circuit 350 in the solid-state imaging element 200 sequentially sets the selection signal Φr and the selection signal Φs to high level to first read the reset level and then read the signal level.

[0341] Fig.42 1 is a timing diagram showing an example of global shutter operation of an even-numbered frame according to the ninth embodiment of the present technology. During the exposure period of each even-numbered frame, the front-stage circuit 310 in the solid-state imaging element 200 sequentially sets the selection signal Φs and the selection signal Φr to a high level to first keep the capacitor element 322 at a reset level and then keep the capacitor element 321 at a signal level.

[0342] Fig.43 1 is a timing diagram showing an example of the reading operation of the even-numbered frame according to the ninth embodiment of the present technology. During the reading period of each even-numbered frame, the post-stage circuit 350 in the solid-state imaging element 200 sequentially sets the selection signal Φs and the selection signal Φr to the high level to first read the reset level and then read the signal level.

[0343] like Fig.40 and Fig.42 As shown, for both the even frame and the odd frame, the level held in the capacitor element 321 and the level held in the capacitor element 322 are reversed. Thus, for both the even frame and the odd frame, the polarity of the PRNU is opposite. The column signal processing circuit 260 in the subsequent stage calculates the arithmetic average of the odd frame and the even frame. Therefore, the PRNUs with opposite polarities can be offset.

[0344] This control is effective in capturing a moving image or adding frames to each other. In addition, it is not necessary to add any element to the pixel 300, and this control can be realized only by changing the driving method.

[0345] Note that the first to third modifications of the first embodiment and the second to eighth embodiments can also be applied to the ninth embodiment.

[0346] As described above, in the ninth embodiment of the present technology, since the level held in the capacitor element 321 and the level held in the capacitor element 322 are reversed for both odd and even frames, the polarity of PRNU can be reversed for both odd and even frames. The column signal processing circuit 260 adds the odd and even frames, thereby suppressing the degradation of PRNU.

[0347] <10. Tenth Implementation Plan>

[0348] In the first embodiment described above, the column signal processing circuit 260 finds the difference between the reset level and the signal level for each column. However, in this configuration, when light with very high intensity is incident on a pixel, a black dot phenomenon may occur in which the brightness decreases and thus becomes black due to charge overflow of the photoelectric conversion element 311. The solid-state imaging element 200 of the tenth embodiment is different from the solid-state imaging element 200 of the first embodiment in that whether the black dot phenomenon occurs is determined for each pixel.

[0349] Fig.44 2 is a circuit diagram showing a configuration example of a column signal processing circuit 260 according to a tenth embodiment of the present technology. The column signal processing circuit 260 of the fifth embodiment is further provided with a plurality of CDS processing sections 291 and a plurality of selectors 292. The ADC 270, the CDS processing section 291 and the selector 292 are provided for each column.

[0350] In addition, the ADC 270 includes a comparison section 280 and a counter 271. The comparison section 280 compares the level of the vertical signal line 309 with the ramp signal Rmp received from the DAC 213, and outputs a comparison result VCO. The comparison result VCO is supplied to the counter 271 and the control circuit 212. The comparison section 280 includes: a selector 281; capacitor elements 282 and 283; auto-zero switches 284 and 286; and a comparator 285.

[0351] The selector 281 connects the vertical signal line 309 of the corresponding column or the node of the predetermined reference voltage VREF to the non-inverting input terminal (+) of the comparator 285 via the capacitor element 282 according to the input side selection signal selin. The input side selection signal selin is supplied from the control circuit 212.

[0352] The comparator 285 compares the level of the non-inverting input terminal (+) with the level of the inverting input terminal (−), and outputs the comparison result VCO to the counter 271. The ramp signal Rmp is input to the inverting input terminal (−) via the capacitor element 283.

[0353] The auto-zero switch 284 short-circuits the non-inverting input terminal (+) and the output terminal of the comparison result VCO according to the auto-zero signal AZ received from the control circuit 212. The auto-zero switch 286 short-circuits the inverting input terminal (-) and the output terminal of the comparison result VCO according to the auto-zero signal AZ.

[0354] The counter 271 counts the count value until the comparison result VCO is inverted, and outputs a digital signal CNT_out indicating the count value to the CDS processing unit 291 .

[0355] The CDS processing section 291 performs CDS processing on the digital signal CNT_out. The CDS processing section 291 calculates a difference between the digital signal CNT_out corresponding to the reset level and the data signal CNT_out corresponding to the signal level, and outputs the difference to the selector 292 as CDS_out.

[0356] The selector 292 outputs the digital signal CDS_out after CDS processing or the full-code digital signal FULL as the pixel data of the corresponding column to the data processing unit 262 according to the output side selection signal selout received from the control circuit 212 .

[0357] Fig.45 1 is a timing chart showing one example of the global shutter operation according to the tenth embodiment of the present technology. The control method of the transistor at the time of the global shutter according to the tenth embodiment is similar to the corresponding method of the first embodiment.

[0358] Here, it is assumed that light with very high intensity is incident on the pixel 300. In this case, the photoelectric conversion element 311 is full of charge, and the charge overflows from the photoelectric conversion element 311 to the FD 314, which causes the potential of the FD 314 to decrease after FD reset. Fig.45 The dot-dash line in shows the potential variation of FD314 when weak sunlight which causes a relatively small amount of charge overflow is incident. Fig.45 The dotted line in φ represents the potential variation of the FD 314 when strong sunlight that causes a relatively large amount of charge overflow is incident.

[0359] When weak sunlight is incident, at time T3 when the FD reset ends, the reset level drops, but the level has not dropped completely at this time.

[0360] On the other hand, when strong sunlight is incident, the reset level has completely dropped at time T3. In this case, the signal level becomes the same as the reset level, and the potential difference between the signal level and the reset level becomes "0", so that the digital signal after CDS processing becomes the same as the digital signal in the dark state, and thus becomes black. As described above, the phenomenon that the pixel becomes black despite the incident light with very high intensity such as sunlight is called a black dot phenomenon or highlight blooming.

[0361] In addition, if the level of FD 314 of the pixel where the black spot phenomenon has occurred is too low, the operating point of the front-stage circuit 310 cannot be ensured, and therefore the current id1 of the current source transistor 316 changes. Since the current source transistor 316 of each pixel is connected to a common power supply or ground, when the current of a certain pixel changes, the change of the IR voltage drop of the pixel will affect the sampling level of other pixels. The pixel where the black spot phenomenon has occurred becomes an aggressor, and the pixel where the sampling level change is caused by the pixel where the black spot phenomenon has occurred becomes a victim. As a result, stripe noise will appear.

[0362] Note that in the case where the discharge transistor 317 is provided as in the seventh embodiment, in the pixel suffering from black spots (blooming highlights), the overflowing charge is discharged toward the discharge transistor 317 side, so that the black spot phenomenon is less likely to occur. However, even if the discharge transistor 317 is provided, a part of the charge may flow to the FD 314, and the black spot phenomenon may be difficult to completely eliminate. In addition, there is a disadvantage that the ratio of the effective area / charge amount in each pixel becomes lower due to the addition of the discharge transistor 317. Therefore, it is preferable to suppress the black spot phenomenon without using the discharge transistor 317.

[0363] As a method of suppressing the black dot phenomenon without using the discharge transistor 317, there are two methods that can be considered. The first method is to adjust the clip level of the FD 314. The second method is a method of determining whether the black dot phenomenon occurs during reading, and when the black dot phenomenon occurs, replacing the output with a full code.

[0364] In the first method, Fig.45The high level of the FD reset signal rst in (in other words, the gate of the FD reset transistor 313) is equivalent to the power supply voltage VDD, and the low level is equivalent to the clipping level of the FD 314. In the first embodiment, the difference between the high level and the low level (i.e., the amplitude) is set to a value corresponding to the dynamic range. In contrast, in the tenth embodiment, the value is adjusted to a value to which an additional margin is also added. Here, the value corresponding to the dynamic range is equivalent to the difference between the power supply voltage VDD and the potential of the FD 314 when the digital signal becomes a full code.

[0365] By lowering the gate voltage (low level of the FD reset signal rst) when the FD reset transistor 313 is turned off, it is possible to prevent the FD 314 from excessively dropping due to blooming, and thereby prevent the operating point of the pre-stage amplifier transistor 315 from being destroyed.

[0366] Note that the dynamic range varies depending on the analog gain of the ADC. When the analog gain is low, the dynamic range needs to be wider, and conversely, when the analog gain is high, the dynamic range can be narrower. Therefore, the gate voltage when the FD reset transistor 313 is turned off can also be changed according to the analog gain.

[0367] Fig.46 is a timing chart showing an example of a read operation according to the tenth embodiment of the present technology. At time T11 immediately after the read start time T10, when the selection signal Φr becomes high level, the potential of the vertical signal line 309 varies in the pixel with incident sunlight. Fig.46 The dot-dash line in represents the potential variation of the vertical signal line 309 when weak sunlight is incident. Fig.46 The dotted line in represents the potential variation of the vertical signal line 309 when strong sunlight is incident.

[0368] During the auto-zero period from time T10 to time T12, for example, the control circuit 212 supplies the input side selection signal selin of "0" to connect the comparator 285 to the vertical signal line 309. During this auto-zero period, the control circuit 212 performs auto-zero by using the auto-zero signal AZ.

[0369] In the second method, for example, during the determination period from time T12 to time T13, the control circuit 212 provides an input side selection signal selin of "1". The input side selection signal selin disconnects the comparator 285 from the vertical signal line 309 and connects the comparator 285 to the node of the reference voltage VREF. The reference voltage VREF is set to an expected value of the level of the vertical signal line 309 when blooming is not generated. For example, when the gate-source voltage of the post-amplification transistor 351 is set to Vgs2, Vrst is equivalent to Vreg-Vgs2. In addition, during the determination period, the DAC 213 reduces the level of the ramp signal Rmp from Vrmp_az to Vrmp_sun.

[0370] Furthermore, in the determination period, when blooming does not occur, the reset level Vrst of the vertical signal line 309 is almost the same as the reference voltage VREF and does not change much from the case when the potential of the non-inverting input terminal (+) of the comparator 285 is auto-zeroed. On the other hand, since the inverting input terminal (-) is lowered from Vrmp_az to Vrmp_sun, the comparison result VCO becomes a high level.

[0371] Conversely, when blooming occurs, the reset level Vrst becomes sufficiently higher than the reference voltage VREF, and when the following expression is established, the comparison result VCO becomes a low level.

[0372] Vrst-VREF>Vrmp_az-Vrmp_sun……Equation 5

[0373] That is, the control circuit 212 can determine whether blooming has occurred based on whether the comparison result VCO changes to a low level during the determination period.

[0374] Note that in order to prevent misjudgment due to differences in threshold voltage of the subsequent amplifier transistor 351 or differences in IR drop of the in-plane Vreg, a large margin for solar determination (the right side of Equation 5) must be ensured.

[0375] After time T13 after the determination period ends, the control circuit 212 connects the comparator 285 to the vertical signal line 309. In addition, after the P-phase stable period from time T13 to time T14 ends, the P-phase is read during the period from time T14 to time T15. After the D-phase stable period from time T15 to time T19 ends, the D-phase is read during the period from time T19 to time T20.

[0376] When it is determined that blooming does not occur within the determination period, the control circuit 212 controls the selector 292 using the output-side selection signal selout so as to output the digital signal CDS_out after the CDS processing as it is.

[0377] On the other hand, when it is determined that blooming occurs during the determination period, the control circuit 212 uses the output side selection signal selout to control the selector 292 to output the full code FULL instead of the digital signal CDS_out after CDS processing. Therefore, the black dot phenomenon can be suppressed.

[0378] Note that the first to third modified examples of the first embodiment or the second to ninth embodiments can also be applied to the tenth embodiment.

[0379] As described above, according to the tenth embodiment of the present technology, since the control circuit 212 determines whether the black dot phenomenon occurs based on the comparison result VCO and outputs a full code when the black dot phenomenon occurs, the black dot phenomenon can be suppressed.

[0380] <11. Eleventh Implementation Plan>

[0381] In the first embodiment described above, the vertical scanning circuit 211 performs control for exposing all rows (all pixels) simultaneously (i.e., global shutter operation). However, in the case where simultaneity of exposure is not required but low noise is required during testing or analysis, it is desirable to perform rolling shutter operation. The solid-state imaging element 200 of this eleventh embodiment is different from the solid-state imaging element 200 of the first embodiment in that rolling shutter operation is performed during testing, etc.

[0382] Fig.47 11 is a timing chart showing an example of a rolling shutter operation according to the eleventh embodiment of the present technology. The vertical scanning circuit 211 performs control for sequentially selecting a plurality of rows and starting exposure. Fig.47 The exposure control of the nth row is shown.

[0383] During the period from time T0 to time T2, the vertical scanning circuit 211 supplies a high-level subsequent stage selection signal selb, a high-level selection signal Φr, and a high-level selection signal Φs to the n-th row. In addition, at time T0 when exposure starts, the vertical scanning circuit 211 supplies a high-level FD reset signal rst and a high-level subsequent stage reset signal rstb to the n-th row during one pulse period. At time T1 when exposure ends, the vertical scanning circuit 211 supplies a transfer signal trg to the n-th row. Fig.47 By performing a rolling shutter operation in the solid-state imaging element 200, it is possible to generate image data with low noise.

[0384] Note that during normal image pickup, the solid-state image pickup element 200 of the eleventh embodiment performs a global shutter operation in a manner similar to that of the first embodiment.

[0385] Furthermore, the first to third modified examples of the first embodiment or the second to tenth embodiments can also be applied to the eleventh embodiment.

[0386] As described above, according to the eleventh embodiment of the present technology, since the vertical scanning circuit 211 performs control for sequentially selecting a plurality of rows and starting exposure (ie, rolling shutter operation), low-noise image data can be generated.

[0387] <12. Twelfth Implementation Plan>

[0388] In the above-described first embodiment, the source of the front-stage source follower (the front-stage amplifier transistor 315 and the current source transistor 316) is connected to the power supply voltage VDD, and reading is performed in units of rows when the source follower is in the on state. However, in this driving method, the circuit noise of the front-stage source follower generated when reading is performed in units of rows is likely to propagate to the subsequent stage, and thus random noise increases. The solid-state imaging element 200 of this twelfth embodiment is different from the solid-state imaging element 200 of the first embodiment in that noise is reduced by keeping the front-stage source follower in the off state during reading.

[0389] Fig.48 1 is a block diagram showing a configuration example of a solid-state imaging element 200 according to a twelfth embodiment of the present technology. The solid-state imaging element 200 of the twelfth embodiment is different from the solid-state imaging element 200 of the first embodiment in that a regulator 420 and a switching section 440 are further provided. Fig.48 In the embodiment, the communication interfaces 214 and 215 are not shown. In addition, the pixel array section 220 of the twelfth embodiment has an arrangement of a plurality of effective pixels 301 and a predetermined number of dummy pixels 430. The dummy pixels 430 are arranged around the area where the plurality of effective pixels 301 are arranged.

[0390] Furthermore, the power supply voltage VDD is supplied to each of the dummy pixels 430 , and the power supply voltage VDD and the source voltage Vs are supplied to each of the effective pixels 301 . Fig.48 Not shown in FIG. 3 is a signal line for supplying the power supply voltage VDD to the effective pixel 301. In addition, the power supply voltage VDD is supplied from a pad 410 located outside the solid-state imaging element 200.

[0391] The regulator 420 generates a constant generated voltage Vgen based on the input voltage Vi received from the dummy pixel 430, and supplies the generated voltage Vgen to the switching section 440. The switching section 440 selects the power supply voltage VDD from the pad 410 or the generated voltage Vgen from the regulator 420, and supplies the selected voltage as the source voltage Vs to each column of the effective pixel 301.

[0392] Fig.49 is a circuit diagram showing a configuration example of a dummy pixel 430, a regulator 420, and a switch section 440 according to a twelfth embodiment of the present technology. Fig.49 , a is a circuit diagram of the dummy pixel 430 and the regulator 420 , and b is a circuit diagram of the switch section 440 .

[0393] like Fig.49 As shown in a in FIG. 1 , the dummy pixel 430 includes a reset transistor 431, an FD 432, an amplifier transistor 433, and a current source transistor 434. The reset transistor 431 initializes the FD 432 according to the reset signal RST received from the vertical scanning circuit 211. The FD 432 is used to accumulate charge and generate a voltage corresponding to the amount of charge. The amplifier transistor 433 amplifies the level of the voltage of the FD 432 and supplies the amplified voltage as the input voltage Vi to the regulator 420.

[0394] In addition, the sources of the reset transistor 431 and the amplifier transistor 433 are each connected to the power supply voltage VDD. The current source transistor 434 is connected to the drain of the amplifier transistor 433. The current source transistor 434 supplies the current id1 under the control of the vertical scanning circuit 211.

[0395] The regulator 420 includes a low-pass filter 421, a buffer amplifier 422, and a capacitor element 423. The low-pass filter 421 allows a component in a low frequency band lower than a predetermined frequency among the signals of the input voltage Vi to pass as an output voltage Vj.

[0396] The output voltage Vj is input to the non-inverting input terminal (+) of the buffer amplifier 422. The inverting input terminal (−) of the buffer amplifier 422 is connected to the output terminal of the buffer amplifier 422. The capacitor element 423 holds the voltage of the output terminal of the buffer amplifier 422 to Vgen. This Vgen is supplied to the switch section 440.

[0397] like Fig.49 As shown in b in FIG. 8 , the switching unit 440 includes an inverter 441 and a plurality of switching circuits 442 . The switching circuits 442 are arranged one by one for each column of the effective pixels 301 .

[0398] The inverter 441 inverts the switching signal SW received from the control circuit 212. The inverter 441 supplies the inverted signal to each of the switching circuits 442.

[0399] The switching circuits 442 each select the power supply voltage VDD or the generated voltage Vgen, and supply the selected voltage as the source voltage Vs to the corresponding column in the pixel array section 220. The switching circuit 442 includes switches 443 and 444. The switch 443 opens and closes the path between the node of the power supply voltage VDD and the corresponding column according to the switching signal SW. The switch 444 opens and closes the path between the node of the generated voltage Vgen and the corresponding column according to the inverted signal of the switching signal SW.

[0400] Fig.50 1 is a timing diagram showing an example of how the dummy pixel 430 and the regulator 420 according to the twelfth embodiment of the present technology operate. At a time T10 before a row is about to be read, the vertical scanning circuit 211 supplies a reset signal RST of a high level (here, the power supply voltage VDD) to each of the dummy pixels 430. The potential Vfd of the FD 432 in each of the dummy pixels 430 is initialized to the power supply voltage VDD. Then, when the reset signal RST becomes low, reset feedthrough causes the potential Vfd to change to VDD-Vft.

[0401] After the reset, the input voltage Vi drops to VDD-Vgs-Vft. Due to the pass action of the low-pass filter 421, Vj and Vgen become almost constant voltages.

[0402] After the timing T20 immediately before reading of the next row is performed, similar control is performed for each row, and a constant generated voltage Vgen is supplied.

[0403] Fig.51 1 is a circuit diagram showing a configuration example of an effective pixel 301 according to a twelfth embodiment of the present technology. The circuit structure of the effective pixel 301 is similar to that of the pixel 300 of the first embodiment except that the source voltage Vs from the switching section 440 is supplied to the source of the pre-stage amplifier transistor 315.

[0404] Fig.52 1 is a timing diagram showing an example of global shutter operation according to the twelfth embodiment of the present technology. In the twelfth embodiment, when all pixels are exposed at the same time, the switching section 440 selects the power supply voltage VDD and supplies the power supply voltage VDD as the source voltage Vs. In addition, at time T4, the voltage of the previous node 320 decreases from VDD-Vgs-Vth to VDD-Vgs-Vsig. Here, Vth represents the threshold voltage of the transfer transistor 312.

[0405] Fig.53 1 is a timing chart showing an example of a read operation according to the twelfth embodiment of the present technology. In the twelfth embodiment, at the time of reading, the switching section 440 selects the generated voltage Vgen and supplies the generated voltage Vgen as the source voltage Vs. The generated voltage Vgn is adjusted to VDD-Vgs-Vft. In addition, in the twelfth embodiment, the vertical scanning circuit 211 controls the current source transistors 316 of all rows (all pixels) to stop the supply of the current id1.

[0406] Fig.54 3 is a diagram for explaining the effect according to the twelfth embodiment of the present technology. In the first embodiment, when reading in units of rows, the source follower (the front-stage amplifier transistor 315 and the current source transistor 316) of the pixel 300 to be read is turned on. However, in this driving method, the circuit noise of the front-stage source follower is likely to propagate to the rear stage (capacitor element, rear-stage source follower, and ADC), and therefore, the read noise increases.

[0407] For example, in a first embodiment, Fig.54 As shown in FIG. 1 , the kTC noise generated in the pixel during the global shutter operation is 450 μVrms. In addition, when reading in units of rows, the noise generated in the front-stage source follower (the front-stage amplifier transistor 315 and the current source transistor 316) is 380 μVrms. The noise generated by the rear-stage source follower and thereafter is 160 μVrms. Therefore, the total noise is 610 μVrms. In this way, in the first embodiment, the proportion of the noise of the front-stage source follower in the total noise value becomes relatively large.

[0408] In order to reduce the noise of the preceding source follower, in the twelfth embodiment, as described above, an adjustable voltage (Vs) is supplied to the source of the preceding source follower. During the global shutter (exposure) operation, the switching section 440 selects the power supply voltage VDD and supplies the power supply voltage VDD as the source voltage Vs. Then, after the exposure ends, the switching section 440 switches the source voltage Vs to VDD-Vgs-Vft. In addition, during the global shutter (exposure) operation, the control circuit 212 turns on the current source transistor 316 of the preceding stage, and after the exposure ends, the control circuit 212 turns off the current source transistor 316 of the preceding stage.

[0409] like Fig.52 and Fig.53 As shown in FIG. 1 , by the above control, the potential of the front-stage node is consistent when the global shutter is operated and when reading is performed in units of rows, thereby making it possible to improve PRNU. In addition, since the front-stage source follower is turned off when reading is performed in units of rows, Fig.54As shown, the circuit noise of the source follower is not generated but becomes 0 μVrms. Note that in the front-stage source follower, the front-stage amplifier transistor 315 is in the on state.

[0410] As described above, according to the twelfth embodiment of the present technology, since the preceding-stage source follower is placed in an off state during reading, noise generated in the source follower can be reduced.

[0411] <13. Application examples of mobile objects>

[0412] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device mounted on any type of mobile body including but not limited to automobiles, electric vehicles, hybrid vehicles, automatic motorcycles, bicycles, personal mobility vehicles, airplanes, unmanned aerial vehicles, ships, and robots.

[0413] Fig.55 is a block diagram of an example of a schematic configuration of a vehicle control system as one example of a moving body control system to which the technology according to the present disclosure can be applied.

[0414] The vehicle control system 12000 includes a plurality of electronic control units interconnected via a communication network 12001. Fig.55 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F: interface) 12053 are shown.

[0415] The drive system control unit 12010 controls the operation of the devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for the following devices: a drive force generating device such as an internal combustion engine, a drive motor, etc. for generating a drive force for the vehicle; a drive force transmitting mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating a braking force for the vehicle.

[0416] The body system control unit 12020 controls the operation of various devices equipped on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for the following devices: a keyless entry system; a smart key system; a power window device; or various lights such as headlights, reverse lights, brake lights, turn signals, fog lights, etc. In this case, radio waves emitted from a portable device that replaces the key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, power window device, lights, etc. of the vehicle.

[0417] The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the vehicle exterior and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform processing for detecting an object such as a person, a vehicle, an obstacle, a sign, or text on the road surface, or processing for detecting the distance to the object.

[0418] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as distance measurement information. In addition, the light received by the imaging unit 12031 may be visible light, or may be non-visible light such as infrared light.

[0419] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the state of the driver. For example, the driver state detection unit 12041 includes a camera for photographing the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or the driver's concentration level, or can determine whether the driver is dozing off.

[0420] Based on the information outside or inside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device, and output the control instruction to the driving system control unit 12010. For example, the microcomputer 12051 can perform coordinated control for realizing the functions of ADAS (Advanced Driver Assistance System), the functions of which include collision avoidance or impact mitigation of the vehicle, following driving based on vehicle-to-vehicle distance, vehicle constant speed driving, vehicle collision warning, vehicle lane departure warning, etc.

[0421] In addition, based on the information outside or inside the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform coordinated control such as automatic driving aimed at enabling the vehicle to drive autonomously without the need for driver operation by controlling the driving force generating device, steering mechanism or braking device, etc.

[0422] In addition, based on the information outside the vehicle obtained by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control instruction to the body system control unit 12020. For example, based on the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030, the microcomputer 12051 can perform coordinated control for achieving anti-glare, such as by controlling the headlights to switch from high beam to low beam.

[0423] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle occupants or the outside of the vehicle of information. Fig.55 In the illustrated example, as output devices, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are illustrated. For example, the display portion 12062 may include at least one of an onboard display and a head-up display.

[0424] Fig.56 This is a diagram showing an example of the installation position of the camera unit 12031.

[0425] exist Fig.56 In the figure, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104 and 12105.

[0426] For example, the camera units 12101, 12102, 12103, 12104 and 12105 are arranged at the front bumper, side mirrors, rear bumper, trunk door and the upper part of the windshield in the vehicle 12100. The camera unit 12101 arranged at the front bumper and the camera unit 12105 arranged at the upper part of the windshield in the vehicle mainly acquire images in front of the vehicle 12100. The camera units 12102 and 12103 arranged at the side mirrors mainly acquire images on the sides of the vehicle 12100. The camera unit 12104 arranged at the rear bumper or trunk door mainly acquires images behind the vehicle 12100. The camera unit 12105 arranged at the upper part of the windshield in the vehicle is mainly used to detect vehicles in front, pedestrians, obstacles, signal lights, traffic signs, lanes, etc.

[0427] By the way, Fig.56 An example of the imaging range of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front bumper. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the side mirrors. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the trunk door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, it is possible to obtain a bird's-eye view image of the vehicle 12100 viewed from above.

[0428] At least one of the imaging units 12101 to 12104 may have a function capable of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0429] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can obtain the distance to each solid object within the camera ranges 12111 to 12114 and the change in the distance over time (relative speed relative to the vehicle 12100), thereby extracting the following solid object as the leading vehicle: it is particularly the closest solid object on the driving path of the vehicle 12100 and is a solid object that travels at a predetermined speed (for example, 0 km / h or more) in the same direction as the vehicle 12100. In addition, the microcomputer 12051 can set the inter-vehicle distance that should be ensured in advance with respect to the leading vehicle, and can perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. Therefore, it is possible to perform coordinated control for realizing automatic driving, etc., which enables the vehicle to travel autonomously without the need for driver operation.

[0430] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into three-dimensional object data of two-wheeled vehicles, ordinary cars, large vehicles, pedestrians, telephone poles and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually perceive and obstacles that the driver of the vehicle 12100 is difficult to visually perceive. Then, the microcomputer 12051 determines the collision risk used to represent the degree of danger of collision with each obstacle. In the case where the collision risk is equal to or greater than the set value and there is a possibility of collision, the microcomputer 12051 issues a warning to the driver via the audio speaker 12061 or the display unit 12062, or performs forced deceleration or evasive steering via the drive system control unit 12010. Therefore, the microcomputer 12051 can provide assisted driving for avoiding collisions.

[0431] At least one of the camera units 12101 to 12104 may be an infrared camera capable of detecting infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the image captured by the camera units 12101 to 12104. For example, such identification of pedestrians is performed by the following process: a process of extracting feature points from the image captured by the camera units 12101 to 12104 as infrared cameras; and a process of performing pattern matching processing on a series of feature points representing the contour of the object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that there is a pedestrian in the image captured by the camera units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 to display a square contour line for emphasis superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 to display an icon or the like representing a pedestrian at a desired position.

[0432] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the camera unit 12031 in the above-mentioned configuration. Specifically, for example, Figure 1 The solid-state imaging element 200 in the embodiment can be applied to the imaging section 12031. By applying the technology according to the present disclosure to the imaging section 12031, the convenience of the system can be improved.

[0433] Note that the above-mentioned embodiments show examples for implementing the present technology, and each item in each embodiment has a corresponding relationship with the specific items of the present invention recorded in the claims. Similarly, the specific items of the present invention recorded in the claims and the items with the same name in each embodiment of the present technology have a corresponding relationship. However, the present technology is not limited to each embodiment, and can be implemented by implementing various modifications to each embodiment without departing from the scope of protection of the present technology.

[0434] Note that the effects described herein are merely examples and not limitations, and other effects may also be achieved.

[0435] Note that this technology can also have the following technical solutions.

[0436] (1) A solid-state imaging element comprising:

[0437] a pixel array section having an arrangement of a plurality of pixels, each of the plurality of pixels being configured to generate a pixel signal and to sample and hold the pixel signal;

[0438] a vertical scanning circuit that drives each of the plurality of rows in the pixel array section to output the pixel signal;

[0439] a signal processing circuit that reads the pixel signal and performs predetermined signal processing on the pixel signal; and

[0440] A control circuit controls at least one of the vertical scanning circuit and the signal processing circuit to generate compressed data obtained by compressing image data containing the arrangement of the pixel signals, and the control circuit controls at least one of the vertical scanning circuit and the signal processing circuit according to the result of processing the compressed data to output cut-out data corresponding to a predetermined area cut out from the image data.

[0441] (2) The solid-state imaging device according to (1) above, wherein:

[0442] The control circuit generates data obtained by thinning out the image data in row units and / or in column units as the compressed data.

[0443] (3) The solid-state imaging device according to (1) above, wherein:

[0444] The signal processing circuit includes a compression processing unit that generates the compressed data by pixel addition.

[0445] (4) The solid-state imaging device according to (3) above, wherein:

[0446] The signal processing circuit further includes: a plurality of analog-to-digital converters, each of which converts the pixel signal into a digital signal.

[0447] The pixel signal comprises an analog signal, and

[0448] The compression processing unit generates the compressed data by adding the digital signals.

[0449] (5) The solid-state imaging device according to (3) above, wherein:

[0450] The signal processing circuit further includes: a plurality of analog-to-digital converters, each of which converts the pixel signal into a digital signal.

[0451] The pixel signal comprises an analog signal, and

[0452] The compression processing unit generates the compressed data by adding the pixel signals.

[0453] (6) The solid-state imaging element according to any one of (1) to (5) above, further including a detection processing unit that performs a predetermined detection process on the compressed data.

[0454] (7) The solid-state imaging device according to (6) above, wherein:

[0455] The signal processing circuit outputs the processing result to the outside of the solid-state imaging element.

[0456] (8) The solid-state imaging device according to (6) above, wherein:

[0457] The detection processing unit detects whether there is a face.

[0458] (9) The solid-state imaging device according to (6) above, wherein:

[0459] The detection processing unit detects whether there is a person.

[0460] (10) The solid-state imaging device according to (6) above, wherein:

[0461] The detection processing unit detects a difference between the compressed data and predetermined background data.

[0462] (11) The solid-state imaging device according to (1) above, further comprising:

[0463] A communication interface receives the result of the processing and supplies the result to the control circuit.

[0464] (12) The solid-state imaging device according to any one of (1) to (11) above, wherein:

[0465] The pixel signal includes a predetermined reset level and a signal level corresponding to an exposure amount, and

[0466] Each of the plurality of pixels comprises:

[0467] a first capacitor element and a second capacitor element;

[0468] a preceding stage circuit that sequentially generates the reset level and the signal level and causes the first capacitor element and the second capacitor element to respectively maintain the reset level and the signal level;

[0469] A selection circuit that sequentially performs: control for connecting one of the first capacitor element and the second capacitor element to a predetermined subsequent node, control for disconnecting both the first capacitor element and the second capacitor element from the subsequent node, and control for connecting the other of the first capacitor element and the second capacitor element to a predetermined subsequent node.

[0470] Describing the control of the subsequent nodes;

[0471] a subsequent-stage reset transistor that initializes a level of the subsequent-stage node when both the first capacitor element and the second capacitor element are disconnected from the subsequent-stage node; and

[0472] A subsequent-stage circuit sequentially reads the reset level and the signal level from the first capacitor element and the second capacitor element via the subsequent-stage node and outputs the reset level and the signal level.

[0473] (13) A camera system comprising:

[0474] A solid-state imaging device comprising:

[0475] a pixel array section having an arrangement of a plurality of pixels, each of the plurality of pixels being configured to generate a pixel signal and to sample and hold the pixel signal;

[0476] a vertical scanning circuit that drives each of the plurality of rows in the pixel array section to output the pixel signal;

[0477] a signal processing circuit that reads the pixel signal and performs predetermined signal processing on the pixel signal; and

[0478] a control circuit that controls at least one of the vertical scanning circuit and the signal processing circuit to generate compressed data obtained by compressing image data containing the arrangement of the pixel signals, and controls at least one of the vertical scanning circuit and the signal processing circuit to output cutout data corresponding to a predetermined area cut out from the image data based on a result of processing the compressed data; and

[0479] A host computer performs a process different from the process according to the cut-out data.

[0480] (14) A method for controlling a solid-state imaging element, the method comprising:

[0481] A vertical scanning step in which a vertical scanning circuit is caused to drive each of a plurality of rows in a pixel array section having an arrangement of a plurality of pixels, each of the plurality of pixels being configured to generate a pixel signal and sample and hold the pixel signal to output the pixel signal;

[0482] a signal processing step in which a signal processing circuit is caused to read the pixel signal and perform predetermined signal processing on the pixel signal; and

[0483] Control step: In this step, at least one of the vertical scanning circuit and the signal processing circuit is controlled to generate compressed data by compressing image data including the arrangement of the pixel signals, and based on the result of processing the compressed data, at least one of the vertical scanning circuit and the signal processing circuit is controlled to output cut-out data corresponding to a predetermined area cut out from the image data.

[0484] Reference numerals list

[0485] 100: Camera system

[0486] 110: Host

[0487] 111, 112: Communication interface

[0488] 113: Database

[0489] 114: Authentication Processing Department

[0490] 115: Camera control unit

[0491] 116, 265: Detection and processing unit

[0492] 117, 266: Cut-out area calculation unit

[0493] 118: Behavior Assessment Department

[0494] 150: Camera device

[0495] 200: Solid-state imaging device

[0496] 201: Pixel chip

[0497] 202: Circuit Chip

[0498] 203: Upper pixel chip

[0499] 204: Lower pixel chip

[0500] 211: Vertical scanning circuit

[0501] 212: Control circuit

[0502] 213: DAC (Digital-to-Analog Converter)

[0503] 214, 215: Communication interface

[0504] 220: Pixel array unit

[0505] 221: Upper pixel array portion

[0506] 222: Lower pixel array portion

[0507] 250: Load MOS circuit block

[0508] 251: Load MOS transistor

[0509] 260: Column signal processing circuit

[0510] 261, 264: Compression processing unit

[0511] 262: Data Processing Department

[0512] 263: Demultiplexer

[0513] 270: ADC (Analog-to-Digital Converter)

[0514] 271: Counter

[0515] 280: Comparison Department

[0516] 281, 292: Selector

[0517] 282, 283, 321, 322, 423: Capacitor elements

[0518] 284, 286: Automatic zeroing switch

[0519] 285: Comparator

[0520] 291: CDS (correlated double sampling) processing unit

[0521] 300: Pixels

[0522] 301: Effective pixels

[0523] 310: Pre-stage circuit

[0524] 311: Photoelectric conversion element

[0525] 312: Pass transistor

[0526] 313: FD reset transistor

[0527] 314, 432: FD (floating diffusion)

[0528] 315: Pre-amplifier transistor

[0529] 316, 434: Current source transistor

[0530] 317: discharge transistor

[0531] 323: Pre-stage reset transistor

[0532] 324: Pre-select transistor

[0533] 330: Select Circuit

[0534] 331, 332: Select transistor

[0535] 341: Rear reset transistor

[0536] 350: Post-stage circuit

[0537] 351: Post-amplifier transistor

[0538] 352: Post-stage selection transistor

[0539] 420: Regulator

[0540] 421: Low pass filter

[0541] 422: Buffer Amplifier

[0542] 430: Dummy pixel

[0543] 431: Reset transistor

[0544] 433: Amplifying transistor

[0545] 440: Switching Department

[0546] 441: Inverter

[0547] 442: Switching Circuit

[0548] 443, 444: switch

[0549] 12031: Camera Department

Claims

1. A solid-state imaging element, comprising: a pixel array section having an arrangement of a plurality of pixels, each of the plurality of pixels being configured to generate a pixel signal and to sample and hold the pixel signal; a vertical scanning circuit that drives each of the plurality of rows in the pixel array section to output the pixel signal; a signal processing circuit that reads the pixel signal and performs predetermined signal processing on the pixel signal; and A control circuit controls at least one of the vertical scanning circuit and the signal processing circuit to generate compressed data obtained by compressing image data containing the arrangement of the pixel signals, and the control circuit controls at least one of the vertical scanning circuit and the signal processing circuit according to the result of processing the compressed data to output cut-out data corresponding to a predetermined area cut out from the image data.

2. The solid-state imaging element according to claim 1, wherein The control circuit generates data obtained by thinning out the image data in row units and / or in column units as the compressed data.

3. The solid-state imaging element according to claim 1, wherein The signal processing circuit includes a compression processing unit that generates the compressed data by pixel addition.

4. The solid-state imaging element according to claim 3, wherein: The signal processing circuit further includes: a plurality of analog-to-digital converters, each of which converts the pixel signal into a digital signal. The pixel signal comprises an analog signal, and The compression processing unit generates the compressed data by adding the digital signals.

5. The solid-state imaging element according to claim 3, wherein: The signal processing circuit further includes: a plurality of analog-to-digital converters, each of which converts the pixel signal into a digital signal. The pixel signal comprises an analog signal, and The compression processing unit generates the compressed data by adding the pixel signals.

6. The solid-state imaging element according to claim 1, further comprising: A detection processing unit performs a predetermined detection process on the compressed data.

7. The solid-state imaging element according to claim 6, wherein: The signal processing circuit outputs the processing result to the outside of the solid-state imaging element.

8. The solid-state imaging element according to claim 6, wherein: The detection processing unit detects whether there is a face.

9. The solid-state imaging element according to claim 6, wherein: The detection processing unit detects whether there is a person.

10. The solid-state imaging element according to claim 6, wherein: The detection processing unit detects a difference between the compressed data and predetermined background data.

11. The solid-state imaging element according to claim 1, further comprising: A communication interface receives the result of the processing and supplies the result to the control circuit.

12. The solid-state imaging element according to claim 1, wherein The pixel signal includes a predetermined reset level and a signal level corresponding to an exposure amount, and Each of the plurality of pixels comprises: a first capacitor element and a second capacitor element; a preceding stage circuit that sequentially generates the reset level and the signal level and causes the first capacitor element and the second capacitor element to respectively maintain the reset level and the signal level; a selection circuit that sequentially performs: a control for connecting one of the first capacitor element and the second capacitor element to a predetermined subsequent-stage node, a control for disconnecting both the first capacitor element and the second capacitor element from the subsequent-stage node, and a control for connecting the other of the first capacitor element and the second capacitor element to the subsequent-stage node; a subsequent-stage reset transistor that initializes a level of the subsequent-stage node when both the first capacitor element and the second capacitor element are disconnected from the subsequent-stage node; and A subsequent-stage circuit sequentially reads the reset level and the signal level from the first capacitor element and the second capacitor element via the subsequent-stage node and outputs the reset level and the signal level.

13. Camera system, including: A solid-state imaging device comprising: a pixel array section having an arrangement of a plurality of pixels, each of the plurality of pixels being configured to generate a pixel signal and to sample and hold the pixel signal; a vertical scanning circuit that drives each of the plurality of rows in the pixel array section to output the pixel signal; a signal processing circuit that reads the pixel signal and performs predetermined signal processing on the pixel signal; and a control circuit that controls at least one of the vertical scanning circuit and the signal processing circuit to generate compressed data obtained by compressing image data containing the arrangement of the pixel signals, and controls at least one of the vertical scanning circuit and the signal processing circuit to output cutout data corresponding to a predetermined area cut out from the image data based on a result of processing the compressed data; and A host computer performs a process different from the process according to the cut-out data.

14. A control method for a solid-state imaging element, the control method comprising: A vertical scanning step in which a vertical scanning circuit is caused to drive each of a plurality of rows in a pixel array section to output a pixel signal, the pixel array section having an arrangement of a plurality of pixels each configured to generate the pixel signal and to sample and hold the pixel signal; Signal processing step: In this step, a signal processing circuit is caused to read the pixel signal and perform predetermined signal processing on the pixel signal; as well as Control step: In this step, at least one of the vertical scanning circuit and the signal processing circuit is controlled to generate compressed data obtained by compressing the image data containing the arrangement of the pixel signals, and in this step, at least one of the vertical scanning circuit and the signal processing circuit is controlled according to the result of processing the compressed data to output cut-out data corresponding to a predetermined area cut out from the image data.

Images