Flash memory error correction method and device, medium and SSD (Solid State Disk) equipment

Abstract

The invention relates to the technical field of data storage, and provides a flash memory error correction method and device, a medium and SSD equipment, and the method comprises the steps: carrying out the error correction of a first target die based on an RAID5 error correction technology, and obtaining first error correction data; obtaining a first target read voltage of the first target die and first target data read by adopting the first target read voltage; carrying out XOR operation on the target data read by the first target die under the read voltages at the preset positions on the two sides of the first target read voltage so as to obtain expected error position data of the first target die; executing an XOR operation on the first error correction data and the first target data to obtain first error position data; and judging a real error position of a first target die according to the expected error position data and the first error position data, and performing error correction processing on the first target data according to the real error position of the first target die to obtain correct data of the first target die. According to the invention, the adaptation capability and reliability of the flash memory are enhanced.

Description

Technical Field

[0001] The present invention relates to the field of data storage technology, and in particular to a flash memory error correction method, device, medium and SSD equipment. Background Art

[0002] NAND Flash has been widely used in the storage field due to its large storage capacity, low power consumption, compatibility with silicon processes, good polymorphic characteristics, and non-volatility. However, as the number of NAND Flash read and write times increases, when a large number of errors appear in the stored information, these errors cannot be corrected by the preset error correction technology, and finally an uncorrectable error situation occurs. This situation is also called UNC (uncorrectable in English).

[0003] Currently, RAID5 error correction technology has been widely used in SSD development. RAID5 technology only needs one redundant NAND Flash die to achieve high-speed and high-concurrency data read and write operations and ensure data correctness. Usually, RAID5 is configured with N+1 dies in SSD. RAID5 technology can ensure that any of the N+1 dies can guarantee the correctness of the data in this die through the correct information on other dies when its own error correction capability (such as BCH and LDPC error correction) cannot correct the error. However, when two dies cannot correct errors at the same time, RAID5 error correction technology cannot correct the information of any or both of the two dies through the correct information on other dies. As a result, errors occur in the stored information. Summary of the invention

[0004] In order to solve the above technical problem or at least partially solve the above technical problem, the present invention provides a flash memory error correction method, apparatus, medium and SSD device.

[0005] One aspect of the present invention provides a flash memory error correction method for correcting an error when a UNC error is simultaneously generated on a first target die and a second target die in a flash memory, the method comprising:

[0006] Correct the first target die based on the RAID5 error correction technology to obtain first error correction data of the first target die;

[0007] Acquire a first target read voltage of a first target die and first target data read by using the first target read voltage;

[0008] Performing an XOR operation on target data read from the first target die at read voltages at preset positions on both sides of the first target read voltage to obtain expected error position data of the first target die;

[0009] Performing an XOR operation on the first error correction data and the first target data to obtain first error location data, where the first error location data includes an error location of the first target die at a first target read voltage and an error location of the second target die at a second target read voltage;

[0010] The actual error position of the first target die is determined according to the expected error position data and the first error position data, and the first target data is error corrected according to the actual error position of the first target die to obtain correct data of the first target die.

[0011] Further, the first target read voltage of the first target die is an optimal read voltage of the first target die, and obtaining the first target read voltage of the first target die includes:

[0012] Obtaining a quasi-optimal read voltage of a first target die;

[0013] Performing a read voltage scan around the quasi-optimal read voltage of the first target die according to a specified read voltage scan range to obtain first target scan data read under different read voltages;

[0014] Performing an exclusive OR operation on each first target scanning data read at different read voltages and the first error correction data respectively, obtaining first error position scanning data corresponding to each read voltage, and obtaining the number of error positions in each first error position scanning data;

[0015] The read voltage corresponding to the first error location scan data having the least number of error locations is selected as the optimal read voltage for the first target die.

[0016] Further, the performing error correction on the first target die based on the RAID5 error correction technology to obtain first error correction data of the first target die includes:

[0017] Acquire a second target read voltage of a second target die and second target data read by using the second target read voltage;

[0018] The first target die is corrected based on the second target data of the second target die and the RAID5 error correction technology.

[0019] Further, the determining the actual error position of the first target die according to the expected error position data and the first error position data includes:

[0020] comparing the first error position marked in the first error position data with the expected error position marked in the expected error position data;

[0021] A portion of the first error position data where the first error position does not overlap with the expected error position is flipped to eliminate the error position of the second target die and obtain a true error position of the first target die.

[0022] Further, the performing error correction processing on the first target data according to the actual error position of the first target die includes:

[0023] S51, selecting some error positions from the real error positions of the first target die as target positions to be flipped;

[0024] S52, performing a flip operation on the data in the target to-be-flipped bit in the first target data to obtain first original data of the first target die;

[0025] S53, decoding the first original data of the first target die, and determining whether the decoding is successful, if the decoding is successful, executing step S541, if the decoding fails, executing step S542;

[0026] S541, using the data successfully obtained by decoding as the correct data of the first target die;

[0027] S542, select some error positions from the unselected real error positions of the first target die as newly added target bits to be flipped, and repeat the operations of steps S52-S53 until decoding is successful.

[0028] Further, after obtaining the correct data of the first target die, the method further includes:

[0029] The second target die is corrected based on the correct data of the first target die and the RAID5 error correction technology to obtain the correct data of the second target die.

[0030] Another aspect of the present invention further provides a flash memory error correction device for correcting errors when a UNC error is simultaneously generated on a first target die and a second target die in a flash memory, the device comprising:

[0031] A first error correction module, configured to perform error correction on the first target die based on a RAID5 error correction technology to obtain first error correction data of the first target die;

[0032] A first acquisition module, used to acquire a first target read voltage of a first target die and first target data read by using the first target read voltage;

[0033] A first position acquisition module, used for performing an XOR operation on target data read from the first target die at a read voltage at preset positions on both sides of the first target read voltage, so as to obtain expected error position data of the first target die;

[0034] A second position acquisition module, configured to perform an XOR operation on the first error correction data and the first target data to obtain first error position data, wherein the first error position data includes an error position of the first target die at a first target read voltage and an error position of the second target die at the first target read voltage;

[0035] A second error correction module is used to determine the actual error position of the first target die according to the expected error position data and the first error position data, and perform error correction processing on the first target data according to the actual error position of the first target die to obtain correct data of the first target die.

[0036] Further, the first target read voltage of the first target die is an optimal read voltage of the first target die, and the first acquisition module includes:

[0037] A first acquisition submodule, used to acquire a quasi-optimal read voltage of a first target die;

[0038] a scanning module, configured to perform a read voltage scan around the quasi-optimal read voltage of the first target die according to a specified read voltage scan range to obtain first target scan data read under different read voltages,

[0039] a position acquisition submodule, used to perform an exclusive OR operation on each first target scanning data read at different read voltages and the first error correction data, respectively, to obtain first error position scanning data corresponding to each read voltage, and to obtain the number of error positions in each first error position scanning data;

[0040] The optimal read voltage selection submodule is used to select the read voltage corresponding to the first error position scanning data with the least number of error positions as the optimal read voltage of the first target die.

[0041] Another aspect of the present invention provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above methods are implemented.

[0042] Another aspect of the present invention further provides an SSD device, which includes a storage controller, the storage controller includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the above method when executing the program.

[0043] The flash memory error correction method, device, medium and SSD device provided by the present invention perform error correction on the first target die based on the RAID5 error correction technology to obtain the first error correction data of the first target die, and obtain the expected error position data of the first target die by performing an XOR operation on the target data read by the first target die at the read voltage at the preset positions on both sides of the first target read voltage; obtain the first error position data by performing an XOR operation on the first error correction data and the first target data; since the first error correction data contains the error information of the second target die and the first target data contains the error information of the first target die, after performing the XOR operation, the first error position data will simultaneously contain the error position of the first target die at the first target read voltage and the error position of the second target die at the second target read voltage; since the expected error position data contains the position where the first target die may have an error, the error position introduced by the second target die can be flipped according to the expected error position data and the first error position data, thereby obtaining the real error position of the first target die, and then the first target data is error-corrected based on the real error position, so that the correct data of the first target die can be obtained. Based on RAID5, the present invention does not need to change the existing hardware design and encoding and decoding algorithm, and can realize the error correction of the first target die through software operation, thereby enhancing the adaptability and reliability of the flash memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0045] Figure 1 1 is a probability distribution diagram of the same error bit number in different dies in an embodiment of the present invention;

[0046] Figure 2 A schematic diagram of a flash memory error correction method according to an embodiment of the present invention;

[0047] Figure 3 A schematic diagram of error data distribution of a flash memory error correction method according to an embodiment of the present invention;

[0048] Figure 4 Schematic diagram of the optimal reading voltage in an embodiment of the present invention;

[0049] Figure 5 Schematic diagram of the structure of a flash memory error correction device in an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0051] Before introducing the flash memory error correction method according to the embodiment of the present invention, a brief introduction to the background technology of the present invention is given first:

[0052] Optimal read voltage: The information stored in NAND Flash is represented and encoded by the threshold voltage of the storage cell in a specific range. By setting a reasonable read voltage, these voltage ranges can be distinguished and read errors can be reduced. Usually, the read voltage can be adjusted within a certain range. The read bias voltage that minimizes the error of the read information is called the optimal read voltage.

[0053] Threshold voltage distribution: The English name is threshold voltage distribution. NAND Flash is represented and encoded by the threshold voltage of the storage cell in a specific range. The threshold voltages of many storage cells in a specific range will form a statistical distribution, and this statistical distribution is the threshold voltage distribution.

[0054] RAID error correction technology: also known as redundant array of disks technology, it ensures storage speed and data reliability through parallel transmission and redundant information bits. Currently, this technology is divided into multiple levels, and each level has its own application scenario regardless of its merits. Among them, RAID5 and RAID6 technologies have been widely used in SSD storage. RAID5 technology distributes data and parity on all N+1 dies, and can ensure data security when one of the dies cannot correct errors. RAID6 technology can ensure data security when two dies cannot correct errors. The present invention mainly improves and explains RAID5 technology.

[0055] UNC: The English name is uncorrectable. Usually it is because there are a lot of errors in the stored information, and these errors cannot be corrected by the preset error correction technology, and finally an uncorrectable situation occurs.

[0056] Among them, RAID5 technology can be expressed as N+1, that is, one die is used to store the check information bit, and the data of this die is obtained by XOR operation of the data at the same position in N dies. If there is a data error in the N+1 dies, the correct data can be obtained by XOR operation of the data at the same position in other dies with correct data. At the same time, each die has its own data protection measures. However, if UNC appears in the data of two dies, then it is obvious that RAID5 technology cannot achieve the error correction effect in this working mode. The present invention makes corresponding improvements to the existing RAID5 technology that cannot achieve the data error correction capability of two dies.

[0057] In addition, before introducing the flash memory error correction method provided by the embodiment of the present invention in detail, the present invention first proves that the probability of the error bit occurring in the same position in the same page of two dies in NAND Flash is extremely low. The size of an error correction unit frame is M (such as 1024B*8=8096b), assuming that the number of frame errors in the two dies is L, then the probability of the same position error is calculated as shown in the following formula:

[0058]

[0059] Figure 1 The probability distribution of the number of bit errors at the same position when taking different L values. It can be seen from the figure that when the number of common errors is greater than 6, the probability is less than 1% (L=60~140). Therefore, it can be concluded that the probability of erroneous bits at the same position in the same page of two dies in NAND Flash is extremely low.

[0060] Based on the above facts, the flash memory error correction method proposed in the embodiment of the present invention is as follows: Figure 2 As shown, the present invention is mainly used to correct errors when UNC errors are generated simultaneously on a first target die and a second target die in a flash memory. The method comprises the following steps:

[0061] S1. Correct the first target die based on RAID5 error correction technology to obtain first error correction data of the first target die;

[0062] In the embodiment of the present invention, the error correction of the first target die based on the RAID5 error correction technology is specifically performed by performing an XOR operation on the data of all dies other than the first target die to obtain the first error correction data of the first target die. At this time, since the data on the second target die also has errors, the errors of the second target die are obviously introduced into the first error correction data.

[0063] It should be noted that the present invention can perform error correction on the data of the first target die based on the data of the second target die, and can also perform error correction on the first target die based on the second target data at the optimal read voltage of the second target die after the optimal read voltage of the second target die. At this time, the error positions of the second target die introduced into the first error correction data are minimized, thereby further reducing the probability of the error positions of the first die and the second die overlapping.

[0064] S2, obtaining a first target read voltage of a first target die and first target data read using the first target read voltage;

[0065] In an embodiment of the present invention, the first target read voltage of the first target die may be a current read voltage of the first target die or a quasi-optimal read voltage selected based on calculation of a scanning algorithm. As a preferred embodiment of the present invention, the first target read voltage of the first target die may also be an optimal read voltage of the first target die. Since the information error read out of the first target die is minimal under the optimal read voltage, the probability of overlap with the error position of the second target die will be further reduced.

[0066] S3, performing an XOR operation on the target data read from the first target die at the read voltages at the preset positions on both sides of the first target read voltage to obtain expected error position data of the first target die;

[0067] In the embodiment of the present invention, if the two values ​​subjected to the XOR operation are the same, 0 is output, and if they are different, 1 is output. The XOR operation is performed on the target data at the preset positions on both sides of the first target read voltage to identify the position where the error may occur in the first target die. At this time, the position where the error may occur is 1, and the position where the error will not occur is 0. By observing the position of 1, the position where the read error may occur in the first target die, that is, the expected error position, can be obtained.

[0068] S4, performing an XOR operation on the first error correction data and the first target data to obtain first error position data, where the first error position data includes an error position of the first target die at a first target read voltage and an error position of the second target die at a second target read voltage;

[0069] In the embodiment of the present invention, since the first error correction data includes errors caused by the second target die, and the first target data includes errors caused by the first target die, and since the overlap rate of the error positions of the two is very low, after performing the XOR operation, if the two values ​​at the same position are the same, 0 is output, and if they are different, 1 is output. At this time, the positions causing the errors all output bit 1, so the error position of the data can be judged by the position of 1, but the first error position data at this time cannot distinguish whether it is an error caused by the first target die or an error caused by the second target die.

[0070] S5. Determine the true error position of the first target die according to the expected error position data and the first error position data, and perform error correction processing on the first target data according to the true error position of the first target die to obtain correct data of the first target die.

[0071] In the embodiment of the present invention, the first error position data includes the error position caused by the first target die and the error position caused by the second target die, and the expected error position data includes the position where the first target die may have an error, based on which the error position caused by the second target die can be determined, and then the real error position of the first target die can be determined. Then, based on the real error position of the first target die, the first target data can be corrected to obtain the original data of the first target die. After obtaining the original data of the first target die, the original data of the first target die is input into the currently used decoder for decoding, and the correct data of the first target die is obtained. Through the RAID5 technology, the correct data of the second target can be further obtained based on the correct data of the first target die.

[0072] Based on RAID5, the present invention does not need to change the existing hardware design and encoding and decoding algorithm, and realizes the error correction capability of two target dies through software operation, thereby enhancing the adaptability and reliability of the flash memory.

[0073] Further, in the embodiment of the present invention, when the first target read voltage of the first target die is the optimal read voltage of the first target die, obtaining the first target read voltage of the first target die in step S2 specifically further includes the following steps:

[0074] S21, obtaining a quasi-optimal read voltage of a first target die;

[0075] The present invention uses a preset modeling method or algorithm to find the lowest point between two adjacent states, and uses the read voltage corresponding to the lowest point as the quasi-optimal read voltage of the storage unit. The preset modeling method or algorithm is a prior art and will not be described in detail in the present invention.

[0076] S22, performing a read voltage scan around the quasi-optimal read voltage of the first target die according to a specified read voltage scan range to obtain first target scan data read under different read voltages;

[0077] In the embodiment of the present invention, a first target scan data can be obtained under each different read voltage, and when the scan read voltage is the optimal read voltage, the first target scan data has the least error data. In the embodiment of the present invention, the scan range of the read voltage should be smaller than the distance between the two peak voltages of the threshold voltage distribution state.

[0078] S23, performing an exclusive OR operation on each first target scanning data read at different read voltages and the first error correction data, respectively, to obtain first error position scanning data corresponding to each read voltage, and obtaining the number of error positions in each first error position scanning data;

[0079] In the embodiment of the present invention, the error positions of the second target die contained in the first error correction data will not change, and the change in the number of error positions after each XOR operation is caused by the first target die. Therefore, when the total number of error positions is the least, the scanning read voltage of the first target die is the optimal read voltage.

[0080] S24, selecting a read voltage corresponding to the first error location scan data having the least number of error locations as an optimal read voltage for the first target die.

[0081] In the embodiment of the present invention, the optimal read voltage is unknown when error correction cannot be successful. The obtained optimal read voltage is usually erroneous. The larger the error of the found optimal read voltage is, the more erroneous data will be read in the first target die, and the probability of overlapping with the erroneous information in the second target die will increase, affecting the final error correction result.

[0082] Although it has been verified in the aforementioned embodiments that the probability of the same-position error occurring in the two storage media is very low, in order to further ensure the accuracy of the error correction of the present invention, the optimal read voltage of the first target die is obtained by scanning, thereby further reducing the probability of the error overlap between the first target die and the second target die.

[0083] Furthermore, in step S1, by searching for the quasi-optimal read voltage of the second target die, data with the least error positions of the second target die can be obtained. Therefore, in a preferred embodiment of the present invention, the error correction of the first target die based on the RAID5 error correction technology includes: obtaining the second target read voltage of the second target die and the second target data read using the second target read voltage; and error correction of the first target die based on the second target data of the second target die and the RAID5 error correction technology. At this time, the obtained first error correction data can include the error position of the second target die under the second target read voltage.

[0084] Furthermore, the second target read voltage of the second target die may be a quasi-optimal read voltage of the second target die or an optimal read voltage of the second target die, wherein the quasi-optimal read voltage of the second target die is most preferred, that is, the quasi-optimal read voltage of the second target die is calculated based on the scanning algorithm.

[0085] In the embodiment of the present invention, the original error of the second target die is reduced by finding the second target read voltage of the second target die, and the first error position data obtained in executing step S4 includes the error position of the first target die under the first target read voltage and the error position of the second target die under the second target read voltage of the second target die, which further reduces the probability of overlap of the error positions of the first target die and the second target die, thereby improving the accuracy of error correction.

[0086] Further, in step S3, when an XOR operation is performed on the target data read from the first target die at the read voltages at the preset positions on both sides of the first target read voltage, the read voltages at the preset positions on both sides of the first target read voltage should be between the peak voltages of the threshold voltage distribution states on the left and right of the optimal read voltage of the first target die, that is, the read voltage of the first target die at the preset position on the left side of the first target read voltage is a read voltage between the optimal read voltage of the first target die and the peak voltage of the threshold voltage distribution state on the left side of the first target die, and the read voltage of the first target die at the preset position on the right side of the first target read voltage is a read voltage between the optimal read voltage of the first target die and the peak voltage of the threshold voltage distribution state on the right side of the first target die.

[0087] It should be noted that for a bistable (SLC, Single-Level Cell) memory cell, the flash memory cell has two stable threshold voltage states. When executing step S3, an XOR operation is performed on the target data read at the read voltages at the preset positions on both sides of the first target read voltage of the two stable threshold voltages. For a multi-stable (MLC / TLC / QLC, etc.) memory cell, this is achieved by increasing the number of stable states of the threshold voltage. At this time, when executing step S3, an XOR operation is performed on the target data read at the read voltages at the preset positions on the left side of the multiple target voltages and the target data read at the read voltages at the preset positions on the right side of the multiple target voltages.

[0088] like Figure 3 As shown, the boundary of the threshold voltage distribution state is the end of the two threshold voltage distribution states at the dotted line position, and the preset positions on the left and right sides should not exceed the peak position of the threshold voltage distribution state to ensure that in two data readings, one read is the correct data related to the best read voltage in the first target die, and the other read is the wrong data related to the best read voltage of the first target die. After the XOR operation, the position where the error may occur in the first target die can be obtained.

[0089] Further, in step S5, determining the true error position of the first target die based on the expected error position data and the first error position data specifically includes: comparing the first error position marked in the first error position data with the expected error position marked in the expected error position data; flipping the portion of the first error position in the first error position data that does not overlap with the expected error position to eliminate the error position of the second target die and obtain the true error position of the first target die.

[0090] Furthermore, in the embodiment of the present invention, the error correction processing of the first target data based on the real error position of the first target die further includes the following steps:

[0091] S51, selecting some error positions from the real error positions of the first target die as target positions to be flipped;

[0092] In the embodiment of the present invention, some error positions of the real error positions of the first target die may be randomly selected as target positions to be flipped, and the specific number of selected positions may be set according to actual conditions.

[0093] S52, performing a flip operation on the data in the target to-be-flipped bit in the first target data to obtain first original data of the first target die;

[0094] S53, decoding the first original data of the first target die, and determining whether the decoding is successful, if the decoding is successful, executing step S541, if the decoding fails, executing step S542;

[0095] It should be noted that the original data after the flip operation is performed in step S52 may still contain error information. At this time, the decoder needs to decode the first original data. If the number of error data in the first original data is within the error correction capability of the decoder, the decoding is successful to obtain the correct data of the first target die. If the decoding is unsuccessful, the number of errors in the first original data exceeds the error correction capability of the decoder. At this time, it is necessary to increase the target number of to-be-flipped bits of the first target data and re-decode until the decoding is successful to obtain the correct data of the first target die.

[0096] S541, using the successfully decoded data as the correct data of the first target die;

[0097] S542, select some error positions from the unselected real error positions of the first target die as newly added target bits to be flipped, and repeat the operations of steps S52-S53 until decoding is successful.

[0098] In an embodiment of the present invention, when repeatedly performing a flip operation, the flip operation can be performed on the data at the target position to be flipped in the original first target data, or the flip operation can be performed only on the data at the newly added target position to be flipped based on the first original data obtained in the last iteration to obtain the first original data in this iteration.

[0099] In the embodiment of the present invention, after step S5, the second target die is corrected based on the correct data of the first target die and the RAID5 error correction technology to obtain the real data of the second target die, thereby completing the error correction of the two target dies at the same time.

[0100] The following is combined with Figure 4 The flash memory error correction method of the present invention is further described in detail in the specific embodiment of the present invention. In the specific embodiment of the present invention, the first target die is die7, and the second target die is die2, wherein:

[0101] Figure 4 (a) is the error correction data of die7 obtained by performing an XOR operation on other dies except die7, where the gray circles are errors in the error correction data caused by the erroneous data in die2. It should be noted that this figure is a simplified demonstration and the actual position of the gray circles is unknown.

[0102] Figure 4(b) is the data read from die7, where the blue circle is the erroneous data in die7 and the actual position of the blue circle is also unknown.

[0103] Figure 4 (c) Figure 4 (a) and Figure 4 The result of performing XOR operation on two sets of data in (b) is understandable, because Figure 4 (a) and Figure 4 (b) shows the data in die7. Except for the error position, the data in other positions are the same. The data after the XOR operation is zero. Figure 4 (a) and Figure 4 (b) The error position is different, that is, the position where it is different from the actual data in die7 is different. After performing the XOR operation, the data at these positions is 1. Figure 4 (c) shows all the error locations in die2 and die7, as shown by the locations of the gray and blue circles in the figure. The yellow circles are the common error locations of die2 and die7. Obviously, according to the previous assumptions and arguments, the probability of common errors is very low, so the probability of yellow circles appearing is very low.

[0104] Figure 4 (d) is the data of die7 under different read voltages when the read voltage of die7 is scanned. Figure 4 (a) is a schematic diagram of the result of performing an XOR operation on the data. Figure 3 It can be seen that during the read voltage scan, the error position caused by the gray circle will not change, and the number and position of the blue circle will change with the change of the read voltage. It should be noted that in actual applications, the yellow origin, that is, the position where common errors occur in die2 and die7 is rare. Therefore, the optimal read voltage of die7 can be determined by judging the number of 1s after the XOR operation.

[0105] Figure 4 (e) is the result of reading the die7 data once at the preset positions on both sides of the optimal read voltage in die7 and performing an XOR operation. The position shown in the figure is the expected error position of die7.

[0106] Figure 4 (f) is the expected error position based on die7 Figure 4 The actual error position of die 7 is obtained by flipping the first error position data with the least error position selected in (d). Figure 4 (f) The data within the solid circle is retained, and the data in the first error position that is not in the solid circle is replaced. Figure 4 (f) Data flipping within the solid circle.

[0107] After obtaining the true error position of die7, the data of die7 can be corrected according to the true error position of die7, that is, the data at the true error position is flipped to obtain the correct original data of die7, and the correct data of die7 can be obtained by decoding. After obtaining the true original data of die7, the correct original data of die2 can be obtained by performing an XOR operation on other dies except die2, and the correct data of die2 can be obtained after decoding, thus completing the error correction of the two dies at the same time.

[0108] For the method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0109] Figure 5 The schematic diagram of the structure of a flash memory error correction device according to an embodiment of the present invention is shown. The device is used to correct errors when UNC errors occur simultaneously on the first target die and the second target die in the flash memory. Figure 5 The flash memory error correction device of the embodiment of the present invention specifically includes a first error correction module 501, a first acquisition module 502, a first position acquisition module 503, a second position acquisition module 504, and a second error correction module 504, wherein:

[0110] A first error correction module 501 is used to perform error correction on the first target die based on the RAID5 error correction technology to obtain first error correction data of the first target die;

[0111] A first acquisition module 502 is used to acquire a first target read voltage of a first target die and first target data read using the first target read voltage;

[0112] A first position acquisition module 503 is used to perform an XOR operation on target data read from the first target die at a read voltage at preset positions on both sides of the first target read voltage to obtain expected error position data of the first target die;

[0113] A second position acquisition module 504 is used to perform an XOR operation on the first error correction data and the first target data to obtain first error position data, where the first error position data includes an error position of the first target die at the first target read voltage and an error position of the second target die;

[0114] The second error correction module 505 is used to determine the actual error position of the first target die according to the expected error position data and the first error position data, and perform error correction processing on the first target data according to the actual error position of the first target die to obtain correct data of the first target die.

[0115] Further, the first target read voltage of the first target die is an optimal read voltage of the first target die, and the first acquisition module includes:

[0116] A first acquisition submodule, used to acquire a quasi-optimal read voltage of a first target die;

[0117] a scanning module, configured to perform a read voltage scan around the quasi-optimal read voltage of the first target die according to a specified read voltage scan range to obtain first target scan data read under different read voltages,

[0118] a position acquisition submodule, used to perform an exclusive OR operation on each first target scanning data read at different read voltages and the first error correction data, respectively, to obtain first error position scanning data corresponding to each read voltage, and to obtain the number of error positions in each first error position scanning data;

[0119] The optimal read voltage selection submodule is used to select the read voltage corresponding to the first error position scanning data with the least number of error positions as the optimal read voltage of the first target die.

[0120] Furthermore, the flash memory error correction device of the embodiment of the present invention further includes:

[0121] A second acquisition module, used to acquire a second target read voltage of a second target die and second target data read by using the second target read voltage;

[0122] The first error correction module 501 is specifically used to correct the first target die based on the second target data of the second target die and the RAID5 error correction technology, so that the obtained first error correction data includes the error position under the optimal read voltage of the second target die.

[0123] Furthermore, the second error correction module specifically includes:

[0124] A comparison submodule, used for comparing the first error position marked in the first error position data with the expected error position marked in the expected error position data;

[0125] The real error position acquisition submodule is used to flip the part of the first error position data that does not overlap with the expected error position to eliminate the error position of the second target die and obtain the real error position of the first target die.

[0126] A selection submodule, used to select some error positions from the real error positions of the first target die as target positions to be flipped;

[0127] a correction flip submodule, configured to perform a flip operation on the data in the target to-be-flipped bit in the first target data to obtain first original data of the first target die;

[0128] A decoding module, used for decoding first original data of a first target die;

[0129] A judgment submodule is used to judge whether the decoding is successful. If the decoding is successful, the module goes to the data output submodule. If the decoding fails, the module goes to the second selection submodule.

[0130] A data output submodule, used to use the data successfully obtained by decoding as the correct data of the first target die;

[0131] The second selection submodule selects some error positions from the unselected real error positions of the first target die as newly added target positions to be flipped, and returns to the correction flip submodule until decoding is successful.

[0132] Furthermore, the first error correction module 501 of the embodiment of the present invention is also used to correct the second target die based on the correct data of the first target die and the RAID5 error correction technology after obtaining the correct data of the first target die, so as to obtain the correct data of the second target die.

[0133] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0134] In addition, an embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the steps of the above method are implemented.

[0135] In this embodiment, if the module / unit integrated in the SSD device is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media does not include electrical carrier signals and telecommunication signals.

[0136] In addition, an embodiment of the present invention further provides an SSD device, which includes a storage controller, the storage controller includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the steps of the above method when executing the program. Figure 2 Alternatively, when the processor executes the computer program, the functions of each module / unit in the above flash memory error correction device embodiment are realized, for example Figure 5 The first error correction module 501, the first acquisition module 502, the first position acquisition module 503, the second position acquisition module 504 and the second error correction module 505 are shown.

[0137] The flash memory error correction method, apparatus, medium and SSD device provided in the present embodiment correct errors of the first target die based on the RAID5 error correction technology to obtain first error correction data of the first target die, and obtain expected error position data of the first target die by performing an XOR operation on the target data read from the first target die at the read voltage at the preset positions on both sides of the first target read voltage; obtain first error position data by performing an XOR operation on the first error correction data and the first target data; since the first error correction data includes the error information of the second target die and the first target data includes the error information of the first target die, after performing the XOR operation, the first error position data will simultaneously include the error position of the first target die at the first target read voltage and the error position of the second target die at the second target read voltage; since the expected error position data includes the position where the first target die may have an error, the error position introduced by the second target die can be flipped according to the expected error position data and the first error position data, thereby obtaining the real error position of the first target die, and then the first target data is error-corrected based on the real error position, so that the correct data of the first target die can be obtained, and the correct data of the second target die can be obtained through the RAID5 technology according to the correct data of the first target die. Based on RAID5, the present invention does not need to change the existing hardware design and encoding and decoding algorithm, and realizes the error correction capability of two target dies through software operation, thereby enhancing the adaptability and reliability of the flash memory.

[0138] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0139] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0140] In addition, those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present invention and form different embodiments. For example, any one of the claimed embodiments may be used in any combination.

[0141] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A flash memory error correction method, characterized in that: For correcting an error when a UNC error is simultaneously generated on a first target die and a second target die in a flash memory, the method comprising: Correct the first target die based on the RAID5 error correction technology to obtain first error correction data of the first target die; Acquire a first target read voltage of a first target die and first target data read using the first target read voltage; Performing an XOR operation on target data read from the first target die at a read voltage at preset positions on both sides of the first target read voltage to obtain expected error position data of the first target die; Performing an XOR operation on the first error correction data and the first target data to obtain first error location data, where the first error location data includes an error location of the first target die at a first target read voltage and an error location of the second target die at a second target read voltage; The actual error position of the first target die is determined according to the expected error position data and the first error position data, and the first target data is error corrected according to the actual error position of the first target die to obtain correct data of the first target die.

2. The method according to claim 1, characterized in that The first target read voltage of the first target die is an optimal read voltage of the first target die, and obtaining the first target read voltage of the first target die includes: Obtaining a quasi-optimal read voltage of a first target die; Performing a read voltage scan around the quasi-optimal read voltage of the first target die according to a specified read voltage scan range to obtain first target scan data read under different read voltages; Performing an exclusive OR operation on each first target scanning data read at different read voltages and the first error correction data respectively, obtaining first error position scanning data corresponding to each read voltage, and obtaining the number of error positions in each first error position scanning data; The read voltage corresponding to the first error location scan data having the least number of error locations is selected as the optimal read voltage for the first target die.

3. The method according to claim 2, characterized in that The error correction of the first target die based on the RAID5 error correction technology includes: Acquire a second target read voltage of a second target die and second target data read by using the second target read voltage; The first target die is corrected based on the second target data of the second target die and the RAID5 error correction technology.

4. The method according to any one of claims 1 to 3, characterized in that Determining the actual error position of the first target die according to the expected error position data and the first error position data includes: comparing the first error position marked in the first error position data with the expected error position marked in the expected error position data; A portion of the first error position data where the first error position does not overlap with the expected error position is flipped to eliminate the error position of the second target die and obtain a true error position of the first target die.

5. The method according to claim 4, characterized in that The performing error correction processing on the first target data according to the actual error position of the first target die includes: S51, selecting some error positions from the real error positions of the first target die as target positions to be flipped; S52, performing a flip operation on the data in the target to-be-flipped bit in the first target data to obtain first original data of the first target die; S53, decoding the first original data of the first target die, and determining whether the decoding is successful, if the decoding is successful, executing step S541, if the decoding fails, executing step S542; S541, using the data successfully obtained by decoding as the correct data of the first target die; S542, select some error positions from the unselected real error positions of the first target die as newly added target bits to be flipped, and repeat the operations of steps S52-S53 until decoding is successful.

6. The method according to claim 5, characterized in that After obtaining the correct data of the first target die, the method further includes: The second target die is corrected based on the correct data of the first target die and the RAID5 error correction technology to obtain the correct data of the second target die.

7. A flash memory error correction device, characterized in that: The device is used to correct a UNC error when a first target die and a second target die in a flash memory simultaneously generate an error, the device comprising: A first error correction module, configured to perform error correction on the first target die based on a RAID5 error correction technology to obtain first error correction data of the first target die; A first acquisition module, used to acquire a first target read voltage of a first target die and first target data read by using the first target read voltage; A first position acquisition module, used for performing an XOR operation on target data read from the first target die at a read voltage at preset positions on both sides of the first target read voltage, so as to obtain expected error position data of the first target die; A second position acquisition module, configured to perform an XOR operation on the first error correction data and the first target data to obtain first error position data, wherein the first error position data includes an error position of the first target die at a first target read voltage and an error position of the second target die at a second target read voltage; A second error correction module is used to determine the actual error position of the first target die according to the expected error position data and the first error position data, and perform error correction processing on the first target data according to the actual error position of the first target die to obtain correct data of the first target die.

8. The device according to claim 7, characterized in that The first target read voltage of the first target die is an optimal read voltage of the first target die, and the first acquisition module includes: A first acquisition submodule, used to acquire a quasi-optimal read voltage of a first target die; a scanning module, configured to perform a read voltage scan around the quasi-optimal read voltage of the first target die according to a specified read voltage scan range to obtain first target scan data read under different read voltages, a position acquisition submodule, used to perform an exclusive OR operation on each first target scanning data read at different read voltages and the first error correction data, respectively, to obtain first error position scanning data corresponding to each read voltage, and to obtain the number of error positions in each first error position scanning data; The optimal read voltage selection submodule is used to select the read voltage corresponding to the first error position scanning data with the least number of error positions as the optimal read voltage of the first target die.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. An SSD device, characterized in that: The SSD device includes a storage controller, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method as described in any one of claims 1 to 6 when executing the program.

Images