Chip and memory management method thereof
By using memory area linked lists in the chip to search and map idle memory blocks, the memory fragmentation problem caused by continuous memory allocators and the inadequate use of memory management units for applications is solved, and more efficient memory management and usage is achieved.
Patent Information
- Application Number
- CN202411337539.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-24
- Publication Date
- 2025-01-17
AI Technical Summary
The continuous memory allocator in the prior art is prone to memory fragmentation, and the memory management unit cannot be effectively used for system applications, reducing the flexibility of memory usage.
Design a chip that includes memory management circuit and computing circuit, searches for idle memory blocks through memory area linked lists and performs memory mapping, optimizes memory allocation and management, and improves memory usage efficiency.
It effectively avoids memory fragmentation, improves memory usage flexibility, and enables the system to utilize memory resources more efficiently.
Smart Images
Figure CN119322755A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of memory technology, and in particular to a chip and a memory management method thereof. Background Art
[0002] Contiguous Memory Allocator (CMA) and Memory Management Unit (MMU) are two common memory allocation and / or management methods in Linux systems. The contiguous memory allocator is suitable for allocating continuous and large blocks of memory, but its disadvantage is that it is easy to cause memory fragmentation.
[0003] The memory management unit provides a mapping between virtual memory addresses and physical memory addresses. However, the memory blocks reserved for the memory management unit can only be used by devices, but not by system applications, which greatly reduces the flexibility of memory usage.
[0004] Therefore, a better approach to memory management is needed. Summary of the invention
[0005] One of the purposes of the present application is to provide a chip and a memory management method thereof to improve the deficiencies of the prior art.
[0006] One embodiment of the present application provides a chip. The chip is coupled to a memory. The memory includes a memory segment. The memory segment includes multiple memory blocks. The chip includes a memory management circuit and a computing circuit. The computing circuit is coupled to the memory and the memory management circuit, and is used to run a memory management driver to perform the following steps: receiving a memory request; searching for at least one idle memory block in a memory area according to a memory area linked list, wherein the memory area linked list includes a node, the node corresponds to the memory area, and the memory area is a part of the memory segment; and using the memory management circuit to perform memory mapping on the at least one idle memory block found.
[0007] Another embodiment of the present application provides a memory management method, which is applied to a memory. The memory includes a memory segment. The memory segment includes multiple memory blocks. The method includes the following steps: receiving a memory request; searching for at least one idle memory block in a memory area according to a memory area linked list, wherein the memory area linked list includes a node, the node corresponds to the memory area, and the memory area is a part of the memory segment; and using a memory management circuit to perform memory mapping on the at least one idle memory block found.
[0008] The technical means embodied in the embodiments of the present application can improve at least one of the shortcomings of the prior art, so the present application can use memory more efficiently compared to the prior art.
[0009] The features, implementation and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1 is a functional block diagram of an embodiment of the electronic device of the present application;
[0011] Figure 2A is a schematic diagram of the memory segment of this application;
[0012] Figure 2B It is a schematic diagram of an embodiment of the memory block structure array and the memory area linked list of the present application;
[0013] Figure 3 is a flow chart of an embodiment of the memory management method of the present application;
[0014] Figure 4 yes Figure 3 A flowchart of an embodiment of step S340;
[0015] Figure 5 yes Figure 3 A flowchart of an embodiment of step S360; and
[0016] Figure 6 It is a flow chart of an embodiment of releasing memory of the present application.
[0017] 100: electronic device;
[0018] 110: chip;
[0019] 112: Computational circuit;
[0020] 114: memory management circuit;
[0021] 116: Application circuit;
[0022] 120: Memory;
[0023] 121: memory segment;
[0024] 122: contiguous memory allocator;
[0025] 124: memory management driver;
[0026] 126: memory block structure array;
[0027] 128: memory area linked list;
[0028] 201, 202: memory area;
[0029] MB: memory block;
[0030] 205_1, 205_2, 205_3, 205_4, 205_5, 205_6, 205_7, 205_8, 205_9, 205_10, 205_11: memory block structure (MBS);
[0031] 212: The physical address corresponding to the memory block;
[0032] 214: The address of the structure of the memory area to which it belongs;
[0033] 216: Virtual address of the next memory block;
[0034] 220: Starting point;
[0035] 222: head node of the memory area;
[0036] 224: Number of memory areas;
[0037] 230, 240: nodes;
[0038] 232, 242: The virtual address of the first memory block in the memory area;
[0039] 234, 244: reference count;
[0040] 236, 246: List of free memory blocks;
[0041] addrA, addrB, addrC, addrD: virtual addresses;
[0042] MBS: memory block structure;
[0043] 300: Memory management methods;
[0044] S305, S310, S320, S330, S340, S350, S360, S370, S380, S410, S412, S414, S416, S420, S430, S510, S520, S530, S540, S550, S560, S605, S610, S620, S630, S640, S650: steps. DETAILED DESCRIPTION
[0045] The technical terms used in the following descriptions refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification.
[0046] The disclosure of this application includes a chip and a memory management method thereof. Since some of the components included in the chip of this application may be known components individually, the details of the known components will be omitted in the following description without affecting the full disclosure and feasibility of the device invention. In addition, part or all of the process of the memory management method of this application may be in the form of software and / or firmware, which can be executed by the chip of this application or its equivalent device. Without affecting the full disclosure and feasibility of the method invention, the following description of the method invention will focus on the step content rather than the hardware.
[0047] See also Figure 1 , Figure 1 The electronic device 100 includes a chip 110 and a memory 120 .
[0048] The chip 110 includes a computing circuit 112, a memory management circuit 114 and an application circuit 116. The computing circuit 112 can be a circuit or electronic component with program execution capability, such as a central processing unit, a microprocessor, a microprocessing unit, a digital signal processor, an application specific integrated circuit (ASIC), or an equivalent circuit thereof. The computing circuit 112 implements part of the functions of the electronic device 100 by executing program codes and / or program instructions stored in the memory 120, such as executing memory management program instructions to allocate and manage the memory 120. In some embodiments, the memory management circuit 114 can be implemented by a known memory management unit. The application circuit 116 is responsible for part of the functions of the electronic device 100.
[0049] The memory 120 includes a reserved memory section 121, and stores a continuous memory allocator 122, a memory management driver 124, a memory block structure array 126, and a memory area linked list 128. The memory section 121 is a physically continuous memory section. The continuous memory allocator 122 and the memory management driver 124 are stored in the memory 120 in the form of program codes or program instructions, and are executed by the computing circuit 112.
[0050] The contiguous memory allocator 122 may be a part of the operating system (eg, Linux) of the electronic device 100 and is used to perform known memory allocation.
[0051] The memory management driver 124 serves as a bridge between the computing circuit 112 and the continuous memory allocator 122, and is used to manage the use or allocation of the internal memory block MB of the memory segment 121 according to the memory request issued by the computing circuit 112, and to make a memory allocation request to the continuous memory allocator 122 when necessary.
[0052] The memory block structure array 126 records a plurality of memory block structures MBS in the form of an array or a linked list, and the plurality of memory block structures MBS correspond to all memory blocks MB in the memory segment 121. For example, if the size of the memory segment 121 is 256MB (Megabyte) and the size of a memory block MB is 128KB, the memory segment 121 includes 2000 (=256MB / 128KB (Kilobyte)) memory blocks MB, and the memory block structure array 126 includes 2000 memory block structures MBS.
[0053] The memory region linked list 128 records at least one memory region allocated by the continuous memory allocator 122 in the memory segment 121 in the form of a linked list.
[0054] See also Figure 2A , Figure 2A 1 is a schematic diagram of the memory segment 121 of the present application. The memory segment 121 includes at least one memory area, and each memory area includes a plurality of memory blocks MB. Figure 2A In the example, the memory segment 121 includes a memory area 201 and a memory area 202, and the memory area 201 and the memory area 202 each include a plurality of memory blocks MB.
[0055] See also Figure 2B , Figure 2B It is a schematic diagram of an embodiment of the memory block structure array and the memory area linked list of the present application.
[0056] The memory block structure array 126 includes a plurality of memory block structures MBS. Each memory block structure MBS corresponds to a memory block MB, including a physical address 212 corresponding to the memory block, an address 214 of a structure of the memory area to which it belongs, and a virtual address 216 of the next memory block. Based on a setting file pre-generated by the calculation circuit 112 (which can be stored in the memory 120, not shown), the continuous memory allocator 122 can find a continuous memory space (i.e., a memory segment 121) in the memory 120, and create a memory block structure array 126 corresponding to or describing the memory space. The setting file includes but is not limited to the size of the memory block MB and the minimum allocation size. Allocating the memory segment 121 and creating the memory block structure array 126 can be executed when the electronic device 100 is started.
[0057] The memory area linked list 128 includes a start point 220, a node 230, and a node 240. Each node in the memory area linked list 128 corresponds to a memory area. For example, the node 230 and the node 240 may correspond to the memory area 201 and the memory area 202, respectively. The node 230 (240) includes a virtual address 232 (242) of the first memory block of the corresponding memory area, a reference count 234 (244), and a list 236 (246) of idle memory blocks.
[0058] exist Figure 2B In the embodiment of the present invention, node 230 is the head node of the memory region linked list 128, and node 240 is connected to node 230. The implementation of the linked list is well known to those skilled in the art, so it will not be described in detail. Starting point 220 includes a head node 222 of the memory region and a number 224 of the memory regions. The head node 222 of the memory region points to node 230. Because each node corresponds to a memory region, Figure 2B In the embodiment, the number of memory regions 224 is equal to 2 (ie, node 230 and node 240).
[0059] For example, in Figure 2B In the embodiment, the memory area corresponding to the node 230 includes at least 7 memory blocks MB corresponding to the memory block structures 205_1, 205_2, 205_3, 205_4, 205_5, 205_6, and 205_7, and the memory area corresponding to the node 240 includes at least 4 memory blocks MB corresponding to the memory block structures 205_8, 205_9, 205_10, and 205_11.
[0060] The virtual address 232 of the first memory block of the memory area corresponding to the node 230 points to the virtual address of the memory block structure 205_1. The virtual address 242 of the first memory block of the memory area corresponding to the node 240 points to the virtual address of the memory block structure 205_8. The reference count 234 and the reference count 244 record the number of allocated memory blocks MB in the respective memory areas. The list of idle memory blocks 236 and the list of idle memory blocks 246 point to the idle (free) memory blocks MB in the memory area. There are only two states of memory blocks MB in any memory area: allocated or idle.
[0061] See also Figure 3 , Figure 3 1 is a flow chart of an embodiment of the memory management method of the present application. In the following description, it is assumed that the size of the memory segment 121 is 256MB, the size of each memory block MB is 128KB, and the minimum allocation size is 16MB. The memory management method 300 is executed by the computing circuit 112 and includes the following steps.
[0062] Step S305: Receive a memory request from an application or device (eg, application circuit 116). It is assumed below that the requested memory size is 20 MB.
[0063] Step S310: Determine whether the memory area linked list 128 is empty, that is, determine whether the number of memory areas 224 is 0 (equivalent to determining whether the number of nodes in the memory area linked list 128 is 0). If yes, execute step S320; otherwise, execute step S360.
[0064] Step S320: Adjust the requested memory size according to the minimum allocation size. This step is alignment, which is used to prevent memory fragmentation in the memory segment 121. Assuming that the size of the memory segment 121 is X (X is an integer), the minimum allocation size is a factor of X, and the adjusted requested memory size is an integer multiple of the minimum allocation size. For example, because the requested memory size is 20MB and the minimum allocation size is 16MB (16 is a factor of 256), the adjusted requested memory size is [20 / 16]×16=32MB.
[0065] Step S330: Request memory from the continuous memory allocator 122 according to the adjusted requested memory size. Continuing with the previous example, since the adjusted requested memory size is 32MB, the memory management driver 124 requests 32MB of memory from the continuous memory allocator 122. Since the size of a memory block MB is 128KB, the continuous memory allocator 122 will allocate a memory area including 250 (=32MB / 128KB) memory blocks MB in the memory segment 121. Then, the calculation circuit 112 can obtain the physical addresses of the 250 memory blocks MB according to the memory block structure array 126.
[0066] Step S340: Modify the memory area linked list 128 based on the requested memory. Figure 4 , Figure 4 is a flow chart of an embodiment of step S340, including the following steps.
[0067] Step S410: Create a node in the memory area linked list 128. For example, assuming that the memory area linked list 128 originally does not have any node (i.e., the memory management driver 124 has never requested memory from the continuous memory allocator 122), the computing circuit 112 (more specifically, the memory management driver 124) creates the node 230 in this step.
[0068] Step S410 includes the following sub-steps.
[0069] Step S412: Set the virtual address 232 of the first memory block of the memory area. Figure 2B Assuming that the memory area corresponding to the node 230 includes the memory blocks MB corresponding to the first 250 memory block structures MBS of the memory block structure array 126, the memory management driver 124 points the virtual address 232 of the first memory block of the memory area to the virtual address of the memory block structure 205_1.
[0070] Step S414: Setting the reference count 234. Since only 160 (=20MB / 128KB) of the 250 memory blocks MB are actually used (the remaining 90 (=12MB / 128KB) are requested for alignment), the reference count 234 is set to 160.
[0071] Step S416: Set the list 236 of idle memory blocks. Figure 2B. Assuming that the starting point of the idle memory block MB is the memory block MB corresponding to the memory block structure 205_1, the memory management driver 124 points the list 236 of idle memory blocks to the virtual address of the memory block structure 205_1. Continuing with the previous example, the number of memory areas 224 inserts the memory block structure MBS corresponding to the idle 12 (=32-20) MB memory block into the list 236 of idle memory blocks, so that the list 236 of idle memory blocks includes 90 (=12MB / 128KB) memory block structures MBS. Each memory block structure MBS is a node of the list 236 of idle memory blocks.
[0072] Step S420: insert the newly created node (i.e., the node 230 created in the previous step) into the memory area linked list 128. More specifically, if the newly created node is the first node of the memory area linked list 128, the head node 222 of the memory area is pointed to the newly created node; otherwise, the newly created node is inserted at the end of the memory area linked list 128.
[0073] Step S430: increase the number 224 of the memory areas of the starting point 220 by 1.
[0074] Back to Figure 3 .
[0075] Step S350: Use the memory management circuit 114 to perform memory mapping. More specifically, the calculation circuit 112 provides the physical address and virtual address of the allocated memory block MB to the memory management circuit 114 for memory mapping. Continuing with the previous example, the memory management driver 124 inserts the memory block structure MBS corresponding to the requested memory (20MB) in the memory block structure array 126 into the mapping address record linked list of the memory management circuit 114 for mapping, that is, writes the mapping relationship between the physical address and the virtual address of each allocated memory block MB into the mapping address record linked list of the memory management circuit 114. After mapping, the physical address and virtual address of the first memory block structure MBS of the multiple memory block structures MBS are saved to the mapping address record linked list of the memory management circuit 114.
[0076] For example, see Figure 2B After mapping, the memory management circuit 114 records the virtual address addrA and the virtual address addrB. The address range between the two virtual addresses corresponds to the allocated memory blocks MB (i.e., the above-mentioned 160 (=20MB / 128KB) memory blocks MB, for example, corresponding to the memory block structures 205_2, 205_5, 205_6, ...) of the memory area 201 (i.e., the memory area corresponding to the node 230).
[0077] Step S360: Search for an idle memory block MB according to the memory area linked list 128. When the memory area linked list 128 is not empty (for example, the node 230 has been established in the previous example), it means that there is an allocated memory area (for example, the memory area 201), and any of the allocated memory areas may have an idle memory block MB (for example, the memory block MB pointed to by the list of idle memory blocks 236). This step is to use the idle memory blocks MB in the allocated memory area to use the memory segment 121 more efficiently. The details of this step will be described below. Figure 5 For explanation.
[0078] Step S370: Determine whether the total size of the idle memory blocks is greater than or equal to the requested memory size. If so, perform memory mapping with the idle memory blocks MB obtained from step S360 (step S350); otherwise, execute step S380.
[0079] Step S380: Update the requested memory size according to the total size of the idle memory blocks. Continuing with the previous example, the total size of the idle memory blocks MB is 12MB. If the requested memory size is 18MB at this time, the memory management driver 124 will update the requested memory size to 18-12=6MB. Then, in step S320, the memory management driver 124 will adjust the requested memory size to [6 / 16]×16=16MB. It should be noted that in the following step S350, the memory management driver 124 will provide the idle memory blocks MB obtained from step S360 and the memory area allocated from step S340 (more specifically, take 6MB therein) to the memory management circuit 114 for mapping.
[0080] It can be seen that the memory management driver 124 will give priority to using the idle memory blocks MB in the existing memory area to improve the use efficiency of the memory segment 121 and avoid waste.
[0081] In some embodiments, after the memory management circuit 114 completes the mapping (i.e., after step S350), the computing circuit 112 provides the mapped virtual address to the application or the application circuit 116. That is, in the present application, both the application and the device can use the memory segment 121. For example, the chip 110 can be an image processing chip, and the application circuit 116 can be an image decoding circuit.
[0082] See also Figure 5 , Figure 5 It is a flow chart of an embodiment of step S360, including the following steps.
[0083] Step S510 : access a node in the memory area linked list 128 . Continuing with the previous example, assuming that the memory area linked list 128 only has the node 230 , the memory management driver 124 accesses the node 230 .
[0084] Step S520: access the list 236 of idle memory blocks of the node, accumulate the number of idle memory blocks, and update the reference count of the node.
[0085] Step S530: Determine whether the idle memory blocks MB are sufficient. If yes, execute step S560; otherwise, execute step S540.
[0086] Step S540: Determine whether there is any idle memory block MB in the node. If yes, execute step S520; otherwise, execute step S550.
[0087] In other words, in steps S520 to S540, the memory management driver 124 continues to search for idle memory blocks MB in a certain node (i.e., in the memory area corresponding to the node) until there are enough idle memory blocks MB (step S530 is yes), or the node has no idle memory blocks MB (step S540 is no). In this process, the memory management driver 124 accumulates the number of idle memory blocks and increases the reference count of the node by 1 (step S520) each time it finds an idle memory block MB (indicating that the state of the memory block MB changes from idle to allocated).
[0088] Step S550: Determine whether all nodes have been visited. If yes, execute step S560; otherwise, execute step S510.
[0089] Step S560: Calculate the total size of the accumulated idle memory blocks. For example, if the number of accumulated idle memory blocks MB is P, and the size of each memory block MB is Q, then the total size is P×Q.
[0090] Continuing with the previous example, since the requested memory size is 18MB and the total size of the idle memory blocks MB of node 230 is 12MB, the results of step S530 and step S540 are no. Then, since the memory area linked list 128 only has node 230 at this time, the result of step S550 is yes. Then, Figure 3 If the result of step S370 is no, the memory management driver 124 executes steps S380, S320, S330, S340 and S350 to establish the node 240 (ie, request the memory area 202 from the continuous memory allocator 122). Figure 2BHere, it is assumed that the memory management circuit 114 records the virtual address addrC and the virtual address addrD, and the address range between the two virtual addresses corresponds to the allocated memory block MB of the memory area 202.
[0091] In another example, assume that the requested memory size is 10MB. Because the total size (12MB) of the idle memory blocks MB of the node 230 is larger than the requested memory size (10MB), the result of step S530 is yes, and the result of the next step S370 is also yes. That is, in this example, the memory management driver 124 does not need to request memory from the continuous memory allocator 122, and the node 240 will not be established. After the memory management method 300 ends, there are still idle memory blocks MB in the node 230 (a total of 12-10=2MB).
[0092] It should be noted that when the result of step S370 is yes, the memory management driver 124 does not need to request memory from the continuous memory allocator 122, so the memory management driver 124 will not adjust the requested memory size to an integer multiple of the minimum allocation size (i.e., step S320 will not be executed). In other words, in the present application, although the memory management method 300 implements an alignment mechanism, even if the requested memory size is not an integer multiple of the minimum allocation size (for example, 10MB in the above example is not an integer multiple of 16MB), the memory request will not trigger the alignment operation (i.e., step S320 will not be executed).
[0093] See also Figure 6 , Figure 6 It is a flow chart of an embodiment of releasing memory of the present application. Figure 6 The process is executed by the calculation circuit 112 and includes the following steps.
[0094] Step S605: Find multiple memory blocks MB to be released according to the mapping address record linked list of the memory management circuit 114. For example, refer to Figure 2B , the memory block structure 205_2 can be found according to the virtual address addrA, and then all memory blocks MB between the virtual address addrA and the virtual address ad drB can be found according to the memory block structure array 126 (the multiple memory blocks MB are allocated memory blocks MB).
[0095] Step S610: Return the memory block MB to the corresponding memory area (ie, release the plurality of memory blocks MB). Figure 2BBecause each memory block structure MBS records the address 214 of the structure of the memory area to which it belongs, the memory management driver 124 can find the memory area to which any memory block MB belongs according to the address 214 of the structure of the memory area to which it belongs. The details of this step are to insert the memory block structure MBS of the memory block MB into the list of idle memory blocks of the corresponding memory area.
[0096] Step S620: Update the reference count. Assuming that R memory blocks MB are released in the previous step (ie, R memory block structures MBS are inserted into the list of free memory blocks), the reference count is subtracted by R in this step.
[0097] Step S630: Determine whether the reference count is 0. If so (indicating that all memory blocks MB in the memory area are idle, that is, have been released), execute step S640; otherwise, retain the memory area (that is, retain the corresponding node) (step S650).
[0098] Step S640: releasing the memory area, that is, deleting the node from the memory area linked list 128 .
[0099] Although the aforementioned embodiments take Linux as an example, this is not a limitation of the present application. Persons skilled in the art can appropriately apply the present application to other types of operating systems based on the disclosure of the present application.
[0100] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. Technicians in this technical field may change the technical features of the present application based on the explicit or implicit contents of the present application. All these changes may fall within the scope of patent protection sought by the present application. The scope of patent protection of the present application shall be based on the scope of the patent application of this specification.
Claims
1. A chip, characterized in that: A memory is coupled, the memory includes a memory segment, the memory segment includes a plurality of memory blocks, and the chip includes: a memory management circuit; and A computing circuit is coupled to the memory and the memory management circuit, and is used to run a memory management driver to perform the following steps: receiving a memory request; Searching for at least one idle memory block in a memory area according to a memory area linked list, wherein the memory area linked list includes a node, the node corresponds to the memory area, and the memory area is a part of the memory segment; and The memory management circuit is used to perform memory mapping on the at least one idle memory block that is searched.
2. The chip according to claim 1, characterized in that: The node is a first node, the memory area is a first memory area, and the computing circuit further performs the following steps: When a total size of the at least one idle memory block found is smaller than a requested memory size of the memory request, a second node is established in the memory area linked list, the second node corresponds to a second memory area, and the second memory area is a part of the memory segment including a plurality of memory blocks and an allocated memory block; as well as The allocated memory block is imaged using the memory management circuit.
3. The chip according to claim 2, characterized in that: The total size is a first total size, and a sum of the first total size and a second total size of the allocated memory block is equal to the requested memory size.
4. The chip according to claim 2, characterized in that: The first memory area and the second memory area are allocated by a continuous memory allocator.
5. The chip according to claim 1, characterized in that: The node includes a list of idle memory blocks, and the list of idle memory blocks points to the at least one idle memory block that is searched.
6. The chip according to claim 5, characterized in that: The step of searching the at least one idle memory block in the memory area according to the memory area linked list is to access the list of the idle memory blocks.
7. The chip according to claim 5, characterized in that: The memory area includes a plurality of allocated memory blocks, and the computing circuit further performs the following steps: Inserting a plurality of memory block structures corresponding to the plurality of allocated memory blocks into the list of the idle memory blocks to release the plurality of allocated memory blocks.
8. The chip according to claim 7, characterized in that: The calculation circuit further performs the following steps: When the multiple allocated memory blocks of the node have all been released, the node is deleted from the memory area linked list.
9. The chip according to claim 8, characterized in that The node includes a reference count, and the computing circuit further performs the following steps: It is determined whether all of the multiple allocated memory blocks of the node have been released according to the reference count.
10. The chip according to claim 1, characterized in that: The memory area is an integer multiple of a minimum allocation size, and when a total size of the at least one idle memory block found is greater than or equal to a requested memory size of the memory request, the requested memory size is not adjusted to an integer multiple of the minimum allocation size.
11. A memory management method, characterized in that: Applied to a memory, the memory includes a memory segment, the memory segment includes a plurality of memory blocks, the method includes: receiving a memory request; Searching for at least one idle memory block in a memory area according to a memory area linked list, wherein the memory area linked list includes a node, the node corresponds to the memory area, and the memory area is a part of the memory segment; and A memory management circuit is used to perform memory mapping on the at least one idle memory block that is searched.
12. The method according to claim 11, characterized in that The node is a first node, the memory area is a first memory area, and the method further includes: When a total size of the at least one idle memory block found is smaller than a requested memory size of the memory request, establishing a second node in the memory area linked list, wherein the second node corresponds to a second memory area, and the second memory area is a part of the memory segment including a plurality of memory blocks and an allocated memory block; and The allocated memory block is imaged using the memory management circuit.
13. The method according to claim 12, characterized in that The total size is a first total size, and a sum of the first total size and a second total size of the allocated memory block is equal to the requested memory size.
14. The method according to claim 11, characterized in that The node includes a list of free memory blocks, and the list of free memory blocks is accessed to search for the at least one free memory block in the memory area.
15. The method according to claim 14, characterized in that The memory area includes a plurality of allocated memory blocks, and the method further includes: Inserting a plurality of memory block structures corresponding to the plurality of allocated memory blocks into the list of the idle memory blocks to release the plurality of allocated memory blocks.
16. The method according to claim 15, characterized in that Also includes: When the multiple allocated memory blocks of the node have all been released, the node is deleted from the memory area linked list.
17. The method according to claim 16, characterized in that The node includes a reference count, and the method further includes: It is determined whether all of the multiple allocated memory blocks of the node have been released according to the reference count.
18. The method according to claim 11, characterized in that The memory area is an integer multiple of a minimum allocation size, and when a total size of the at least one idle memory block found is greater than or equal to a requested memory size of the memory request, the requested memory size is not adjusted to an integer multiple of the minimum allocation size.