Method for extracting metal interconnection capacitance parameters in laminated medium

Abstract

The invention provides a method for extracting metal interconnection capacitance parameters in laminated media. The method comprises the following steps: dividing a whole solving area into a metal interconnection area and laminated medium areas above and below the metal interconnection area; performing spatial discretization on a metal interconnection area, setting excitation and partial boundary conditions, and constructing a matrix equation by using a finite element method; constructing numerical boundary equations on an upper interface and a lower interface for the upper laminated medium and the lower laminated medium through analytical solutions respectively; the matrix equation of the metal interconnection area and the numerical boundary equation on the interface are assembled and solved, and a potential distribution result is obtained; and calculating surface charge distribution of the metal conductor according to a potential distribution result, thereby obtaining an interconnection capacitance value. The method has the advantages of high calculation efficiency and low calculation resource consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of numerical simulation calculation, and in particular to a method for extracting metal interconnect capacitance parameters in a stacked dielectric. Background Art

[0002] As the size of integrated circuits continues to shrink, the impact of metal interconnects on integrated circuit performance becomes more and more significant. In order to ensure design quality, shorten design cycles and reduce costs, it is necessary to accurately and efficiently extract metal interconnect capacitance.

[0003] The extraction of metal interconnect capacitance parameters can be mainly divided into three methods: analytical model, empirical formula technology and numerical method. Analytical model and empirical formula technology can provide fast approximate results, however, when applied to complex structure scenarios, their accuracy will be seriously reduced. In contrast, numerical methods such as finite element method and boundary element method have high accuracy in processing complex metal interconnect structures, but at the same time, they face the challenges of long solution time and high consumption of computing resources. Summary of the invention

[0004] In view of the defects in the prior art, the purpose of the present invention is to provide a method for extracting metal interconnect capacitance parameters in a stacked dielectric. The method of the present invention has the advantages of high computational efficiency and low consumption of computational resources.

[0005] To solve the above problems, the technical solution of the present invention is:

[0006] A method for extracting metal interconnect capacitance parameters in a stacked dielectric, the method comprising the following steps:

[0007] S1: Divide the entire solution area into the metal interconnection area and the stacked dielectric areas above and below it;

[0008] S2: spatially discretize the metal interconnection area, set excitation and some boundary conditions, and construct the matrix equation using the finite element method;

[0009] S3: For the upper and lower stacked media, numerical boundary equations on the upper and lower interfaces are constructed through analytical solutions respectively;

[0010] S4: Assemble and solve the matrix equation of the metal interconnection area and the numerical boundary equation on the interface to obtain the potential distribution result;

[0011] S5: Based on the potential distribution results, the charge distribution on the surface of the metal conductor is calculated to obtain the interconnection capacitance value.

[0012] Preferably, in step S1, the entire calculation area can be divided into three areas from top to bottom: an upper stacked dielectric area, a metal interconnection area and a lower stacked dielectric area; the upper stacked dielectric area and the metal interconnection area are an upper interface, and the lower stacked dielectric area and the metal interconnection area are a lower interface; wherein, the upper and lower stacked dielectric areas only contain a number of stacked rectangular uniform dielectric layers; and the metal interconnection area contains irregularly shaped metal conductors and conformal dielectrics.

[0013] Preferably, in step S2, the metal interconnection area is spatially discretized using triangular grid units, and the excitation and some boundary conditions are set as follows: a metal conductor k is selected and set to a constant voltage of 1V, other conductors are set to a constant voltage of 0V, and both sides of the metal interconnection area are insulating boundary conditions.

[0014] Preferably, in the process of constructing the matrix equation using the finite element method, the electrostatic field control equation in the medium region to be solved is:

[0015]

[0016] Where u is the electric potential and ε is the dielectric constant;

[0017] In each discrete unit e, the potential u e You can use node value And its corresponding shape function is approximately:

[0018]

[0019] in, is the shape function corresponding to node j; Substitute it into the electrostatic field control equation and perform the Galerkin test to obtain the weighted residual R of unit e e for:

[0020] R e =K e u e -f e

[0021] in,

[0022]

[0023]

[0024]

[0025] Γ e is the area S surrounding the unit e e The side, n eis the unit external normal vector; by assembling all units and handling the boundary conditions, the matrix equation is obtained:

[0026] Ku-f=b

[0027] Here, b is the vector associated with the boundary condition.

[0028] Preferably, in step S3, the lower stacked dielectric region comprises N layers in total, namely, the 1st, 2nd, ..., Nth layers from top to bottom, wherein the thickness and relative dielectric constant of the jth layer are t j and ε j , the width of each dielectric layer is w; the two sides of the lower stacked dielectric region are insulating boundaries, the lower boundary is set to a 0V voltage boundary condition, and the upper boundary is set to a u(x) voltage boundary condition; the following potential and electric flux continuity conditions are satisfied between two adjacent dielectric layers:

[0029]

[0030]

[0031] By using the separation of variables method, the potential analytical solution in the form of Fourier series in the lower stacked dielectric region can be obtained as:

[0032]

[0033] Among them, λ m =mπ / w,A m,j and B m,j is the coefficient of the mth order;

[0034] Through the above-mentioned boundary conditions of the lower stacked dielectric region and the continuity conditions between dielectric layers, all coefficient expressions can be obtained as follows:

[0035]

[0036] A 0,j+1 =A 0,j +B 0,j t i ,B 0,j+1 =B 0,j ε j ε j+1

[0037]

[0038] B m,N = coth(λ m t N )

[0039]

[0040] Am,j+1 =A m,j [cosh(λ m t j )-B m,j sinh(λ m t j )]

[0041] The electric flux at the lower interface can be obtained by differentiating the electric potential:

[0042]

[0043] In this expression, B 0,1 and A m,1 Related to u(x), u(x) can be expressed as the expression of the electric potential and shape function on the interface:

[0044]

[0045] Where P is the number of discrete nodes on the lower interface, N p is the shape function corresponding to node p; substituting the above formula into the electric flux expression of the lower interface, it can be written as follows:

[0046]

[0047] The above analytical expressions establish the relationship between the electric flux and the electric potential on the lower interface, namely, the numerical boundary equation; similarly, the numerical boundary equation on the upper interface corresponding to the upper stacked dielectric region can be obtained through the same steps.

[0048] Preferably, in step S4, based on the matrix equation established by the finite element method in the metal interconnection region, the analytical expression of D(x) obtained in step S3 is substituted into f corresponding to the nodes on the upper and lower interfaces to obtain:

[0049]

[0050] Therefore, the original matrix equation in step S2 can be rewritten as follows:

[0051] (KF)u=b

[0052] By solving the linear equations, the electric potential result u can be obtained.

[0053] Preferably, in step S5, the total charge of the metal conductor g can be obtained by the potential:

[0054]

[0055] Since the voltage applied to metal conductor k is 1V, the capacitance between metal conductor k and conductor g is

[0056]

[0057] Compared with the prior art, the present invention has the following beneficial effects:

[0058] 1. When solving the metal interconnection area, the flexible finite element method is used to handle complex irregular-shaped metal conductors and their surrounding conformal media while maintaining high accuracy;

[0059] 2. When solving the upper and lower stacked dielectric regions, the numerical boundary equations on the upper and lower interfaces can be efficiently obtained by using accurate and fast analytical solutions;

[0060] 3. Use appropriate methods in different areas to take advantage of the flexibility of numerical solutions and the speed of analytical solutions. Compared with the traditional finite element method, since only spatial discretization is required in the metal interconnection area, the scale of the matrix equation to be solved is significantly reduced, and the computational efficiency is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0062] Figure 1 It is a flowchart of the method for extracting metal interconnect capacitance parameters in a stacked dielectric according to the present invention;

[0063] Figure 2 This is a schematic diagram of the calculation area decomposition;

[0064] Figure 3 is a schematic diagram of the lower stacked medium area;

[0065] Figure 4 FIG. 1 is a diagram of a metal interconnect structure containing multi-layer dielectrics according to a specific embodiment. DETAILED DESCRIPTION

[0066] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0067] Specifically, the present invention provides a method for extracting metal interconnect capacitance parameters in a stacked dielectric, such as Figure 1 As shown, the method comprises the following steps:

[0068] S1: Divide the entire solution area into the metal interconnection area and the stacked dielectric areas above and below it;

[0069] Specifically, in step S1, Figure 2 As shown in the figure, the entire calculation area can be divided into three areas from top to bottom: the upper stacked dielectric area, the metal interconnection area, and the lower stacked dielectric area. The upper stacked dielectric area and the metal interconnection area are the upper interface, and the lower stacked dielectric area and the metal interconnection area are the lower interface. The upper and lower stacked dielectric areas only contain a number of stacked rectangular uniform dielectric layers; the metal interconnection area contains irregularly shaped metal conductors and conformal dielectrics.

[0070] S2: spatially discretize the metal interconnection area, set excitation and some boundary conditions, and construct the matrix equation using the finite element method;

[0071] Specifically, in step S2, the metal interconnection area is spatially discretized using triangular grid units, and the boundary conditions are: the two sides of the metal interconnection area are insulating boundary conditions, the metal conductor k is selected and set to a constant voltage of 1V, and other metals are set to a constant voltage boundary condition of 0V.

[0072] In the process of constructing the matrix equation using the finite element method, the electrostatic field control equation to be solved in the medium region is:

[0073]

[0074] Where u is the electric potential and ε is the dielectric constant.

[0075] In each discrete unit e, the potential u e The node value u j e And its corresponding shape function is approximately:

[0076]

[0077] in, is the shape function corresponding to node j. Substitute it into the electrostatic field control equation and perform the Galerkin test to obtain the weighted residual R of unit e e for:

[0078] R e =K e u e -f e

[0079] in,

[0080]

[0081]

[0082]

[0083] Γ e is the area S surrounding the unit e e The side, n e is the unit external normal vector. By assembling all the units and processing the boundary conditions, the matrix equation is obtained:

[0084] Ku-f=b

[0085] Here, b is the vector associated with the boundary condition.

[0086] S3: For the upper and lower stacked media, numerical boundary equations on the upper and lower interfaces are constructed through analytical solutions respectively;

[0087] Specifically, in step S3, Figure 3 As shown, the lower stacked dielectric region contains N layers, from top to bottom, they are the 1st, 2nd, ..., Nth layers, where the thickness and relative dielectric constant of the jth layer are t j and ε j , the width of each dielectric layer is w. The two sides of the lower stacked dielectric region are insulating boundaries, the lower boundary is set to a 0V voltage boundary condition, and the upper boundary is set to a voltage boundary condition of u(x). The following potential and electric flux continuity conditions are satisfied between two adjacent dielectric layers:

[0088]

[0089]

[0090] By using the separation of variables method, the potential analytical solution in the form of Fourier series in the lower stacked dielectric region can be obtained as:

[0091]

[0092] Among them, λ m =mπ / w,A m,j and B m,j is the coefficient of the mth order.

[0093] Through the above-mentioned boundary conditions of the lower stacked dielectric region and the continuity conditions between dielectric layers, all coefficient expressions can be obtained as follows:

[0094]

[0095] A 0,j+1 =A 0,j +B 0,j t i ,B 0,j+1 =B 0,jε j ε j+1

[0096]

[0097] B m,N = coth(λ m t N )

[0098]

[0099] A m,j+1 =A m,j [cosh(λ m t j )-B m,j sinh(λ m t j )]

[0100] The electric flux at the lower interface can be obtained by differentiating the electric potential:

[0101]

[0102] In this expression, B 0,1 and A m,1 Related to u(x), u(x) can be expressed as the expression of the electric potential and shape function on the interface:

[0103]

[0104] Where P is the number of discrete nodes on the lower interface, N p is the shape function corresponding to node p. Substituting the above formula into the electric flux expression of the lower interface, it can be written as follows:

[0105]

[0106] The above analytical expression establishes the relationship between the electric flux and the electric potential on the lower interface, that is, the numerical boundary equation. In the specific implementation, the infinite series in the formula is selected to be 500 orders, which can meet the calculation accuracy requirements.

[0107] Similarly, the numerical boundary equations on the upper interface corresponding to the upper stacked dielectric region can be obtained through the same steps.

[0108] S4: Assemble and solve the matrix equation of the metal interconnection area and the numerical boundary equation on the interface to obtain the potential distribution result;

[0109] Specifically, in step S4, based on the matrix equation established by the finite element method in the metal interconnection region, the analytical expression of D(x) obtained in step S3 is substituted into f corresponding to the nodes on the upper and lower interfaces to obtain:

[0110]

[0111] Therefore, the original matrix equation in step S2 can be rewritten as follows:

[0112] (KF)u=b

[0113] By solving the linear equations, the electric potential result u can be obtained.

[0114] S5: Based on the potential distribution results, the charge distribution on the surface of the metal conductor is calculated to obtain the interconnection capacitance value.

[0115] Specifically, in step S5, the total charge of the metal conductor g can be obtained by the potential:

[0116]

[0117] Since the voltage applied to metal conductor k is 1V, the capacitance between metal conductor k and conductor g is

[0118]

[0119] According to the above extraction method, a specific embodiment is calculated.

[0120] In this embodiment, a metal interconnect structure including 36 layers of stacked dielectrics is considered, such as Figure 4 As shown, the metal interconnect region in the middle of the structure contains four conductors, and the conductor numbers are also shown in Figure 4 middle.

[0121] The conventional finite element method and the method of the present invention are used for simulation respectively, and the metal conductor 1 is set as the main conductor. The interconnection capacitance results are summarized in Table 1. It can be seen that the results of the method of the present invention are consistent with those of the conventional finite element method, and the weighted average relative error is only 0.36%, which fully demonstrates the accuracy of the method of the present invention.

[0122]

[0123] Table 1

[0124] In terms of efficiency, the traditional finite element method discretizes the entire structure spatially and generates 67,721 grids, while the method of the present invention discretizes only the metal interconnection area and generates 3,029 grids, so the number of unknowns is reduced to about 1 / 22. In terms of computing memory and computing time, the traditional finite element method consumes 153.1MB of memory and the computing time is 13.5s, while the method of the present invention only uses 7.3MB of memory and the computing time is only 0.7s, which are 4.8% and 5.2% of the traditional finite element method, respectively. This fully demonstrates the advantages of the method of the present invention in computing resource consumption.

[0125] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A method for extracting metal interconnect capacitance parameters in a stacked dielectric, characterized in that: The method comprises the following steps: The entire solution area is divided into a metal interconnection area and the stacked dielectric areas above and below it; The metal interconnection region is spatially discretized, excitation and some boundary conditions are set, and the matrix equation is constructed using the finite element method; For the upper and lower stacked media, numerical boundary equations on the upper and lower interfaces are constructed through analytical solutions respectively; The matrix equation of the metal interconnection area and the numerical boundary equation on the interface are assembled and solved to obtain the potential distribution result; Based on the potential distribution results, the charge distribution on the surface of the metal conductor is calculated, and then the interconnection capacitance value is obtained.

2. The method for extracting metal interconnect capacitance parameters in a stacked dielectric according to claim 1, characterized in that: In the step of dividing the entire solution area into a metal interconnection area and stacked dielectric areas above and below it, the entire calculation area can be divided into three areas from top to bottom: an upper stacked dielectric area, a metal interconnection area, and a lower stacked dielectric area; the upper stacked dielectric area and the metal interconnection area are an upper interface, and the lower stacked dielectric area and the metal interconnection area are a lower interface; wherein, the upper and lower stacked dielectric areas only contain a number of stacked rectangular uniform dielectric layers; and the metal interconnection area contains irregularly shaped metal conductors and conformal dielectrics.

3. The method for extracting metal interconnect capacitance parameters in a stacked dielectric according to claim 1, characterized in that: In the steps of spatially discretizing the metal interconnection area, setting excitation and some boundary conditions, and constructing a matrix equation using the finite element method, the metal interconnection area is spatially discretized using triangular grid units, and the excitation and some boundary conditions are set as follows: a target metal conductor is selected and set to a constant voltage of 1V, other conductors are set to a constant voltage of 0V, and both sides of the metal interconnection area are insulating boundary conditions.

4. The method for extracting metal interconnect capacitance parameters in a stacked dielectric according to claim 1, characterized in that: In the steps of spatially discretizing the metal interconnection area, setting excitation and some boundary conditions, and constructing a matrix equation using the finite element method, the space is discretized using the finite element method, and the electric potential is represented by the node value and its corresponding shape function in each discrete unit, which is then substituted into the electrostatic field control equation for a Galerkin test to obtain the unit stiffness matrix equation, and then the overall stiffness matrix equation is obtained by assembling all units and processing the boundary conditions.

5. The method for extracting metal interconnect capacitance parameters in a stacked dielectric according to claim 1, characterized in that: In the step of constructing numerical boundary equations on the upper and lower interfaces of the upper and lower stacked dielectrics by analytical solutions, both sides of the lower stacked dielectric region are insulating boundaries, the lower boundary is set to a 0V boundary condition, the upper boundary is set to a voltage boundary condition, and the potential and electric flux continuity conditions are satisfied between the two adjacent dielectric layers; By separation of variables method, the analytical solutions of the electric potential and electric flux in the upper and lower stacked dielectric regions in the form of Fourier series are obtained as numerical boundary equations.

6. The method for extracting metal interconnect capacitance parameters in a stacked dielectric according to claim 1, characterized in that: In the step of assembling and solving the matrix equation of the metal interconnection area and the numerical boundary equation on the interface to obtain the potential distribution result, the matrix equation established in the metal interconnection area by the finite element method is used as a basis, and the analytical expression of the electric flux obtained in the step of constructing the numerical boundary equation on the upper and lower interfaces by analytical solution for the upper and lower stacked dielectrics is respectively used, the obtained matrix equation is updated, and the potential result is obtained by solving it.

7. The method for extracting metal interconnect capacitance parameters in a stacked dielectric according to claim 1, characterized in that: In the step of calculating the surface charge distribution of the metal conductor according to the potential distribution result and then obtaining the interconnect capacitance value, the total charge of each metal conductor is calculated according to the obtained potential distribution result, thereby calculating the metal interconnect capacitance.

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