Composite substrate comprising transfer foil with porous silicon carbide layer, power

Abstract

The invention relates to a composite substrate including a transfer foil having a porous silicon carbide layer, a power semiconductor device and a method of manufacture. A method of manufacturing a silicon carbide device includes forming a transfer foil (110) including a porous silicon carbide layer (116). A composite substrate (100) is formed, the composite substrate (100) comprising a transfer foil (110) and a support substrate (190), where the transfer foil (110) and the support substrate (190) are brought into contact with each other and connected to each other. The epitaxial layer (120) is formed on the side of the porous silicon carbide layer (116) facing the support substrate (190). The composite substrate (100) is divided into a device substrate (150) and a recovery substrate (160), where the device substrate (150) comprises an epitaxial layer (120) and the recovery substrate (160) comprises a support substrate (190).

Description

Technical Field

[0001] Examples of the present disclosure relate to a composite substrate including a transfer foil having a porous silicon carbide layer, a power semiconductor device, and a method for manufacturing a power semiconductor device. The method uses the transfer foil to transfer the porous silicon carbide layer to a support substrate. The composite substrate includes the transfer foil and the support substrate. A power semiconductor device can be obtained from the composite substrate. Background Art

[0002] The processing of semiconductor wafers generally involves forming an ingot by vertical ribbon melting or by pulling a seed rod from a crucible filled with molten semiconductor material, and slicing the ingot. The typical slicing process destroys a significant portion of the previously produced crystal. Alternative techniques obtain epitaxial semiconductor wafers by forming a thin release layer near the front side of a reusable semiconductor seed wafer, epitaxially growing a semiconductor layer on the front side and then mechanically detaching the epitaxially grown semiconductor layer from the seed wafer with the aid of the release layer. For example, an epitaxially grown semiconductor wafer is cleaved from a single crystal base substrate along a release layer formed by laser irradiation. There is a steady need for a method of providing semiconductor wafers in an economical manner. Summary of the invention

[0003] Embodiments of the present disclosure relate to a method for manufacturing a silicon carbide device. The method includes: forming a transfer foil including a porous silicon carbide layer. A composite substrate is formed, the composite substrate including the transfer foil and a support substrate, wherein the transfer foil and the support substrate are brought into contact with each other and connected to each other. An epitaxial layer is formed on a side of the porous silicon carbide layer opposite to the support substrate. The composite substrate is divided into a device substrate and a recovery substrate, the device substrate including the epitaxial layer, and the recovery substrate including the support substrate.

[0004] The method decouples the process of providing suitable epitaxial seeds from the actual epitaxial process and simplifies the processing of thin silicon carbide substrates for power semiconductor devices. A high-quality source substrate provides the epitaxial seeds, and a low-cost support substrate can be used for the epitaxial process. The porous silicon carbide layer first transfers the epitaxial seeds to the low-cost support substrate, and then enables efficient separation of the device substrate with electronic components formed therein from the low-cost support substrate.

[0005] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings serve to further understand the embodiments and are an integral part of the description. The accompanying drawings illustrate embodiments of power semiconductor devices, composite substrates, and methods of manufacturing semiconductor devices and together with the description serve to explain the embodiments. The following detailed description and claims include additional embodiments.

[0007] Figures 1A to 1D Schematic vertical cross-sectional views showing a transfer foil, a composite substrate, a device substrate, and a recycled substrate at various stages of a semiconductor device manufacturing method including transferring and horizontally dividing a porous silicon carbide layer according to an embodiment.

[0008] FIG. 2A to FIG. 2D Schematic vertical cross-sectional views showing a transfer foil, a composite substrate, a device substrate, and a recycled substrate at various stages of a semiconductor device manufacturing method including transferring and horizontally dividing a porous silicon carbide layer according to an embodiment involving a transfer foil including an auxiliary layer.

[0009] FIG. 3A to FIG. 3D Schematic vertical cross-sectional views of a composite substrate and a device substrate at various stages of a semiconductor device manufacturing method including transferring and horizontally dividing a porous silicon carbide layer according to an embodiment involving forming electronic components before dividing the porous silicon carbide layer.

[0010] FIG. 4A to FIG. 4C Schematic vertical cross-sectional views of a source substrate and a transfer foil at various stages of a semiconductor device manufacturing method including transferring and horizontally dividing a porous silicon carbide layer according to an embodiment including forming a porous silicon carbide layer for a transfer foil on a source substrate.

[0011] Figure 5 is a schematic vertical cross-sectional view of a composite substrate including a porous silicon carbide layer and a silicon carbide recycled substrate according to an embodiment, wherein the porous silicon carbide layer is directly bonded to the silicon carbide recycled substrate.

[0012] Figure 6 is a schematic vertical cross-sectional view of a composite substrate including a porous silicon carbide layer and a silicon carbide recycled substrate according to an embodiment, wherein an interface layer is formed between the porous silicon carbide layer and the silicon carbide recycled substrate.

[0013] Figure 7 is a schematic vertical cross-sectional view of a silicon carbide power diode having a laterally homogeneously doped porous silicon carbide portion.

[0014] Figure 8 is a schematic vertical cross-sectional view of a silicon carbide power transistor having a laterally homogeneously doped porous silicon carbide portion. DETAILED DESCRIPTION

[0015] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and are illustrated in the accompanying drawings as illustrations of specific embodiments in which a composite wafer, a power semiconductor device, and a method for manufacturing a semiconductor device can be implemented. Other embodiments may be used and structural or logical changes may be made without departing from the concepts of the present disclosure. Features illustrated or described for one embodiment can be used on other embodiments or used in combination with other embodiments to produce another embodiment. It is intended that the present disclosure includes such modifications and variations. Examples are described in a certain manner, which should not be interpreted as limiting the scope of the attached claims. The accompanying drawings are not drawn to scale and are for illustrative purposes only. If not otherwise indicated, corresponding elements are designated by the same reference numerals in different drawings.

[0016] The terms "having", "containing", "including", "comprising" and the like are open ended and indicate the presence of stated structures, elements or features but do not exclude the presence of additional elements or features. The articles "a", "an" and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0017] The term "directly electrically connected" describes a permanent low resistance ohmic connection between directly electrically connected elements, such as direct contact between the elements involved or a low resistance connection via metal and / or heavily doped semiconductor materials. The terms "electrically connected" and "signal connected" include direct electrical connections and additionally allow for additional electrical elements in the signal path or power supply path between the electrically connected or signal connected elements.

[0018] The term “power semiconductor device” refers to active semiconductor devices, such as diodes and transistors, having a high voltage blocking capability of at least 30 V (e.g., 48 V, 100 V, 600 V, 1.6 kV, 3.3 kV, or greater) and having a nominal on-state current or forward current of at least 200 mA (e.g., 1 A, 10 A, or greater).

[0019] Ranges given for physical dimensions include the boundary values. For example, the range of parameter y from a to b is read as a≤y≤b. The same applies to ranges with a boundary value (e.g., "at most" and "at least").

[0020] The main component of a layer or structure of a chemical compound or alloy is the element whose atoms form the chemical compound or alloy.

[0021] The term “on” should not be interpreted as meaning only “directly on.” On the contrary, if an element is disposed “on another element” (for example, a layer is “on another layer” or “on a substrate”), another component (for example, another layer) may be disposed between the two elements (for example, if a layer is “on a substrate,” another layer may be disposed between the layer and the substrate).

[0022] According to aspects of the present disclosure, a method for manufacturing a semiconductor device may include: forming a transfer foil including a porous silicon carbide layer. A composite substrate is formed, the composite substrate may include a transfer foil and a support substrate, wherein the transfer foil and the support substrate are brought into contact with each other and connected to each other. An epitaxial layer may be formed on a side of the porous silicon carbide layer opposite to the support substrate. The composite substrate is divided into a device substrate and a recycling substrate, the device substrate includes the epitaxial layer, and the recycling substrate includes the support substrate.

[0023] The transfer foil may have two parallel foil surfaces and a uniform thickness given by the distance between the two foil surfaces. In the following, two surfaces or planes may be considered to be "parallel" if their (e.g., imaginary) extensions enclose an angle of less than 5°, or less than 3°, or less than 1°.

[0024] The transfer foil may be a rigid film that may be composed of a porous silicon carbide layer, or may be a layer stack that includes at least one auxiliary layer in addition to the porous silicon carbide layer. (One or more) auxiliary layers may include a material different from porous single crystal silicon carbide, or may be composed of said material. If the layer stack includes a single auxiliary layer, the auxiliary layer may include an organic material or an inorganic material or may be composed of an organic material or an inorganic material. If the layer stack includes two or more auxiliary layers, all auxiliary layers may include an organic material or may be composed of an organic material, all auxiliary layers may include an inorganic material or may be composed of an inorganic material, or at least one auxiliary layer in the auxiliary layer may include an organic material or may be composed of an organic material and at least one auxiliary layer in the other auxiliary layers may include an inorganic material or may be composed of an inorganic material. For example, the auxiliary layer or at least one auxiliary layer is based on silicon and includes silicon oxide and / or silicon nitride. The auxiliary layer or at least one auxiliary layer may be based on silicon carbide. The auxiliary layer or at least one auxiliary layer may be based on carbon. The auxiliary layer may include glass, ceramic or resin.

[0025] The lateral extent of the transfer foil can be large enough to completely cover the planar main surface of a standard wafer. In particular, the transfer foil can be shaped so that the transfer foil covers a circle with a diameter of at least 4 inches, 150 mm, 200 mm or 300 mm. The shape of the transfer foil in the horizontal plane can be a circle or a polygon, such as a rectangle, square or hexagon.

[0026] The porous silicon carbide layer may have two parallel main surfaces. The thickness of the porous silicon carbide layer given by the distance between the two main surfaces may be uniform along the porous silicon carbide layer. There may also be a case where the thickness of the porous silicon carbide layer varies along the porous silicon carbide layer by up to 35% (or up to 10% or up to 5%) of the average thickness of the porous silicon carbide layer. The thickness of the porous silicon carbide layer may be in the range from 1 nm to 50 μm.

[0027] The porous silicon carbide layer includes a single crystal 3D support structure ("skeleton structure") having closed and / or connected (e.g., interconnected) pores. The major surface of the porous silicon carbide layer may be formed by functional groups (such as Si-O-Si, Si-F2 and / or CH x )cover.

[0028] Defining the porosity of a layer as the ratio of the interstitial volume (i.e., "void volume") in the layer to the total volume of the layer, the average porosity of a porous silicon carbide layer is in the range of from 10% to 80%, for example, in the range of from 30% to 60%. The local porosity determined for a unit volume greater than the maximum pore size may vary from 1% to 80%.

[0029] In the porous silicon carbide layer, the local porosity may be homogeneous. Alternatively, the porosity of the porous silicon carbide layer may be uniform only along the direction parallel to the main surface, and may vary in the direction orthogonal to the main surface. For example, the porosity may increase gradually or stepwise as the distance from one or both main surfaces increases, or the porosity may decrease as the distance from both main surfaces increases. The porous silicon carbide layer may include partial layers of different porosities stacked vertically. For example, the porous silicon carbide layer may include a coarse porous partial layer and a fine porous partial layer, wherein the porosity of the coarse porous partial layer is greater than the porosity of the fine porous partial layer. For example, the coarse porous partial layer may include large pores having an average diameter greater than 50nm (e.g., in the range of from 50nm to 200nm) and a high overall porosity of at least 30% and at most 80% (e.g., in the range of from 40% to 60%). The fine porous partial layer may comprise small pores having an average diameter of at most 50 nm (eg less than 40 nm) and a low overall porosity of at most 50% (eg in the range from 5% to 35%).

[0030] The porous silicon carbide layer may include a surface portion, wherein the surface portion includes pores at a porosity of less than 5%, or has almost no pores. The surface portion may directly adjoin one of the major surfaces of the porous silicon carbide layer.

[0031] The transfer foil can be obtained by forming a porous surface layer along the top surface of a source substrate from single-crystal silicon carbide and detaching the porous surface layer or a part of the porous surface layer from the source substrate.

[0032] Forming the porous surface layer may include metal assisted photochemical etching (MAPCE). Metal assisted photochemical etching may use a noble metal layer as an electrode.

[0033] Alternatively, a porous surface layer may be formed by electrochemical etching, which induces anodic dissolution of the source substrate. For example, the source substrate may be contacted with an electrolyte containing fluorine, such as hydrofluoric acid (HF) and a surfactant (surfactant). The surfactant may contain tetramethylammonium hydroxide (TMAH), potassium hydroxide (KOH) and / or ethanol. Alternatively, the electrolyte may be an aqueous HF solution. The cathode electrode may be immersed in the electrolyte, and a potential may be applied between the cathode electrode and the source substrate forming the anode electrode. The electrochemical etching may be a dark process, or may be photoelectrochemical etching assisted by light.

[0034] The transfer foil including the porous silicon carbide layer can be detached from the source substrate by mechanical force. For example, the stressor layer can be applied on the top surface of the porous surface layer, and the mechanical stress induced in the source substrate by the stressor layer can cause the porous silicon carbide layer to cleave along a horizontal plane. The stressor layer can be part of the transfer foil. The stressor layer can be removed before forming the composite substrate, or after forming the composite substrate.

[0035] The transfer foil and the support substrate are brought into contact with each other and connected to each other, wherein a stable and permanent chemical bond can be formed between the first main surface (bonding surface) of the porous silicon carbide layer and the process surface of the support substrate. The support substrate consists of a support material different from the material of the source substrate, or comprises a top layer from a substrate material different from the base material of the source substrate, from which the porous silicon carbide layer is obtained.

[0036] The process surface of the support substrate extends along two orthogonal horizontal (lateral) directions. The normal on the process surface defines the vertical direction.

[0037] The substrate material and the source substrate may have the same main components silicon and carbon, but different microstructures (German: Gefüge). The support substrate may be a substrate other than a defect-free or nearly defect-free single-crystal silicon carbide substrate and may be cheaper than the source substrate from which the porous silicon carbide layer is obtained.

[0038] The transfer foil and the supporting substrate are connected to one another to form a one-piece composite substrate.

[0039] The epitaxial layer may be formed directly on the second main surface (epitaxial surface) of the porous silicon carbide layer of the transfer foil. For example, the epitaxial layer may be formed directly on the surface portion of the porous silicon carbide layer. Forming the epitaxial layer includes a deposition process and, if applicable, a heat treatment for recrystallization of the deposited material to obtain 4H-SiC. The deposition process may include chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), organometallic vapor phase epitaxy (OMVPE) and / or molecular beam epitaxy (MBE). The epitaxial layer forms a silicon carbide single crystal, wherein the atoms of the single crystal continue the crystal lattice of the porous silicon carbide layer.

[0040] Dividing the composite substrate may include dividing the porous silicon carbide layer into two parts in a horizontal direction, for example, cleaving the porous silicon carbide layer in a horizontal direction, wherein the composite substrate is separated into a device substrate and a recovery substrate. The device substrate includes an epitaxial layer and may also include a device portion of the cleaved porous silicon carbide layer. The recovery substrate includes a support substrate and may also include a recovery portion of the cleaved porous silicon carbide layer.

[0041] The device substrate is separated from the recovered substrate in a single piece. The recovered portion of the cleaved porous silicon carbide layer remains connected to the support substrate.

[0042] The recovered portion of the cleaved porous silicon carbide layer may form a continuous layer or may include laterally separated islands. The device portion of the cleaved porous silicon carbide layer may form a continuous layer or may include laterally separated islands.

[0043] Dividing the composite substrate may include applying mechanical stress to the composite substrate in such a way that the segmentation process in the porous silicon carbide layer relieves the mechanical stress before another portion of the composite substrate is mechanically damaged. The mechanical stress may act in a horizontal lateral direction, in a horizontal radial direction, in a vertical direction, and / or as a torsional shear stress. Generating the mechanical stress may include generating a temperature difference along a vertical direction, utilizing a difference in thermal expansion coefficients between the composite substrate and at least one auxiliary structure securely connected to one of the major surfaces of the composite substrate, twisting and / or pulling out a chuck securely connected to one of the major surfaces of the composite substrate, and / or applying a lever force to peel off the device substrate.

[0044] Alternatively or in addition, dividing the composite substrate may include: selectively damaging the skeleton structure of the porous silicon carbide layer physically and / or chemically until the device substrate is separated from the recovery substrate, or until the application of a relatively weak mechanical force is sufficient to remove the device substrate from the composite substrate. For example, a horizontal fluid beam, a horizontal particle beam, or a horizontal radiation may be directed to the exposed lateral surface of the porous silicon carbide layer to remove material from the skeleton structure and weaken the skeleton structure of the porous silicon carbide layer. Alternatively or in addition, damaging the skeleton structure may include: filling the pores with an auxiliary filling material, and using the physical properties of the auxiliary filling material to damage the skeleton structure. Alternatively or in addition, damaging the skeleton structure may use the large surface of the pores to highly selectively chemically decompose or chemically convert the silicon carbide in the porous silicon carbide layer into volatile components and / or mechanically less stable compounds.

[0045] After the doped regions, insulator structures and / or conductive structures of the electronic components have been formed on and / or in the epitaxial layer, the epitaxial layer can be separated from the base portion along the porous structure. For example, after forming the semiconductive portion of the semiconductor device in the epitaxial layer, the epitaxial layer can be separated from the base portion. The separation process can include: separating (e.g., cleaving) the porous structure along an approximately horizontal plane through the coarse porous layered portion.

[0046] After removal of the recovered portion of the cleaved porous silicon carbide layer, the recovered substrate can be reused as a support substrate. The device substrate can be used to manufacture a semiconductor device, wherein the device portion of the cleaved porous silicon carbide layer can be completely removed. Alternatively, the device portion of the cleaved porous silicon carbide layer can be flattened and / or leveled, for example planarized.

[0047] The method highly decouples epitaxy from porosification and enables cost-effective production of thin silicon carbide device substrates, such as those suitable for power semiconductor devices.

[0048] According to an embodiment, the support substrate may include a polycrystalline silicon carbide substrate, a single crystal silicon carbide wafer having a polymorph different from that of the porous silicon carbide layer, or a single crystal silicon carbide recycled substrate.

[0049] The polycrystalline silicon carbide substrate may be an unprocessed or nearly unprocessed polycrystalline silicon carbide wafer. When the porous silicon carbide layer is formed of 4H-SiC, the single crystal silicon carbide substrate of a polymorph different from that of the porous silicon carbide layer may contain or consist of 2H-SiC, 3C-SiC and / or 6H-SiC.

[0050] The single crystal silicon carbide recycled substrate may include single crystal silicon carbide of any polymorph, but is not suitable for obtaining defect-free standard silicon carbide semiconductor devices on an economic scale. The recycled substrate may be a single crystal 4H-SiC wafer that does not meet at least one of the relevant specifications established for wafers used in the manufacture of power semiconductor devices. For example, the single crystal silicon carbide recycled wafer contains more impurity atoms and / or more crystal defects, has a resistivity outside a specified range or a surface orientation outside a specified range. The support substrate can be cheaper than the source substrate.

[0051] According to an embodiment, forming the composite substrate may include bonding the porous silicon carbide layer and the support substrate together. A permanent bond is formed between the porous silicon carbide layer and the support substrate.

[0052] The permanent bond can be a glue-free bond or an adhesive bond. The glue-free bond is produced by direct bonding or sintering (German: Schmelzbonden). The adhesive bond is produced by applying an adhesive.

[0053] For example, the bonding surface of the porous silicon carbide layer can be directly bonded to the process surface of the supporting substrate. In this case, no adhesive material or no material other than the material from the supporting substrate and the porous silicon carbide layer can exist along the interface between the porous silicon carbide layer and the supporting substrate. Direct bonding can be based on chemical bonding directly between two bonding members. For example, the two bonding members can be two of the following members: (i) a supporting substrate, (ii) a porous silicon carbide layer, (iii) an (optional) non-adhesive bonding layer on the supporting substrate, (iv) an (optional) non-adhesive bonding layer on the porous silicon carbide layer. The non-adhesive bonding layer may include, or be composed of, a semiconductive material and / or a metallic material.

[0054] Melt bonding may include pre-bonding at ambient temperature and annealing at elevated temperature. Pre-bonding brings the bonding surface of the porous silicon carbide layer into physical contact with the process surface of the support substrate. Annealing may activate and / or strengthen the chemical bonding between the support substrate and the porous silicon carbide layer. Direct bonding (melt bonding) may be assisted by applying a silicon carbide-based liquid, a liquid silicon carbide precursor, or amorphous silicon to the process surface of the support substrate and / or the bonding surface of the porous silicon carbide layer prior to pre-bonding.

[0055] Alternatively, the porous silicon carbide layer of the transfer foil can be adhesively bonded to the process surface of the support substrate via an intermediate bonding layer. The bonding is based on chemical bonding between the cured bonding layer and the support substrate and chemical bonding between the cured bonding layer and the porous silicon carbide layer.

[0056] Adhesive bonding may include applying a curable adhesive to a process surface of the support substrate and / or to a bonding surface of the porous silicon carbide layer, pressing the support substrate and the transfer foil against each other with the curable adhesive therebetween, and curing the adhesive, wherein the adhesive cures and forms a cured adhesive layer. As an example, the curable adhesive may be applied as a liquid, a tape, or a layer on a tape.

[0057] Typically, prior to bonding, surface pretreatment or surface conditioning may be performed. For example, such pretreatment or conditioning may include treatment with plasma and / or wet chemical solutions.

[0058] According to an embodiment, the porous silicon carbide layer may include a bonding surface having a C-plane, and forming the composite substrate includes bonding the bonding surface of the porous silicon carbide layer to a support substrate.

[0059] The C-face bonding surface can simplify bonding the transfer foil directly to the Si-face of a single crystal recycled substrate of the same polymorph as the porous silicon carbide layer. Bonding the C-face of the porous silicon carbide layer to a support substrate can make the Si-face of the porous silicon carbide layer accessible for further processing.

[0060] According to an embodiment, the porous silicon carbide layer may include an epitaxial surface having a Si face, and the epitaxial layer is formed on the epitaxial surface of the porous silicon carbide layer.

[0061] The porous silicon carbide layer can be formed to have a significantly lower porosity along the surface having the Si face than along the surface having the C face.

[0062] Growing an epitaxial layer on an epitaxial surface having a Si face can be less complicated than growing an epitaxial layer on a C face.

[0063] According to an embodiment, electronic components may be formed in and / or on the epitaxial layer before singulating the composite substrate.

[0064] The electronic component may be an active semiconductor component. For example, the electronic component is a semiconductor diode or a transistor. The doped semiconductor region of the electronic component (such as the anode region of a semiconductor diode or the source / emitter region of a transistor) can be formed in the epitaxial layer. The anode electrode of the semiconductor diode or the source / emitter electrode of the transistor can be formed on the epitaxial layer. The gate electrode of the transistor can be formed on the epitaxial layer, or in a trench extending from the front side into the epitaxial layer.

[0065] According to embodiments, the method may include backside processing of an exposed backside surface of a device substrate.

[0066] Dividing the composite substrate includes cleaving the porous silicon carbide layer, wherein the back surface of the device substrate is separated from the front side surface of the recovered substrate. The exposed back surface is formed by the device portion of the cleaved porous silicon carbide layer.

[0067] The backside processing may include CMP that planarizes and / or recesses the device portion of the cleaved porous silicon carbide layer, wherein the device portion of the cleaved porous silicon carbide layer may be completely removed from the device substrate, or wherein the planarized device portion of the cleaved porous silicon carbide layer forms a porous backside layer of the device substrate. Alternatively or in addition, the backside processing may include the introduction of dopants through the exposed backside surface, selective heat treatment, and / or deposition of materials (e.g., deposition of a metal layer).

[0068] According to embodiments, a metal layer may be formed on the exposed back surface of the device substrate.

[0069] The metal layer may be a homogeneous layer or may be a layer stack comprising two or more vertically stacked sub-layers of different composition and / or structure.

[0070] According to an embodiment, an ohmic contact may be formed on the back side of the device substrate.

[0071] Forming the ohmic contact may include: introducing impurities through the exposed back surface of the device substrate to form a heavily doped contact layer along the back surface, and forming a metal layer on the heavily doped contact layer, wherein the metal layer and the heavily doped contact layer form an ohmic contact. Introducing impurities may include: implanting dopants through the back surface of the device substrate. Forming the ohmic contact may include local heat treatment of the back surface, for example, laser thermal annealing (LTA).

[0072] The metal layer may form an electrode of a vertical semiconductor device, wherein current flows between the front side and the back side in the forward mode of a semiconductor diode or in the on-state of a power transistor.

[0073] According to an embodiment, forming the transfer foil may include forming a porous surface layer on a front side of the single crystal silicon carbide source substrate and separating a foil portion of the porous surface layer from the source substrate, wherein the foil portion forms a porous silicon carbide layer of the transfer foil.

[0074] The source substrate has a planar first major surface extending along two orthogonal horizontal (lateral) directions. A normal on the first major surface defines a vertical direction.

[0075] The foil portion is removed in a single piece from the rest of the source substrate. The substrate portion of the porous surface layer may remain connected to the non-porous, non-porous substrate portion of the source substrate. The substrate portion may form a continuous layer, or may comprise laterally separated islands.

[0076] Separating the foil portion from the porous surface layer divides the porous surface layer into two portions in a horizontal direction and may include applying mechanical stress to the source substrate in such a way that the dividing process in the porous surface layer relieves the mechanical stress before another portion of the source substrate is mechanically damaged. The mechanical stress may act in a horizontal lateral direction, in a horizontal radial direction, in a vertical direction, or as a torsional shear stress. Generating the mechanical stress may include generating a temperature difference in a vertical direction, utilizing a difference in thermal expansion coefficients between the source substrate and at least one auxiliary structure firmly connected to one of the main surfaces of the source substrate, twisting and / or pulling out a chuck firmly connected to one of the main surfaces of the source substrate, and / or applying a lever force to peel off the foil portion.

[0077] Alternatively or in addition, separating the foil portion of the porous surface layer from the source substrate may include: selectively damaging the skeleton structure of the porous surface layer physically and / or chemically until the foil portion of the porous surface layer is disassembled from the substrate portion, or until the application of a relatively weak mechanical force is sufficient to disassemble the foil portion from the source substrate. For example, a horizontal fluid beam, a horizontal particle beam, or a horizontal radiation may be directed to the exposed lateral surface of the porous surface layer to remove material from the skeleton structure and weaken the skeleton structure of the porous surface layer. Alternatively or in addition, damaging the skeleton structure may include: filling the pores with an auxiliary filling material, and using the physical properties of the auxiliary filling material to damage the skeleton structure. Alternatively or in addition, damaging the skeleton structure may use the large surface of the pores to highly selectively chemically decompose or chemically convert the silicon carbide in the porous surface layer into volatile components and / or mechanically less stable compounds.

[0078] The transfer foil may include an auxiliary layer applied to one of the main surfaces of the porous silicon carbide layer. For example, the auxiliary layer may be formed or applied on the porous surface layer before dividing the porous surface layer. Alternatively or in addition, the auxiliary layer may be applied to at least one of the main surfaces of the porous silicon carbide layer after separating the foil portion from the source substrate.

[0079] The recovered portion of the source substrate, which includes a substrate portion of a porous surface layer and a non-porous substrate portion of the source substrate, can be remade. For example, the substrate portion of the porous surface layer can be planarized or completely removed so that in the next cycle, another porous surface layer can be formed in the recovered portion of the remade source substrate.

[0080] According to an embodiment, forming the porous surface layer may include metal assisted photochemical etching (MAPCE).

[0081] MAPCE can form a porous silicon carbide layer on the C-face of the source substrate.

[0082] According to an embodiment, dividing the composite substrate may include generating horizontal mechanical stress in the porous silicon carbide layer.

[0083] Horizontal mechanical stresses may be generated by radial forces, lateral forces and / or by torsion. The mechanical stresses may generate horizontal cracks in the vertical columns of the skeleton structure in the porous silicon carbide layer and / or promote the growth of horizontal cracks until the composite substrate is separated into two parts.

[0084] Generating the horizontal mechanical stress may include forming or securely attaching (e.g., bonding) a stressor layer on a major surface of the composite substrate, and exposing the composite substrate to a thermal treatment, wherein different degrees of thermal expansion in the composite substrate and the stressor layer generate radial mechanical stress in the composite substrate. The mechanical stress may have a maximum value in a horizontal layer portion having a highest porosity.

[0085] According to another aspect of the present disclosure, a composite substrate may include a support substrate including single crystal silicon carbide. A single crystal porous silicon carbide layer is located on a process surface of the support substrate, wherein the polymorph of the support substrate is different from the polymorph of the porous silicon carbide layer, and / or the support substrate is a recycled wafer. An epitaxial layer is formed on a side of the porous silicon carbide layer opposite the support substrate.

[0086] The support substrate may include a non-porous single-crystal silicon carbide layer, or may consist of non-porous single-crystal silicon carbide.

[0087] According to an embodiment, the single-crystalline porous silicon carbide layer may be in direct contact with the process surface of the support substrate. For example, the single-crystalline porous silicon carbide layer is directly bonded to a non-porous single-crystalline silicon carbide layer of the support substrate, or directly bonded to a support substrate composed of non-porous single-crystalline silicon carbide. Chemical bonding (e.g., silicon-carbon bonding) is formed between the single-crystalline porous silicon carbide layer and the support substrate.

[0088] According to an embodiment, the epitaxial layer may be in direct contact with the porous silicon carbide layer. For example, the porous silicon carbide layer may include a low porosity surface layer portion having a porosity of less than 5% and a thickness of at most 300 nm. The epitaxial layer may be in direct contact with the low porosity surface layer portion.

[0089] According to another aspect of the present disclosure, a power semiconductor device may include a single crystal porous silicon carbide portion having a laterally homogeneous porosity. A non-porous silicon carbide portion is in direct contact with a major surface of the porous silicon carbide portion. An active semiconductor element includes a semiconductive region formed in the non-porous silicon carbide portion. A first load electrode is formed on a front side of the non-porous silicon carbide portion opposite to the porous silicon carbide portion. A second load electrode is formed on a rear side of the porous silicon carbide portion opposite to the major surface of the porous silicon carbide portion.

[0090] According to an embodiment, the single-crystalline porous silicon carbide portion may have a laterally constant dopant concentration gradient.

[0091] In the skeleton structure of the porous silicon carbide part, the dopant concentration is constant along the lateral direction.

[0092] The doping level in the porous silicon carbide portion and the doping level in the non-porous silicon carbide portion may be the same or at least similar, wherein the doping level in the porous silicon carbide portion is at most 50% lower than the doping level in the non-porous silicon carbide portion or exceeds the doping level in the non-porous silicon carbide portion by at most 50%. Alternatively, the doping level in the porous silicon carbide portion is at most 50% lower than the doping level in the non-porous silicon carbide portion or exceeds the doping level in the non-porous silicon carbide portion by more than 50%.

[0093] Figures 1A to 1D Referring to an embodiment having a transfer foil 110, the transfer foil 110 comprises no more than a porous silicon carbide layer 116, such as Figure 1A as shown in .

[0094] The porous silicon carbide layer 116 has two parallel main surfaces 111, 112. The main surfaces 111, 112 are planar or at least approximately planar and have lateral extensions along two orthogonal horizontal directions. The first main surface 111 on the first side of the porous silicon carbide layer 116 may have a carbon face (C face). The second main surface 112 on the second side of the porous silicon carbide layer 116 may have a silicon face (Si face).

[0095] The lateral extension may be large enough to completely cover the front side of a standard wafer having a diameter of at least 4 inches, 150 mm, 200 mm, or 300 mm. As an example, the horizontal shape of the porous silicon carbide layer 116 may be rectangular or circular. The distance between the first main surface 111 and the second main surface 112 corresponds to the thickness th1 along the vertical direction orthogonal to the horizontal direction. The thickness th1 of the porous silicon carbide layer 116 may be in the range of from 5 nm to 100 μm (e.g., 10 μm to 30 μm).

[0096] The porous silicon carbide layer 116 includes closed and / or connected pores embedded in a single crystal bulk support structure (skeleton structure). The single crystal support structure has a 4H polymorph. The dopant concentration in the single crystal support structure is uniform along the horizontal direction and can be uniform or can show no step or step changes along the vertical direction.

[0097] The porosity of the porous silicon carbide layer is constant in the horizontal direction. In the vertical direction, the porosity of the porous silicon carbide layer is constant or has a step-free or step-like variation. The average porosity of the porous silicon carbide layer is in the range from 10% to 80%, for example in the range from 30% to 60%. Along the second main surface 112, the porosity may be less than 5%, for example, less than 1%. Along the first main surface 111, the porosity may be higher than along the second main surface 112, for example, higher than 50%.

[0098] The first main surface 111 and / or the second main surface 112 of the porous silicon carbide layer may be formed by functional groups (such as Si-O-Si, Si-F2 and / or CH x )cover.

[0099] The porous silicon carbide layer 116 is brought into contact with a planar process surface 191 of a support substrate 190. A stable and permanent chemical bond is formed between the porous silicon carbide layer 116 and the support substrate 190.

[0100] Support substrate 190 comprises or consists of a non-porous substrate material, wherein the thermal expansion coefficient of the substrate material and the thermal expansion coefficient of porous silicon carbide layer 116 may be equal or deviate from each other by no more than 5% relative to an average of the two thermal expansion coefficients.

[0101] The lateral extension of the support substrate 190 may conform to a standard wafer having a diameter of at least 4 inches, 150 mm, 200 mm, or 300 mm.

[0102] As an example, the material of the support substrate 190 is different from a non-porous single-crystal silicon carbide substrate having a polymorph of the porous silicon carbide layer 116 and meeting the specifications of a source substrate for the manufacture of a power semiconductor device in terms of resistivity, crystal orientation, crystal defect density, dopant concentration, hydrogen content, and / or oxygen content. For example, the substrate material of the support substrate 190 may be single-crystal 3C-SiC, 2H-SiC, or 6H-SiC or polycrystalline silicon carbide. Alternatively, the support substrate is a recycled wafer that does not meet the specifications of an initial substrate for the manufacture of a power semiconductor device.

[0103] Connecting the porous silicon carbide layer 116 and the supporting substrate 190 may include: before bringing the bonding surface 111 of the porous silicon carbide layer 116 and the process surface 191 of the supporting substrate 190 into contact with each other, directly bonding or sintering bonding with or without applying liquid silicon carbide to the process surface 191 of the supporting substrate 190 and / or the first main surface 111 (bonding surface) of the porous silicon carbide layer 116.

[0104] Figure 1B A single piece composite substrate 100 is shown, comprising a porous silicon carbide layer 116 and a support substrate 190 .

[0105] The epitaxial layer 120 is formed directly on the second main surface 112 (epitaxial surface) of the porous silicon carbide layer 116. Forming the epitaxial layer 120 includes a deposition process and, if applicable, a heat treatment for recrystallization of the deposited material to obtain 4H-SiC. The deposition process may include chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), organic metal vapor phase epitaxy (OMVPE) and / or molecular beam epitaxy (MBE). The epitaxial layer 120 grows in registration with the crystal lattice of the porous silicon carbide layer 116. The initial stage of epitaxy can be controlled to promote a certain lateral overgrowth of the voids in the epitaxial surface 112 across the porous silicon carbide layer 116.

[0106] exist Figure 1C , a single piece composite substrate 100 includes a support substrate 190, a porous silicon carbide layer 116, and an epitaxial layer 120 grown on an epitaxial surface 112 of the porous silicon carbide layer 116. The epitaxial layer 120 forms a single crystal, wherein atoms of the single crystal continue the crystal lattice of the porous silicon carbide layer 116. The porous silicon carbide layer 116 may include a low-porosity surface layer along the epitaxial surface 112, wherein the surface layer is formed before epitaxy and / or in an initial stage of epitaxy.

[0107] One or more active electrical components can be formed in and / or on the epitaxial layer 120. The porous silicon carbide layer 116 is then cleaved in the approximately horizontal cleavage portion 115. The cleavage portion 115 may include a coarse porous layered portion of the porous silicon carbide layer 116. In particular, the cleavage portion 115 may include a vertical high porosity sublayer of the porous silicon carbide layer 116, wherein the porosity of the porous silicon carbide layer 116 has a maximum value in the high porosity sublayer. The vertical extension of the cleavage portion 115 may be small relative to the thickness th1 of the porous silicon carbide layer 116. The cleavage portion 115 may have a certain distance relative to both the epitaxial layer 120 and the supporting substrate 190, or may be directly adjacent to the supporting substrate 190.

[0108] Cracking porous silicon carbide layer 116 may include: attaching a stressor substrate having a thermal expansion coefficient different from that of composite substrate 100 to at least one of the main surfaces of composite substrate 100, and then cooling or heating the composite including the stressor substrate and composite substrate 100 to generate thermomechanical stress in porous silicon carbide layer 116 along a horizontal radial direction.

[0109] Alternatively, thermomechanical stress may be induced in the porous silicon carbide layer 116 by creating a vertical temperature gradient in the composite substrate 100. Any type of cleavage process as discussed above can be used.

[0110] like Figure 1D As shown in Figure 1C The composite substrate 100 is separated into a device substrate 150 and a recovered substrate 160. The device substrate 150 includes the epitaxial layer 120 and the device portion 118 of the porous silicon carbide layer 116. The recovered substrate 160 includes the recovered portion 119 of the porous silicon carbide layer 116 and a support substrate 190.

[0111] The device substrate 150 can be further processed. For example, the device portion 118 of the porous silicon carbide layer 116 can be removed from the device substrate 150. The removal of the device portion 118 can include mechanical, chemical, physical polishing or a combination of different polishing methods, such as chemical mechanical polishing (CMP). CMP can expose the back surface of the epitaxial layer 120. A metal layer can be deposited on the back surface of the epitaxial layer 120. By slicing, a semiconductor die of a power semiconductor device is obtained from the device substrate 150.

[0112] The recovered portion 119 of the cleaved porous silicon carbide layer 116 is removed from the recovered substrate 160. Then, the recovered substrate 160 can be reused as another supporting substrate 190, and the process of transferring the porous silicon carbide layer 116 to a supporting substrate, growing an epitaxial layer on the porous silicon carbide layer 116, and dividing the device substrate from the obtained composite substrate can be repeated.

[0113] exist FIG. 2A to FIG. 2D In the embodiment, the transfer foil 110 includes an auxiliary layer 117 formed on or attached to the epitaxial surface 112 of the porous silicon carbide layer 116, such as Figure 2A as shown in .

[0114] The auxiliary layer 117 may be a homogeneous layer or a layer stack comprising at least two vertically stacked layers of different composition and / or microstructure. The auxiliary layer 117 may comprise an adhesive tape and / or a rigid support layer.

[0115] The interface layer 130 may be formed on the process surface 191 of the support substrate 190. The interface layer 130 includes a layer including silicon. For example, the interface layer 130 includes or consists of silicon nitride.

[0116] The porous silicon carbide layer 116 is brought into contact with the planar process surface 131 of the interface layer 130. A stable and permanent chemical bond is formed between the porous silicon carbide layer 116 and the interface layer 130. The auxiliary layer 117 is removed.

[0117] Figure 2B A porous silicon carbide layer 116 is shown wherein the bonding surface 111 is directly bonded to the interface layer 130. In the absence of the interface layer 130, the porous silicon carbide layer 116 is directly bonded to the support substrate 190.

[0118] Figure 2C and Figure 2D 1. The growth of the epitaxial layer 120 on the epitaxial surface 112 of the porous silicon carbide layer 116 and the segmentation of the composite substrate 100 along the cleaved portion 115 of the porous silicon carbide layer 116 are shown, as described above with reference to FIG. Figure 1C and Figure 1D As described above, the difference therein is that the interface layer 130 is formed between the porous silicon carbide layer 116 and the support substrate 190 .

[0119] FIG. 3A to FIG. 3D A method of obtaining semiconductor die 200 from device substrate 150 that has been cleaved from composite substrate 100 using porous silicon carbide layer 116 applied by transfer foil 110 is illustrated.

[0120] The composite substrate 100 is formed by bonding a transfer foil 110 including a porous silicon carbide layer 116 on a process surface 191 of a support substrate 190 and growing a low n-doped epitaxial layer 120 on an epitaxial surface 112 of the porous silicon carbide layer 116 by epitaxy.

[0121] Semiconducting regions, conductive structures, and insulating structures of the electronic component 210 are formed in and / or on the epitaxial layer 120 .

[0122] like Figure 3A As shown in FIG. 1 , the epitaxial layer 120 includes a plurality of equally sized device regions 220 arranged along two orthogonal horizontal directions. In each device region 220 , electronic components 210 of the same type are formed.

[0123] In the illustrated embodiment, acceptor atoms are implanted through the main surface 121 of the front side of the epitaxial layer 120 opposite to the porous silicon carbide layer 116 to form a p-doped anode region 281 in each device region 220. A metal layer or a metal layer stack is deposited and patterned to form an anode electrode 282 in each device region 220, wherein the anode electrode 282 forms an ohmic contact with the anode region 281. An insulator layer or an insulator layer stack is deposited and patterned to form a passivation structure 283 in each device region 220 that particularly covers the sidewalls of the anode electrode 282.

[0124] The composite substrate 100 is divided into a device substrate 150 and a recycling substrate, as shown in FIG. Figure 1D described.

[0125] Figure 3B A device substrate 150 is shown that includes the epitaxial layer 120 and the device portion 118 of the porous silicon carbide layer.

[0126] The polishing process removes the device portion 118 of the porous silicon carbide layer and exposes the epitaxial layer 120 at the back side of the device substrate 150 .

[0127] like Figure 3C As shown in FIG. 1 , the back surface 152 of the device substrate 150 exposes the epitaxial layer 120 .

[0128] Donor atoms may be introduced, for example, implanted, through the back surface 152 of the device substrate 150. One or more metal-containing layers are deposited on the back surface 152 of the device substrate 150. Before depositing the one or more metal-containing layers, or after depositing the one or more metal-containing layers, a local heat treatment activates the introduced donor atoms.

[0129] The activated donor atoms form a heavily doped contact layer 122 along the back surface 152 of the device substrate 150. The one or more deposited metal-containing layers form a metal layer structure 170. The heavily doped contact layer 122 and the metal layer structure 170 form an ohmic contact.

[0130] The dicing process separates the device regions 220 of the device substrate 150 from each other in the lateral direction, wherein each separated device region 220 forms a semiconductor die 200 of a vertical power semiconductor diode, wherein the cathode electrode is formed by a portion of the metal layer structure 170. The forward current of the power semiconductor diode flows between the anode electrode 282 located at the front side and the cathode electrode located at the back side of the semiconductor die 200.

[0131] Instead of a power semiconductor diode, a vertical transistor (e.g., a MOSFET or an IGBT) can be formed in the semiconductor die 200. Instead of completely removing the device portion 118 of the porous silicon carbide layer 116 and forming the metal layer structure 170 on the surface of the epitaxial layer 120, the CMP may remove only a portion of the device portion 118 of the porous silicon carbide layer 116, and the metal layer structure 170 is formed on the recessed and planarized surface of the device portion 118 of the porous silicon carbide layer 116.

[0132] FIG. 4A to FIG. 4C A process of forming a transfer foil 110 including a single-crystalline porous silicon carbide layer 116 is illustrated.

[0133] Figure 4AA non-porous single crystal silicon carbide source substrate 300 is shown. The source substrate 300 is a single crystal wafer or ingot and has two parallel main surfaces 301, 302. The polymorph of silicon carbide is 4H. The first main surface 301 may have an off-axis cut of about 4 degrees relative to the main crystal plane. The first main surface 301 on the front side of the source substrate 300 has a C-plane.

[0134] By MAPCE, a porous surface layer 310 is formed on the first major surface 301 of the source substrate 300. MAPCE porosifies the surface layer of the source substrate 300 below the first surface 301 (makes it porous).

[0135] Figure 4B A porous surface layer 310 formed by MAPCE and a non-porous substrate portion 390 of the source substrate 300 are shown. The porous surface layer 310 is formed in a section of the source substrate 300 directly below the first major surface 301 .

[0136] The separation process divides the porous surface layer 310 into a foil portion 316 and a substrate portion 315. The foil portion 316 includes a first layer portion of the porous surface layer 310 and forms the porous silicon carbide layer 116 of the transfer foil 110. The substrate portion 315 includes a second layer portion of the porous surface layer 316. The substrate portion 315 and the non-porous substrate portion 390 of the porous surface layer 310 form a recovered portion 360 of the source substrate 300.

[0137] Before separating foil portion 316 and substrate portion 315 or after separating foil portion 316 and substrate portion 315, an auxiliary layer may be formed on or attached to the front side of foil portion 316 so that transfer foil 110 includes porous silicon carbide layer 116 and the auxiliary layer.

[0138] The recovered portion of the source substrate, which includes the substrate portion of the divided porous surface layer and the non-porous substrate portion of the source substrate, is remade. For example, the substrate portion of the porous surface layer is planarized or completely removed so that in the next cycle, another porous surface layer can be formed in the recovered portion of the remade source substrate.

[0139] Figure 5 and Figure 6 Composite substrate 100 is shown including support substrate 190 including single crystal silicon carbide. Single crystal porous silicon carbide layer 116 of 4H polymorph is present on process surface 191 of support substrate 190. Support substrate 190 is a recycled wafer, or has a polymorph other than 4H.

[0140] Epitaxial layer 120 is formed on epitaxial surface 112 of porous silicon carbide layer 116 opposite to support substrate 190. Epitaxial layer 120 is in direct contact with porous silicon carbide layer 116. Porous silicon carbide layer 116 includes a low porosity surface layer portion having a porosity of less than 5%. Epitaxial layer 120 is in direct contact with the low porosity surface layer portion.

[0141] exist Figure 5 In the embodiment of the present invention, the single-crystal porous silicon carbide layer 116 is in direct contact with the process surface 191 of the support substrate 190. A silicon-carbon bond is formed between the single-crystal porous silicon carbide layer 116 and the support substrate 190.

[0142] exist Figure 6 In the embodiment of the present invention, the single crystal porous silicon carbide layer 116 is in direct contact with the interface layer 130 formed on the process surface 191 of the support substrate 190. A chemical bond is formed between the single crystal porous silicon carbide layer 116 and the interface layer 130. A chemical bond is also formed between the interface layer 130 and the support substrate 190. The interface layer 130 may include nitrogen atoms.

[0143] Figure 7 and Figure 8 Shows that you can Figure 6 The semiconductor die 200 of the power semiconductor devices 501 and 502 is obtained by using the composite substrate.

[0144] Semiconductor die 200 includes a single crystal silicon carbide body 230 having a planar front surface 231 on the front side and an opposite planar back surface 232. Front surface 231 and back surface 232 are parallel to each other and extend in a horizontal direction. The distance between front surface 231 and back surface 232 defines the thickness of the silicon carbide body. The vertical direction is defined as being orthogonal to the horizontal direction.

[0145] Silicon carbide body 230 includes a single-crystal porous silicon carbide portion 270 and a non-porous silicon carbide portion 280 between porous silicon carbide portion 270 and front surface 231. Non-porous silicon carbide portion 280 is in direct contact with a planar horizontal major surface 271 of porous silicon carbide portion 270.

[0146] The first load electrode 291 is formed on the front side of the non-porous silicon carbide portion 280 opposite to the porous silicon carbide portion 270. The second load electrode 292 is formed on the rear side of the porous silicon carbide portion 270 opposite to the main surface 271 of the porous silicon carbide portion 270. The first and second load electrodes 291 include one or more metal layers. The insulating passivation structure 283 covers a portion of the front side surface 231 adjacent to the first load electrode 291, a portion of the first load electrode 291, and a side wall of the first load electrode 291.

[0147] The semiconductor body 230 includes a heavily doped contact portion 222 formed along a back surface 232 of the semiconductor body 230 and a lightly doped drift region between the front surface 231 and the contact portion 222. The contact portion 222 is obtained from the contact layer 122 of the device substrate 150, such as Figure 3D In the illustrated embodiment, the contact portion 222 is completely formed in the porous silicon carbide portion 270. The contact portion 222 and the second load electrode 292 form an ohmic contact.

[0148] Figure 7 A power semiconductor diode 501 is shown, wherein the first load electrode 291 forms an anode electrode 282 and the second load electrode 292 forms a cathode electrode. The anode electrode 282 forms an anode terminal A, or is connected to the anode terminal A. The cathode electrode forms a cathode terminal K, or is connected to the cathode terminal K. The contact portion 222 is heavily n-doped. A p-doped anode region 281 is formed along the front surface 231 of the semiconductor body 230. The anode region 281 and the anode electrode 282 form an ohmic contact. The anode region 281 and the drift region 235 form a pn junction.

[0149] Figure 8 A power transistor 502 is shown, wherein a first load electrode 291 forms a source electrode and a second load electrode 292 forms a drain electrode. The source electrode forms a source terminal S, or is connected to the source terminal S. The drain electrode forms a drain terminal D, or is connected to the drain terminal D. The contact portion 222 is heavily n-doped. A transistor control region 284 is formed along the front surface 231 of the semiconductor body 230. The transistor control region 284 comprises: an n-doped source region of the transistor cell TC; and one or more p-doped wells, separating the source region and the n-doped drift region 235. The source electrode forms an ohmic contact with the source region and the p-doped well.

[0150] The porosity of the porous silicon carbide portion 270 is constant along the lateral direction. The porosity is constant along the lateral direction. The porosity decreases along the vertical direction with increasing distance from the back surface 232 of the silicon carbide body 230 .

[0151] The dopant concentration in the porous silicon carbide portion 270 is constant along the lateral direction. The dopant concentration is constant along the lateral direction.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a transfer foil (110) including a porous silicon carbide layer (116); forming a composite substrate (100) comprising the transfer foil (110) and a support substrate (190), wherein the transfer foil (110) and the support substrate (190) are brought into contact with each other and connected to each other; forming an epitaxial layer (120) on a side of the porous silicon carbide layer (116) opposite to the support substrate (190); and The composite substrate (100) is divided into a device substrate (150) and a recycling substrate (160), the device substrate (150) including the epitaxial layer (120), and the recycling substrate (160) including the supporting substrate (190).

2. The method according to claim 1, The support substrate (190) comprises a polycrystalline silicon carbide substrate, a substrate of single-crystalline silicon carbide comprising a polymorph different from the polymorph of the porous silicon carbide layer, and / or a silicon carbide recycled substrate.

3. The method according to claim 1, Wherein forming the composite substrate (100) includes bonding the transfer foil (110) to the support substrate (190).

4. The method according to any one of claims 1 to 3, The porous silicon carbide layer (116) includes a bonding surface (111) having a C-plane, and forming the composite substrate (100) includes bonding the bonding surface (111) of the porous silicon carbide layer (116) to the support substrate (190).

5. The method according to any one of claims 1 to 4, The porous silicon carbide layer (116) includes an epitaxial surface (112) having a Si face, and the epitaxial layer (120) is formed on the epitaxial surface (112) of the porous silicon carbide layer (116).

6. The method according to any one of claims 1 to 5, further comprising: Before dividing the composite substrate (100), semiconducting regions (281, 284) of electronic components (210) are formed in the epitaxial layer (120) and / or on the epitaxial layer (120).

7. The method according to any one of claims 1 to 6, further comprising: Backside processing of the exposed backside surface of the device substrate (150).

8. The method according to any one of claims 1 to 7, further comprising: A metal layer structure (170) is formed on the exposed back surface of the device substrate (150).

9. The method according to any one of claims 1 to 8, further comprising: An ohmic contact is formed on the back side of the device substrate (150).

10. The method according to any one of claims 1 to 9, The forming of the transfer foil (110) comprises forming a porous surface layer (310) on the front side of a single crystal silicon carbide source substrate (300) and separating a foil portion (316) of the porous surface layer (310) from the source substrate (300), wherein the foil portion (316) forms the porous silicon carbide layer (116) of the transfer foil (110).

11. The method according to claim 10, The forming of the porous surface layer (310) comprises metal-assisted photochemical etching.

12. The method according to any one of claims 1 to 11, Wherein dividing the composite substrate (100) includes inducing horizontal mechanical stress in the porous silicon carbide layer (116).

13. A composite substrate comprising: A support substrate (190) comprising single crystal silicon carbide; a single crystal porous silicon carbide layer (116) disposed on a process surface (191) of the support substrate (190), wherein the polymorph of the support substrate (190) is different from the polymorph of the porous silicon carbide layer (116), and / or the support substrate (190) is a recycled wafer; and An epitaxial layer (120) is formed on a side of the porous silicon carbide layer (116) opposite to the support substrate (190).

14. Composite substrate according to the preceding claim, The single-crystal porous silicon carbide layer (116) is in direct contact with the process surface (191) of the support substrate (190).

15. The composite substrate according to any one of the two preceding claims, The epitaxial layer (120) is in direct contact with the porous silicon carbide layer (116).

16. A power semiconductor device, comprising: a single crystal porous silicon carbide portion (270) having laterally homogeneous porosity; a non-porous silicon carbide portion (280) in direct contact with a major surface (271) of the porous silicon carbide portion (270); an active electronic component (210) comprising a semiconducting region formed in the non-porous silicon carbide portion (280); a first load electrode (291) formed on a front side of the non-porous silicon carbide portion (280) opposite to the porous silicon carbide portion (270); and A second load electrode (292) is formed on the rear side of the porous silicon carbide portion (270) opposite to the main surface (271) of the porous silicon carbide portion (270).

17. A power semiconductor device according to the preceding claim, The single crystal porous silicon carbide portion (270) has a constant dopant concentration gradient in a lateral direction.

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