Timekeeping and timing method and system based on ZYNQ architecture
By integrating multiple timing methods and efficient AXI bus communication in the ZYNQ architecture, the problem of insufficient reliability of high costs, high latency and single timing source in the existing technology is solved, and a high-precision and high-reliability punctual timing system is realized , adapt to the time synchronization needs in complex environments.
Patent Information
- Application Number
- CN202411290247.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-14
- Publication Date
- 2025-01-17
AI Technical Summary
The existing punctual timing system has high cost, high latency and insufficient reliability of a single timing source due to the use of DSP+FPGA architecture, which cannot meet the needs of modern complex and variable application environments.
Adopting a punctual method based on ZYNQ architecture, the AXI bus is used for high-precision timing, integrating three timing methods: real-time clock, rubidium atomic clock and Beidou system. External timing information is obtained through the PS terminal and transmitted to the PL terminal through the AXI bus for timing operation. , realize high-speed and high-precision punctual process, and perform real-time processing of time information and synchronization of time calibration second signals on the PL end.
It realizes high-speed and high-precision time synchronization, significantly improves the system's fault tolerance and reliability, simplifies the system structure, has plug-and-play functions, is easy to integrate and maintain, and ensures the accuracy and stability of the timing process. .
Smart Images
Figure CN119324774A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of time synchronization, and is applied to the ZYNQ series SOC platform of Xilinx Company, and in particular to a time keeping and timing method and system based on the ZYNQ architecture. Background Art
[0002] With the increasing application of ZYNQ system-on-chip (SOC) in recent years, the demand for a high-precision timekeeping and timing system based on the ZYNQ-SOC architecture has become increasingly urgent. The ZYNQ chip integrates the processing system (PS) and programmable logic (PL), which exchange high-speed data through the Advanced Extension Interface (AXI) bus, which is designed with the characteristics of fast communication and low latency. In addition, the ZYNQ chip has shown obvious advantages in subsequent development and application with its low energy consumption, high performance, ease of use and relatively low cost, which makes it an ideal choice for building an efficient timekeeping and timing system.
[0003] Traditional timekeeping and timing systems usually use a digital signal processor (DSP) plus a field programmable gate array (FPGA) architecture and rely on an external memory interface (EMIF) bus for communication. However, when such systems are directly migrated to the ZYNQ architecture, the accuracy of the timekeeping system will be adversely affected due to the high communication delay of the EMIF bus, so extensive modifications and adaptations are required. In addition, the procurement cost of the DSP and FPGA combination is high, which is not economical for cost-effective application scenarios.
[0004] More importantly, a single timing source can no longer adapt to the complex and ever-changing application environment of modern times. In order to ensure successful timing in various environments, the system must support multiple timing methods. This requires the new timekeeping and timing system to not only overcome the problems existing in the traditional architecture, such as large communication delays and high costs, but also be able to integrate multiple timing methods to improve the reliability and applicability of the system. Summary of the invention
[0005] The purpose of the present invention is to solve the problems of high cost, high delay and insufficient reliability of a single timing source caused by the existing timekeeping and timing system adopting the DSP+FPGA architecture, so a timekeeping and timing method and system based on the ZYNQ architecture is proposed. The present invention utilizes the transmission characteristics of the AXI bus in the ZYNQ architecture to perform high-precision timekeeping and three different modes of timing (including real-time clock mode RTC, rubidium atomic clock mode RB and Beidou system mode); at the same time, through the design and packaging of the timekeeping and timing logic, the high-speed and high-precision timekeeping and timing process of the SOC architecture under the ZYNQ platform is realized.
[0006] The present invention adopts the following technical solutions to achieve the purpose:
[0007] A timekeeping and timing method based on a ZYNQ architecture, wherein the ZYNQ architecture comprises a PS end and a PL end connected by an AXI bus communication; the method comprises: the PS end performs a timekeeping and time display process, and the PL end receives the timekeeping and performs a timekeeping process; the PS end obtains external timekeeping information and a time calibration second signal, and transmits the timekeeping information and the time calibration second signal to the PL end through the AXI bus; the PL end performs a timekeeping operation based on the received timekeeping information and the time calibration second signal, obtains real-time time information and performs a timekeeping process, and the real-time time information is transmitted to the PS end through the AXI bus; the PS end displays the received time information to the outside.
[0008] Furthermore, the PS end obtains the timing information and the time calibration second signal generated from various external methods through the receiver, and selects the corresponding timing method, and then transmits the timing information and the time calibration second signal to the PL end through the AXI bus for timing operation; after completing the timing, the PS end updates the received time information in real time through the AXI bus; when the timing operation is completed, when the PL end performs the timekeeping process, if the real-time time information exceeds the normal range, the PL end sends an alarm signal to the PS end. After receiving the alarm signal, the PS end transmits the timing information and the time calibration second signal to the PL end again to re-perform timing.
[0009] Specifically, the PS end obtains the timing information and time calibration second signals generated by three external timing modes through the receiver. The three timing modes are real-time clock mode RTC, rubidium atomic clock mode RB and Beidou system mode; when the receiver receives the timing information and time calibration second signals corresponding to the above three timing modes, the PS end selects one of the timing modes, obtains the corresponding timing information and time calibration second signal, and forms the corresponding timing mode selection signal in the timing information, which is transmitted to the PL end.
[0010] Furthermore, after the timing operation is completed, the PL end enters the timekeeping process; during the timekeeping process, the PL end determines in real time whether the time calibration second signal from the PS end is online. If it is online, the second signal in its own time information will jump synchronously with the jump of the time calibration second signal; if the time calibration second signals corresponding to the three timing methods are not online, the PL end will perform the timekeeping process based on the internal clock source of the chip in the ZYNQ architecture.
[0011] The present invention also provides a timekeeping and timing system based on a ZYNQ architecture, wherein the ZYNQ architecture includes a PS end and a PL end connected through an AXI bus communication; the PS end is also connected to a receiver and a display screen, and the receiver is connected to a timing source component; the timing source component is used to generate timing information and a time calibration second signal, and the receiver is used to obtain the timing information and the time calibration second signal from the timing source component and transmit the two to the PS end; the PS end is used to perform a timekeeping and time display process, transmit the timing information and the time calibration second signal to the PL end through the AXI bus, and simultaneously receive real-time time information from the PL end, and transmit the time information to the display screen for external display; the PL end is used to receive timekeeping, and according to the received timing information and the time calibration second signal, performs a timekeeping operation, obtains real-time time information and performs a timekeeping process, and simultaneously transmits the real-time time information to the PS end through the AXI bus.
[0012] In summary, due to the adoption of this technical solution, the beneficial effects of the present invention are as follows:
[0013] The present invention has the characteristics of high speed and high precision, can perfectly adapt to the system-on-chip SOC architecture under the ZYNQ platform, and fully utilize the advantages of its high-speed AXI bus.
[0014] The present invention integrates three timing modes, significantly improves the fault tolerance of the corresponding system, and ensures the reliability of timing in complex environments. The system structure is concise and clear, and the logical part can be encapsulated as an IP core, thereby realizing the plug-and-play function and facilitating integration and maintenance.
[0015] In addition, the present invention can perform signal processing on time information in real time and accurately align it with the second signal after timing, effectively avoiding the problem of insufficient accuracy of the second signal, thereby ensuring the accuracy and stability of the entire timekeeping and timing process. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 A schematic diagram of the connection relationship of the ZYNQ architecture timekeeping and timing system applied in the present invention;
[0017] Figure 2 Schematic diagram of the timing process in the method of the present invention;
[0018] Figure 3 It is a schematic diagram of the flow chart of the time keeping process in the method of the present invention. DETAILED DESCRIPTION
[0019] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.
[0020] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0021] Example 1
[0022] Combination Figure 1 Given the system connection relationship, this embodiment provides a timekeeping method based on the ZYNQ architecture, wherein the ZYNQ architecture includes a PS end and a PL end connected through an AXI bus communication; the method is: the PS end performs a timekeeping and time display process, and the PL end receives the timekeeping and performs a timekeeping process; the PS end obtains external timekeeping information and a time calibration second signal, and transmits the timekeeping information and the time calibration second signal to the PL end through the AXI bus; the PL end performs a timekeeping operation based on the received timekeeping information and the time calibration second signal, obtains real-time time information and performs a timekeeping process, and the real-time time information is transmitted to the PS end through the AXI bus; the PS end displays the received time information to the outside.
[0023] The ZYNQ architecture itself allows designers to implement software and hardware co-design on a single device, thereby optimizing the performance, power consumption and cost of the overall system. The method of this embodiment makes full use of the characteristics of the ZYNQ architecture to achieve high-precision time synchronization and timekeeping functions through the collaborative work of software and hardware. Since the PL side can perform special hardware optimization, the efficiency and accuracy of time processing are improved; in actual application, the method of this embodiment can reduce the power consumption of the overall system, and operations that do not require frequent updates can be efficiently completed on the PL side.
[0024] In this embodiment, the timing information received by the PL end from the PS end includes multiple time units (hundred years, years, months, days, hours, minutes, seconds) and a timing mode selection signal. After receiving the multiple time units, the PL end stores them in a register and performs a timing judgment before executing the timing operation.
[0025] The timing judgment is: if the current time information of the PL end is found to be inconsistent with the received timing information after comparison, it means that the time needs to be updated, so the timing switch is triggered to perform the timing operation.
[0026] In the timing operation, the units larger than seconds among the various time units are directly set as their own time information according to the timing information content, which is to ensure that these larger time units can be quickly synchronized to the latest timing information. The units less than or equal to seconds are all set to 99 in their own time information, and start counting from 0 at the next rising edge of the clock; this method can ensure that after the timing operation, the time units of seconds and below can start counting from a unified starting point, thereby ensuring the absolute accuracy of the second signal, without offset, and maintaining the continuity and accuracy of time.
[0027] After completing the timing operation, the PL terminal enters the timekeeping state, continues the timing process of the real-time time information, and waits for the arrival of the next timing information. Therefore, even if there is no new timing information, the overall system can maintain the continuity and accuracy of time.
[0028] The above method of this embodiment ensures that the PL end can accurately keep synchronized with the external timing information through a detailed timing mechanism; by processing different time units separately and adopting a specific counting strategy in the timing process, the time management logic of the PL end is simplified while ensuring time accuracy, making this method particularly suitable for application scenarios that require high-precision time synchronization, such as in the time synchronization process of communication networks and power systems.
[0029] Example 2
[0030] On the basis of Example 1, this example continues to introduce in detail the rest of the timekeeping and timing method based on the ZYNQ architecture. First, in this example, the PS end obtains the timing information and the time calibration second signal generated by three external methods through the receiver, and selects the corresponding timing method, and then transmits the timing information and the time calibration second signal to the PL end through the AXI bus for timing operation; after the timing is completed, the PS end updates the received time information in real time through the AXI bus; when the timing operation is completed, when the PL end performs the timekeeping process, if the real-time time information exceeds the normal range, the PL end sends an alarm signal to the PS end. After receiving the alarm signal, the PS end transmits the timing information and the time calibration second signal to the PL end again to re-perform timing.
[0031] Combination Figure 2 As shown in the figure, the three modes of this embodiment are respectively the real-time clock mode RTC, the rubidium atomic clock mode RB and the Beidou system mode; when the receiver receives the timing information and the calibration second signal corresponding to the three timing modes, the PS end selects one of the timing modes, obtains the corresponding timing information and the calibration second signal, and forms the corresponding timing mode selection signal in the timing information, which is transmitted to the PL end.
[0032] In this embodiment, the PS end displays the received time information externally through a display screen connected thereto, and simultaneously displays the timing mode selection signal in the timing information externally through the display screen.
[0033] At the same time, as a preferred embodiment of this invention, the PL end has multiple IP cores. According to different time-keeping and timing scenarios and conditions, the PL end encapsulates the timing logic corresponding to the three timing modes in the IP core for execution; when the timing operation is completed, the PL end enters the time-keeping process; the time-keeping logic corresponding to the time-keeping process and the timing logic corresponding to the timing operation are respectively encapsulated in different IP cores, and data is exchanged and interacted between different IP cores.
[0034] In the ZYNQ architecture of this embodiment, by encapsulating different functions into independent IP cores, the modularization and reuse of functions can be achieved, thereby improving the design efficiency and performance of the system. Specifically, according to different time-keeping and timing scenarios and conditions, the PL side designs three different timing logics, and encapsulates these three logics in three different IP cores. Each IP core contains complete timing logic, and the appropriate IP core can be selected for timing operations according to the specific scenario.
[0035] In addition to the timing logic, the PL side also designs logic specifically for the timekeeping process and encapsulates it in another IP core. These timekeeping logic IP cores are responsible for maintaining the continuity and accuracy of time after the timing operation is completed. Data communication between different IP cores can be achieved through shared memory, AXI bus or other existing internal communication mechanisms. After completing the timing operation, the timing logic IP core needs to pass the updated time information to the timekeeping logic IP core so that the latter can start the timekeeping timing correctly.
[0036] like Figure 3 As shown in the figure, after the timing operation is completed, the PL end enters the timekeeping process; during the timekeeping process, the PL end determines in real time whether the time calibration second signal from the PS end is online. If it is online, the second signal in its own time information will jump synchronously with the jumping of the time calibration second signal; if the time calibration second signals corresponding to the three timing modes are not online, the PL end will perform the timekeeping process based on the internal clock source of the chip in the ZYNQ architecture.
[0037] For the above Figure 3In the method part shown, after the timing operation is completed, the PL end enters the timekeeping process and needs to maintain the continuity of time in the absence of new timing information. At this time, the PL end needs to monitor the status of the time-correction second signal from the PS end in real time. The PL end synchronizes the jump of the time-correction second signal, which means that every time a jump of the time-correction second signal is received (usually indicating the end of one second), the PL end will update the counter of its own time information to maintain consistency. In the absence of the time-correction second signal, its internal clock source is usually a high-precision oscillator or clock generator inside the ZYNQ chip, which can provide a relatively stable clock signal, but there may be a small cumulative error in the long run.
[0038] In the timekeeping and timing process of this embodiment, the clock of the AXI bus is directly generated inside the chip in the ZYNQ architecture, and the corresponding clock rate is pre-configured. As an auxiliary part, this method can ensure that the data transmission on the AXI bus has high precision and stability, and also simplifies the design complexity of the system. The configuration of the clock rate can be achieved through parameter settings in the hardware description language, or through a specific configuration file. Different clock rates can correspond to different data transmission rates, thereby adapting to different application scenario requirements.
[0039] Example 3
[0040] This embodiment provides a timekeeping and timing system based on the ZYNQ architecture. The composition and connection relationship of each component in the system can be found in Figure 1 The system of this embodiment can effectively implement the method process of embodiment 1 and embodiment 2, and the specific introduction of the system is as follows:
[0041] A timekeeping and timing system based on a ZYNQ architecture, wherein the ZYNQ architecture comprises a PS end and a PL end connected via an AXI bus communication; the PS end is also connected to a receiver and a display screen, and the receiver is connected to a timekeeping source component; the timekeeping source component is used to generate timekeeping information and a time-correction second signal, and the receiver is used to obtain the timekeeping information and the time-correction second signal from the timekeeping source component and transmit the two to the PS end; the PS end is used to perform a timekeeping and time display process, transmit the timekeeping information and the time-correction second signal to the PL end via the AXI bus, and simultaneously receive real-time time information from the PL end, and transmit the time information to the display screen for external display; the PL end is used to receive timekeeping, and according to the received timekeeping information and the time-correction second signal, performs a timekeeping operation, obtains real-time time information and performs a timekeeping process, and simultaneously transmits the real-time time information to the PS end via the AXI bus.
[0042] In this embodiment, the timing source component has three different timing modes, namely, real-time clock mode RTC, rubidium atomic clock mode RB and Beidou system mode; corresponding to the three different timing modes, the timing source component includes a real-time clock module, a rubidium atomic clock device and a Beidou antenna.
[0043] The real-time clock (RTC) is a clock circuit commonly used in embedded systems. It can run independently of the power state of the main system and continue to keep time even when the system is turned off. Therefore, the real-time clock module in the timing source component has the characteristics of low power consumption, self-sustaining and high accuracy, and exists in the timing source component as a selected timing method.
[0044] The rubidium atomic clock is a high-precision clock based on the energy level transition frequency of the rubidium atom. Its principle is similar to that of the cesium atomic clock, but its cost is relatively low. The rubidium atomic clock device in the timing source component has extremely high time accuracy and good long-term stability, so it can provide a more reliable time reference and exists in the timing source component as a selected timing method.
[0045] Beidou antennas serve as receiving antennas for the Beidou satellite navigation system, which is a global satellite navigation system that can provide accurate position, speed and time information. The Beidou system has extremely high time synchronization accuracy and a wide coverage range, providing services to users around the world. It is suitable for application scenarios that require location information while requiring high-precision time synchronization. Therefore, it is also selected as a timing method and exists in the timing source component.
[0046] By supporting multiple timing modes, the timing source component of this embodiment can provide timing services with different accuracy levels to meet the needs of different application scenarios. Such diversified timing modes make the system more flexible and reliable.
Claims
1. A timekeeping method based on a ZYNQ architecture, wherein the ZYNQ architecture includes a PS end and a PL end connected by an AXI bus communication; characterized in that: The method comprises: the PS end performs the timing and time display process, and the PL end receives the timing and performs the time keeping process; the PS end obtains the external timing information and the time calibration second signal, and transmits the timing information and the time calibration second signal to the PL end through the AXI bus; The PL end performs timing operations based on the received timing information and the calibration second signal to obtain real-time time information and perform the timekeeping process. The real-time time information is transmitted to the PS end through the AXI bus; the PS end displays the received time information to the outside.
2. The time keeping and timing method based on ZYNQ architecture according to claim 1, characterized in that: The timing information received by the PL end from the PS end includes multiple time units and timing mode selection signals; after receiving the multiple time units, the PL end stores them in the register and performs a timing judgment before executing the timing operation; the timing judgment is: if the current time information of the PL end is inconsistent with the received timing information, the timing switch is triggered to execute the timing operation; in the timing operation, the units greater than seconds among the multiple time units are directly set as their own time information according to the content of the timing information, and the units less than or equal to seconds are all set to 99 in their own time information, and count from 0 at the next rising edge of the clock.
3. The time keeping and timing method based on ZYNQ architecture according to claim 1, characterized in that: The PS side obtains the timing information and the time-correction second signal generated by various external methods through the receiver, selects the corresponding timing method, and then transmits the timing information and the time-correction second signal to the PL side through the AXI bus for timing operation; after completing the timing, the PS side updates the received time information in real time through the AXI bus; when the timing operation is completed, when the PL side performs the timekeeping process, if the real-time time information exceeds the normal range, the PL side sends an alarm signal to the PS side. After receiving the alarm signal, the PS side transmits the timing information and the time-correction second signal to the PL side again to re-perform timing.
4. The time keeping and timing method based on ZYNQ architecture according to claim 3 is characterized in that: The PS end obtains the timing information and calibration second signals generated by three external timing modes through the receiver. The three timing modes are real-time clock mode RTC, rubidium atomic clock mode RB and Beidou system mode. When the receiver receives the timing information and calibration second signals corresponding to the above three timing modes, the PS end selects one of the timing modes, obtains the corresponding timing information and calibration second signals, and forms the corresponding timing mode selection signal in the timing information, which is transmitted to the PL end.
5. The time keeping and timing method based on ZYNQ architecture according to claim 4 is characterized in that: The PS terminal displays the received time information through the display screen connected to it, and simultaneously displays the timing mode selection signal in the timing information through the display screen.
6. The time keeping and timing method based on ZYNQ architecture according to claim 4, characterized in that: There are multiple IP cores in the PL end. According to different time-keeping and timing scenarios and conditions, the PL end encapsulates the timing logic corresponding to the three timing modes in the IP core for execution; when the timing operation is completed, the PL end enters the time-keeping process; the time-keeping logic corresponding to the time-keeping process and the timing logic corresponding to the timing operation are respectively encapsulated in different IP cores, and data is exchanged and interacted between different IP cores.
7. The time keeping and timing method based on ZYNQ architecture according to claim 6, characterized in that: After the timing operation is completed, the PL end enters the timekeeping process; during the timekeeping process, the PL end determines in real time whether the time calibration second signal from the PS end is online. If it is online, the second signal in its own time information will jump synchronously with the jump of the time calibration second signal; If the calibration second signals corresponding to the three timing modes are not online, the PL end will perform the timekeeping process based on the internal clock source of the chip in the ZYNQ architecture.
8. The time keeping and timing method based on ZYNQ architecture according to claim 1, characterized in that: During the timekeeping process, the clock of the AXI bus is directly generated inside the chip in the ZYNQ architecture and the corresponding clock rate is pre-configured.
9. A timekeeping and timing system based on ZYNQ architecture, wherein the ZYNQ architecture includes a PS end and a PL end connected by an AXI bus communication; characterized in that: The PS end is also connected to a receiver and a display screen, and the receiver is connected to the timing source component; the timing source component is used to generate timing information and a time calibration second signal, and the receiver is used to obtain the timing information and the time calibration second signal from the timing source component and transmit the two to the PS end; the PS end is used to perform the timing and time display process, transmit the timing information and the time calibration second signal to the PL end through the AXI bus, and receive real-time time information from the PL end at the same time, and transmit the time information to the display screen for external display; The PL end is used to receive timing information, perform timing operations based on the received timing information and the calibration second signal, obtain real-time time information and perform the timekeeping process, and at the same time transmit the real-time time information to the PS end through the AXI bus.
10. The time keeping and timing system based on ZYNQ architecture according to claim 9, characterized in that: The timing source component has three different timing modes, namely real-time clock mode RTC, rubidium atomic clock mode RB and Beidou system mode; corresponding to the three different timing modes, the timing source component includes a real-time clock module, a rubidium atomic clock device and a Beidou antenna.