Preparation method of semiconductor structure, semiconductor structure, memory and electronic equipment

Abstract

The invention provides a preparation method of a semiconductor structure, the semiconductor structure, a memory and electronic equipment. The preparation method of the semiconductor structure comprises the following steps: sequentially preparing a first doping layer, a sacrificial layer and a second doping layer on a substrate; etching the second doping layer, the sacrificial layer and the first doping layer in the first direction to form a plurality of first grooves in the first direction; etching to remove part of the sacrificial layer exposed in the first groove in the first direction, and preparing a first channel sub-layer between the first doping layer and the second doping layer; the second doping layer, the sacrificial layer and the first doping layer are etched in the first direction to form a plurality of first-direction second grooves, and the first-direction second grooves and the first-direction first grooves are alternately arranged at intervals; the sacrificial layer is removed through etching, a second channel sub-layer is prepared between the first doping layer and the second doping layer, and the second channel sub-layer makes contact with the first channel sub-layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, a memory and an electronic device. Background Art

[0002] In the field of semiconductor technology such as memory, reducing the critical dimensions of the device is an effective way to improve device performance. However, the short channel effect limits the further miniaturization of the device size. Vertical channel transistor (VerticalChannel Transistor, referred to as: VCT) is a new type of semiconductor device. Compared with traditional planar transistors, the channel length of vertical channel array transistors can better overcome the problem of short channel effect in planar devices, thus achieving a higher stacking density. However, with the continuous reduction of device size, limited by the actual preparation process, the vertical channel transistors prepared in traditional technology will have the problem of poor channel quality. Summary of the invention

[0003] Based on this, it is necessary to provide a method for preparing a semiconductor structure to improve the channel quality of a vertical channel transistor in view of the problems in the above background technology. Furthermore, a semiconductor structure, a memory and an electronic device are provided.

[0004] According to some embodiments of the present disclosure, the present disclosure provides a method for preparing a semiconductor structure, which comprises the following steps:

[0005] sequentially preparing a first doping layer, a sacrificial layer, and a second doping layer on a substrate;

[0006] Etching the second doped layer, the sacrificial layer and the first doped layer along a first direction to form a plurality of first grooves in a first direction;

[0007] Etching and removing the portion of the sacrificial layer exposed in the first groove in the first direction, and preparing a first channel sublayer between the first doped layer and the second doped layer;

[0008] Etching the second doped layer, the sacrificial layer and the first doped layer along the first direction to form a plurality of second grooves in the first direction, wherein the second grooves in the first direction are alternately arranged with the first grooves in the first direction;

[0009] The sacrificial layer is removed by etching, and a second channel sublayer is prepared between the first doped layer and the second doped layer, wherein the second channel sublayer contacts the first channel sublayer.

[0010] In some embodiments of the present disclosure, the step of preparing the second channel sublayer includes: preparing the second channel sublayer on the first channel sublayer by epitaxial growth; and / or,

[0011] The step of preparing the first channel sublayer includes: preparing the first channel sublayer on the sacrificial layer by epitaxial growth.

[0012] In some embodiments of the present disclosure, the thickness of the first channel sublayer in a direction away from the second channel sublayer is 5 nm to 20 nm; and / or,

[0013] The thickness of the second channel sublayer in a direction away from the first channel sublayer is 5 nm to 20 nm.

[0014] In some embodiments of the present disclosure, the thickness of the sacrificial layer in its height direction is 20 nm to 100 nm.

[0015] In some embodiments of the present disclosure, the method for preparing the semiconductor structure further includes the following step: preparing a bit line structure in the substrate under the first doping layer.

[0016] In some embodiments of the present disclosure, the bit line structure extends along a second direction intersecting the first direction;

[0017] Before preparing the bit line structure, the following steps are also included: etching the second doped layer, the sacrificial layer, the first doped layer and the substrate along the second direction to form a plurality of second direction grooves, the bottoms of the second direction grooves are located in the substrate, and preparing a second direction dielectric layer in the second direction grooves;

[0018] In the step of preparing the bit line structure, the bit line structure is prepared between adjacent second-direction dielectric layers.

[0019] In some embodiments of the present disclosure, the step of forming a plurality of second-direction grooves includes:

[0020] The second doping layer, the sacrificial layer, the first doping layer and the substrate are etched multiple times along the second direction to form a plurality of second direction grooves arranged at intervals.

[0021] In some embodiments of the present disclosure, the step of preparing a second-direction dielectric layer in the second-direction groove is performed before the step of forming a plurality of first-direction first grooves;

[0022] The step of preparing the bit line structure is performed after forming a plurality of first trenches in the first direction and forming a plurality of second trenches in the first direction.

[0023] In some embodiments of the present disclosure, the first channel sublayer and the second channel sublayer are combined as a channel layer, and the method for preparing the semiconductor structure further includes the following steps: preparing a gate dielectric layer surrounding the channel layer, and preparing a word line conductive layer on a side of the gate dielectric layer away from the channel layer.

[0024] In some embodiments of the present disclosure, after preparing the first channel sublayer, the following steps are further included: preparing a first sidewall protection layer on a surface of the first channel sublayer on one side close to the first groove in the first direction;

[0025] After preparing the second channel sublayer, the following steps are also included: preparing a second sidewall protection layer on a surface of the second channel sublayer on one side close to the second groove in the first direction;

[0026] Before preparing the gate dielectric layer and the word line conductive layer surrounding the channel layer, the method further includes the following steps: removing a portion of the first sidewall protection layer and a portion of the second sidewall protection layer to expose the channel layer.

[0027] In some embodiments of the present disclosure, after preparing the second channel sublayer, the following steps are further included: preparing an isolation layer in the first trench in the first direction and in the second trench in the first direction;

[0028] The gate dielectric layer and the word line conductive layer are prepared between the isolation layer and the channel layer.

[0029] In some embodiments of the present disclosure, the material of the sacrificial layer includes a silicon-germanium alloy, and the material of the first channel sublayer and the material of the second channel sublayer both include silicon.

[0030] Furthermore, the present disclosure also provides a semiconductor structure, comprising: a substrate and a plurality of active pillars disposed on the substrate, the active pillars comprising a first source-drain layer, a channel layer and a second source-drain layer stacked in sequence on the substrate, the channel layer being disposed between the first source-drain layer and the second source-drain layer;

[0031] The semiconductor structure further comprises a plurality of first trenches in the first direction and a plurality of second trenches in the first direction, wherein the first trenches in the first direction and the second trenches in the first direction both extend along the first direction, and the first trenches in the first direction and the second trenches in the first direction are alternately arranged, and each of the active pillars is located between adjacent first trenches in the first direction and adjacent second trenches in the first direction;

[0032] The channel layer includes a first channel sublayer and a second channel sublayer in contact with each other. The first channel sublayer is located on a side of the second channel sublayer close to the first groove in the first direction. The second channel sublayer is located on a side of the first channel sublayer close to the second groove in the first direction.

[0033] Furthermore, the present disclosure also provides a memory, which includes a semiconductor structure prepared by the method for preparing a semiconductor structure described in any of the above embodiments, or includes a semiconductor structure as described in any of the above embodiments.

[0034] Furthermore, the present disclosure also provides an electronic device, which includes the memory as described in any of the above embodiments.

[0035] In the preparation method of the semiconductor structure disclosed in the present invention, a first channel sublayer is prepared after etching a first groove in a first direction, and a second channel sublayer in contact with the first channel sublayer is prepared after etching a second groove in the first direction. By etching in steps and preparing in batches, it is possible to further prepare the second channel sublayer on the basis of the first channel sublayer. Compared with a single first channel sublayer, further providing a second channel sublayer can significantly increase the overall thickness of the channel layer, which can make it more difficult for the channel layer as a whole to be over-etched. And the first channel sublayer and the second channel sublayer prepared in batches make the channel layer as a whole more symmetrical. Therefore, the preparation method disclosed in the present invention can effectively improve the performance of the channel layer.

[0036] In addition, the grooves are etched twice in the first direction, which makes the grooves formed each time have a larger interval, thereby reducing the demand for equipment resolution in the preparation process. Taking the above factors into consideration, the preparation method disclosed in the present invention can solve the problems of pattern layer accuracy and channel layer quality at the same time, thus effectively improving the preparation yield of high-density small-size devices.

[0037] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, drawings of other embodiments can be obtained based on these drawings without creative work.

[0039] Figure 1 A schematic diagram of the steps of a method for preparing a semiconductor structure disclosed in the present invention;

[0040] Figure 2A is a schematic structural diagram of a substrate and a first doping layer, a sacrificial layer and a second doping layer arranged on the substrate, Figure 2B for Figure 2A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 2C for Figure 2A A schematic diagram of the cross-sectional structure along BB' in the structure shown;

[0041] Figure 3A For Figure 2A A schematic diagram of a structure in which a first groove in a second direction is formed on the basis of the structure shown in FIG. Figure 3B for Figure 3A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 3C for Figure 3A A schematic diagram of the cross-sectional structure along BB' in the structure shown;

[0042] Figure 4A For Figure 3A A schematic diagram of the structure of preparing the first dielectric layer based on the structure shown in FIG. Figure 4B for Figure 4A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 4C for Figure 4A A schematic diagram of the cross-sectional structure along BB' in the structure shown;

[0043] Figure 5A For Figure 4A A schematic diagram of a structure for preparing a second groove in a second direction based on the structure shown in FIG. Figure 5B for Figure 5A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 5C for Figure 5A A schematic diagram of the cross-sectional structure along BB' in the structure shown;

[0044] Fig. 6A For Figure 5A A schematic diagram of the structure of preparing the second dielectric layer based on the structure shown in FIG. Figure 6B for Fig. 6A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 6C for Fig. 6A A schematic diagram of the cross-sectional structure along BB' in the structure shown;

[0045] Fig. 7A For Fig. 6A A schematic diagram of a structure in which a first groove in a first direction is formed on the basis of the structure shown in FIG. Figure 7B for Fig. 7A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 7C for Fig. 7AA schematic diagram of the cross-sectional structure along BB' in the structure shown;

[0046] Fig. 8A For Fig. 7A Schematic diagram of the structure after etching away part of the sacrificial layer based on the structure shown. Figure 8B for Fig. 8A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 8C for Fig. 8A A schematic diagram of the cross-sectional structure along BB' in the structure shown;

[0047] Fig.9A For Fig. 8A A schematic diagram of the structure of preparing the first channel sublayer based on the structure shown in FIG. Fig. 9B for Fig.9A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Fig. 9C for Fig.9A A schematic diagram of the cross-sectional structure along BB' in the structure shown;

[0048] Fig. 10A For Fig.9A A schematic diagram of a structure for preparing a first sidewall protection layer based on the structure shown in FIG. Fig. 10B for Fig. 10A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Fig. 10C for Fig. 10A A schematic diagram of the cross-sectional structure along BB' in the structure shown;

[0049] Fig.11A For Fig. 10A A schematic diagram of a structure in which a second groove in the first direction is formed on the basis of the structure shown in FIG. Fig. 11B for Fig.11A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Fig. 11C for Fig.11A A schematic diagram of the cross-sectional structure along BB' in the structure shown;

[0050] Fig. 12A For Fig.11A A schematic diagram of a structure for preparing a second channel sublayer based on the structure shown in FIG. Fig. 12B for Fig. 12A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Fig. 12C for Fig. 12A A schematic diagram of the cross-sectional structure along BB' in the structure shown;

[0051] Fig.13A For Fig. 12A A schematic diagram of the structure of preparing a second sidewall protection layer based on the structure shown in FIG. Fig. 13B for Fig.13A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Fig. 13C for Fig.13A A schematic diagram of the cross-sectional structure along BB' in the structure shown;

[0052] Fig.14A For Fig.13A A schematic diagram of a bit line structure is prepared based on the structure shown in FIG. Fig. 14B for Fig.14A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Fig. 14C for Fig.14A A schematic diagram of the cross-sectional structure along BB' in the structure shown;

[0053] Fig.15A For Fig.14A A schematic diagram of a structure in which a portion of the first sidewall protection layer and a portion of the second sidewall protection layer are etched based on the structure shown in FIG. Fig. 15B for Fig.15A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Fig. 15C for Fig.15A A schematic diagram of the cross-sectional structure along BB' in the structure shown;

[0054] Fig.16A For Fig.15A A schematic diagram of a word line structure prepared based on the structure shown in FIG. Fig. 16B for Fig.16A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Fig. 16C for Fig.16A A schematic diagram of the cross-sectional structure along BB' in the structure shown;

[0055] The reference numerals and their meanings are as follows:

[0056] 10. substrate; 11. first doped layer; 12. sacrificial layer; 13. second doped layer; 14. hard mask layer; 15. filling layer; 16. isolation layer; 17. top protective layer; 101. first groove in first direction; 102. second groove in first direction; 110. first sidewall protective layer; 120. second sidewall protective layer; 201. first groove in second direction; 202. second groove in second direction; 210. first dielectric layer; 220. second dielectric layer; 310. channel layer; 311. first channel sublayer; 312. second channel sublayer; 320. first source and drain layer; 330. second source and drain layer; 410. bit line structure; 420. word line structure. DETAILED DESCRIPTION

[0057] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0059] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0060] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0061] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0062] The disclosed embodiments are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the present disclosure. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing, and the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the present disclosure.

[0063] Figure 1 Schematic diagram of the steps of a method for preparing a semiconductor structure disclosed in the present invention. Figure 1 As shown, the preparation method includes steps S1 to S6, which are specifically as follows.

[0064] Step S1 : sequentially preparing a first doping layer 11 , a sacrificial layer 12 , and a second doping layer 13 on a substrate 10 .

[0065] Figure 2A is a schematic structural diagram of a substrate 10 and a first doping layer 11, a sacrificial layer 12 and a second doping layer 13 disposed on the substrate 10, Figure 2B for Figure 2A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 2C for Figure 2A Schematic diagram of the cross-sectional structure along BB' in the structure shown.

[0066] like Figure 2A The structure shown has a first direction and a second direction intersecting each other, the first direction being Figure 2A The x direction is marked in the figure, and the second direction is Figure 2A The first direction and the second direction may be obliquely intersecting or perpendicularly intersecting. In this embodiment, the x direction and the y direction are perpendicular to each other. In addition, Figure 2A The structure shown in also has a third direction, which is perpendicular to the plane defined by the first direction and the second direction, and the third direction is Figure 2A The z direction is marked in . Figure 2A to Figure 2CAs shown, the first doped layer 11, the sacrificial layer 12 and the second doped layer 13 are sequentially stacked in the third direction on the substrate 10. In addition, the stacking direction of the first doped layer 11, the sacrificial layer 12 and the second doped layer 13 is the height direction, and the height direction is the third direction.

[0067] In some examples of this embodiment, the material of the substrate 10 may be a semiconductor material. For example, the material of the substrate 10 may be selected from one or more of silicon, gallium arsenide, silicon carbide and germanium. In this embodiment, the material of the substrate 10 may be silicon, and the silicon may be an intrinsic silicon material or a doped silicon material. Further, the material of the substrate 10 may be single crystal silicon, for example, a single crystal silicon wafer may be selected as the substrate 10. The material of the substrate 10 may be used to prepare the bit line structure 410 in the semiconductor structure. Further, the substrate 10 may also have a logic circuit, or the material of the substrate 10 may also be used to prepare a logic circuit.

[0068] In some examples of this embodiment, the material of the first doping layer 11 may be a doped semiconductor material, and the first doping layer 11 may have a first doping type. Further, the material of the first doping layer 11 may be selected from one or more of silicon, gallium arsenide, silicon carbide, and germanium. In this embodiment, the material of the first doping layer 11 may be silicon.

[0069] In some examples of this embodiment, the first doping layer 11 may be prepared by epitaxial growth.

[0070] In some examples of this embodiment, the thickness of the first doping layer 11 in its height direction may be 10 nm to 100 nm. For example, the thickness of the first doping layer 11 may be 10 nm, 30 nm, 50 nm, 80 nm, 100 nm, or the thickness of the first doping layer 11 may be in the range between any two of the above thicknesses.

[0071] In some examples of this embodiment, the sacrificial layer 12 may be prepared by epitaxial growth.

[0072] In some examples of this embodiment, the thickness of the sacrificial layer 12 in its height direction may be 20nm to 100nm. For example, the thickness of the sacrificial layer 12 may be 20nm, 40nm, 60nm, 80nm, 100nm, or the thickness of the sacrificial layer 12 may also be in the range between any two of the above thicknesses. In this embodiment, the height direction of the sacrificial layer 12 is the third direction. It can be understood that in this embodiment, the sacrificial layer 12 is used to pre-occupy the position of the channel layer 310. Therefore, the thickness of the sacrificial layer 12 determines the length (height) of the channel layer 310 prepared subsequently. By setting the thickness of the sacrificial layer 12 to 20nm to 100nm, it is convenient to prepare a channel layer 310 with better performance.

[0073] In some examples of this embodiment, the material of the sacrificial layer 12 is different from the material of the first doping layer 11 and the material of the second doping layer 13, so that the sacrificial layer 12 has different etching rates from the first doping layer 11 and the second doping layer 13. Furthermore, the sacrificial layer 12 can also be used as a substrate for the epitaxial growth of the channel layer 310, so the material of the sacrificial layer 12 can be selected accordingly according to the material of the channel layer 310 actually grown. In this embodiment, the material of the sacrificial layer 12 may include a silicon-germanium alloy. The silicon-germanium alloy has a high etching rate and can serve as a substrate for the epitaxial growth of silicon materials. It can be understood that the material of the sacrificial layer 12 can also be other suitable materials.

[0074] In some examples of this embodiment, the second doping layer 13 may be prepared by epitaxial growth.

[0075] In some examples of this embodiment, the material of the second doping layer 13 may be a doped semiconductor material, and the doping type of the second doping layer 13 may be the same as the doping type of the first doping layer 11. Further, the material of the second doping layer 13 may be selected from one or more of silicon, gallium arsenide, silicon carbide and germanium. In this embodiment, the material of the second doping layer 13 may be silicon.

[0076] In some examples of this embodiment, the thickness of the second doping layer 13 may be 10 nm to 100 nm. For example, the thickness of the second doping layer 13 may be 10 nm, 30 nm, 50 nm, 80 nm, 100 nm, or the thickness of the second doping layer 13 may be in a range between any two of the above thicknesses. Further, the thickness of the second doping layer 13 may be the same as the thickness of the first doping layer 11.

[0077] In some examples of this embodiment, the following step is further included: etching the second doping layer 13, the sacrificial layer 12, the first doping layer 11 and the substrate 10 along the second direction to form a plurality of second direction grooves. Further, the second doping layer 13, the sacrificial layer 12, the first doping layer 11 and the substrate 10 may be etched multiple times along the second direction to form a plurality of second direction grooves spaced apart. The etching performed later may be performed between the second direction grooves formed by the etching performed earlier.

[0078] In some examples of this embodiment, the following step is further included: etching the second doping layer 13, the sacrificial layer 12 and the first doping layer 11 twice along the second direction respectively, so as to respectively etch a plurality of second direction first grooves 201 and a plurality of second direction second grooves 202, wherein the second direction first grooves 201 and the second direction second grooves 202 are alternately arranged. The first direction grooves include the second direction first grooves 201 and the second direction second grooves 202.

[0079] Figure 3A For Figure 2A A schematic diagram of a structure in which a first groove 201 in the second direction is formed on the basis of the structure shown in FIG. Figure 3B for Figure 3A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 3C for Figure 3A The schematic diagram of the cross-sectional structure along BB' in the structure shown. Figure 3A to Figure 3C As shown, the second direction first trench 201 extends along the second direction.

[0080] In some instances of this embodiment, before the first etching, a pattern layer can be prepared on the second doping layer 13, the opening of the pattern layer defines the position of the first groove 201 in the second direction, and the second doping layer 13, the sacrificial layer 12 and the first doping layer 11 are etched based on the opening of the pattern layer to form the first groove 201 in the second direction.

[0081] In some examples of this embodiment, the material of the pattern layer may be photoresist.

[0082] In some examples of this embodiment, the first etching method may be dry etching.

[0083] In some examples of this embodiment, during the first etching process, the process further includes: etching and removing a portion of the substrate 10 so that the bottom of the second-direction first groove 201 is located in the substrate 10. It can be understood that there are multiple second-direction first grooves 201, and the multiple second-direction first grooves 201 can be arranged side by side at intervals. Further, the multiple second-direction first grooves 201 can be arranged in sequence at intervals in the first direction.

[0084] In some examples of this embodiment, a step of preparing a first dielectric layer 210 in the first trench 201 in the second direction is also included. Figure 4A For Figure 3A A schematic diagram of the structure of preparing the first dielectric layer 210 based on the structure shown in FIG. Figure 4B for Figure 4A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 4C for Figure 4A The schematic diagram of the cross-sectional structure along BB' in the structure shown. Figure 4A to Figure 4C As shown, the first dielectric layer 210 is filled in the first trench 201 in the second direction.

[0085] In some examples of this embodiment, the material of the first dielectric layer 210 can be selected from insulating materials, for example, the material of the first dielectric layer 210 can be silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the first dielectric layer 210 can be silicon oxide. The first dielectric layer 210 can shield the groove wall of the first groove 201 in the second direction. In addition, by providing the first dielectric layer 210, it can also support the pattern layer prepared subsequently.

[0086] Figure 5A For Figure 4A A schematic diagram of a structure for preparing a second groove 202 in the second direction based on the structure shown in FIG. Figure 5B for Figure 5A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 5C for Figure 5A Schematic diagram of the cross-sectional structure along BB' in the structure shown.

[0087] In some instances of this embodiment, before performing the second etching, a pattern layer can be prepared on the second doping layer 13, the opening of the pattern layer defines the position of the second groove 202 in the second direction, and the second doping layer 13, the sacrificial layer 12 and the first doping layer 11 are etched based on the opening of the pattern layer to form the second groove 202 in the second direction.

[0088] In some examples of this embodiment, the material of the pattern layer may be photoresist.

[0089] In some examples of this embodiment, the second etching method may be dry etching.

[0090] In some examples of this embodiment, the second etching process further includes: etching and removing a portion of the substrate 10 so that the bottom of the second trench 202 in the second direction is located in the substrate 10. Figure 5A to Figure 5C As shown, there are multiple second-direction second grooves 202, and the multiple second-direction second grooves 202 can be arranged side by side and spaced apart. Further, the multiple second-direction second grooves 202 can be arranged in sequence and spaced apart in the first direction. The second-direction second grooves 202 and the second-direction first grooves 201 are arranged alternately and spaced apart.

[0091] In some examples of this embodiment, the interval between adjacent second-direction first grooves 201 and second-direction second grooves 202 remains constant.

[0092] Compared with the method of etching a groove along the second direction once, the method of performing etching twice separately allows a larger interval between the grooves formed in each etching, so the required pattern size is also larger, which can alleviate the problems caused by the diffraction effect, help reduce the demand for equipment resolution in the preparation process, and also help to prepare devices with smaller feature sizes, further improving device density.

[0093] In some examples of this embodiment, a step of preparing a second dielectric layer 220 in the second groove 202 in the second direction is also included. Fig. 6A For Figure 5A A schematic diagram of the structure of preparing the second dielectric layer 220 based on the structure shown in FIG. Figure 6B for Fig. 6A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 6C for Fig. 6A The schematic diagram of the cross-sectional structure along BB' in the structure shown. Figure 6A to Figure 6C As shown, the second dielectric layer 220 is filled in the second trench 202 in the second direction.

[0094] In some examples of this embodiment, the material of the second dielectric layer 220 can be selected from insulating materials, for example, the material of the second dielectric layer 220 can be silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the second dielectric layer 220 can be silicon oxide. The second dielectric layer 220 can shield the groove wall of the second groove 202 in the second direction. In addition, by providing the second dielectric layer 220, it can also support the pattern layer prepared subsequently.

[0095] Step S2 , etching the second doping layer 13 , the sacrificial layer 12 and the first doping layer 11 along the first direction to form a plurality of first trenches 101 in the first direction.

[0096] In some examples of this embodiment, before forming a plurality of first trenches 101 in the first direction, a step of preparing a hard mask layer 14 on the second doping layer 13 is also included. Fig. 6A For Fig. 6A A schematic diagram of a structure for preparing a hard mask layer 14 based on the structure shown in FIG. Figure 6B for Fig. 6A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 6C for Fig. 6A Schematic diagram of the cross-sectional structure along BB' in the structure shown.

[0097] Reference Figure 6A to Figure 6CAs shown, the hard mask layer 14 is stacked on the second doped layer 13. In some examples of this embodiment, the hard mask layer 14 covers the second doped layer 13. The hard mask layer 14 is used to form a specific pattern and maintain a stable shape during the etching process. In addition, the hard mask layer 14 can also protect the second doped layer 13, the sacrificial layer 12 and the first doped layer 11 located below, avoiding unnecessary etching in the subsequent etching process.

[0098] In some examples of this embodiment, the material of the hard mask layer 14 may be an inorganic material, such as silicon nitride or polysilicon. In this embodiment, the material of the hard mask layer 14 is polysilicon.

[0099] Fig. 7A For Fig. 6A A schematic diagram of a structure in which a first groove 101 in a first direction is formed on the basis of the structure shown in FIG. Figure 7B for Fig. 7A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 7C for Fig. 7A The schematic diagram of the cross-sectional structure along BB' in the structure shown. Figure 7A to Figure 7C As shown, the first direction first trench 101 extends along the first direction.

[0100] In some examples of this embodiment, before forming the first groove, a pattern layer may be prepared on the second doping layer 13, the opening of the pattern layer defines the position of the first groove 101 in the first direction, and the second doping layer 13, the sacrificial layer 12 and the first doping layer 11 are etched based on the opening of the pattern layer to form the first groove 101 in the first direction. It can be understood that in this step, the step of etching the hard mask layer 14 is also included.

[0101] In some examples of this embodiment, in the step of forming the first trench 101 in the first direction, the etching method may be dry etching.

[0102] In some examples of this embodiment, in the step of forming the first trench 101 in the first direction, the etching is controlled to stop when the etching reaches the substrate 10 , so that the bottom of the first trench 101 in the first direction is flush with the bottom of the first doping layer 11 .

[0103] In some examples of this embodiment, the pre-prepared first dielectric layer 210 and the second dielectric layer 220 are also etched together.

[0104] Understandably, Figure 7A to Figure 7COnly a partial area of ​​the semiconductor structure is shown in the figure, so only one first-direction first trench 101 is shown in the figure, but for the entire semiconductor structure, multiple first-direction first trenches 101 may be provided therein. Multiple first-direction first trenches 101 may be arranged side by side and spaced apart. Further, multiple first-direction first trenches 101 may be arranged in sequence and spaced apart in the second direction.

[0105] Step S3 , etching and removing the portion of the sacrificial layer 12 exposed in the first trench, and preparing a first channel sublayer 311 between the first doping layer 11 and the second doping layer 13 .

[0106] Fig. 8A For Fig. 7A A schematic diagram of the structure after etching away part of the sacrificial layer 12 based on the structure shown in FIG. Figure 8B for Fig. 8A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Figure 8C for Fig. 8A Schematic diagram of the cross-sectional structure along BB' in the structure shown.

[0107] Reference Figure 8A to Figure 8C As shown, since the hard mask layer 14 shields the second doped layer 13, the groove wall of the first groove 101 in the first direction is mainly etched in this step. At this time, an etchant that can selectively etch the sacrificial layer 12 can be used for etching to preferentially etch the sacrificial layer 12. By controlling the etching time, part of the sacrificial layer 12 close to the first groove 101 in the first direction can be removed, so that there is a vacancy between the first doped layer 11 and the second doped layer 13 after the sacrificial layer 12 is removed. In this step, part of the sacrificial layer 12 should be retained to support the second doped layer 13 and keep the overall structure stable. In addition, the position occupied by the retained part of the sacrificial layer 12 can also be used as the position for the subsequent preparation of the second channel sublayer 312.

[0108] Fig.9A For Fig. 8A A schematic diagram of a structure for preparing a first channel sublayer 311 based on the structure shown in FIG. Fig. 9B for Fig.9A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Fig. 9C for Fig.9A Schematic diagram of the cross-sectional structure along BB' in the structure shown.

[0109] Reference Figures 9A to 9C As shown, the first channel sublayer 311 is prepared between the first doping layer 11 and the second doping layer 13, and the first channel sublayer 311 contacts the first doping layer 11 and the second doping layer 13. It can be understood that the first channel sublayer 311 can be used as a channel between the first doping layer 11 and the second doping layer 13.

[0110] In some examples of this embodiment, the step of preparing the first channel sublayer 311 may include: preparing the first channel sublayer 311 by epitaxial growth on the sacrificial layer 12. Further, the first channel sublayer 311 may be prepared by chemical vapor deposition. In this embodiment, the first channel sublayer 311 may be prepared on the sacrificial layer 12 by low pressure chemical vapor deposition.

[0111] In some examples of this embodiment, the material of the first channel sublayer 311 may include a semiconductor material. In this embodiment, the material of the first channel sublayer 311 includes silicon. The first channel sublayer 311 may have a different doping type from the first doping layer 11 .

[0112] It can be understood that there is a direct relationship between the height of the first channel sublayer 311 (i.e., the channel length) and the thickness of the sacrificial layer 12, so by setting a suitable thickness when preparing the sacrificial layer 12, a first channel sublayer 311 of corresponding height can be obtained. The height of the first channel sublayer 311 refers to the distance between the top and the bottom of the first channel sublayer 311 in the third direction.

[0113] In some examples of this embodiment, the thickness of the first channel sublayer 311 in the direction away from the sacrificial layer 12 is 5 nm to 20 nm. Figure 1 and Fig.9A As shown, the direction of the first channel sublayer 311 away from the sacrificial layer 12 is along the second direction. It can be understood that the sacrificial layer 12 is removed in the subsequent preparation process, and the second channel sublayer 312 is prepared in the area where the sacrificial layer 12 is located, so the direction of the first channel sublayer 311 away from the sacrificial layer 12 is also away from the second channel sublayer 312. The thickness of the first channel sublayer 311 refers to the distance between the side surface of the first channel sublayer 311 close to the sacrificial layer 12 and the side surface away from the sacrificial layer 12.

[0114] In some examples of this embodiment, the thickness of the first channel sublayer 311 in the direction away from the sacrificial layer 12 may be 5 nm, 7 nm, 10 nm, 12 nm, 15 nm or 20 nm. Further, the thickness of the first channel sublayer 311 in the direction away from the sacrificial layer 12 may also be in a range between any two of the above thicknesses.

[0115] Although the first channel sublayer 311 can be used as a channel, the thickness of the first channel sublayer 311 grown on the sacrificial layer 12 in the direction away from the sacrificial layer 12 is limited, which makes it easy to be damaged in subsequent processes. In addition, there is a large difference in the morphology between the surface of the prepared first channel sublayer 311 close to the first groove 101 in the first direction and the surface away from the first groove 101 in the first direction. Both of these factors will cause the performance of the channel layer 310 to deteriorate, thereby affecting the yield of the device. The preparation method disclosed in the present invention improves the above problems by etching the second groove 102 in the first direction and preparing the second channel sublayer 312.

[0116] In some examples of this embodiment, after preparing the first channel sublayer 311 , a step of preparing a first sidewall protection layer 110 in the first trench 101 in the first direction may be further included. Fig. 10A For Fig.9A A schematic diagram of a structure for preparing a first sidewall protection layer 110 based on the structure shown in FIG. Fig. 10B for Fig. 10A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Fig. 10C for Fig. 10A Schematic diagram of the cross-sectional structure along BB' in the structure shown.

[0117] Reference Figures 10A to 10C As shown, the first sidewall protection layer 110 covers the groove wall of the first groove 101 in the first direction. Further, the first sidewall protection layer 110 also covers the first channel sublayer 311, which can play a role in protecting the first channel sublayer 311.

[0118] In some examples of this embodiment, the material of the first sidewall protection layer 110 may be selected from insulating materials, for example, the material of the first sidewall protection layer 110 may be silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the first sidewall protection layer 110 may be silicon oxide.

[0119] In some examples of this embodiment, the first sidewall protection layer 110 can be prepared by atomic layer deposition. The material of the first sidewall protection layer 110 will also adhere to the bottom of the first trench 101 in the first direction and above the second doping layer 13 during the deposition process, but this can be removed by vertical etching.

[0120] In some examples of this embodiment, after preparing the first sidewall protection layer 110 , a step of preparing a filling layer 15 in the first trench 101 in the first direction is further included. The filling layer 15 is used to fill the first trench 101 in the first direction, so as to facilitate the subsequent preparation of a pattern layer on the second doping layer 13 .

[0121] In some examples of this embodiment, the material of the filling layer 15 may be selected from insulating materials, for example, the material of the filling layer 15 may be silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the filling layer 15 may be silicon nitride.

[0122] Step S4 , etching the second doping layer 13 , the sacrificial layer 12 and the first doping layer 11 along the first direction to form a plurality of second trenches 102 in the first direction.

[0123] Fig.11A For Fig. 10A A schematic diagram of a structure in which a second groove 102 in the first direction is formed on the basis of the structure shown in FIG. Fig. 11B for Fig.11A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Fig. 11C for Fig.11A The schematic diagram of the cross-sectional structure along BB' in the structure shown. Figures 11A to 11C As shown, there may be multiple first-direction second grooves 102. The first-direction second grooves 102 and the first-direction first grooves 101 may be arranged alternately and spaced apart.

[0124] In some examples of this embodiment, the distance between adjacent first-direction first trenches 101 and first-direction second trenches 102 remains constant.

[0125] In some instances of this embodiment, before forming the second groove 102 in the first direction, a pattern layer can be prepared on the second doping layer 13, the opening of the pattern layer defines the position of the second groove 102 in the first direction, and the second doping layer 13, the sacrificial layer 12 and the first doping layer 11 are etched based on the opening of the pattern layer to form the second groove 102 in the first direction.

[0126] In some examples of this embodiment, in the step of forming the second trench 102 in the first direction, the etching is controlled to stop when the etching reaches the substrate 10 , so that the bottom of the second trench 102 in the first direction is flush with the bottom of the first doping layer 11 .

[0127] Reference Figures 11A to 11C As shown, part of the sacrificial layer 12 is still retained in step S3 , and the part of the sacrificial layer 12 is etched through when forming the second groove 102 in the first direction, so the sacrificial layer 12 is also exposed in the second groove 102 in the first direction.

[0128] Step S5 , etching and removing the sacrificial layer 12 , and preparing a second channel sublayer 312 between the first doping layer 11 and the second doping layer 13 .

[0129] Fig. 12A For Fig.11A A schematic diagram of a structure for preparing a second channel sublayer 312 based on the structure shown in FIG. Fig. 12B for Fig. 12A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Fig. 12C for Fig. 12A Schematic diagram of the cross-sectional structure along BB' in the structure shown.

[0130] Reference Figures 12A to 12C As shown, the sacrificial layer 12 between the first doped layer 11 and the second doped layer 13 is completely removed. After the sacrificial layer 12 is removed, there is a vacancy between the first doped layer 11 and the second doped layer 13 that was originally occupied by the sacrificial layer 12. At this time, the second channel sublayer 312 can be prepared in the vacancy. The second channel sublayer 312 contacts the first channel sublayer 311, so that the second channel sublayer 312 and the first channel sublayer 311 together constitute the channel layer 310 in the semiconductor structure. Unless otherwise specified, the "channel layer 310" in this embodiment includes the first channel sublayer 311 and the second channel sublayer 312.

[0131] In some examples of this embodiment, the step of preparing the second channel sublayer 312 includes: preparing the second channel sublayer 312 by epitaxial growth on the first channel sublayer 311. Further, the second channel sublayer 312 can be prepared by chemical vapor deposition. In this embodiment, the second channel sublayer 312 can be prepared on the first channel sublayer 311 by low-pressure chemical vapor deposition. It can be understood that by epitaxially preparing the second channel sublayer 312 on the first channel sublayer 311, the second channel sublayer 312 has the same height as the first channel sublayer 311, and the second channel sublayer 312 can also directly contact the first doping layer 11 and the second doping layer 13.

[0132] In some examples of this embodiment, the material of the second channel sublayer 312 may include a semiconductor material. In this embodiment, the material of the second channel sublayer 312 includes silicon.

[0133] In some examples of this embodiment, the thickness of the second channel sublayer 312 in the direction away from the first channel sublayer 311 is 5 nm to 20 nm. Figure 1 and Fig. 12A As shown, the second channel sublayer 312 is away from the first channel sublayer 311 along the second direction. The thickness of the second channel sublayer 312 refers to the distance between the side surface of the second channel sublayer 312 close to the first channel sublayer 311 and the side surface away from the first channel sublayer 311.

[0134] In some examples of this embodiment, the thickness of the first channel sublayer 311 in the direction away from the sacrificial layer 12 may be 5 nm, 7 nm, 10 nm, 12 nm, 15 nm or 20 nm. Further, the thickness of the first channel sublayer 311 in the direction away from the sacrificial layer 12 may also be in a range between any two of the above thicknesses.

[0135] It can be understood that through steps S4 to S5, the second channel sublayer 312 can be further prepared on the basis of the first channel sublayer 311. Compared with the single first channel sublayer 311, further providing the second channel sublayer 312 can significantly increase the overall thickness of the channel layer 310, which can make it more difficult for the channel layer 310 to be over-etched as a whole. And the first channel sublayer 311 and the second channel sublayer 312 prepared in batches make the channel layer 310 more symmetrical as a whole. Therefore, the preparation method disclosed in the present invention can effectively improve the performance of the channel layer 310.

[0136] In addition, the grooves are etched twice in the first direction, which makes the grooves formed each time have a larger interval, thus reducing the demand for equipment resolution in the preparation process. Taking the above factors into consideration, the preparation method disclosed in the present invention can solve the problems of pattern layer accuracy and channel layer 310 quality at the same time, thus effectively improving the preparation yield of high-density and small-size devices.

[0137] In some examples of this embodiment, after preparing the second channel sublayer 312 , a step of preparing a second sidewall protection layer 120 in the second trench 102 in the first direction is further included. Fig.13A For Fig. 12A A schematic diagram of a structure for preparing a second sidewall protection layer 120 based on the structure shown in FIG. Fig. 13B for Fig.13A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Fig. 13C for Fig.13A Schematic diagram of the cross-sectional structure along BB' in the structure shown.

[0138] Reference Figures 13A to 13C As shown, the second sidewall protection layer 120 covers the groove wall of the second groove 102 in the first direction. Further, the second sidewall protection layer 120 also covers the second channel sublayer 312, which can play a role in protecting the second channel sublayer 312.

[0139] In some examples of this embodiment, the material of the second sidewall protection layer 120 may be selected from insulating materials, for example, the material of the second sidewall protection layer 120 may be silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the material of the second sidewall protection layer 120 may be silicon oxide.

[0140] In some examples of this embodiment, the second sidewall protection layer 120 may be prepared by an atomic layer deposition method.

[0141] Reference Figures 13A to 13CAs shown, after preparing the second sidewall protection layer 120, a step of removing the filling layer 15 located in the first trench 101 in the first direction may be further included. It can be understood that when removing the filling layer 15, the impact on the first sidewall protection layer 110 and the second sidewall protection layer 120 should be minimized as much as possible, so the material of the filling layer 15 can be different from the material of the first sidewall protection layer 110 and the second sidewall protection layer 120.

[0142] Reference Figures 13A to 13C As shown, after steps S1 to S5, the sacrificial layer 12 between the first doped layer 11 and the second doped layer 13 is removed, and the first channel sublayer 311 and the second channel sublayer 312 are prepared in the region where the sacrificial layer 12 is located, and the first channel sublayer 311 and the second channel sublayer 312 are used as a channel layer 310 as a whole. A plurality of grooves along the first direction and a plurality of grooves along the second direction divide the first doped layer 11 into a plurality of first source and drain layers 320, and divide the second doped layer 13 into a plurality of second source and drain layers 330. The first source and drain layer 320, the second source and drain layer 330, and the channel layer 310 located therebetween serve as active pillars, which can serve as the main functional region of the transistor.

[0143] In some examples of this embodiment, the method for preparing the semiconductor structure may further include the following steps: preparing a word line structure 420 and a bit line structure 410. The extension directions of the bit line structure 410 and the word line structure 420 may be set according to actual needs. In this embodiment, in order to facilitate preparation on an existing structure, the word line structure 420 may extend along a first direction, and the bit line structure 410 may extend along a second direction.

[0144] Fig.14A For Fig.13A A schematic diagram of a structure of a bit line structure 410 is prepared based on the structure shown in FIG. Fig. 14B for Fig.14A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Fig. 14C for Fig.14A Schematic diagram of the cross-sectional structure along BB' in the structure shown.

[0145] In some examples of this embodiment, the step of preparing the bit line structure 410 may include: preparing the bit line structure 410 in the substrate 10 under the first doping layer 11 .

[0146] In some examples of this embodiment, in the step of preparing the bit line structure 410 , the bit line structure 410 is prepared between adjacent second-direction dielectric layers.

[0147] Further, the bit line structure 410 can be prepared based on the material of the substrate 10. For example, a portion of the substrate 10 located between the second direction dielectric layers is metallized to convert the material of the substrate 10 into a conductive metal compound to serve as the bit line structure 410. In this embodiment, the material of the bit line structure 410 can include one or more of cobalt silicide and nickel silicide. It can be understood that the material of the substrate 10 contains silicon, and a conductive metal silicide can be formed by metallizing the substrate 10.

[0148] In another embodiment, when etching the first groove 101 in the first direction and etching the second groove 102 in the first direction, part of the substrate 10 can also be etched away, and when preparing the bit line structure 410, a metal conductive material can be prepared between the substrates 10 and the metal conductive material can be diffused into the substrate 10 to form a conductive bit line structure 410.

[0149] Reference Figures 14A to 14C As shown, the bit line structures 410 are separated by the first dielectric layer 210 and the second dielectric layer 220 so that each bit line structure 410 is independently conductive.

[0150] It can be understood that the first channel sublayer 311 and the second channel sublayer 312 are combined as the channel layer 310. In some examples of this embodiment, preparing the word line structure 420 further includes the following steps: preparing a gate dielectric layer surrounding the channel layer 310, and preparing a word line conductive layer on a side of the gate dielectric layer away from the channel layer 310. It can be understood that the word line structure 420 includes the gate dielectric layer and the word line conductive layer.

[0151] Furthermore, before preparing the gate dielectric layer, the following step is also included: removing a portion of the first sidewall protection layer 110 and the second sidewall protection layer 120 located on both sides of the first channel sublayer 311 and the second channel sublayer 312 to expose the channel layer 310 . Fig.15A For Fig.14A A schematic diagram of a structure in which a portion of the first sidewall protection layer 110 and a portion of the second sidewall protection layer 120 are etched based on the structure shown in FIG. Fig. 15B for Fig.15A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Fig. 15C for Fig.15A Schematic diagram of the cross-sectional structure along BB' in the structure shown.

[0152] Reference Figures 15A to 15CAs shown, the first sidewall protection layer 110 and the second sidewall protection layer 120 located on both sides of the channel layer 310 (including the first channel sublayer 311 and the second channel sublayer 312) are removed to expose the first channel sublayer 311 and the second channel sublayer 312. In this embodiment, the etching progress can be controlled to retain a portion of the first sidewall protection layer 110 and a portion of the second sidewall protection layer 120 located between the first doping layers 11 to prevent the material of the word line conductive layer from being deposited between the first doping layers 11.

[0153] Furthermore, in some examples of this embodiment, the first dielectric layer 210 and the second dielectric layer 220 located between adjacent channel layers 310 are also removed. Similarly, the etching progress can be controlled to retain a portion of the first dielectric layer 210 and a portion of the second dielectric layer 220 located between the first doping layer 11.

[0154] Reference Figures 15A to 15C As shown, in some examples of this embodiment, before etching the first sidewall protection layer 110 and the second sidewall protection layer 120, a step of preparing an isolation layer 16 in the first direction first trench 101 and the first direction second trench 102 is also included. The isolation layer 16 extends along the second direction and is used to separate the structures on both sides of the trench in the first direction to avoid crosstalk between the subsequently prepared word line structures 420.

[0155] Fig.16A For Fig.15A A schematic diagram of a structure of a word line structure 420 is prepared based on the structure shown in FIG. Fig. 16B for Fig.16A The schematic diagram of the cross-sectional structure along AA' in the structure shown, Fig. 16C for Fig.16A Schematic diagram of the cross-sectional structure along BB' in the structure shown.

[0156] Reference Figures 16A to 16C As shown, the word line structure 420 extends along a first direction.

[0157] In some examples of this embodiment, the material of the word line conductive layer in the word line structure 420 may be selected from metal materials. For example, the material of the word line conductive layer may include one or more of copper, tungsten, silver and gold.

[0158] In some examples of this embodiment, the word line conductive layer may be prepared by atomic layer deposition or chemical vapor deposition.

[0159] In some examples of this embodiment, before preparing the word line conductive layer, a step of preparing a gate dielectric layer on the sidewall of the channel layer 310 is also included. The gate dielectric layer can be disposed around the channel layer 310 and is used to insulate and space the word line conductive layer from the channel layer 310.

[0160] In some examples of this embodiment, the material of the gate dielectric layer may be selected from high dielectric constant (high K) materials. For example, the material of the gate dielectric layer may include hafnium oxide.

[0161] In some examples of this embodiment, the gate dielectric layer may be prepared by atomic layer deposition or chemical vapor deposition.

[0162] In some examples of this embodiment, after preparing the word line structure 420, a step of preparing a top protective layer 17 in the first direction first trench 101, the first direction second trench 102, the second direction first trench 201, and the second direction second trench 202 is also included, and the top protective layer 17 insulates and separates adjacent second doping layers 13. In addition, the top protective layer 17 can also protect the word line structure 420.

[0163] It can be understood that through the above steps S1 to S5 and the specific preparation methods therein, a semiconductor structure can be prepared, which contains a plurality of vertical channel transistors arranged in an array.

[0164] Reference Figures 16A to 16C As shown, in this embodiment, the semiconductor structure includes: a substrate 10 and a plurality of active pillars disposed on the substrate 10, the active pillars including a first source-drain layer 320, a channel layer 310 and a second source-drain layer 330 stacked in sequence on the substrate 10, and the channel layer 310 is disposed between the first source-drain layer 320 and the second source-drain layer 330. The semiconductor structure also has a plurality of first-direction first trenches 101 and a plurality of first-direction second trenches 102, the first-direction first trenches 101 and the first-direction second trenches 102 both extend along the first direction, and the first-direction first trenches 101 and the first-direction second trenches 102 are alternately disposed, and each active pillar is located between adjacent first-direction first trenches 101 and first-direction second trenches 102. The channel layer 310 includes a first channel sublayer 311 and a second channel sublayer 312 that are in contact with each other. The first channel sublayer 311 is closer to the first trench 101 in the first direction, and the second channel sublayer 312 is closer to the second trench 102 in the first direction.

[0165] It can be understood that the second channel sublayer 312 and the first channel sublayer 311 are prepared successively. In some examples of this embodiment, the second channel sublayer 312 is prepared on the first channel sublayer 311. Further, the second channel sublayer 312 is epitaxially grown on the first channel sublayer 311.

[0166] In some examples of this embodiment, the semiconductor structure may further include a gate dielectric layer and a word line structure 420, wherein the gate dielectric layer is disposed around the channel layer 310, the word line structure 420 extends along the first direction, and the word line structure 420 is disposed on a side of the gate dielectric layer away from the channel layer 310. The gate dielectric layer is used to insulate and space the word line structure 420 and the channel layer 310.

[0167] In some examples of this embodiment, the semiconductor structure may further include a bit line structure 410. The bit line structure 410 may extend along a second direction intersecting the first direction, and the bit line structure 410 may be disposed below the first source and drain layer 320 and electrically connected to the first source and drain layer 320.

[0168] Furthermore, the present disclosure also provides a memory. The memory may be a dynamic random access memory or a magnetic random access memory. It is understood that when the memory is a dynamic random access memory, the transistor in the semiconductor structure may be electrically connected to the capacitor.

[0169] Furthermore, the present disclosure also provides an electronic device, which includes the above-mentioned memory. The electronic device may be a mobile phone or a computer.

[0170] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.

[0171] It should be understood that, unless otherwise specified herein, the execution of the steps described is not strictly limited in order, and the steps may be executed in other orders. Moreover, at least a portion of the steps described may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0172] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0173] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The steps include: sequentially preparing a first doping layer, a sacrificial layer, and a second doping layer on a substrate; Etching the second doped layer, the sacrificial layer and the first doped layer along a first direction to form a plurality of first grooves in a first direction; Etching and removing the portion of the sacrificial layer exposed in the first groove in the first direction, and preparing a first channel sublayer between the first doped layer and the second doped layer; Etching the second doped layer, the sacrificial layer and the first doped layer along the first direction to form a plurality of second grooves in the first direction, wherein the second grooves in the first direction are alternately arranged with the first grooves in the first direction; The sacrificial layer is removed by etching, and a second channel sublayer is prepared between the first doped layer and the second doped layer, wherein the second channel sublayer contacts the first channel sublayer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of preparing the second channel sublayer comprises: preparing the second channel sublayer on the first channel sublayer by epitaxial growth; and / or, The step of preparing the first channel sublayer includes: preparing the first channel sublayer on the sacrificial layer by epitaxial growth.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The thickness of the first channel sublayer in a direction away from the second channel sublayer is 5 nm to 20 nm; and / or, The second channel sublayer is 5 nm to 20 nm in a direction away from the first channel sublayer.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The thickness of the sacrificial layer in the height direction is 20 nm to 100 nm.

5. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that: The method for preparing the semiconductor structure further comprises the following step: preparing a bit line structure in the substrate under the first doping layer.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: The bit line structure extends along a second direction intersecting the first direction; Before preparing the bit line structure, the following steps are also included: etching the second doped layer, the sacrificial layer, the first doped layer and the substrate along the second direction to form a plurality of second direction grooves, the bottoms of the second direction grooves are located in the substrate, and preparing a second direction dielectric layer in the second direction grooves; In the step of preparing the bit line structure, the bit line structure is prepared between adjacent second-direction dielectric layers.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The step of forming a plurality of second direction grooves comprises: The second doping layer, the sacrificial layer, the first doping layer and the substrate are etched multiple times along the second direction to form a plurality of grooves spaced apart from each other in the second direction.

8. The method for preparing a semiconductor structure according to claim 6, characterized in that: The step of preparing a second-direction dielectric layer in the second-direction groove is performed before the step of forming a plurality of first-direction first grooves; The step of preparing the bit line structure is performed after forming a plurality of first trenches in the first direction and forming a plurality of second trenches in the first direction.

9. The method for preparing a semiconductor structure according to any one of claims 1 to 4 and 6 to 8, characterized in that: The first channel sublayer and the second channel sublayer are combined as a channel layer, and the method for preparing the semiconductor structure further includes the following steps: preparing a gate dielectric layer surrounding the channel layer, and preparing a word line conductive layer on a side of the gate dielectric layer away from the channel layer.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: After preparing the first channel sublayer, the following steps are also included: preparing a first sidewall protection layer on a surface of the first channel sublayer on one side close to the first groove in the first direction; After preparing the second channel sublayer, the following steps are also included: preparing a second sidewall protection layer on a surface of the second channel sublayer on one side close to the second groove in the first direction; Before preparing the gate dielectric layer and the word line conductive layer surrounding the channel layer, the method further includes the following steps: removing a portion of the first sidewall protection layer and a portion of the second sidewall protection layer to expose the channel layer.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that: After preparing the second channel sublayer, the method further includes the following steps: preparing an isolation layer in the first trench in the first direction and in the second trench in the first direction; The gate dielectric layer and the word line conductive layer are prepared between the isolation layer and the channel layer.

12. The method for preparing a semiconductor structure according to any one of claims 1 to 4, 6 to 8 and 10 to 11, characterized in that: The material of the sacrificial layer includes a silicon-germanium alloy, and the material of the first channel sublayer and the material of the second channel sublayer both include silicon.

13. A semiconductor structure, characterized in that: include: A substrate and a plurality of active pillars disposed on the substrate, wherein the active pillars include a first source-drain layer, a channel layer and a second source-drain layer stacked in sequence on the substrate, and the channel layer is disposed between the first source-drain layer and the second source-drain layer; The semiconductor structure further comprises a plurality of first trenches in the first direction and a plurality of second trenches in the first direction, wherein the first trenches in the first direction and the second trenches in the first direction both extend along the first direction, and the first trenches in the first direction and the second trenches in the first direction are alternately arranged, and each of the active pillars is located between adjacent first trenches in the first direction and adjacent second trenches in the first direction; The channel layer includes a first channel sublayer and a second channel sublayer in contact with each other. The first channel sublayer is located on a side of the second channel sublayer close to the first groove in the first direction. The second channel sublayer is located on a side of the first channel sublayer close to the second groove in the first direction.

14. A memory, characterized in that: It comprises a semiconductor structure prepared by the method for preparing a semiconductor structure according to any one of claims 1 to 12, or it comprises the semiconductor structure according to claim 13.

15. An electronic device, characterized in that: Comprising the memory as claimed in claim 14.

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