Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a semiconductor substrate, an epitaxial layer is formed on the first surface of the semiconductor substrate, and a plurality of junction implants are formed in the epitaxial layer; the JFET region is positioned among the plurality of junction implants, and the distance between two adjacent junction implants in the plurality of junction implants is defined as a JFET gap; the plurality of buried injection regions are located in part of the JFET region, the top surface of each buried injection region is lower than the top surface of the JFET region, and the doping type of each buried injection region is opposite to that of the JFET region. According to the semiconductor structure and the forming method thereof, the buried injection region is formed in the JFET region to serve as an electric field shielding layer, balance of an electric field and current is achieved under the condition that the channel density is not reduced, the process is simple, and continuous miniaturization of the size of the JFET region is not affected.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Wide bandgap semiconductors have a high critical breakdown electric field and can withstand high blocking voltages while providing low on-resistance, making them very suitable for making power semiconductor devices. However, if the electric field inside the device is not properly handled, it will lead to the concentration of the electric field inside the device and premature breakdown, and on the other hand, it will lead to the concentration of the electric field in the gate dielectric and reduce the gate reliability.

[0003] Compared with silicon devices, the interface state density of silicon carbide devices is 1 to 2 orders of magnitude higher, which results in low channel mobility at the silicon carbide / silicon oxide interface. The use of square cell and hexagonal cell technology is very beneficial to increase the channel density per unit area, but it will also lead to the concentration of electric fields in the silicon carbide device and in the gate dielectric. In addition, the current concentration in the diagonal JFET region of the SiC MOSFET square cell and hexagonal cell will also reduce the high reliability of the device.

[0004] Therefore, optimizing the channel resistance of SiC MOSFET using square cell and hexagonal cell technologies necessarily requires optimizing the electric field balance in the device body and gate dielectric, as well as the current balance in the JFET region of the device. Summary of the invention

[0005] The invention of the present application aims to optimize the electric field balance in the SiC MOSFET device body and gate dielectric, as well as the current balance in the JFET region of the device.

[0006] One aspect of the present application provides a semiconductor structure, including: a semiconductor substrate, an epitaxial layer is formed on the first surface of the semiconductor substrate, and a plurality of junction implants are formed in the epitaxial layer; a JFET region is located between the plurality of junction implants, and the distance between two adjacent junction implants in the plurality of junction implants is defined as a JFET gap; and a plurality of buried implant regions are located in part of the JFET region, the top surface of the buried implant region is lower than the top surface of the JFET region, and the doping type of the buried implant region is opposite to the doping type of the JFET region.

[0007] In some embodiments of the present application, the JFET gap is uniform in the entire semiconductor structure, and the plurality of buried implant regions are uniformly located in the JFET region.

[0008] In some embodiments of the present application, each of the plurality of junction implants is strip-shaped.

[0009] In some embodiments of the present application, the JFET gap is not uniform in the entire semiconductor structure, and the JFET region is divided into a first JFET sub-region and a second JFET sub-region according to different JFET gaps.

[0010] In some embodiments of the present application, the JFET gap of the first JFET sub-region is smaller than the JFET gap of the second JFET sub-region, and the plurality of buried implant regions are located in the second JFET sub-region.

[0011] In some embodiments of the present application, each of the several junction implants is rectangular or hexagonal.

[0012] In some embodiments of the present application, the material of the semiconductor substrate includes doped silicon carbide, the material of the epitaxial layer includes doped silicon carbide, the semiconductor substrate and the epitaxial layer have the same doping type, and the doping concentration of the semiconductor substrate is greater than the doping concentration of the epitaxial layer.

[0013] In some embodiments of the present application, the plurality of buried implant regions also partially extend into the junction implant.

[0014] In some embodiments of the present application, the doping concentration of the plurality of buried implant regions is 9E15 to 6E17 cm -3 .

[0015] Another aspect of the present application also provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, wherein an epitaxial layer is formed on the first surface of the semiconductor substrate, and a plurality of junction implants are formed in the epitaxial layer; forming a JFET region between the plurality of junction implants, and the distance between two adjacent junction implants among the plurality of junction implants is defined as a JFET gap; and forming a plurality of buried implant regions in part of the JFET region, wherein the top surface of the buried implant region is lower than the top surface of the JFET region, and the doping type of the buried implant region is opposite to the doping type of the JFET region.

[0016] In some embodiments of the present application, the JFET gap is uniform in the entire semiconductor structure, and the plurality of buried implant regions are uniformly located in the JFET region.

[0017] In some embodiments of the present application, each of the plurality of junction implants is strip-shaped.

[0018] In some embodiments of the present application, the JFET gap is not uniform in the entire semiconductor structure, and the JFET region is divided into a first JFET sub-region and a second JFET sub-region according to different JFET gaps.

[0019] In some embodiments of the present application, the JFET gap of the first JFET sub-region is smaller than the JFET gap of the second JFET sub-region, and the plurality of buried implant regions are located in the second JFET sub-region.

[0020] In some embodiments of the present application, each of the several junction implants is rectangular or hexagonal.

[0021] In some embodiments of the present application, the material of the semiconductor substrate includes doped silicon carbide, the material of the epitaxial layer includes doped silicon carbide, the semiconductor substrate and the epitaxial layer have the same doping type, and the doping concentration of the semiconductor substrate is greater than the doping concentration of the epitaxial layer.

[0022] In some embodiments of the present application, the plurality of buried implant regions also partially extend into the junction implant.

[0023] In some embodiments of the present application, the doping concentration of the plurality of buried implant regions is 9E15 to 6E17 cm -3 .

[0024] The present application provides a semiconductor structure and a method for forming the same, forming a buried injection region in a JFET region as an electric field shielding layer, achieving a balance between electric field and current without reducing the channel density, and having a simple process without affecting the continued miniaturization of the size of the JFET region. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The following figures describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale.

[0026] in:

[0027] Figure 1 A schematic diagram of a longitudinal cross-sectional structure of a semiconductor structure according to some embodiments of the present application;

[0028] Figure 2 A top view of the semiconductor structure described in the first embodiment of the present application;

[0029] Figure 3 A top view of the semiconductor structure according to the second embodiment of the present application;

[0030] Figure 4 A top view of the semiconductor structure described in the third embodiment of the present application;

[0031] Figure 5 The present invention is a flowchart of a method for forming a semiconductor structure according to some embodiments of the present application. DETAILED DESCRIPTION

[0032] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0033] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

[0034] Figure 1 It is a schematic diagram of the longitudinal cross-section structure of the semiconductor structure described in some embodiments of the present application. Figure 1 The semiconductor structure unit 10 described in some embodiments of the present application is shown.

[0035] refer to Figure 1 As shown, the semiconductor structure unit 10 includes a semiconductor substrate 100, an epitaxial layer 110 is formed on the first surface of the semiconductor substrate 100, a plurality of junction implants 120 are formed in the epitaxial layer 110, each junction implant 120 includes a well region 121 and a source well 122, and the source well 122 is located in the well region 121 and can be surrounded by the well region 121.

[0036] In some embodiments of the present application, the material of the semiconductor substrate 100 includes doped silicon carbide, the material of the epitaxial layer 110 includes doped silicon carbide, the semiconductor substrate 100 and the epitaxial layer 110 have the same doping type, and the doping concentration of the semiconductor substrate 100 is greater than the doping concentration of the epitaxial layer 110.

[0037] In some embodiments of the present application, the doping type of the semiconductor substrate 100 is N-type, and the doping concentration of the semiconductor substrate 100 is 1E19 to 1E20 cm -3 The doping type of the epitaxial layer 110 is N-type, and the doping concentration of the epitaxial layer 110 is 5E13 to 1E17 cm -3 .

[0038] In some embodiments of the present application, the doping type of the well region 121 is P type, and the doping concentration of the well region 121 is 1E16 to 3E19 cm -3 The doping type of the source well 122 is N-type, and the doping concentration of the source well 122 is 1E20 to 1E21 cm-3 .

[0039] Continue to refer Figure 1 As shown, the semiconductor structure unit 10 further includes a JFET (junction field effect transistor) region 130, which is located between the plurality of junction implants 120, and the distance between two adjacent junction implants 120 in the plurality of junction implants 120 is defined as a JFET gap. The depth of the JFET region 130 may be greater than the depth of the junction implant 120. The JFET region 130 may extend to the bottom of a portion of the junction implant 120.

[0040] In some embodiments of the present application, the doping type of the JFET region 130 is N-type, and the doping concentration of the JFET region 130 is 1E16 to 2E17 cm -3 .

[0041] Continue to refer Figure 1 As shown, the semiconductor structure unit 10 also includes a plurality of buried implant regions 140 located in part of the JFET region 130 , the top surface of the buried implant region 140 is lower than the top surface of the JFET region 130 , and the doping type of the buried implant region 140 is opposite to the doping type of the JFET region 130 .

[0042] In some embodiments of the present application, the doping type of the buried implant region 140 is P-type, and the doping concentration of the buried implant region 140 is 9E15 to 6E17 cm -3 .

[0043] In some embodiments of the present application, the plurality of buried implant regions 140 also partially extend into the junction implant 120 .

[0044] Continue to refer Figure 1 As shown, the semiconductor structure unit 10 also includes: a gate dielectric layer 150, which is located on the surface of the epitaxial layer 110, and the gate dielectric layer 150 extends between the source well 122 of each of the junction implants 120; a gate layer 170, which is located on the surface of the gate dielectric layer 150; a source metal 160, which is located on the surface of the epitaxial layer 110, and the source metal 160 is on a portion of the well region 121 and the source well 122 in each junction implant 120; and a drain metal 180, which is located on the second surface of the semiconductor substrate 100 opposite to the first surface.

[0045] It should be noted that the semiconductor structure unit 10 is named as such because it is the smallest unit of a larger semiconductor structure. The semiconductor structure of the present application may include hundreds or thousands of the semiconductor structure units 10 repeated in various geometric configurations. Figure 1The semiconductor structure unit 10 shown is represented as a two-dimensional cross-section. In fact, the semiconductor structure unit 10 extends into and out of the page as a rectangular cuboid in three dimensions. The semiconductor structure unit 10 can be mirrored or repeated to extend into and out of the page. In addition, the semiconductor structure unit 10 can be symmetrically mirrored on its left and right sides and can continue to be repeated in this way to achieve the desired size.

[0046] Figure 2 This is a top view of the semiconductor structure described in the first embodiment of the present application. In the first embodiment, Figure 1 Can be Figure 2 The longitudinal cross-section along the dotted line AA in FIG. The gate dielectric layer, the gate layer and the source metal are not Figure 2 Shown in.

[0047] refer to Figure 2 As shown, in the first embodiment of the present application, the JFET gap is uniform in the entire semiconductor structure (for example, each of the plurality of junction implants 120 is strip-shaped), and the plurality of buried implant regions 140 are uniformly located in the JFET region 130 . Figure 2 The configuration shown is often referred to as a "strip cell" design because the junction implants 120 are in the form of strips across the device.

[0048] In the technical solution of the present application, when the JFET gap is uniform in the entire semiconductor structure, a plurality of buried implant regions 140 are uniformly arranged in the JFET region 130, so that the balance of electric field and current can be achieved without reducing the channel density, and the process is simple and does not affect the continued miniaturization of the size of the JFET region.

[0049] The first embodiment of the present application uses the stripe shape of each of the plurality of junction implants 120 as an example to illustrate the situation when the JFET gap is uniform in the entire semiconductor structure. The second and third embodiments will be combined to illustrate the situation when the JFET gap is not uniform in the entire semiconductor structure using the rectangular or hexagonal shape of each of the plurality of junction implants 120 as an example.

[0050] Figure 3 This is a top view of the semiconductor structure described in the second embodiment of the present application. In the second embodiment, Figure 1 Can be Figure 3 The longitudinal cross-section along the dotted line BB in FIG. Among them, the gate dielectric layer, the gate layer and the source metal are not Figure 3 Shown in.

[0051] refer to Figure 3As shown, in the second embodiment of the present application, the JFET gap is not uniform in the entire semiconductor structure, and according to different JFET gaps, the JFET region 130 is divided into a first JFET sub-region 130 a and a second JFET sub-region 130 b .

[0052] In the second embodiment of the present application, the JFET gap of the first JFET sub-region 130 a is smaller than the JFET gap of the second JFET sub-region 130 b , and the plurality of buried implant regions 140 are located in the second JFET sub-region 130 b . Figure 3 In order to clearly illustrate the second JFET sub-region 130 b , the buried implant region 140 is omitted in one of the second JFET sub-regions 130 b .

[0053] In the second embodiment of the present application, each of the plurality of junction implants 120 is rectangular. Figure 3 The configuration shown is often referred to as a "square cell" design because the junction implants 120 are square in shape across the device.

[0054] Figure 4 This is a top view of the semiconductor structure described in the third embodiment of the present application. In the third embodiment, Figure 1 Can be Figure 4 The longitudinal cross-sectional view along the dotted line CC in FIG. Wherein, the gate dielectric layer, the gate layer and the source metal are not Figure 4 Shown in.

[0055] refer to Figure 4 As shown, in the third embodiment of the present application, the JFET gap is not uniform in the entire semiconductor structure, and according to different JFET gaps, the JFET region 130 is divided into a first JFET sub-region 130 a and a second JFET sub-region 130 b .

[0056] In a third embodiment of the present application, a JFET gap of the first JFET sub-region 130 a is smaller than a JFET gap of the second JFET sub-region 130 b , and the plurality of buried implant regions 140 are located in the second JFET sub-region 130 b . Figure 4 In order to clearly illustrate the second JFET sub-region 130 b , the buried implant region 140 is omitted in one of the second JFET sub-regions 130 b .

[0057] In the third embodiment of the present application, each of the plurality of junction implants 120 is hexagonal. Figure 4 The configuration shown is often referred to as a "hexagonal cell" design because the junction implants 120 are hexagonal in shape across the device.

[0058] In the technical solution of the present application, when the JFET gap is uneven in the entire semiconductor structure, a plurality of buried injection regions 140 are provided in the JFET region 130 where the JFET gap is larger, so that the balance of electric field and current can be achieved without reducing the channel density, and the process is simple and does not affect the continued miniaturization of the size of the JFET region.

[0059] Figure 5 The present invention is a flowchart of a method for forming a semiconductor structure according to some embodiments of the present application.

[0060] The present invention also provides a method for forming a semiconductor structure. Figure 5 As shown, including:

[0061] Step S1: providing a semiconductor substrate, wherein an epitaxial layer is formed on a first surface of the semiconductor substrate, and a plurality of junction implants are formed in the epitaxial layer;

[0062] Step S2: forming a JFET region between the plurality of junction implants, wherein a distance between two adjacent junction implants among the plurality of junction implants is defined as a JFET gap;

[0063] Step S3: forming a plurality of buried implant regions in part of the JFET region, wherein the top surface of the buried implant regions is lower than the top surface of the JFET region, and the doping type of the buried implant regions is opposite to the doping type of the JFET region.

[0064] refer to Figure 1 As shown, step S1, providing a semiconductor substrate 100, wherein an epitaxial layer 110 is formed on the first surface of the semiconductor substrate 100, wherein a plurality of junction implants 120 are formed in the epitaxial layer 110, each junction implant 120 includes a well region 121 and a source well 122, wherein the source well 122 is located in the well region 121 and can be surrounded by the well region 121.

[0065] In some embodiments of the present application, the material of the semiconductor substrate 100 includes doped silicon carbide, the material of the epitaxial layer 110 includes doped silicon carbide, the semiconductor substrate 100 and the epitaxial layer 110 have the same doping type, and the doping concentration of the semiconductor substrate 100 is greater than the doping concentration of the epitaxial layer 110.

[0066] In some embodiments of the present application, the doping type of the semiconductor substrate 100 is N-type, and the doping concentration of the semiconductor substrate 100 is 1E19 to 1E20 cm -3 The doping type of the epitaxial layer 110 is N-type, and the doping concentration of the epitaxial layer 110 is 5E13 to 1E17 cm -3 .

[0067] In some embodiments of the present application, the method of forming the epitaxial layer 110 on the first surface of the semiconductor substrate 100 includes an epitaxial growth process.

[0068] In some embodiments of the present application, the doping type of the well region 121 is P type, and the doping concentration of the well region 121 is 1E16 to 3E19 cm -3 The doping type of the source well 122 is N-type, and the doping concentration of the source well 122 is 1E20 to 1E21 cm -3 .

[0069] In some embodiments of the present application, the method of forming the well region 121 and the source well 122 of the junction implant 120 includes an ion implantation process.

[0070] Continue to refer Figure 1 As shown, in step S2, a JFET region 130 is formed between the plurality of junction implants 120, and the distance between two adjacent junction implants 120 in the plurality of junction implants 120 is defined as a JFET gap. The depth of the JFET region 130 may be greater than the depth of the junction implant 120. The JFET region 130 may extend to the bottom of a portion of the junction implant 120.

[0071] In some embodiments of the present application, the doping type of the JFET region 130 is N-type, and the doping concentration of the JFET region 130 is 1E16 to 2E17 cm -3 .

[0072] In some embodiments of the present application, the method of forming the JFET region 130 includes an ion implantation process.

[0073] Continue to refer Figure 1 As shown, in step S3, a plurality of buried implant regions 140 are formed in part of the JFET region 130 , wherein the top surface of the buried implant region 140 is lower than the top surface of the JFET region 130 , and the doping type of the buried implant region 140 is opposite to the doping type of the JFET region 130 .

[0074] In some embodiments of the present application, the doping type of the buried implant region 140 is P-type, and the doping concentration of the buried implant region 140 is 9E15 to 6E17 cm -3 In some embodiments of the present application, the doping concentration of the plurality of buried implant regions 140 is greater than the doping concentration of the JFET region 130 .

[0075] In some embodiments of the present application, the plurality of buried implant regions 140 also partially extend into the junction implant 120 .

[0076] In some embodiments of the present application, the method of forming the plurality of buried implant regions 140 includes an ion implantation process.

[0077] Continue to refer Figure 1 As shown, a gate dielectric layer 150 is formed, and the gate dielectric layer 150 is located on the surface of the epitaxial layer 110, and the gate dielectric layer 150 extends between the source wells 122 of each of the junction implants 120; a gate layer 170 is formed, and the gate layer 170 is located on the surface of the gate dielectric layer 150; a source metal 160 is formed, and the source metal 160 is located on the surface of the epitaxial layer 110, and the source metal 160 is on a portion of the well region 121 and the source well 122 in each junction implant 120; a drain metal 180 is formed, and the drain metal 180 is located on the second surface of the semiconductor substrate 100 opposite to the first surface.

[0078] refer to Figure 2 As shown, in the first embodiment of the present application, the JFET gap is uniform in the entire semiconductor structure (for example, each of the plurality of junction implants 120 is strip-shaped), and the plurality of buried implant regions 140 are uniformly located in the JFET region 130 . Figure 2 The configuration shown is often referred to as a "strip cell" design because the junction implants 120 are in the form of strips across the device.

[0079] In the technical solution of the present application, when the JFET gap is uniform in the entire semiconductor structure, a plurality of buried implant regions 140 are uniformly arranged in the JFET region 130, so that the balance of electric field and current can be achieved without reducing the channel density, and the process is simple and does not affect the continued miniaturization of the size of the JFET region.

[0080] refer to Figure 3 As shown, in the second embodiment of the present application, the JFET gap is not uniform in the entire semiconductor structure, and according to different JFET gaps, the JFET region 130 is divided into a first JFET sub-region 130 a and a second JFET sub-region 130 b .

[0081] In the second embodiment of the present application, the JFET gap of the first JFET sub-region 130 a is smaller than the JFET gap of the second JFET sub-region 130 b , and the plurality of buried implant regions 140 are located in the second JFET sub-region 130 b . Figure 3 In order to clearly illustrate the second JFET sub-region 130 b , the buried implant region 140 is omitted in one of the second JFET sub-regions 130 b .

[0082] In the second embodiment of the present application, each of the plurality of junction implants 120 is rectangular. Figure 3The configuration shown is often referred to as a "square cell" design because the junction implants 120 are square in shape across the device.

[0083] refer to Figure 4 As shown, in the third embodiment of the present application, the JFET gap is not uniform in the entire semiconductor structure, and according to different JFET gaps, the JFET region 130 is divided into a first JFET sub-region 130 a and a second JFET sub-region 130 b .

[0084] In a third embodiment of the present application, a JFET gap of the first JFET sub-region 130 a is smaller than a JFET gap of the second JFET sub-region 130 b , and the plurality of buried implant regions 140 are located in the second JFET sub-region 130 b . Figure 4 In order to clearly illustrate the second JFET sub-region 130 b , the buried implant region 140 is omitted in one of the second JFET sub-regions 130 b .

[0085] In the third embodiment of the present application, each of the plurality of junction implants 120 is hexagonal. Figure 4 The configuration shown is often referred to as a "hexagonal cell" design because the junction implants 120 are hexagonal in shape across the device.

[0086] In the technical solution of the present application, when the JFET gap is uneven in the entire semiconductor structure, a plurality of buried injection regions 140 are provided in the JFET region 130 where the JFET gap is larger, so that the balance of electric field and current can be achieved without reducing the channel density, and the process is simple and does not affect the continued miniaturization of the size of the JFET region.

[0087] The present application provides a semiconductor structure and a method for forming the same, forming a buried injection region in a JFET region as an electric field shielding layer, achieving a balance between electric field and current without reducing the channel density, and having a simple process without affecting the continued miniaturization of the size of the JFET region.

[0088] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0089] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can also be intermediate elements.

[0090] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or there can be intervening elements. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recited features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0091] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.

[0092] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A semiconductor structure, characterized in that: include: A semiconductor substrate, wherein an epitaxial layer is formed on a first surface of the semiconductor substrate, and a plurality of junction implants are formed in the epitaxial layer; A JFET region is located between the plurality of junction implants, wherein a distance between two adjacent junction implants among the plurality of junction implants is defined as a JFET gap; A plurality of buried implant regions are located in part of the JFET region, wherein the top surface of the buried implant region is lower than the top surface of the JFET region, and the doping type of the buried implant region is opposite to the doping type of the JFET region.

2. The semiconductor structure according to claim 1, wherein: The JFET gap is uniform in the entire semiconductor structure, and the plurality of buried implant regions are uniformly located in the JFET region.

3. The semiconductor structure according to claim 2, wherein: Each of the plurality of junction implants is stripe-shaped.

4. The semiconductor structure according to claim 1, wherein: The JFET gap is not uniform in the entire semiconductor structure, and the JFET region is divided into a first JFET sub-region and a second JFET sub-region according to different JFET gaps.

5. The semiconductor structure according to claim 4, characterized in that A JFET gap of the first JFET sub-region is smaller than a JFET gap of the second JFET sub-region, and the plurality of buried implant regions are located in the second JFET sub-region.

6. The semiconductor structure according to claim 4, wherein: Each of the several junction implants is rectangular or hexagonal.

7. The semiconductor structure according to claim 1, wherein: The material of the semiconductor substrate includes doped silicon carbide, the material of the epitaxial layer includes doped silicon carbide, the semiconductor substrate and the epitaxial layer have the same doping type, and the doping concentration of the semiconductor substrate is greater than the doping concentration of the epitaxial layer.

8. The semiconductor structure according to claim 1, wherein: The buried implant regions also partially extend into the junction implant.

9. The semiconductor structure according to claim 1, wherein: The doping concentration of the buried implant regions is 9E15 to 6E17 cm -3 .

10. A method for forming a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, wherein an epitaxial layer is formed on a first surface of the semiconductor substrate, and a plurality of junction implants are formed in the epitaxial layer; forming a JFET region between the plurality of junction implants, wherein a distance between two adjacent junction implants among the plurality of junction implants is defined as a JFET gap; A plurality of buried implant regions are formed in part of the JFET region, wherein the top surface of the buried implant region is lower than the top surface of the JFET region, and the doping type of the buried implant region is opposite to the doping type of the JFET region.

11. The method for forming a semiconductor structure according to claim 10, wherein: The JFET gap is uniform in the entire semiconductor structure, and the plurality of buried implant regions are uniformly located in the JFET region.

12. The method for forming a semiconductor structure according to claim 11, wherein: Each of the plurality of junction implants is stripe-shaped.

13. The method for forming a semiconductor structure according to claim 10, wherein: The JFET gap is not uniform in the entire semiconductor structure, and the JFET region is divided into a first JFET sub-region and a second JFET sub-region according to different JFET gaps.

14. The method for forming a semiconductor structure according to claim 13, wherein: A JFET gap of the first JFET sub-region is smaller than a JFET gap of the second JFET sub-region, and the plurality of buried implant regions are located in the second JFET sub-region.

15. The method for forming a semiconductor structure according to claim 13, wherein: Each of the several junction implants is rectangular or hexagonal.

16. The method for forming a semiconductor structure according to claim 10, wherein: The material of the semiconductor substrate includes doped silicon carbide, the material of the epitaxial layer includes doped silicon carbide, the semiconductor substrate and the epitaxial layer have the same doping type, and the doping concentration of the semiconductor substrate is greater than the doping concentration of the epitaxial layer.

17. The method for forming a semiconductor structure according to claim 10, wherein: The buried implant regions also partially extend into the junction implant.

18. The method for forming a semiconductor structure according to claim 10, wherein: The doping concentration of the buried implant regions is 9E15 to 6E17 cm -3 .

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