Novel ultra-low power consumption polymorphic lossless reading ferroelectric memcapacitor and preparation method thereof

Abstract

The invention belongs to the technical field of novel storage materials and microelectronic devices, and particularly discloses a novel ultra-low power consumption polymorphic lossless reading ferroelectric memory capacitor and a preparation method thereof. The ferroelectric memcapacitor comprises a first electrode, a second electrode and a ferroelectric layer, wherein the first electrode and the second electrode are oppositely arranged, the ferroelectric layer is arranged between the first electrode and the second electrode, and the ferroelectric layer is of a laminated structure formed by alternately arranging hafnium oxide (Hf02) layers and zirconium oxide (Zr02) layers. The multi-state memory which has the advantages of being simple in structure, compatible with the CMOS technology, capable of being miniaturized, low in power consumption, lossless, rapid in reading, good in durability and the like is obtained through combination of structural design and technology optimization. By utilizing the characteristic that the dielectric constant can be changed by the nonvolatile polarization effect of the hafnium zirconium oxide ferroelectric layer, a nonvolatile adjustable capacitance value is formed for data storage, a storage window is maximized, an operation voltage is minimized, and polymorphic storage is realized; the common problems of low read-write speed, high write-in power consumption, poor durability and the like of the conventional nonvolatile memory are effectively solved.

Description

Technical Field

[0001] The present invention relates to the field of novel storage materials and microelectronic devices, and in particular to a novel ultra-low power consumption multi-state lossless reading ferroelectric memcapacitor and a preparation method thereof. Background Art

[0002] In the future, advanced fields such as high-bandwidth DRAM (dynamic random access memory), in-memory computing, neural network artificial intelligence, nonlinear science, etc. will have higher requirements on the read and write speed, operating voltage, power consumption, and integration of storage devices.

[0003] Compared with the current DRAM that uses the charge storage principle, non-ferroelectric memory has a broader application prospect because it does not need to use voltage to maintain the storage state and does not need to refresh the storage content periodically. However, due to the limitations of current material technology, the mainstream non-volatile memory on the market generally has disadvantages such as slow reading and writing speeds and high writing power consumption, making it difficult to replace or even surpass the current DRAM.

[0004] However, the ferroelectric memories currently on the market or reported often require a ferroelectric capacitor and a transistor switch (1T1C) structure, which not only affects the integration and process complexity, but also the reading method of the polarization current of the ferroelectric capacitor will cause the storage state to be rewritten. If the original storage state is to be maintained, the necessary write-back operation will seriously affect its read-write efficiency and power consumption, and it is even more impossible to fully utilize the multi-state storage potential of the ferroelectric material itself. In addition, due to the problem of the semiconductor and ferroelectric interface, the durability of ferroelectric transistors (FeFETs) is usually much lower than DRAM.

[0005] Therefore, the introduction of a polystate memory with simple structure, compatible with CMOS process, miniaturization, low power consumption and lossless reading can provide powerful high computing power and low power consumption hardware low-level support for the upcoming artificial intelligence (AI) era. Summary of the invention

[0006] The purpose of the present invention is to provide a novel ultra-low power consumption multi-state lossless reading ferroelectric memcapacitor and a preparation method thereof, so as to solve the above technical problems.

[0007] In order to achieve the above object, the specific technical solution adopted by the present invention is as follows:

[0008] In the first aspect, the present invention provides a novel ultra-low power consumption multi-state lossless read ferroelectric memory capacitor, which is a sandwich structure, including a first electrode and a second electrode arranged opposite to each other, and a ferroelectric layer arranged between the first electrode and the second electrode, wherein the ferroelectric layer is a stacked structure in which hafnium oxide (HfO2) layers and zirconium oxide (ZrO2) layers are alternately arranged.

[0009] Furthermore, the material of the first electrode and the second electrode is any one of ruthenium, molybdenum, titanium, gold, silver, nickel, platinum, tungsten, aluminum, indium, tin, chromium, or any one of the alloys, nitride oxides, and metal oxide semiconductors of the above materials.

[0010] Furthermore, the thickness of the first electrode and the second electrode is 2-50 nm.

[0011] Furthermore, the thickness of the ferroelectric layer is 1.5-30 nm, and the thickness of the stacked single layer is 0.1-2 nm.

[0012] Furthermore, the hafnium-zirconium mixing ratio of the ferroelectric layer is (10-0.1):1.

[0013] In a second aspect, the present invention provides a method for preparing the novel ultra-low power consumption multi-state lossless read ferroelectric memcapacitor, comprising the following steps:

[0014] S1. Preparation of insulating dielectric layer: growing insulating material as insulating dielectric layer on the upper surface of semiconductor by sol-gel, spin coating, chemical vapor deposition, thermal oxidation, vacuum evaporation, magnetron sputtering, pulsed laser deposition, atomic layer deposition or molecular beam epitaxy;

[0015] S2. Preparing a first electrode: depositing a conductive medium as the first electrode on the upper surface of the insulating dielectric layer by spin coating, magnetron sputtering, atomic layer deposition or vacuum evaporation;

[0016] S3. Preparing a ferroelectric layer: preparing a ferroelectric material as a polymorphic ferroelectric layer on the upper surface of the first electrode by sol-gel, spin coating, chemical vapor deposition, thermal oxidation, vacuum evaporation, magnetron sputtering, pulsed laser deposition, atomic layer deposition or molecular beam epitaxy;

[0017] S4. Preparing a second electrode: depositing a conductive medium as the second electrode on the upper surface of the ferroelectric layer by spin coating, magnetron sputtering, atomic layer deposition or vacuum evaporation;

[0018] S5. Regulation of the three-phase composition of the ferroelectric layer: After completing the above steps, the device is subjected to high-temperature annealing treatment by means of a rapid heating device, rapid laser pulses, heating by a thin film deposition or growth device, etc. Under the joint action of the thin film stack and the electrode, the ferroelectric layer material undergoes a phase transformation to form a mixed crystal of a ferroelectric phase, an antiferroelectric phase, and a non-ferroelectric phase.

[0019] Furthermore, in step S5, the annealing temperature is 350-650°C.

[0020] The present invention has the following beneficial effects:

[0021] 1. The present invention utilizes the non-volatile polarization effect of the hafnium zirconium oxide ferroelectric layer to change the dielectric constant, forming a non-volatile adjustable capacitance for data storage. Based on this variable capacitance principle and structural design, the invention realizes the innovation of hafnium zirconium oxide ferroelectrics applied to memcapacitors. Only the MFM structure is required for operation, and no semiconductor is required to assist reading like the existing memcapacitors such as MFMS and MFMIS. In addition, the hafnium zirconium oxide ferroelectric material is compatible with CMOS processes and has scalability.

[0022] 2. The memory container of the present invention can retain data for more than 10 years and can withstand 1E11 erase and write times, thus having good durability.

[0023] 3. The memory container of the present invention can realize clear 4-bit polymorphic storage, which can meet the basic neural network computing requirements.

[0024] 4. The use of ferroelectric memcapacitors requires opening a storage window at a fixed read voltage point, that is, using different erase and write voltages to adjust the capacitance value to achieve the purpose of polymorphic storage; in order to reduce power consumption, the read voltage usually tends to be as small as possible, but the maximum capacitance window of traditional ferroelectrics is often far away from the voltage zero point, and the zero point window is the minimum point; the memcapacitor of the present invention maximizes the capacitance window near the zero point, thereby achieving the purpose of ultra-low read power consumption, and due to the low operating voltage, the reading speed is also greatly improved.

[0025] 5. The memristor of the present invention only requires a capacitor and no transistor, has a simple structure, low process cost, and is easy to achieve high integration.

[0026] In summary, the present invention is based on the first electrode-ferroelectric layer-second electrode as the basic structure. By setting the ferroelectric layer as a stacked structure in which HfO2 and ZrO2 are alternately arranged, combined with the thickness, material, and hafnium-zirconium mixing ratio control of each layer and annealing treatment during the preparation process, the problems of slow reading and writing speed, high writing power consumption, and poor durability that are common in current non-volatile memories are overcome. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 : A schematic structural diagram of a ferroelectric storage capacitor provided in a specific embodiment of the present invention.

[0028] Figure 2 : Schematic diagram of the structure of the laminated ferroelectric structure in the capacitor according to a specific embodiment of the present invention.

[0029] Figure 3 : Capacitor storage window opening and enlargement results of a specific implementation mode of the present invention.

[0030] Figure 4 : Schematic results of capacitor multistability according to a specific embodiment of the present invention.

[0031] In the figure: 1-first electrode, 2-second electrode, 3-ferroelectric layer; 31-hafnium oxide layer, 32-zirconium oxide layer. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical scheme and advantages of the present invention clearer, the technical contents of the present invention are described in detail below with reference to the accompanying drawings. Obviously, the described embodiments only represent some embodiments of the present invention, not all. Based on the embodiments of the present invention, ordinary technicians in this field can deduce all other embodiments without performing creative work, and these methods are all within the scope of protection of the present invention.

[0033] The words such as "first", "second", etc. used in the embodiments, claims and drawings in the specification of the present invention are only used for the purpose of distinguishing the description and should not be understood as indicating or implying the relative order of their importance. In addition, the terms "including" and "having" and any variations thereof are intended to be inclusive rather than exclusive, for example, including a series of steps or units. The method, system, product or device is not limited to the steps or units explicitly listed, but may include other steps or units inherent to these processes, methods, products or devices. Terms such as "upper", "lower", "left", "right", etc. are only used to describe the position relative to the components in the drawings, and are relative concepts. Their specific directions can be adjusted accordingly according to the changes in the directions in which the components are placed in the drawings.

[0034] The principle and technical effects of the technical solution of the present invention are described below.

[0035] like Figure 1 As shown, the ferroelectric device provided by the present invention includes a first electrode 1 , a ferroelectric layer 3 and a second electrode 2 . Figure 1 It is only a schematic diagram. The sandwich structures 01 and 02 can be metal electrode-ferroelectric film-metal electrode (MFM) structures, but are not limited thereto. In some embodiments, the electrode 1 and the electrode 2 can also be made of other materials besides metal, such as metal oxide semiconductors, etc.;

[0036] Those skilled in the art will understand that, in a ferroelectric device, the first electrode 1 and the second electrode 2 are two electrodes arranged opposite to each other, mainly referring to materials used to introduce an electric field and to attach the ferroelectric layer, and the present invention does not limit the shape of the electrodes.

[0037] The ferroelectric layer 3 of the present invention is a stacked structure of a hafnium oxide layer 31 and a zirconium oxide layer 32. The polymorphic ferroelectric layer can ensure the compatibility and scalability of the ferroelectric device with the CMOS process.

[0038] Due to low power consumption, high-density multi-state storage has a positive effect on the performance and storage density of the memory. The capacitance value / dielectric constant of most hafnium oxide-based ferroelectric materials will change with the polarization state, and have a symmetrical maximum capacitance value / storage window distribution on both sides of the zero point, such as Figure 3 -01, but the optimal window point is often far away from the voltage zero point, which causes difficulties in reading and writing and increases power consumption;

[0039] The present invention utilizes the regulation of metal electrodes (such as the combination of molybdenum and tungsten electrodes in Example 1) to allow a certain built-in electric field to exist in the capacitor when the external voltage is zero, thereby allowing the window originally far away from the zero point to approach the zero point; it should be understood that since the built-in electric field generated by the metal will have certain limitations, and the growth and phase regulation of ferroelectrics and the reliability are highly dependent on the interface metal, it is also necessary to further optimize the storage window by means of interface optimization;

[0040] The present invention also uses annealing treatment to make the metal electrode take away the oxygen of the ferroelectric film (oxygenscavenging), thereby generating a certain number of oxygen vacancies at the metal-ferroelectric layer interface, causing a built-in electric field; it should be noted that this built-in field is usually not conducive to the application of traditional ferroelectrics, but in the present invention, it plays a role in promoting window optimization. The optimized ferroelectric memristor can maximize the zero-point window value. Figure 3 -02, the peak position in the figure is adjusted by regulating the phase composition (including stacking thickness, hafnium-zirconium ratio, and annealing temperature).

[0041] It is understood by those skilled in the art that the degree of ferroelectric remanent polarization can be controlled by the magnitude of the polarization electric field. The dielectric constant in the present invention is affected by the polarization intensity, such as Figure 4 -01, the capacitance value of the zero point can be adjusted continuously from the maximum value to the minimum value in the current window;

[0042] It should be understood that a positive voltage can increase the capacitance value, which can be regarded as a memcapping value-added operation, and a negative voltage can reduce the capacitance value, which can be regarded as a memcapping value-decrement operation; the capacitance value of the memcapping value after the write voltage is removed is determined by the maximum applied voltage value;

[0043] It is worth noting that the storage value reading operation of the memory container of the present invention only requires a small voltage pulse (which may be less than 0.1V) to charge the capacitor, and the integral of the current and time (charge amount) can correspond to the current storage value of the memory;

[0044] like Figure 4 -02, the memory container of the present invention can realize clear 4-bit polymorphic storage, which can meet the basic neural network computing requirements.

[0045] It should be noted that, compared with the existing memory, the memory container of the present invention has many advantages:

[0046] Different from the current mainstream non-volatile non-destructive read memory such as FLASH, the method of controlling the dielectric constant of the memcapporat in the present invention has more outstanding advantages, and the erase voltage is lower (about 1V higher than the polarization voltage of the ferroelectric material, while the mainstream FLASH requires more than 5V);

[0047] Compared with other emerging storage such as resistive random access memory, the memory container of the present invention has a huge advantage in reading and writing power consumption. Compared with impedance-type devices, capacitor-type devices have a natural self-limiting property on the total amount of charge flowing through the device, thereby limiting the total amount of power consumption. During the writing process, the total amount of charge flowing through the device is mainly determined by the ferroelectric polarization charge. During the reading process, when the charge reaches the upper limit of the capacitor storage capacity, the current will stop automatically.

[0048] The read and write speeds are also very advantageous. Those skilled in the art will appreciate that the intrinsic polarization speed (write operation) of ferroelectric materials can reach nanoseconds, and similar to DRAM, the read operation of the memory container of the present invention is similar to the write operation of DRAM, that is, charging the capacitor (usually completed in nanoseconds), so it has the potential to replace or even surpass DRAM in terms of performance.

[0049] The data retention capability is determined by the ferroelectric material and can usually reach more than 10 years, and the durability of the memory container of the present invention can reach 1E11, which is close to the durability index of the current DRAM.

[0050] Compared with most memories (FLAH, resistive random access memory), especially polymorphic storage, the storage value of the memory container of the present invention does not need to be erased and then rewritten, so it also has advantages in writing efficiency and power consumption.

[0051] The process structure is simpler. The core memory device only needs one capacitor, unlike DRAM, FLAH and other memories which require FET transistors, so the process cost is lower. During the experiment, it was found that the thinning of the ferroelectric layer of the memcapacitor to 5nm can maintain a higher window and a lower operating voltage, and can achieve the characteristics of high integration and low power consumption.

[0052] A specific embodiment is provided below to embody the technical solution of the present invention in more detail.

[0053] Example 1

[0054] This embodiment provides a new ultra-low power consumption multi-state lossless read ferroelectric memristor, which has the above-mentioned technical effects and advantages. Figure 1 -02 and Figure 2As shown, it includes a first electrode 1 and a second electrode 2 arranged opposite to each other, and a ferroelectric layer 3 arranged between the first electrode 1 and the second electrode 2. The material of the first electrode 1 is molybdenum with a thickness of 50nm; the material of the second electrode 2 is tungsten with a thickness of 50nm. The ferroelectric layer 3 is a stacked structure in which hafnium oxide layers 31 and zirconium oxide layers 32 are alternately arranged; the thickness of the ferroelectric layer 3 is 6nm, and the thickness of a single stacked layer is 1.2nm; the hafnium-zirconium mixing ratio of the ferroelectric layer 3 is 0.7:1.

[0055] The ferroelectric memristor is obtained by the following preparation method:

[0056] S1. Preparing an insulating dielectric layer: growing a silicon dioxide insulating material as an insulating dielectric layer on the upper surface of the semiconductor by a CVD deposition method;

[0057] S2. Preparing a first electrode: depositing a conductive medium as a first electrode on the upper surface of the insulating dielectric layer by a PVD method;

[0058] S3. Preparing a ferroelectric layer: Preparing a ferroelectric material as a multi-state ferroelectric layer on the upper surface of the first electrode by an atomic layer deposition method;

[0059] S4. Preparing a second electrode: depositing a conductive medium as a second electrode on the upper surface of the ferroelectric layer by a PVD method;

[0060] S5. Control of the three-phase composition of the ferroelectric layer: After completing the above steps, the device is subjected to a high-temperature treatment of 500°C by a rapid annealing method. Under the joint action of the thin film stack and the electrode, the ferroelectric layer material undergoes a phase transformation to form a mixed crystal of ferroelectric phase, antiferroelectric phase, and non-ferroelectric phase.

[0061] In summary, the above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A novel ultra-low power consumption multi-state lossless read ferroelectric memcapacitor, characterized by: The invention comprises a first electrode and a second electrode which are arranged opposite to each other and a ferroelectric layer arranged between the first electrode and the second electrode. The ferroelectric layer is a stacked structure in which hafnium oxide layers and zirconium oxide layers are alternately arranged.

2. The novel ultra-low power consumption multi-state lossless read ferroelectric memcapacitor according to claim 1 is characterized in that: The thickness of the first electrode and the second electrode is 2-50 nm.

3. The novel ultra-low power consumption multi-state lossless read ferroelectric memcapacitor according to claim 1 is characterized in that: The material of the first electrode and the second electrode is any one of ruthenium, molybdenum, titanium, gold, silver, nickel, platinum, tungsten, aluminum, indium, tin, and chromium, or any one of alloys, nitride oxides, and metal oxide semiconductors of the above materials.

4. The novel ultra-low power consumption multi-state lossless read ferroelectric memcapacitor according to claim 1 is characterized in that: The thickness of the ferroelectric layer is 1.5-30 nm, and the thickness of the stacked single layer is 0.1-2 nm.

5. The novel ultra-low power consumption multi-state lossless read ferroelectric memcapacitor according to claim 1 is characterized in that: The hafnium-zirconium mixing ratio of the ferroelectric layer is (10-0.1):

1.

6. The method for preparing the novel ultra-low power consumption multi-state lossless readout ferroelectric memcapacitor according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1. Preparing an insulating dielectric layer: growing an insulating material as an insulating dielectric layer on the upper surface of the semiconductor; S2. Preparing a first electrode: depositing a conductive medium as a first electrode on the upper surface of the insulating dielectric layer; S3. Preparing a ferroelectric layer: Preparing a ferroelectric material as a multi-state ferroelectric layer on the upper surface of the first electrode; S4. Preparing a second electrode: depositing a conductive medium as a second electrode on the upper surface of the ferroelectric layer; S5. Control of the three-phase composition of the ferroelectric layer: After completing the above steps, the device is subjected to high-temperature annealing treatment. Under the joint action of the thin film stack and the electrode, the ferroelectric layer material undergoes a phase transformation to form a mixed crystal of ferroelectric phase, antiferroelectric phase, and non-ferroelectric phase.

7. The novel ultra-low power consumption multi-state lossless read ferroelectric memcapacitor according to claim 1 is characterized in that: In step S5, the annealing temperature is 350-650°C.

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