Storage unit and static random access memory

Abstract

The invention provides a memory cell and a static random access memory. The memory cell comprises a first write-in circuit and a latch circuit. The first writing circuit comprises a first writing word line, a first writing bit line, a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; the first writing word line is connected with the first transistor and the second transistor; the first writing bit line is connected with the third transistor, the fourth transistor and the fifth transistor, and an inverter is connected to a line from the first writing bit line to the fourth transistor and the fifth transistor; the third transistor is grounded and connected with the first transistor, and the first transistor is further connected with the fourth transistor and the fifth transistor; the fourth transistor is grounded and is connected with the second transistor; the fifth transistor is connected with the power supply, and the fifth transistor is connected with the second transistor; a latch circuit is connected between the first transistor and the second transistor. According to the embodiment of the invention, data storage reliability can be improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a storage unit and a static random access memory. Background Art

[0002] Figure 1 The figure is a schematic diagram of the circuit structure corresponding to the write port of a traditional memory cell. The write port includes a write word line WWL and a write bit line WBL. The write word line WWL is connected to the gates of two NMOS tubes. When the write word line WWL is valid, the source and drain of the two NMOS tubes can be controlled to be in a conductive state, and then the state of logic 1 or logic 0 is stored in the latch between the two NMOS tubes through the write bit line WBL.

[0003] However, since the latch composed of the inverter pair has a strong driving capability, the data stored in the latch in the previous cycle will affect the logical state to be stored in the write bit line WBL in the current cycle. For example, the latch stored "0" in the previous cycle, that is, TR is "0" and TF is "1". "1" is to be written in the current cycle, and the write bit line WBL is "1". In this case, TR needs to be changed to "1" and TF needs to be changed to "0". At the moment when the two NMOS tubes are turned on, TR, which was "0" in the previous cycle, will drive the write bit line WBL from "1" to "0". When the write bit lines WBL of n items are connected together at the same time, the load of the write bit line WBL is large enough. At this time, the influence of TR on the write bit line WBL is very small and can be ignored. However, if the write word lines WWL of n items are connected together and valid at the same time, multiple inverter pairs will affect the write bit line WBL at the same time, which can change the value of WBL, so that the wrong data will be stored in the storage unit.

[0004] Therefore, in the write port circuit of the existing memory cell, the latch easily drives the write bit line in reverse, resulting in data storage errors. Summary of the invention

[0005] The present invention provides a storage unit and a static random access memory to solve the problem that in the write port circuit of the existing storage unit, a latch easily reversely drives a write bit line, resulting in data storage errors.

[0006] An embodiment of the present invention provides a storage unit, the storage unit comprising: a first writing circuit and a latch circuit;

[0007] The first write circuit includes a first write word line, a first write bit line, a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; the first write word line is connected to the control pins of the first transistor and the second transistor; the first write bit line is connected to the control pins of the third transistor, the fourth transistor and the fifth transistor, and an inverter is connected to the line from the first write bit line to the fourth transistor and the fifth transistor; the input pin of the third transistor is grounded, the output pin of the third transistor is connected to the input pin of the first transistor, and the input pin of the first transistor is also connected to the control pins of the fourth transistor and the fifth transistor; the input pin of the fourth transistor is grounded, and the output pin of the fourth transistor is connected to the input pin of the second transistor; the input pin of the fifth transistor is connected to a power supply, and the output pin of the fifth transistor is connected to the input pin of the second transistor; the latch circuit is connected between the output pin of the first transistor and the output pin of the second transistor.

[0008] Optionally, the storage unit further includes a second writing circuit;

[0009] The second write circuit includes a second write word line, a second write bit line, a sixth transistor and a seventh transistor; the second write word line is connected to the control pins of the sixth transistor and the seventh transistor, the second write bit line is connected to the input pin of the sixth transistor and to the input pin of the seventh transistor, the latch circuit is connected between the output pins of the sixth transistor and the seventh transistor, and an inverter is connected to the line from the second write bit line to the seventh transistor.

[0010] Optionally, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are triodes or MOS transistors.

[0011] Optionally, the first transistor, the second transistor, the third transistor, the fourth transistor, the sixth transistor and the seventh transistor are NMOS transistors, and the fifth transistor is a PMOS transistor;

[0012] The first write word line is connected to the gates of the first transistor and the second transistor; the first write bit line is connected to the gates of the third transistor, the fourth transistor and the fifth transistor; the drain of the third transistor is grounded, the source of the third transistor is connected to the drain of the first transistor, and the drain of the first transistor is also connected to the gates of the fourth transistor and the fifth transistor; the drain of the fourth transistor is grounded, and the source of the fourth transistor is connected to the drain of the second transistor; the source of the fifth transistor is connected to a power supply, and the drain of the fifth transistor is connected to the drain of the second transistor; the latch circuit is connected between the source of the first transistor and the source of the second transistor;

[0013] The second write word line is connected to the gates of the sixth transistor and the seventh transistor, the second write bit line is connected to the drain of the sixth transistor and the drain of the seventh transistor, and the latch circuit is connected between the sources of the sixth transistor and the seventh transistor.

[0014] Optionally, the first write bit line and the second write bit line share the same port.

[0015] Optionally, the storage unit includes at least two of the first writing circuits and at least two of the second writing circuits.

[0016] Optionally, the storage unit further includes a reading circuit;

[0017] The read circuit includes a read word line, a read bit line, an eighth transistor and a ninth transistor;

[0018] The read word line is connected to the control pin of the eighth transistor, the read bit line is connected to the output pin of the eighth transistor, the control pin of the ninth transistor is connected to the latch circuit, the output pin of the ninth transistor is connected to the input pin of the eighth transistor, and the input pin of the ninth transistor is grounded.

[0019] Optionally, the eighth transistor and the ninth transistor are both NMOS transistors;

[0020] The read word line is connected to the gate of the eighth transistor, the read bit line is connected to the source of the eighth transistor, the gate of the ninth transistor is connected to the latch circuit, the source of the ninth transistor is connected to the drain of the eighth transistor, and the drain of the ninth transistor is grounded.

[0021] Optionally, the latch circuit includes two independent first latches and a second latch;

[0022] The first latch is connected between output pins of the first transistor and the second transistor, and the second latch is connected between an output pin of the sixth transistor and an output pin of the seventh transistor.

[0023] The embodiment of the present invention further provides a static random access memory, the static random access memory comprising the aforementioned multiple storage units;

[0024] The plurality of storage cells are connected in an arrangement of m columns and n rows to form a storage array, wherein the storage cells in the same column share a bit line, and the storage cells in the same row share a word line, and m and n are both positive integers not less than 1.

[0025] Compared with the prior art, the present invention has the following advantages:

[0026] A storage unit provided by an embodiment of the present invention performs a data writing operation through a first writing circuit. When writing data, the data to be written to the first writing bit line WBLA is no longer directly transmitted to the transistors at both ends of the latch circuit, but is controlled by the third transistor, the fourth transistor, the fifth transistor, and the inverter at the front end of the fourth transistor and the fifth transistor to realize the storage operation of logic 0 or logic 1, so that the load of the first writing bit line WBLA becomes the inverter and M3. Compared with the traditional writing circuit, the load of the writing bit line does not have a latch with strong reverse driving capability, and the latch will no longer drive the writing bit line, so that data storage is more reliable and less prone to errors. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0028] Figure 1 It is a schematic diagram of a writing circuit in a storage unit in the prior art;

[0029] Figure 2 is a schematic diagram of a first storage unit in an embodiment of the present invention;

[0030] Figure 3 is a schematic diagram of a second storage unit in an embodiment of the present invention;

[0031] Figure 4 is a schematic diagram of a third storage unit in an embodiment of the present invention;

[0032] Figure 5 is a schematic diagram of a fourth storage unit in an embodiment of the present invention;

[0033] Figure 6 is a schematic diagram of a fifth storage unit in an embodiment of the present invention;

[0034] Figure 7 is a schematic diagram of a reading circuit of a storage unit in an embodiment of the present invention;

[0035] Figure 8 is a schematic diagram of another reading circuit of a storage unit in an embodiment of the present invention;

[0036] Fig. 9 is a schematic diagram of a sixth storage unit in an embodiment of the present invention;

[0037] Fig.10 is a schematic diagram of the structure of a first memory in an embodiment of the present invention;

[0038] Fig.11 is a schematic diagram of the structure of a second memory in an embodiment of the present invention;

[0039] Fig.12 It is a schematic diagram of the structure of the third memory in the embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] Reference Figure 2 , an embodiment of the present invention provides a storage unit, the storage unit comprising: a first write circuit 10 and a latch circuit 11;

[0042] The first write circuit 10 includes a first write word line WWLAM, a first write bit line WBLA, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a fifth transistor M5; the first write word line WWLAM is connected to the control pins of the first transistor M1 and the second transistor M2; the first write bit line WBLA is connected to the control pins of the third transistor M3, the fourth transistor M4 and the fifth transistor M5, and an inverter I3 is connected to the line from the first write bit line WBLA to the fourth transistor M4 and the fifth transistor M5; the input pin of the third transistor M3 is connected to the control pin of the third transistor M3; the input pin of the third transistor M3 is connected to the control pin of the fourth transistor M4 and the fifth transistor M5; the first write word line WWLAM is connected to the control pin of the third transistor M1 and the second transistor M2; the first write bit line WBLA is connected to the control pin of the third transistor M3, the fourth transistor M4 and the fifth transistor M5; the input pin of the third transistor M3 is connected to the control pin of the third transistor M3; the first write bit line WBLA is connected to the control pin of the third transistor M3, the fourth transistor M4 and the fifth transistor M5; the first write word line WWLAM is connected to the control pin of the third transistor M1 and the second transistor M2; the first write bit line WBLA is connected to the control pin of the third transistor M3, the fourth transistor M4 and the fifth transistor M5; the first write bit line WBLA is connected to the control pin of the third transistor M3 The pin is grounded, the output pin of the third transistor M3 is connected to the input pin of the first transistor M1, and the input pin of the first transistor M1 is also connected to the control pins of the fourth transistor M4 and the fifth transistor M5; the input pin of the fourth transistor M4 is grounded, and the output pin of the fourth transistor M4 is connected to the input pin of the second transistor M2; the input pin of the fifth transistor M5 is connected to the power supply, and the output pin of the fifth transistor M5 is connected to the input pin of the second transistor M2; the latch circuit 11 is connected between the output pin of the first transistor M1 and the output pin of the second transistor M2.

[0043] Specifically, in the embodiment of the present invention, the conventional write port of the storage unit is improved and redesigned to obtain a Figure 2 The storage unit shown in FIG. 1 includes: a first write circuit 10 and a latch circuit 11. The first write circuit 10 is a circuit for controlling the data write operation. After the data is written from the first write circuit 10, it can be stored by the latch circuit 11.

[0044] Combination Figure 2 As shown in the figure, the first write circuit 10 includes a first write word line WWLAM, a first write bit line WBLA, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4 and a fifth transistor M5. It should be noted that the write word line is the write address. When the signal of the write word line is 1, it indicates that the write word line is valid. At this time, the transistor connected to the corresponding write word line is in the on state. Conversely, when the signal of the write word line is 0, it indicates that the write word line is invalid, and the transistor is in the off state. The write bit line is the write data. When the write word line is valid, the logic 1 or logic 0 corresponding to the write bit line can be stored in the latch circuit connected to the write circuit. It is easy to understand that the write word line controls which address to write data to, and the write bit line controls the specific data written.

[0045] The first transistor M1 to the fifth transistor M5 used in the embodiment of the present invention may be triodes or MOS transistors with three pins, which may be switched between on and off states under the control of control signals, thereby storing data in a latch circuit of a corresponding address.

[0046] Combination Figure 2 As shown in the figure, the first write word line WWLAM is connected to the control pins of the first transistor M1 and the second transistor M2, and the first write word line WWLAM can control the on-off state of the first transistor M1 and the second transistor M2 by sending signals to the control pins of the first transistor M1 and the second transistor M2. For example, when the first write word line WWLAM sends a signal 1 to the first transistor M1 and the second transistor M2, the first transistor M1 and the second transistor M2 can be in the on state, and when the first write word line WWLAM sends a signal 0 to the first transistor M1 and the second transistor M2, the first transistor M1 and the second transistor M2 can be in the off state.

[0047] The first write bit line WBLA is connected to the control pins of the third transistor M3, the fourth transistor M4, and the fifth transistor M5, and an inverter I3 is connected to the line from the first write bit line WBLA to the fourth transistor M4 and the fifth transistor M5. The first write bit line WBLA can control the on-off state of the third transistor M3 by directly sending a signal to the control pin of the third transistor M3, and the signal of the first write bit line WBLA can control the on-off state of the fourth transistor M4 and the fifth transistor M5 after being inverted.

[0048] The input pin of the third transistor M3 is grounded, the output pin of the third transistor M3 is connected to the input pin of the first transistor M1, and the input pin of the first transistor M1 is also connected to the control pins of the fourth transistor M4 and the fifth transistor M5. When the third transistor M3 is turned on, the third transistor M3 can transmit a low-level signal 0 to the TF end of the latch circuit 11 through the first transistor M1. The signal of the first write bit line WBLA is transmitted to the control pins of the fourth transistor M4 and the fifth transistor M5 after inversion processing, and is also transmitted to the input pin of the first transistor M1. At this time, if the third transistor M3 is turned off, the inverted signal of the first write bit line WBLA can be transmitted to the TF end of the latch circuit 11 through the first transistor M1.

[0049] The input pin of the fourth transistor M4 is grounded, and the output pin of the fourth transistor M4 is connected to the input pin of the second transistor M2. The input pin of the fifth transistor M5 is connected to the power supply, and the output pin of the fifth transistor M5 is connected to the input pin of the second transistor M2. When the fourth transistor M4 is turned on and the fifth transistor M5 is turned off, the fourth transistor M4 can transmit a low-level signal 0 to the TR end of the latch circuit 11 through the second transistor M2. When the fourth transistor M4 is turned off and the fifth transistor M5 is turned on, the fifth transistor M5 can transmit a high-level signal 1 to the TR end of the latch circuit 11 through the second transistor M2. It should be noted that the signals at both ends of the latch circuit 11 are inverted signals to each other, and can maintain a stable state of 0 or 1, so it can be used to store data.

[0050] Therefore, in the storage unit of the embodiment of the present invention, a new data write port is designed, and this data write port relies on the first write circuit to perform data write operation. When writing data, the data to be written to the first write bit line WBLA is no longer directly transmitted to the transistors at both ends of the latch circuit, but through the control of the third transistor, the fourth transistor, the fifth transistor and the inverter at the front end of the fourth transistor and the fifth transistor, the storage operation of logic 0 or logic 1 is realized, so that the load of the first write bit line WBLA becomes the inverter and M3. Compared with the traditional write circuit, the load of the write bit line does not have a latch with strong reverse driving ability, and the latch will no longer drive the write bit line, so that data storage is more reliable and less prone to errors.

[0051] Optionally, refer to Figure 3 , the storage unit further includes a second write circuit 12;

[0052] The second write circuit 12 includes a second write word line WWLB, a second write bit line WBLB, a sixth transistor M6 and a seventh transistor M7; the second write word line WWLB is connected to the control pins of the sixth transistor M6 and the seventh transistor M7, the second write bit line WBLB is connected to the input pin of the sixth transistor M6 and the input pin of the seventh transistor M7, the latch circuit 11 is connected between the output pins of the sixth transistor M6 and the seventh transistor M7, and an inverter I4 is connected to the line from the second write bit line WBLB to the seventh transistor M7.

[0053] Specifically, if Figure 3 As shown in FIG. 1 , another storage unit according to an embodiment of the present invention may further include a second write circuit 12, wherein the second write circuit 12 and the first write circuit 10 are circuits corresponding to two different write data ports on the same storage unit. Figure 3As shown in FIG. 1 , the second write circuit 12 includes a second write word line WWLB, a second write bit line WBLB, a sixth transistor M6, and a seventh transistor M7. The second write word line WWLB is connected to the control pins of the sixth transistor M6 and the seventh transistor M7.

[0054] The second write word line WWLB can control the on-off state of the sixth transistor M6 and the seventh transistor M7 by sending a signal to the control pins of the sixth transistor M6 and the seventh transistor M7. For example, when the second write word line WWLB sends a signal 1 to the sixth transistor M6 and the seventh transistor M7, the sixth transistor M6 and the seventh transistor M7 can be in an on state, and when the second write word line WWLB sends a signal 0 to the sixth transistor M6 and the seventh transistor M7, the sixth transistor M6 and the seventh transistor M7 can be in an off state.

[0055] The second write bit line WBLB is connected to the input pin of the sixth transistor M6 and the input pin of the seventh transistor M7. A latch circuit 11 is connected between the output pins of the sixth transistor M6 and the seventh transistor M7. Another inverter I4 is connected to the line from the second write bit line WBLB to the seventh transistor M7. The data to be written to the second write bit line WBLB is transmitted to the TR end of the latch circuit 11 through the sixth transistor M6, and the data to be written to the second write bit line WBLB is transmitted to the TF end of the latch circuit 11 through the inverter I4 and the seventh transistor M7. Thus, the conventional way of writing and storing data can be realized. It should be noted that when the latch circuit 11 connected to the first write circuit 10 and the second write circuit 12 is the same latch, the first write circuit 10 and the second write circuit 12 can perform write operations at different times. The first write circuit 10 and the second write circuit 12 can respectively provide two write speed requirements, high speed and low speed, to meet the needs of different usage scenarios.

[0056] Optionally, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are triodes or MOS transistors.

[0057] Specifically, in an embodiment of the present invention, each transistor used has a switch function. When each switch is combined in different states, the latch circuit can be isolated from the first write bit line WBLA. In practical applications, the transistor with a switch function can be a triode or a MOS tube. In addition, NPN triodes, PNP triodes or NMOS tubes, PMOS tubes can be selected according to circuit requirements. It is easy to understand that when a triode is used, the base of the triode is the control pin of the transistor, one of the collector and the emitter is an input pin, and the other is an output pin. When a MOS tube is used, the gate of the MOS tube is the control pin of the transistor, one of the source and the drain is an input pin, and the other is an output pin.

[0058] Optionally, refer to Figure 4 , the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the sixth transistor M6 and the seventh transistor M7 are NMOS transistors, and the fifth transistor M5 is a PMOS transistor;

[0059] The first write word line WWLAM is connected to the gates G of the first transistor M1 and the second transistor M2; the first write bit line WBLA is connected to the gates G of the third transistor M3, the fourth transistor M4 and the fifth transistor M5; the drain D of the third transistor M3 is grounded, the source S of the third transistor M3 is connected to the drain D of the first transistor M1, and the drain D of the first transistor M1 is also connected to the gates G of the fourth transistor M4 and the fifth transistor M5; the drain D of the fourth transistor M4 is grounded, and the source S of the fourth transistor M4 is connected to the drain D of the second transistor M2; the source S of the fifth transistor M5 is connected to the power supply VDD, and the drain S of the fifth transistor M5 is connected to the drain D of the second transistor M2; the latch circuit 11 is connected between the source S of the first transistor M1 and the source S of the second transistor M2;

[0060] The second write word line WWLB is connected to the gates G of the sixth transistor M6 and the seventh transistor M7, the second write bit line WBLB is connected to the drain D of the sixth transistor M6 and to the drain D of the seventh transistor M7, and the latch circuit 11 is connected between the sources of the sixth transistor M6 and the seventh transistor M7.

[0061] Specifically, in the embodiment of the present invention, when the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the sixth transistor M6 and the seventh transistor M7 are NMOS transistors, and the fifth transistor M5 is a PMOS transistor, the corresponding first write circuit 10 and the second write circuit 12 are as follows: Figure 4shown.

[0062] In the first write circuit 10, the first write word line WWLAM is connected to the gates G of the first transistor M1 and the second transistor M2, and the first write bit line WBLA is connected to the gates G of the third transistor M3, the fourth transistor M4, and the fifth transistor M5. The drain D of the third transistor M3 is grounded, the source S of the third transistor M3 is connected to the drain D of the first transistor M1, and the drain D of the first transistor M1 is also connected to the gates G of the fourth transistor M4 and the fifth transistor M5. The drain D of the fourth transistor M4 is grounded, and the source S of the fourth transistor M4 is connected to the drain D of the second transistor M2. The source S of the fifth transistor M5 is connected to the power supply VDD, and the drain S of the fifth transistor M5 is connected to the drain D of the second transistor M2. A latch circuit 11 is connected between the source S of the first transistor M1 and the source S of the second transistor M2.

[0063] Therefore, when the first write word line WWLAM is a valid signal, the first transistor M1 and the second transistor M2 can be controlled to be turned on. When logic 0 needs to be stored, the signal of the first write bit line WBLA is set to 0. Under the action of the first write bit line WBLA, the third transistor M3 is turned off. The signal of the first write bit line WBLA is inverted by the inverter I3 and becomes 1. The fourth transistor M4 can be controlled to be turned on and the fifth transistor M5 can be controlled to be turned off. At this time, the input pin of the first transistor M1 can obtain the inverted signal 1 output from the inverter I3 from the gate G of the fourth transistor M4. The output pin of the first transistor M1 transmits the signal 1 to the TF terminal of the latch circuit 11. At the same time, after the input pin of the fourth transistor M4 is grounded, the low-level signal 0 can be transmitted to the TR terminal of the latch circuit 11 through the second transistor M2, thereby completing the storage process of logic 0.

[0064] When logic 1 needs to be stored, the signal of the first write bit line WBLA is set to 1. Under the action of the first write bit line WBLA, the third transistor M3 is turned on, and the signal of the first write bit line WBLA becomes 0 after being inverted by the inverter I3. The fourth transistor M4 can be controlled to be disconnected, and the fifth transistor M5 can be controlled to be turned on. At this time, the input pin of the first transistor M1 can obtain the low-level signal 0 from the ground terminal through the third transistor M3, and the output pin of the first transistor M1 transmits the signal 0 to the TF terminal of the latch circuit 11. At the same time, the fifth transistor M5 can transmit the high-level signal 1 of the power supply to the TR terminal of the latch circuit 11 through the second transistor M2, thereby completing the storage process of logic 1.

[0065] Optionally, refer to Figure 5 , the first write bit line WBLA and the second write bit line WBLB share the same port.

[0066] Specifically, in the embodiment of the present invention, both the first write bit line WBLA and the second write bit line WBLB are used to write storage data into the latch circuit 11. Figure 5 As shown in the figure, the first write bit line WBLA and the second write bit line WBLB can share the same port. At this time, the signal of the first write bit line WBLA or the second write bit line WBLB can be inverted by the inverter I3 and then transmitted to the fourth transistor M4 and the fifth transistor M5. The signal of the first write bit line WBLA or the second write bit line WBLB can also be inverted by the inverter I3 and transmitted to the seventh transistor M7. Data storage is completed when the first write word line WWLAM and the second write word line WWLB are respectively valid. This structure of sharing a write bit line port can obviously save the number of inverters, reduce circuit overhead, and save circuit power consumption.

[0067] Optionally, refer to Figure 6 , the storage unit includes at least two of the first writing circuits 10 and at least two of the second writing circuits 12.

[0068] Specifically, if Figure 6 As shown, in one implementation, the above-mentioned storage unit may include at least two first write circuits 10 and at least two second write circuits 12. The two first write circuits 10 may form two corresponding first write ports A, and the two second write circuits 12 may form two corresponding second write ports B. When storing data, both the first write circuit 10 and the second write circuit 12 may be used. Similar to the aforementioned embodiment, in this storage unit, when the first write bit line WBLA and the second write bit line WBLB share the same port, the number of ports can be effectively saved and the circuit overhead can be reduced.

[0069] Optionally, refer to Figure 7 , the storage unit further includes a reading circuit 13;

[0070] The read circuit 13 includes a read word line RWL, a read bit line RBL, an eighth transistor M8 and a ninth transistor M9;

[0071] The read word line RWL is connected to the control pin of the eighth transistor M8, the read bit line RBL is connected to the output pin of the eighth transistor M8, the control pin of the ninth transistor M9 is connected to the latch circuit 11, the output pin of the ninth transistor M9 is connected to the input pin of the eighth transistor M8, and the input pin of the ninth transistor M9 is grounded.

[0072] Specifically, if Figure 8As shown, in one implementation, the memory cell of the embodiment of the present invention further includes a read circuit 13, and the read circuit 13 is used to read the stored data from the latch circuit 11. The read circuit 13 includes a read word line RWL, a read bit line RBL, an eighth transistor M8, and a ninth transistor M9. The read word line RWL is used to select the corresponding latch circuit 11, and then the data at the TR end of the latch circuit 11 is read through the read bit line RBL and the corresponding transistor.

[0073] Combination Figure 8 As shown in the figure, the read word line RWL is connected to the control pin of the eighth transistor M8. When the read word line RWL is valid, the eighth transistor M8 is turned on. When the TR end of the latch circuit 11 is 0 or 1, the ninth transistor M9 can be controlled to be turned on or off respectively. When the eighth transistor M8 is turned on, the read bit line RBL can read the data from the TR end. When the read bit line RBL is pre-charged to 1, if the ninth transistor M9 is turned on, it means that the stored data is 1, and the read bit line RBL reads 1; if the ninth transistor M9 is turned off and disconnected, it means that the stored data is 0, and the read bit line RBL reads 0. Similar to the aforementioned write circuit, the eighth transistor M8 and the ninth transistor M9 can be triodes or MOS tubes, and the description is not repeated here.

[0074] Optionally, refer to Figure 6 , the storage unit includes at least two reading circuits 13.

[0075] Specifically, if Figure 6 As shown, in one implementation, by providing two or more reading circuits 13 , the requirements for parallel reading and outputting of different data can be met, and the data reading efficiency can be improved.

[0076] Optionally, refer to Fig. 9 , the latch circuit 11 includes two independent first latches 111 and second latches 112;

[0077] The first latch 111 is connected between the output pins of the first transistor M1 and the second transistor M2 , and the second latch 112 is connected between the output pin of the sixth transistor M6 and the output pin of the seventh transistor M7 .

[0078] Specifically, if Fig. 9As shown, in one embodiment, the latch circuit 11 may include two independent first latches 111 and second latches 112. Each latch includes two connected inverter pairs, for example, the first latch 111 may include inverter I11 and inverter I21, and the second latch 112 may include inverter I12 and inverter I22. The first latch 111 is connected between the first transistor M1 and the second transistor M2, and the second latch 112 is connected between the sixth transistor M6 and the seventh transistor M7. Thus, by configuring two independent latches for the first write circuit 10 and the second write circuit 13, it is possible to store data using the first write circuit 10 and the second write circuit 13 at the same time, respectively, and the storage efficiency can be further improved. Of course, it is understandable that when the first write circuit 10 and the second write circuit 13 share the same latch, the write operation needs to be performed at different times.

[0079] Reference Figures 10 to 12 , an embodiment of the present invention further provides a static random access memory, the static random access memory comprising the aforementioned multiple storage units;

[0080] The plurality of storage cells are connected in an arrangement of m columns and n rows to form a storage array, wherein the storage cells in the same column share a bit line, and the storage cells in the same row share a word line, and m and n are both positive integers not less than 1.

[0081] In order to increase the storage capacity, two or more of the above-mentioned storage units can be connected to form a storage array with m columns and n rows. Fig.10 As shown in FIG. 1 , when m is 1, n memory cells are arranged in a row, and the n memory cells share the first write bit line WBLA and the second write bit line WBLB. Fig.11 As shown in FIG. 1 , when n is 1, m memory cells are arranged in a row, and the m memory cells share the first write word line WWLAM and the second write word line WWLB, and can also share the read word line RWL of the read circuit. Fig.12 As shown in FIG. 1 , when n and m are both greater than 1, all memory cells are arranged in a rectangular array, memory cells in the same column share a bit line, and memory cells in the same row share a word line.

[0082] Since the aforementioned first write circuit is adopted in the above-mentioned memory, within one working cycle, n first write word lines WWLAM can be effective at the same time, and data can be written into the corresponding latch circuit through the first write bit line WBLA, and storage errors will not occur, which can improve the efficiency and accuracy of writing data.

[0083] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

[0084] It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention, and these improvements and modifications should also be regarded as within the scope of protection of the present invention.

[0085] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0086] The above is a detailed introduction to a storage unit and a static random access memory provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the structure of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A storage unit, characterized in that: The memory cell comprises: a first write circuit and a latch circuit, wherein the first write circuit comprises a first write word line, a first write bit line, a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; The first write word line is connected to the control pins of the first transistor and the second transistor; The first write bit line is connected to the control pins of the third transistor, the fourth transistor and the fifth transistor, and an inverter is connected to the line from the first write bit line to the fourth transistor and the fifth transistor; the input pin of the third transistor is grounded, the output pin of the third transistor is connected to the input pin of the first transistor, and the input pin of the first transistor is also connected to the control pins of the fourth transistor and the fifth transistor; the input pin of the fourth transistor is grounded, and the output pin of the fourth transistor is connected to the input pin of the second transistor; the input pin of the fifth transistor is connected to a power supply, and the output pin of the fifth transistor is connected to the input pin of the second transistor; the latch circuit is connected between the output pin of the first transistor and the output pin of the second transistor.

2. The storage unit according to claim 1, characterized in that The storage unit also includes a second write circuit; The second write circuit includes a second write word line, a second write bit line, a sixth transistor and a seventh transistor; the second write word line is connected to the control pins of the sixth transistor and the seventh transistor, the second write bit line is connected to the input pin of the sixth transistor and to the input pin of the seventh transistor, the latch circuit is connected between the output pins of the sixth transistor and the seventh transistor, and an inverter is connected to the line from the second write bit line to the seventh transistor.

3. The storage unit according to claim 2, characterized in that The first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are triodes or MOS transistors.

4. The storage unit according to claim 3, characterized in that The first transistor, the second transistor, the third transistor, the fourth transistor, the sixth transistor and the seventh transistor are NMOS transistors, and the fifth transistor is a PMOS transistor; The first write word line is connected to the gates of the first transistor and the second transistor; the first write bit line is connected to the gates of the third transistor, the fourth transistor and the fifth transistor; the drain of the third transistor is grounded, the source of the third transistor is connected to the drain of the first transistor, and the drain of the first transistor is also connected to the gates of the fourth transistor and the fifth transistor; the drain of the fourth transistor is grounded, and the source of the fourth transistor is connected to the drain of the second transistor; the source of the fifth transistor is connected to a power supply, and the drain of the fifth transistor is connected to the drain of the second transistor; the latch circuit is connected between the source of the first transistor and the source of the second transistor; The second write word line is connected to the gates of the sixth transistor and the seventh transistor, the second write bit line is connected to the drain of the sixth transistor and the drain of the seventh transistor, and the latch circuit is connected between the sources of the sixth transistor and the seventh transistor.

5. The storage unit according to claim 2, characterized in that: The first write bit line and the second write bit line share a same port.

6. The storage unit according to claim 2, characterized in that: The memory cell includes at least two of the first write circuits and at least two of the second write circuits.

7. The storage unit according to claim 1, characterized in that The storage unit also includes a read circuit; The read circuit includes a read word line, a read bit line, an eighth transistor and a ninth transistor; The read word line is connected to the control pin of the eighth transistor, the read bit line is connected to the output pin of the eighth transistor, the control pin of the ninth transistor is connected to the latch, the output pin of the ninth transistor is connected to the input pin of the eighth transistor, and the input pin of the ninth transistor is grounded.

8. The storage unit according to claim 7, characterized in that The eighth transistor and the ninth transistor are both NMOS transistors; The read word line is connected to the gate of the eighth transistor, the read bit line is connected to the source of the eighth transistor, the gate of the ninth transistor is connected to the latch circuit, the source of the ninth transistor is connected to the drain of the eighth transistor, and the drain of the ninth transistor is grounded.

9. The storage unit according to claim 2, characterized in that: The latch circuit comprises two independent first latches and a second latch; The first latch is connected between output pins of the first transistor and the second transistor, and the second latch is connected between an output pin of the sixth transistor and an output pin of the seventh transistor.

10. A static random access memory, characterized in that: The static random access memory comprises the storage unit according to any one of claims 1 to 9; The plurality of storage cells are connected in an arrangement of m columns and n rows to form a storage array, wherein the storage cells in the same column share a bit line, and the storage cells in the same row share a word line, and m and n are both positive integers greater than 1.

Images