H bridge control system and method and storage medium

Abstract

The invention provides an H-bridge control system and method and a storage medium, and belongs to the field of power control, the H-bridge control system comprises a processor, an H-bridge circuit and a capacitor, and the H-bridge circuit is connected with the processor, two ends of the capacitor, a modulation wave input end and a modulation wave output end; the processor is used for importing an initial sine wave, performing waveform comparison on the initial sine wave and a preset triangular wave group, and controlling the H-bridge circuit to output a to-be-processed positive half-cycle waveform group and a to-be-processed negative half-cycle waveform group according to a comparison result; and analyzing the positive half-cycle waveform of the to-be-processed positive half-cycle waveform group, and controlling a modulation wave output end to output a target positive half-cycle waveform according to an analysis result. The frequency doubling effect is achieved, normal output can be guaranteed without adding a dead zone, local heating and voltage harmonic output are reduced, and the service life of the insulated gate bipolar transistor is prolonged.

Description

Technical Field

[0001] The present invention mainly relates to the field of power control technology, and in particular to an H-bridge control system, method and storage medium. Background Art

[0002] The unit modules of existing high-voltage equipment are designed with 4 single-tube IGBTs of H-bridge. Among them, the control methods are divided into unipolar modulation and bipolar modulation. Among them, the advantages of unipolar modulation are: the output waveform of unipolar modulation is completely symmetrical in the positive and negative half cycles, the waveform stability is good, the IGBT has no dead zone restriction, and there will be no situation where two IGBTs are turned on at the same time at any time. However, its disadvantages are as follows:

[0003] 1. Inconsistent IGBT temperature rise. The IGBTs are turned on inconsistently, resulting in inconsistent IGBT temperature rise. IGBT3 and IGBT4 only have on-state losses, and the temperature rise is relatively low. IGBT1 and IGBT 2 have two types of on-state and switching losses, and the power will be obviously inconsistent.

[0004] 2. Large harmonics at low frequencies. At low frequencies, the harmonic content of the output voltage of unipolar modulation is much larger than at high frequencies, which will lead to unsatisfactory output characteristics. Especially in high-voltage equipment, when the frequency of the IGBT used in the unit cannot be increased, the harmonic characteristics of the unit itself are very poor.

[0005] 3. Since the IGBT has only one switching working state at any time, the device utilization rate is very low, wasting resources.

[0006] The advantages of bipolar modulation are: bipolar modulation can increase the low-frequency output pulse, thereby improving the output characteristics, making it closer to the ideal square wave signal, and the control method is simple. However, its disadvantages are as follows:

[0007] 1. The output waveforms of the positive and negative half axes of bipolar modulation are not completely symmetrical, which will lead to the appearance of even harmonics and affect the output characteristics.

[0008] 2. The output harmonics are relatively large. Due to the asymmetric waveform, the output harmonics are large.

[0009] 3. When outputting, the IGBT needs to be configured with a dead zone. In order to prevent the direct conduction of the two IGBTs, a dead zone must be added. Small currents require 2us, while large currents may require more than 10us, which affects the integrity of the waveform. Summary of the invention

[0010] The technical problem to be solved by the present invention is to provide an H-bridge control system, method and storage medium in view of the deficiencies in the prior art.

[0011] The technical solution of the present invention to solve the above technical problems is as follows: an H-bridge control system includes a processor, an H-bridge circuit and a capacitor,

[0012] The H-bridge circuit is respectively connected to the processor, two ends of the capacitor, a modulation wave input end, and a modulation wave output end;

[0013] The processor is used to import an initial sine wave, compare the initial sine wave with a preset triangle wave group, and control the H-bridge circuit to output a positive half-cycle waveform group to be processed and a negative half-cycle waveform group to be processed according to the comparison result;

[0014] Performing positive half-cycle waveform analysis on the positive half-cycle waveform group to be processed, and controlling the modulation wave output end to output a target positive half-cycle waveform according to the analysis result;

[0015] Performing negative half-cycle waveform analysis on the negative half-cycle waveform group to be processed, and controlling the modulation wave input terminal to output a target negative half-cycle waveform according to the analysis result;

[0016] The target positive half-cycle waveform and the target negative half-cycle waveform are superimposed to obtain a target waveform.

[0017] Another technical solution of the present invention to solve the above technical problem is as follows: an H-bridge control method comprises the following steps:

[0018] Importing an initial sine wave, performing waveform comparison between the initial sine wave and a preset triangular wave group, and controlling the H-bridge circuit to output a positive half-cycle waveform group to be processed and a negative half-cycle waveform group to be processed according to the comparison result;

[0019] Performing positive half-cycle waveform analysis on the positive half-cycle waveform group to be processed, and controlling the modulation wave output terminal to output a target positive half-cycle waveform according to the analysis result;

[0020] Performing negative half-cycle waveform analysis on the negative half-cycle waveform group to be processed, and controlling the modulation wave input terminal to output a target negative half-cycle waveform according to the analysis result;

[0021] The target positive half-cycle waveform and the target negative half-cycle waveform are superimposed to obtain a target waveform.

[0022] The beneficial effects of the present invention are as follows: by comparing the waveform of the initial sine wave with the waveform of the preset triangle wave group, the H-bridge circuit is controlled to output the positive half-cycle waveform group to be processed and the negative half-cycle waveform group to be processed according to the comparison result, the positive half-cycle waveform of the positive half-cycle waveform group to be processed is analyzed, and the modulation wave output end is controlled to output the target positive half-cycle waveform according to the analysis result, the negative half-cycle waveform of the negative half-cycle waveform group to be processed is analyzed, and the modulation wave input end is controlled to output the target negative half-cycle waveform according to the analysis result, and the target waveform is obtained by superimposing the target positive half-cycle waveform and the target negative half-cycle waveform, thereby achieving the effect of frequency doubling, ensuring normal output without adding a dead zone, reducing local heating and voltage harmonic output, and increasing the life of the insulated gate bipolar transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 One of the structural block diagrams of an H-bridge control system provided by an embodiment of the present invention;

[0024] Figure 2 A schematic diagram of a target waveform of an H-bridge control system provided by an embodiment of the present invention;

[0025] Figure 3 A second structural block diagram of an H-bridge control system provided by an embodiment of the present invention;

[0026] Figure 4 A schematic diagram of a first positive half-cycle waveform to be processed output by a first insulated gate bipolar transistor of an H-bridge control system provided by an embodiment of the present invention;

[0027] Figure 5 A schematic diagram of a second positive half-cycle waveform to be processed output by a fourth insulated gate bipolar transistor of an H-bridge control system provided by an embodiment of the present invention;

[0028] Figure 6 A schematic diagram of a first negative half-cycle waveform to be processed output by a second insulated gate bipolar transistor of an H-bridge control system provided by an embodiment of the present invention;

[0029] Figure 7 A schematic diagram of a second negative half-cycle waveform to be processed output by a third insulated gate bipolar transistor of an H-bridge control system provided by an embodiment of the present invention;

[0030] Figure 8 A schematic diagram of a target positive half-cycle waveform of an H-bridge control system provided by an embodiment of the present invention;

[0031] Fig. 9 A schematic diagram of a target negative half-cycle waveform of an H-bridge control system provided by an embodiment of the present invention;

[0032] Fig.10A schematic diagram of waveform output of a first insulated gate bipolar transistor and a second insulated gate bipolar transistor of an H-bridge control system provided by an embodiment of the present invention;

[0033] Fig.11 A schematic diagram of waveform output of a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor of an H-bridge control system provided by an embodiment of the present invention;

[0034] Fig.12 A schematic flow chart of an H-bridge control method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The principles and features of the present invention are described below in conjunction with the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0036] Figure 1 A block diagram of an H-bridge control system according to an embodiment of the present invention.

[0037] like Figure 1 and 2 As shown, an H-bridge control system includes a processor, an H-bridge circuit and a capacitor.

[0038] The H-bridge circuit is respectively connected to the processor, two ends of the capacitor, a modulation wave input end, and a modulation wave output end;

[0039] The processor is used to import an initial sine wave, compare the initial sine wave with a preset triangle wave group, and control the H-bridge circuit to output a positive half-cycle waveform group to be processed and a negative half-cycle waveform group to be processed according to the comparison result;

[0040] Performing positive half-cycle waveform analysis on the positive half-cycle waveform group to be processed, and controlling the modulated wave output end to output a target positive half-cycle waveform according to the analysis result;

[0041] Performing negative half-cycle waveform analysis on the negative half-cycle waveform group to be processed, and controlling the modulation wave input terminal to output a target negative half-cycle waveform according to the analysis result;

[0042] The target positive half-cycle waveform and the target negative half-cycle waveform are superimposed to obtain a target waveform.

[0043] It should be understood that the H-bridge circuit is respectively connected to the processor, two ends of the capacitor C1, a modulation wave input terminal IN, and a modulation wave output terminal OUT.

[0044] Specifically, a sine wave (ie, target waveform) is synthesized from the upper half waveform (ie, target positive half waveform) and the lower half waveform (ie, target negative half waveform) of the sine wave by time-division subtraction.

[0045] In the above embodiment, by comparing the initial sine wave with the waveform of the preset triangle wave group, the H-bridge circuit is controlled to output the positive half-cycle waveform group to be processed and the negative half-cycle waveform group to be processed according to the comparison result, the positive half-cycle waveform of the positive half-cycle waveform group to be processed is analyzed, and the modulation wave output end is controlled to output the target positive half-cycle waveform according to the analysis result, the negative half-cycle waveform of the negative half-cycle waveform group to be processed is analyzed, and the modulation wave input end is controlled to output the target negative half-cycle waveform according to the analysis result, and the target positive half-cycle waveform and the target negative half-cycle waveform are superimposed to obtain the target waveform, thereby achieving the effect of frequency doubling, ensuring normal output without adding a dead zone, reducing local heat and voltage harmonic output, and increasing the life of the insulated gate bipolar transistor.

[0046] Optionally, as an embodiment of the present invention, Figure 1 and 3 As shown, the H-bridge circuit includes a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor:

[0047] The gate of the first insulated gate bipolar transistor is connected to the first port of the processor, the collector of the first insulated gate bipolar transistor is respectively connected to the collector of the third insulated gate bipolar transistor and one end of the capacitor, the emitter of the first insulated gate bipolar transistor is respectively connected to the modulation wave input end and the collector of the second insulated gate bipolar transistor, the gate of the second insulated gate bipolar transistor is connected to the second port of the processor, the emitter of the second insulated gate bipolar transistor is respectively connected to the other end of the capacitor and the emitter of the fourth insulated gate bipolar transistor, the gate of the third insulated gate bipolar transistor is connected to the third port of the processor, the emitter of the third insulated gate bipolar transistor is respectively connected to the modulation wave output end and the collector of the fourth insulated gate bipolar transistor, and the gate of the fourth insulated gate bipolar transistor is connected to the fourth port of the processor.

[0048] Specifically, Figure 3As shown, the gate of the first insulated gate bipolar transistor I GBT1 is connected to the first port of the processor, the collector of the first insulated gate bipolar transistor I GBT1 is respectively connected to the collector of the third insulated gate bipolar transistor I GBT3 and one end of the capacitor C1, the emitter of the first insulated gate bipolar transistor I GBT1 is respectively connected to the modulation wave input terminal IN and the collector of the second insulated gate bipolar transistor I GBT2, the gate of the second insulated gate bipolar transistor I GBT2 is connected to the second port of the processor, the emitter of the second insulated gate bipolar transistor I GBT2 is respectively connected to the other end of the capacitor C1 and the emitter of the fourth insulated gate bipolar transistor IGBT4, the gate of the third insulated gate bipolar transistor I GBT3 is connected to the third port of the processor, the emitter of the third insulated gate bipolar transistor I GBT3 is respectively connected to the modulation wave output terminal OUT and the collector of the fourth insulated gate bipolar transistor I GBT4, and the gate of the fourth insulated gate bipolar transistor I GBT4 is connected to the fourth port of the processor.

[0049] In the above embodiment, the frequency doubling effect can be achieved through the first insulated gate bipolar transistor, the second insulated gate bipolar transistor, the third insulated gate bipolar transistor and the fourth insulated gate bipolar transistor, and normal output can be guaranteed without adding a dead zone, thereby reducing local heat and voltage harmonic output and increasing the life of the insulated gate bipolar transistor.

[0050] Optionally, as an embodiment of the present invention, in the processor, the process of performing waveform comparison between the initial sine wave and the preset triangle wave group, and controlling the H-bridge circuit to output the positive half-cycle waveform group to be processed and the negative half-cycle waveform group to be processed according to the comparison result includes:

[0051] Determine whether the first initial sine wave data point of the initial sine wave is greater than 0, if so, execute the first solution; if not, execute the second solution;

[0052] The initial sine wave includes an initial sine wave positive half cycle and an initial sine wave negative half cycle;

[0053] Among them, the first solution is:

[0054] Compare the waveforms of the positive half cycle of the initial sine wave with the preset triangular wave group, control the first insulated gate bipolar transistor to output a first positive half cycle waveform to be processed according to a first comparison result, and control the fourth insulated gate bipolar transistor to output a second positive half cycle waveform to be processed according to the first comparison result;

[0055] Compare the negative half cycle of the initial sine wave with the negative half cycle of the preset triangle wave group, control the second insulated gate bipolar transistor to output a first negative half cycle waveform to be processed according to a second comparison result, and control the third insulated gate bipolar transistor to output a second negative half cycle waveform to be processed according to the second comparison result;

[0056] The second solution is:

[0057] Compare the negative half cycle of the initial sine wave with the negative half cycle of the preset triangle wave group, control the second insulated gate bipolar transistor to output the first negative half cycle waveform to be processed according to a second comparison result, and control the third insulated gate bipolar transistor to output the second negative half cycle waveform to be processed according to a second comparison result;

[0058] Compare the waveforms of the positive half cycle of the initial sine wave with the preset triangular wave group, control the first insulated gate bipolar transistor to output the first to-be-processed positive half cycle waveform according to a first comparison result, and control the fourth insulated gate bipolar transistor to output the second to-be-processed positive half cycle waveform according to the first comparison result;

[0059] The positive half-cycle waveform group to be processed includes the first positive half-cycle waveform to be processed and the second positive half-cycle waveform to be processed, and the negative half-cycle waveform group to be processed includes the first negative half-cycle waveform to be processed and the second negative half-cycle waveform to be processed.

[0060] In the above embodiment, the initial sine wave is compared with the preset triangle wave group, and the H-bridge circuit is controlled to output the positive half-cycle waveform group to be processed and the negative half-cycle waveform group to be processed according to the comparison result, which can achieve the effect of frequency doubling, and can ensure normal output without adding a dead zone, thereby reducing local heating and voltage harmonic output, and increasing the life of the insulated gate bipolar transistor.

[0061] Optionally, as an embodiment of the present invention, Figures 1 to 5 As shown, the preset triangle wave group includes initial triangle wave data points at multiple moments and flip triangle wave data points at multiple moments, and the initial sine wave positive half cycle includes sine wave positive half cycle data points at multiple moments.

[0062] In the processor, the process of comparing the positive half cycle of the initial sine wave with the positive half cycle of the preset triangle wave group, controlling the first insulated gate bipolar transistor to output a first positive half cycle waveform to be processed according to a first comparison result, and controlling the fourth insulated gate bipolar transistor to output a second positive half cycle waveform to be processed according to the first comparison result includes:

[0063] At each moment, determine whether the positive half-cycle data point of the sine wave is greater than the initial triangular wave data point; if so, control the first insulated gate bipolar transistor to output a first preset value; if not, control the first insulated gate bipolar transistor to output a second preset value, until all the positive half-cycle data points of the sine wave corresponding to all moments are compared, and all output results are plotted as the first positive half-cycle waveform to be processed;

[0064] For each moment, determine whether the positive half-cycle data point of the sine wave is greater than the flipped triangle wave data point. If so, control the fourth insulated gate bipolar transistor to output the first preset value; if not, control the fourth insulated gate bipolar transistor to output the second preset value, until the positive half-cycle data points of the sine wave corresponding to all moments are compared, and all output results are plotted as the second positive half-cycle waveform to be processed.

[0065] Preferably, the first preset value is 1, and the second preset value is 0.

[0066] Specifically, the output waveform of IGBT1 (i.e., the first positive half-cycle waveform to be processed) is formed by the superposition of a positive half-cycle of a sine wave (i.e., the positive half-cycle of the initial sine wave) and a (1 to -1) triangle wave (i.e., the initial triangle wave data points at multiple moments); the output waveform of IGBT4 (i.e., the second positive half-cycle waveform to be processed) is formed by the superposition of a positive half-cycle of a sine wave (i.e., the positive half-cycle of the initial sine wave) and a flipped triangle wave waveform (i.e., the flipped triangle wave data points at multiple moments).

[0067] It should be understood that if Figure 4 As shown, IGBT1 is a PWM waveform (ie, the first positive half-cycle waveform to be processed), which is formed by comparing the positive half-cycle of a sine wave (ie, the positive half-cycle of an initial sine wave) and a triangle wave (1 to -1) (ie, the initial triangle wave data points at multiple moments).

[0068] It should be understood that if Figure 5 As shown, IGBT4 is a PWM waveform (ie, the second positive half-cycle waveform to be processed), which is formed by comparing the positive half-cycle of the sine wave (ie, the initial positive half-cycle of the sine wave) and the triangle wave (1 to -1) (ie, the flipped triangle wave data points at multiple moments).

[0069] In the above embodiment, the positive half-cycle of the initial sinusoidal wave is compared with the positive half-cycle waveform of the preset triangle wave group, and the first insulated gate bipolar transistor is controlled to output the first positive half-cycle waveform to be processed according to the first comparison result, and the fourth insulated gate bipolar transistor is controlled to output the second positive half-cycle waveform to be processed according to the first comparison result, which can achieve the effect of frequency doubling, ensure normal output without adding a dead zone, and reduce local heating and voltage harmonic output.

[0070] Optionally, as an embodiment of the present invention, Figures 1 to 7As shown, the initial negative half cycle of the sine wave includes negative half cycle data points of the sine wave at multiple moments.

[0071] In the processor, the process of comparing the negative half cycle of the initial sine wave with the negative half cycle of the preset triangle wave group, controlling the second insulated gate bipolar transistor to output the first negative half cycle waveform to be processed according to the second comparison result, and controlling the third insulated gate bipolar transistor to output the second negative half cycle waveform to be processed according to the second comparison result includes:

[0072] At each moment, determine whether the negative half-cycle data point of the sine wave is greater than the initial triangular wave data point; if so, control the second insulated gate bipolar transistor to output the second preset value; if not, control the second insulated gate bipolar transistor to output the first preset value, until the negative half-cycle data points of the sine wave corresponding to all moments are compared, and all output results are plotted as the first negative half-cycle waveform to be processed;

[0073] For each moment, determine whether the negative half-cycle data point of the sine wave is greater than the flipped triangle wave data point. If so, control the third insulated gate bipolar transistor to output the second preset value; if not, control the third insulated gate bipolar transistor to output the first preset value, until the negative half-cycle data points of the sine wave corresponding to all moments are compared, and all output results are plotted as the second negative half-cycle waveform to be processed.

[0074] Preferably, the first preset value is 1, and the second preset value is 0.

[0075] Specifically, the output waveform of IGBT2 (i.e., the first negative half-cycle waveform to be processed) is formed by the superposition of the negative half-cycle of the sine wave (i.e., the negative half-cycle of the initial sine wave) and the (1 to -1) triangle wave (i.e., the initial triangle wave data points at multiple moments); the output waveform of IGBT3 (i.e., the second negative half-cycle waveform to be processed) is formed by the superposition of the negative half-cycle of the sine wave (i.e., the negative half-cycle of the initial sine wave) and the flipped triangle wave waveform (i.e., the flipped triangle wave data points at multiple moments).

[0076] It should be understood that if Figure 6 As shown, IGBT2 is a PWM waveform (i.e., the first negative half-cycle waveform to be processed), which is formed by comparing the negative half-cycle of the sine wave (i.e., the negative half-cycle of the initial sine wave) and the triangle wave (1 to -1) (i.e., the initial triangle wave data points at multiple moments).

[0077] It should be understood that if Figure 7 As shown, IGBT3 is a PWM waveform (i.e., the second negative half-cycle waveform to be processed), which is formed by comparing the negative half-cycle of the sine wave (i.e., the negative half-cycle of the initial sine wave) and the triangle wave (1 to -1) (i.e., the flipped triangle wave data points at multiple moments).

[0078] In the above embodiment, the negative half-cycle of the initial sine wave is compared with the negative half-cycle waveform of the preset triangle wave group, and the second insulated gate bipolar transistor is controlled to output the first negative half-cycle waveform to be processed according to the second comparison result, and the third insulated gate bipolar transistor is controlled to output the second negative half-cycle waveform to be processed according to the second comparison result, which can achieve the effect of frequency doubling, ensure normal output without adding a dead zone, and reduce local heating and voltage harmonic output.

[0079] Optionally, as an embodiment of the present invention, Figure 8 As shown, the first to-be-processed positive half-cycle waveform includes first to-be-processed positive half-cycle data points at multiple moments, and the second to-be-processed positive half-cycle waveform includes second to-be-processed positive half-cycle data points at multiple moments.

[0080] In the processor, a process of performing positive half-cycle waveform analysis on the positive half-cycle waveform group to be processed, and controlling the modulated wave output end to output a target positive half-cycle waveform according to the analysis result includes:

[0081] For each moment, determine whether the first to-be-processed positive half-cycle data point and the second to-be-processed positive half-cycle data point are both first preset values. If so, control the modulated wave output end to output the first preset value; if not, control the modulated wave output end to output the second preset value, until all moments corresponding to the first to-be-processed positive half-cycle data points are determined, and all output results are plotted as the target positive half-cycle waveform.

[0082] Preferably, the first preset value is 1, and the second preset value is 0.

[0083] Specifically, the positive half-cycle waveform of the sine wave (i.e., the target positive half-cycle waveform) is formed by superimposing IGBT1 (i.e., the first positive half-cycle waveform to be processed) and IGBT4 (i.e., the second positive half-cycle waveform to be processed), and its switching frequency is twice that of IGBT1 or IGBT4.

[0084] Specifically, the upper half-cycle waveform of the sine wave (i.e., the target positive half-cycle waveform) is synthesized by IGBT1 (i.e., the first positive half-cycle waveform to be processed) and IGBT4 (i.e., the second positive half-cycle waveform to be processed). When both IGBT1 (i.e., the first positive half-cycle waveform to be processed) and IGBT4 (i.e., the second positive half-cycle waveform to be processed) are 1, a 1 signal can be output; if either one is 0.

[0085] In the above embodiment, a positive half-cycle waveform analysis is performed on the positive half-cycle waveform group to be processed, and the modulated wave output end is controlled to output the target positive half-cycle waveform according to the analysis result, which can achieve the effect of frequency doubling, ensure normal output without adding a dead zone, and reduce local heating and voltage harmonic output.

[0086] Optionally, as an embodiment of the present invention, Fig. 9 As shown, the first negative half-cycle waveform to be processed includes first negative half-cycle data points to be processed at multiple moments, and the second negative half-cycle waveform to be processed includes second negative half-cycle data points to be processed at multiple moments.

[0087] In the processor, a process of performing negative half-cycle waveform analysis on the negative half-cycle waveform group to be processed, and controlling the modulation wave input terminal to output a target negative half-cycle waveform according to the analysis result includes:

[0088] For each moment, determine whether the first negative half-cycle data point to be processed and the second negative half-cycle data point to be processed are both the first preset value. If so, control the modulation wave output end to output the third preset value; if not, control the modulation wave output end to output the second preset value, until the first negative half-cycle data points to be processed corresponding to all moments are determined, and all output results are plotted as the target negative half-cycle waveform.

[0089] Preferably, the first preset value is 1, the second preset value is 0, and the third preset value is -1.

[0090] Specifically, the negative half-cycle waveform of the sine wave (i.e., the target negative half-cycle waveform) is formed by superimposing IGBT2 (i.e., the first negative half-cycle waveform to be processed) and IGBT3 (i.e., the second negative half-cycle waveform to be processed), and its switching frequency is twice that of IGBT2 or IGBT3.

[0091] Specifically, the second half-cycle waveform of the sine wave (i.e., the target negative half-cycle waveform) is synthesized by IGBT2 (i.e., the first negative half-cycle waveform to be processed) and IGBT3 (i.e., the second negative half-cycle waveform to be processed). When both IGBT2 (i.e., the first negative half-cycle waveform to be processed) and IGBT3 (i.e., the second negative half-cycle waveform to be processed) are 1, a 1 signal can be output; if any one of them is 0, a 0 is output.

[0092] In the above embodiment, a negative half-cycle waveform analysis is performed on the negative half-cycle waveform group to be processed, and the modulation wave input end is controlled to output the target negative half-cycle waveform according to the analysis result, thereby achieving a frequency doubling effect. Normal output can be guaranteed without adding a dead zone, reducing local heat and voltage harmonic output, and increasing the life of the insulated gate bipolar transistor.

[0093] Optionally, as another embodiment of the present invention, the present invention uses carrier flipping technology to realize the opening and closing of two IGBTs in the same cycle, and avoids the direct conduction of the upper and lower bridge arms through phase switching technology. At the same time, each IGBT of the present invention has a wave control circuit to control the opening and closing of the IGBT respectively.

[0094] Optionally, as another embodiment of the present invention, the control strategy of the present invention is as follows: IGBT1 and IGBT4 work in the first half cycle of the sine wave, and IGBT2 and IGBT4 work in the second half cycle.

[0095] Optionally, as another embodiment of the present invention, Fig.10 and 11 As shown, observe the waveforms of 4 IGBTs, i.e., IGBT1, 2, 3, and 4. IGBT1 and IGBT2 are IGBTs with the same bridge wall. As can be seen from the figure, they cannot be directly connected at any time, and no dead zone is required; IGBT3 and IGBT4 are IGBTs with the same bridge wall. As can be seen from the figure, they cannot be directly connected at any time, and no dead zone is required. Therefore, the waveform will be smoother.

[0096] Optionally, as another embodiment of the present invention, IGBT1 and IGBT2 of the present invention are IGBTs with the same bridge wall, so they cannot be directly turned on at any time, and no dead zone is added; IGBT3 and IGBT4 are IGBTs with the same bridge wall, so they cannot be directly turned on at any time, and no dead zone is added. Therefore, the waveform will be smoother.

[0097] Optionally, as another embodiment of the present invention, the beneficial effects of the present invention are as follows:

[0098] 1. The frequency doubling effect is achieved by superimposing two low-frequency IGBTs

[0099] 2. The upper and lower bridge walls cannot be directly connected permanently, and normal output can be guaranteed without adding dead zones.

[0100] 3. Each IGBT is turned on almost the same number of times, reducing the problem of local heating

[0101] 4. Increase IGBT control frequency and reduce voltage harmonic output

[0102] 5. The output waveform is completely symmetrical, which can reduce harmonic output

[0103] 6. Reduce the dv / dt of each IGBT and increase the life of IGBT

[0104] 7. Improve the IGBT utilization rate to a maximum of 50%, with 2 IGBTs turned on and off in any cycle.

[0105] Optionally, as another embodiment of the present invention, the present invention has the following features relative to the prior art:

[0106] The IGBT utilization rate is increased to a maximum of 50%, and the purpose of bipolar continuous output can be achieved without adding dead zone. The number of IGBT switches per cycle is the same, reducing local heating. The frequency doubling effect is produced by superimposing two IGBTs, improving the quality of the output voltage and reducing harmonic output, and the waveform is completely symmetrical. Reduce the dv / dt of the IGBT and increase the life of the IGBT.

[0107] Fig.12 A schematic flow chart of an H-bridge control method provided by an embodiment of the present invention.

[0108] Optionally, as another embodiment of the present invention, Fig.12 As shown, an H-bridge control method comprises the following steps:

[0109] Importing an initial sine wave, performing waveform comparison between the initial sine wave and a preset triangular wave group, and controlling the H-bridge circuit to output a positive half-cycle waveform group to be processed and a negative half-cycle waveform group to be processed according to the comparison result;

[0110] Performing positive half-cycle waveform analysis on the positive half-cycle waveform group to be processed, and controlling the modulated wave output end to output a target positive half-cycle waveform according to the analysis result;

[0111] Performing negative half-cycle waveform analysis on the negative half-cycle waveform group to be processed, and controlling the modulation wave input terminal to output a target negative half-cycle waveform according to the analysis result;

[0112] The target positive half-cycle waveform and the target negative half-cycle waveform are superimposed to obtain a target waveform.

[0113] Optionally, another embodiment of the present invention provides an H-bridge control system, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the H-bridge control method described above is implemented. The system may be a computer or other system.

[0114] Optionally, another embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the H-bridge control method as described above is implemented.

[0115] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0116] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0117] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0118] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present invention.

[0119] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0120] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. For such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0121] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. An H-bridge control system, characterized in that: include: Processor, H-bridge circuit and capacitors, The H-bridge circuit is respectively connected to the processor, two ends of the capacitor, a modulation wave input end, and a modulation wave output end; The processor is used to import an initial sine wave, compare the initial sine wave with a preset triangle wave group, and control the H-bridge circuit to output a positive half-cycle waveform group to be processed and a negative half-cycle waveform group to be processed according to the comparison result; Performing positive half-cycle waveform analysis on the positive half-cycle waveform group to be processed, and controlling the modulation wave output end to output a target positive half-cycle waveform according to the analysis result; Performing negative half-cycle waveform analysis on the negative half-cycle waveform group to be processed, and controlling the modulation wave input terminal to output a target negative half-cycle waveform according to the analysis result; The target positive half-cycle waveform and the target negative half-cycle waveform are superimposed to obtain a target waveform.

2. The H-bridge control system according to claim 1, characterized in that: The H-bridge circuit comprises a first insulated gate bipolar transistor, a second insulated gate bipolar transistor, a third insulated gate bipolar transistor and a fourth insulated gate bipolar transistor: The gate of the first insulated gate bipolar transistor is connected to the first port of the processor, the collector of the first insulated gate bipolar transistor is respectively connected to the collector of the third insulated gate bipolar transistor and one end of the capacitor, the emitter of the first insulated gate bipolar transistor is respectively connected to the modulation wave input end and the collector of the second insulated gate bipolar transistor, the gate of the second insulated gate bipolar transistor is connected to the second port of the processor, the emitter of the second insulated gate bipolar transistor is respectively connected to the other end of the capacitor and the emitter of the fourth insulated gate bipolar transistor, the gate of the third insulated gate bipolar transistor is connected to the third port of the processor, the emitter of the third insulated gate bipolar transistor is respectively connected to the modulation wave output end and the collector of the fourth insulated gate bipolar transistor, and the gate of the fourth insulated gate bipolar transistor is connected to the fourth port of the processor.

3. The H-bridge control system according to claim 2, characterized in that: In the processor, the process of performing waveform comparison between the initial sine wave and the preset triangle wave group, and controlling the H-bridge circuit to output the positive half-cycle waveform group to be processed and the negative half-cycle waveform group to be processed according to the comparison result includes: Determine whether the first initial sine wave data point of the initial sine wave is greater than 0, if so, execute the first solution; if not, execute the second solution; The initial sine wave includes an initial sine wave positive half cycle and an initial sine wave negative half cycle; Among them, the first solution is: Compare the waveforms of the positive half cycle of the initial sine wave with the preset triangular wave group, control the first insulated gate bipolar transistor to output a first positive half cycle waveform to be processed according to a first comparison result, and control the fourth insulated gate bipolar transistor to output a second positive half cycle waveform to be processed according to the first comparison result; Compare the negative half cycle of the initial sine wave with the negative half cycle of the preset triangle wave group, control the second insulated gate bipolar transistor to output a first negative half cycle waveform to be processed according to a second comparison result, and control the third insulated gate bipolar transistor to output a second negative half cycle waveform to be processed according to the second comparison result; The second solution is: Compare the negative half cycle of the initial sine wave with the negative half cycle of the preset triangle wave group, control the second insulated gate bipolar transistor to output the first negative half cycle waveform to be processed according to a second comparison result, and control the third insulated gate bipolar transistor to output the second negative half cycle waveform to be processed according to a second comparison result; Compare the waveforms of the positive half cycle of the initial sine wave with the preset triangular wave group, control the first insulated gate bipolar transistor to output the first to-be-processed positive half cycle waveform according to a first comparison result, and control the fourth insulated gate bipolar transistor to output the second to-be-processed positive half cycle waveform according to the first comparison result; The positive half-cycle waveform group to be processed includes the first positive half-cycle waveform to be processed and the second positive half-cycle waveform to be processed, and the negative half-cycle waveform group to be processed includes the first negative half-cycle waveform to be processed and the second negative half-cycle waveform to be processed.

4. The H-bridge control system according to claim 3, characterized in that: The preset triangle wave group includes initial triangle wave data points at multiple moments and flip triangle wave data points at multiple moments, and the initial sine wave positive half cycle includes sine wave positive half cycle data points at multiple moments. In the processor, the process of comparing the positive half cycle of the initial sine wave with the positive half cycle of the preset triangle wave group, controlling the first insulated gate bipolar transistor to output a first positive half cycle waveform to be processed according to a first comparison result, and controlling the fourth insulated gate bipolar transistor to output a second positive half cycle waveform to be processed according to the first comparison result includes: At each moment, determine whether the positive half-cycle data point of the sine wave is greater than the initial triangular wave data point; if so, control the first insulated gate bipolar transistor to output a first preset value; if not, control the first insulated gate bipolar transistor to output a second preset value, until all the positive half-cycle data points of the sine wave corresponding to all moments are compared, and all output results are plotted as the first positive half-cycle waveform to be processed; For each moment, determine whether the positive half-cycle data point of the sine wave is greater than the flipped triangle wave data point. If so, control the fourth insulated gate bipolar transistor to output the first preset value; if not, control the fourth insulated gate bipolar transistor to output the second preset value, until the positive half-cycle data points of the sine wave corresponding to all moments are compared, and all output results are plotted as the second positive half-cycle waveform to be processed.

5. The H-bridge control system according to claim 4, characterized in that: The initial negative half cycle of the sine wave includes negative half cycle data points of the sine wave at multiple moments. In the processor, the process of comparing the negative half cycle of the initial sine wave with the negative half cycle of the preset triangle wave group, controlling the second insulated gate bipolar transistor to output the first negative half cycle waveform to be processed according to the second comparison result, and controlling the third insulated gate bipolar transistor to output the second negative half cycle waveform to be processed according to the second comparison result includes: At each moment, determine whether the negative half-cycle data point of the sine wave is greater than the initial triangular wave data point; if so, control the second insulated gate bipolar transistor to output the second preset value; if not, control the second insulated gate bipolar transistor to output the first preset value, until the negative half-cycle data points of the sine wave corresponding to all moments are compared, and all output results are plotted as the first negative half-cycle waveform to be processed; For each moment, determine whether the negative half-cycle data point of the sine wave is greater than the flipped triangle wave data point. If so, control the third insulated gate bipolar transistor to output the second preset value; if not, control the third insulated gate bipolar transistor to output the first preset value, until the negative half-cycle data points of the sine wave corresponding to all moments are compared, and all output results are plotted as the second negative half-cycle waveform to be processed.

6. The H-bridge control system according to claim 3, characterized in that: The first to-be-processed positive half-cycle waveform includes first to-be-processed positive half-cycle data points at multiple moments, and the second to-be-processed positive half-cycle waveform includes second to-be-processed positive half-cycle data points at multiple moments. In the processor, a process of performing positive half-cycle waveform analysis on the positive half-cycle waveform group to be processed, and controlling the modulated wave output end to output a target positive half-cycle waveform according to the analysis result includes: For each moment, determine whether the first to-be-processed positive half-cycle data point and the second to-be-processed positive half-cycle data point are both first preset values. If so, control the modulated wave output end to output the first preset value; if not, control the modulated wave output end to output the second preset value, until all moments corresponding to the first to-be-processed positive half-cycle data points are determined, and all output results are plotted as the target positive half-cycle waveform.

7. The H-bridge control system according to claim 3, characterized in that: The first negative half-cycle waveform to be processed includes first negative half-cycle data points to be processed at multiple moments, and the second negative half-cycle waveform to be processed includes second negative half-cycle data points to be processed at multiple moments. In the processor, a process of performing negative half-cycle waveform analysis on the negative half-cycle waveform group to be processed, and controlling the modulation wave input terminal to output a target negative half-cycle waveform according to the analysis result includes: For each moment, determine whether the first negative half-cycle data point to be processed and the second negative half-cycle data point to be processed are both the first preset value. If so, control the modulation wave output end to output the third preset value; if not, control the modulation wave output end to output the second preset value, until the first negative half-cycle data points to be processed corresponding to all moments are determined, and all output results are plotted as the target negative half-cycle waveform.

8. An H-bridge control method, characterized in that: The steps include: Importing an initial sine wave, performing waveform comparison between the initial sine wave and a preset triangular wave group, and controlling the H-bridge circuit to output a positive half-cycle waveform group to be processed and a negative half-cycle waveform group to be processed according to the comparison result; Performing positive half-cycle waveform analysis on the positive half-cycle waveform group to be processed, and controlling the modulated wave output end to output a target positive half-cycle waveform according to the analysis result; Performing negative half-cycle waveform analysis on the negative half-cycle waveform group to be processed, and controlling the modulation wave input terminal to output a target negative half-cycle waveform according to the analysis result; The target positive half-cycle waveform and the target negative half-cycle waveform are superimposed to obtain a target waveform.

9. An H-bridge control system, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the H-bridge control method according to claim 8 is implemented.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the H-bridge control method according to claim 8 is implemented.

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